Semiconductor device

Abstract

The semiconductor device includes: a chip; an electrode formed on the chip; an inorganic insulating layer covering the electrode and having a first opening exposing the electrode; an organic insulating layer that covers the inorganic insulating layer, has a second opening that surrounds the first opening with a gap therebetween from the first opening, and exposes an inner peripheral edge of the inorganic insulating layer in a region between the first opening and the second opening; and a Ni plating layer covering the electrode in the first opening and covering the inner peripheral edge of the inorganic insulating layer in the second opening.

Description

[0001] This application is a divisional application; the application number of the parent case is "2020800660908", the application date is September 25, 2020, and the name of the invention is "Semiconductor Device". Technical Field

[0002] The present invention relates to semiconductor devices. Background Art

[0003] Patent Document 1 (Figure 4) discloses a semiconductor device comprising a semiconductor substrate, an aluminum film (electrode), a polyimide film (organic insulating layer), and a Ni plating film (Ni plating layer). The aluminum film is formed on the semiconductor substrate. The polyimide film is formed on the aluminum film and has an opening through which the aluminum film is exposed. The Ni plating film is formed on the aluminum film exposed through the opening in the polyimide film.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: International Publication No. 2018 / 167925A1 Summary of the Invention

[0007] Problems to be solved by the invention

[0008] Organic insulating layers have low adhesion to Ni. Therefore, when a Ni plating layer is formed on an electrode exposed through an opening in the organic insulating layer, a gap extending toward the electrode is formed between the Ni plating layer and the organic insulating layer. As a result, the Ni plating layer becomes insufficiently connected to the electrode, reducing the reliability of the Ni plating layer.

[0009] One embodiment of the present invention provides a semiconductor device having a structure in which a Ni plating layer is formed on an electrode exposed from an opening of an organic insulating layer, and in which the reliability of the Ni plating layer can be improved.

[0010] Solutions to Problems

[0011] One embodiment of the present invention provides a semiconductor device, comprising: a chip; an electrode formed on the chip; an inorganic insulating layer covering the electrode and having a first opening exposing the electrode; an organic insulating layer covering the inorganic insulating layer and having a second opening surrounding the first opening at a distance from the first opening, exposing the inner periphery of the inorganic insulating layer in the area between the first opening and the second opening; and a Ni plating layer covering the electrode in the first opening and covering the inner periphery of the inorganic insulating layer in the second opening.

[0012] In this semiconductor device, the Ni plating layer covers the inner periphery of the inorganic insulating layer, which has a higher adhesion to Ni than the organic insulating layer. This allows the gap formation region to be moved away from the electrode while suppressing the formation of gaps extending toward the electrode. Compared to a configuration in which the inner periphery of the inorganic insulating layer is not exposed, the gap formation region between the organic insulating layer and the inorganic insulating layer can be reduced. Consequently, the reliability of the Ni plating layer can be improved.

[0013] The above and other objects, features, and effects of the present invention will become apparent from the following description of the embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a plan view showing a semiconductor device according to a first embodiment of the present invention.

[0015] Figure 2 Together with the outer surface plating of the first embodiment, Figure 1 A cross-sectional view taken along line II-II is shown.

[0016] Figure 3 yes Figure 2 An enlarged view of region III is shown.

[0017] Figure 4A yes Figure 3 The corresponding figure is an enlarged view of the outer surface plating layer of the second embodiment.

[0018] Figure 4B yes Figure 3 The corresponding figure is an enlarged view of the outer surface plating layer of the third embodiment.

[0019] Figure 4C yes Figure 3 The corresponding figure is an enlarged view of the outer surface plating layer of the fourth embodiment.

[0020] Figure 4D yes Figure 3 The corresponding figure is an enlarged view of the outer surface plating layer of the fifth embodiment.

[0021] Figure 5A Is used to illustrate Figure 1 A cross-sectional view of an example of a method for manufacturing a semiconductor device shown.

[0022] Figure 5B Yes Figure 5A Cross-sectional view of the subsequent process.

[0023] Figure 5C Yes Figure 5B Cross-sectional view of the subsequent process.

[0024] Figure 5DYes Figure 5C Cross-sectional view of the subsequent process.

[0025] Figure 5E Yes Figure 5D Cross-sectional view of the subsequent process.

[0026] Figure 5F Yes Figure 5E Cross-sectional view of the subsequent process.

[0027] Figure 5G Yes Figure 5F Cross-sectional view of the subsequent process.

[0028] Figure 5H Yes Figure 5G Cross-sectional view of the subsequent process.

[0029] Figure 5I Yes Figure 5H Cross-sectional view of the subsequent process.

[0030] Figure 5J Yes Figure 5I Cross-sectional view of the subsequent process.

[0031] Figure 5K Yes Figure 5J Cross-sectional view of the subsequent process.

[0032] Figure 5L Yes Figure 5K Cross-sectional view of the subsequent process.

[0033] Figure 5M Yes Figure 5L Cross-sectional view of the subsequent process.

[0034] Figure 5N Yes Figure 5M Cross-sectional view of the subsequent process.

[0035] Figure 5O Yes Figure 5N Cross-sectional view of the subsequent process.

[0036] Figure 6 yes Figure 2 The corresponding figure is a cross-sectional view showing a semiconductor device according to a second embodiment of the present invention together with the outer surface plating layer of the first embodiment.

[0037] Figure 7 yes Figure 6 An enlarged view of region VII is shown.

[0038] Figure 8A yes Figure 7 The corresponding figure is an enlarged view of the outer surface plating layer of the second embodiment.

[0039] Figure 8B yes Figure 7 The corresponding figure is an enlarged view of the outer surface plating layer of the third embodiment.

[0040] Figure 8C yes Figure 7 The corresponding figure is an enlarged view of the outer surface plating layer of the fourth embodiment.

[0041] Figure 8D yes Figure 7 The corresponding figure is an enlarged view of the outer surface plating layer of the fifth embodiment.

[0042] Figure 9 It is a plan view showing a semiconductor device according to a third embodiment of the present invention.

[0043] Figure 10 Yes Figure 9 Magnified view of area X shown.

[0044] Figure 11 It is along Figure 10 A cross-sectional view taken along line XI-XI is shown.

[0045] Figure 12 It is along Figure 9 A cross-sectional view taken along line XII-XII is shown.

[0046] Figure 13 yes Figure 12 An enlarged view of region XIII is shown.

[0047] Figure 14 yes Figure 12 An enlarged view of region XIV is shown.

[0048] Figure 15 yes Figure 12 The corresponding figure is a cross-sectional view of a semiconductor device according to a fourth embodiment of the present invention.

[0049] Figure 16 yes Figure 15 An enlarged view of region XVI is shown.

[0050] Figure 17 yes Figure 15 An enlarged view of region XVII is shown.

[0051] Figure 18 This is a plan view of a semiconductor package in which the semiconductor device according to the first to fourth embodiments is incorporated, as viewed from one side.

[0052] Figure 19 Observing from the other side Figure 18 A top view of a semiconductor package is shown.

[0053] Figure 20 yes Figure 18 A perspective view of a semiconductor package is shown.

[0054] Figure 21 yes Figure 18 An exploded perspective view of a semiconductor package is shown.

[0055] Figure 22 It is along Figure 18 A cross-sectional view taken along line XXII-XXII is shown.

[0056] Figure 23 yes Figure 18 The circuit diagram of the semiconductor package is shown. DETAILED DESCRIPTION

[0057] Figure 1 It is a plan view showing the semiconductor device 1 according to the first embodiment of the present invention. Figure 2 Together with the outer surface plating layer 42 of the first embodiment, Figure 1 A cross-sectional view taken along line II-II is shown. Figure 3 yes Figure 2 An enlarged view of region III is shown.

[0058] Reference Figures 1 to 3 In this embodiment, semiconductor device 1 is composed of a SiC semiconductor device including a SiC chip 2 (chip). SiC chip 2 comprises a hexagonal SiC single crystal. Hexagonal SiC single crystals include various polycrystalline types, such as 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, and 6H-SiC single crystals. In this embodiment, SiC chip 2 is composed of a 4H-SiC single crystal, but other polycrystalline types may also be used.

[0059] The SiC chip 2 is formed into a rectangular parallelepiped shape. It has a first principal surface 3 on one side, a second principal surface 4 on the other side, and side surfaces 5A, 5B, 5C, and 5D connecting the first principal surface 3 and the second principal surface 4. In a plan view taken from the normal direction Z (hereinafter referred to as "plan view"), the first principal surface 3 and the second principal surface 4 are formed into a quadrilateral shape (a square shape in this embodiment).

[0060] The thickness of the SiC chip 2 may be greater than or equal to 40 μm and less than or equal to 300 μm. The thickness of the SiC chip 2 may be greater than or equal to 40 μm and less than or equal to 100 μm, greater than or equal to 100 μm and less than or equal to 150 μm, greater than or equal to 150 μm and less than or equal to 200 μm, greater than or equal to 200 μm and less than or equal to 250 μm, or greater than or equal to 250 μm and less than or equal to 300 μm. The thickness of the SiC chip 2 is preferably greater than or equal to 60 μm and less than or equal to 150 μm.

[0061] The first principal surface 3 and the second principal surface 4 face the c-plane of the SiC single crystal. The first principal surface 3 faces the silicon plane ((0001) plane) of the SiC single crystal, and the second principal surface 4 faces the carbon plane ((000-1) plane) of the SiC single crystal. The second principal surface 4 may be a rough surface having either or both polishing marks and annealing marks. Annealing marks are laser irradiation marks. The second principal surface 4 may also be an ohmic surface having annealing marks.

[0062] The first principal surface 3 and the second principal surface 4 may also have an off-angle that is tilted at a predetermined off-angle in a predetermined off-direction relative to the c-plane of the SiC single crystal. The off-direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off-angle is preferably tilted at an angle of 0° or more and 10° or less in the off-direction. The off-angle may also be 0° or more and 6° or less. The off-angle may also be 0° or more and 2° or less, 2° or more and 4° or less, or 4° or more and 6° or less.

[0063] The deviation angle is preferably greater than 0° and less than 4.5°. The deviation angle may also be greater than 3° and less than 4.5°. In this case, the deviation angle is preferably greater than 3° and less than 3.5°, or greater than 3.5° and less than 4°. The deviation angle may also be greater than 1.5° and less than 3°. In this case, the deviation angle is preferably greater than 1.5° and less than 2°, or greater than 2° and less than 2.5°.

[0064] The side surfaces 5A to 5D include a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D. The first side surface 5A and the second side surface 5B extend along a first direction X and face each other in a second direction Y that intersects the first direction X. The third side surface 5C and the fourth side surface 5D extend along a second direction Y and face each other in the first direction X. Specifically, the second direction Y is orthogonal to the first direction X.

[0065] The first side surface 5A and the second side surface 5B are formed by the a-plane of the SiC single crystal. When the normal direction Z is used as a reference, the first side surface 5A and the second side surface 5B can also form an inclined surface that is inclined relative to the normal direction Z toward the c-axis direction (

[0001] direction) of the SiC single crystal. When the normal direction Z is set to 0°, the first side surface 5A and the second side surface 5B can also be inclined relative to the normal direction Z at an angle corresponding to the deviation angle. The angle corresponding to the deviation angle can be equal to the deviation angle or an angle that exceeds 0° and is less than the deviation angle.

[0066] The third side surface 5C and the fourth side surface 5D are formed of the m-plane of the SiC single crystal. The third side surface 5C and the fourth side surface 5D extend in a planar manner along the normal direction Z. Specifically, the third side surface 5C and the fourth side surface 5D are formed substantially perpendicular to the first principal surface 3 and the second principal surface 4.

[0067] The side surfaces 5A to 5D may be formed of cleaved surfaces or polished surfaces. The length of the side surfaces 5A to 5D may be 0.1 mm to 10 mm. The length of the side surfaces 5A to 5D is preferably 0.5 mm to 2.5 mm.

[0068] In this embodiment, the SiC chip 2 has a stacked structure including n + n-type SiC substrate 6 and n-type SiC epitaxial layer 7. SiC substrate 6 forms second principal surface 4 and part of side surfaces 5A to 5D of SiC chip 2. SiC epitaxial layer 7 forms first principal surface 3 and part of side surfaces 5A to 5D of SiC chip 2.

[0069] The n-type impurity concentration of the SiC epitaxial layer 7 is lower than that of the SiC substrate 6. The n-type impurity concentration of the SiC substrate 6 may be 1.0×10 18 cm -3 Above and 1.0×10 21 cm -3 The n-type impurity concentration of the SiC epitaxial layer 7 may be 1.0×10 15 cm -3 Above and 1.0×10 18 cm-3 or less.

[0070] The thickness of the SiC substrate 6 may be 40 μm to 250 μm. The thickness of the SiC substrate 6 may be 40 μm to 100 μm, 100 μm to 150 μm, 150 μm to 200 μm, or 200 μm to 250 μm. The thickness of the SiC substrate 6 is preferably 40 μm to 150 μm. Thinning the SiC substrate 6 can reduce the resistance of the SiC substrate 6.

[0071] The thickness of the SiC epitaxial layer 7 may be 1 μm to 50 μm. The thickness of the SiC epitaxial layer 7 is preferably 1 μm to 5 μm, 5 μm to 10 μm, 10 μm to 15 μm, 15 μm to 20 μm, 20 μm to 30 μm, 30 μm to 40 μm, or 40 μm to 50 μm. The thickness of the SiC epitaxial layer 7 is preferably 5 μm to 15 μm.

[0072] SiC chip 2 includes an active region 8 and an outer region 9. Active region 8 includes an SBD (Schottky barrier diode), an example of a functional device (diode). Active region 8 is formed in the center of SiC chip 2, spaced inward from side surfaces 5A to 5D when viewed from above. Active region 8 has a square shape with four sides parallel to side surfaces 5A to 5D when viewed from above.

[0073] The outer region 9 is an area outside the active region 8. The outer region 9 is formed between the side surfaces 5A to 5D and the active region 8. The outer region 9 is formed in a ring shape (specifically, a jointless shape) surrounding the active region 8 in a plan view.

[0074] Semiconductor device 1 includes an n-type diode region 10 formed in the surface portion of first principal surface 3 within active region 8. Diode region 10 is formed in the center portion of first principal surface 3. The planar shape of diode region 10 is arbitrary. Diode region 10 may also be formed into a quadrilateral having four sides parallel to side surfaces 5A to 5D when viewed from above.

[0075] In this embodiment, the diode region 10 is formed using a portion of the SiC epitaxial layer 7. The n-type impurity concentration of the diode region 10 is equal to the n-type impurity concentration of the SiC epitaxial layer 7. The n-type impurity concentration of the diode region 10 may also exceed the n-type impurity concentration of the SiC epitaxial layer 7. In this case, the diode region 10 is formed by introducing n-type impurities into the surface portion of the SiC epitaxial layer 7.

[0076] A protector region 11 containing p-type impurities is formed in the outer region 9 and on the surface of the first main surface 3. The p-type impurities in the protector region 11 may be inactivated or activated. The protector region 11 is formed in a strip shape extending along the diode region 10 when viewed from above. Specifically, the protector region 11 is formed in a ring shape (specifically, a jointless shape) surrounding the diode region 10 when viewed from above.

[0077] Thus, the guard region 11 is formed as a guard ring region. The guard region 11 demarcates the active region 8 (diode region 10). The planar shape of the active region 8 (diode region 10) is regulated by the planar shape of the guard region 11. The guard region 11 can also be formed to have a polygonal ring shape or a circular ring shape when viewed from above.

[0078] The semiconductor device 1 includes a main surface insulating layer 12 formed on the first main surface 3. The main surface insulating layer 12 may have a stacked structure including a silicon oxide layer and a silicon nitride layer. The main surface insulating layer 12 may also have a single-layer structure consisting of a silicon oxide layer or a silicon nitride layer. In this embodiment, the main surface insulating layer 12 has a single-layer structure consisting of a silicon oxide layer.

[0079] The main surface insulating layer 12 has a contact opening 13 that exposes the diode region 10. The contact opening 13 also exposes the inner periphery of the protector region 11. The planar shape of the contact opening 13 is arbitrary. The contact opening 13 can also be a quadrilateral having four sides parallel to the side surfaces 5A to 5D when viewed from above.

[0080] The periphery of the main surface insulating layer 12 is exposed from the side surfaces 5A to 5D. In this embodiment, the periphery of the main surface insulating layer 12 is continuous with the side surfaces 5A to 5D. Alternatively, the periphery of the main surface insulating layer 12 may be formed with a gap inward from the side surfaces 5A to 5D. In this case, the main surface insulating layer 12 is exposed in the portion located in the outer region 9 of the first main surface 3.

[0081] The thickness of the main surface insulating layer 12 may be 0.1 μm to 10 μm. The thickness of the main surface insulating layer 12 may be 0.1 μm to 1 μm, 1 μm to 2 μm, 2 μm to 4 μm, 4 μm to 6 μm, 6 μm to 8 μm, or 8 μm to 10 μm. The thickness of the main surface insulating layer 12 is preferably 0.5 μm to 5 μm.

[0082] Semiconductor device 1 includes a first main surface electrode 21 (electrode) formed on first main surface 3. First main surface electrode 21 is connected to diode region 10 and guard region 11 within contact opening 13. First main surface electrode 21 extends from contact opening 13 onto main surface insulating layer 12. The periphery of first main surface electrode 21 is formed on main surface insulating layer 12 with spaces therebetween inward from side surfaces 5A to 5D. Thus, first main surface electrode 21 exposes the periphery of main surface insulating layer 12.

[0083] The thickness T1 of the first principal surface electrode 21 may be 10 μm to 100 μm. The thickness T1 may be 10 μm to 20 μm, 20 μm to 40 μm, 40 μm to 60 μm, 60 μm to 80 μm, or 80 μm to 100 μm. The thickness T1 is preferably 20 μm to 60 μm.

[0084] Specifically, the first main surface electrode 21 has a stacked structure including a barrier electrode 22 and a main electrode 23 stacked sequentially from the first main surface 3 side. The barrier electrode 22 is formed in a film-like shape along the first main surface 3 and the main surface insulating layer 12. The barrier electrode 22 forms a Schottky junction with the diode region 10. This forms an SBD with the first main surface electrode 21 as the anode and the diode region 10 as the cathode. In other words, the first main surface electrode 21 is the anode electrode of the SBD.

[0085] The barrier electrode 22 may include at least one of a Ti layer, a Pd layer, a Cr layer, a V layer, a Mo layer, a W layer, a Pt layer, and a Ni layer. The thickness of the barrier electrode 22 may be greater than or equal to 0.01 μm and less than or equal to 1 μm. The thickness of the barrier electrode 22 may be greater than or equal to 0.01 μm and less than or equal to 0.1 μm, greater than or equal to 0.1 μm and less than or equal to 0.2 μm, greater than or equal to 0.2 μm and less than or equal to 0.4 μm, greater than or equal to 0.4 μm and less than or equal to 0.6 μm, greater than or equal to 0.6 μm and less than or equal to 0.8 μm, or greater than or equal to 0.8 μm and less than or equal to 1 μm.

[0086] The main electrode 23 is formed in a film-like shape on the barrier electrode 22. The main electrode 23 covers the entire main surface of the barrier electrode 22. The main electrode 23 is composed of an Al-based metal layer. Specifically, the main electrode 23 includes at least one of a pure Al layer (an Al layer composed of Al with a purity of 99% or greater), an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer.

[0087] The main electrode 23 may have a stacked structure comprising two or more of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer stacked in any order. The main electrode 23 may also have a single-layer structure comprising a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, or an AlSiCu alloy layer. The main electrode 23 preferably has a single-layer structure comprising an AlSi alloy layer, an AlCu alloy layer, or an AlSiCu alloy layer.

[0088] The thickness of the main electrode 23 exceeds the thickness of the barrier electrode 22. The thickness of the main electrode 23 may be greater than 10 μm and less than 100 μm. The thickness of the main electrode 23 may be greater than 10 μm and less than 20 μm, greater than 20 μm and less than 40 μm, greater than 40 μm and less than 60 μm, greater than 60 μm and less than 80 μm, or greater than 80 μm and less than 100 μm. The thickness of the main electrode 23 is preferably greater than 20 μm and less than 60 μm. The thickness of the barrier electrode 22 is extremely small compared to the thickness of the main electrode 23, so the thickness T1 of the first main surface electrode 21 is approximately the same as the thickness of the main electrode 23.

[0089] The semiconductor device 1 includes an insulating layer 24 covering the first main surface electrode 21 on the first main surface 3. Figure 1 Insulation layer 24 is hatched. Specifically, insulation layer 24 is formed on main surface insulation layer 12. The periphery of insulation layer 24 is formed with spaces inward from side surfaces 5A to 5D. Thus, insulation layer 24 exposes the periphery of main surface insulation layer 12.

[0090] The periphery of the insulating layer 24 defines dicing streets 25 between the side surfaces 5A to 5D. The dicing streets 25 allow the insulating layer 24 to be physically cut when the semiconductor device 1 is cut from the wafer. This allows for smoother cutting of the semiconductor device 1 from the wafer while suppressing delamination and degradation of the insulating layer 24. Consequently, the insulating layer 24 can appropriately protect the SiC chip 2, first main surface electrode 21, and other protected objects.

[0091] The width of the dicing street 25 may be greater than or equal to 1 μm and less than or equal to 25 μm. The width of the dicing street 25 is the width in a direction perpendicular to the direction in which the dicing street 25 extends. The width of the dicing street 25 may be greater than or equal to 1 μm and less than or equal to 5 μm, greater than or equal to 5 μm and less than or equal to 10 μm, greater than or equal to 10 μm and less than or equal to 15 μm, greater than or equal to 15 μm and less than or equal to 20 μm, or greater than or equal to 20 μm and less than or equal to 25 μm.

[0092] Insulating layer 24 includes a pad opening 26 that exposes first main surface electrode 21. Pad opening 26 exposes first main surface electrode 21 within the region surrounded by contact opening 13 when viewed from above. Alternatively, pad opening 26 may surround contact opening 13 within the region outside contact opening 13 when viewed from above. The planar shape of pad opening 26 is arbitrary. Pad opening 26 may also be formed into a quadrilateral shape having four sides parallel to side surfaces 5A to 5D when viewed from above.

[0093] Specifically, the insulating layer 24 has a laminated structure including an inorganic insulating layer 30 and an organic insulating layer 31, which are stacked sequentially from the SiC chip 2 side. The inorganic insulating layer 30 is formed in a film-like shape along the main surface insulating layer 12 and the first main surface electrode 21. The inorganic insulating layer 30 includes a first inner wall 32 and a first outer wall 33. The first inner wall 32 of the inorganic insulating layer 30 defines a first opening 34 that exposes a portion of the first main surface electrode 21. The first opening 34 forms a portion of the pad opening 26.

[0094] First opening 34 is defined within the area surrounded by contact opening 13 in plan view. First opening 34 may also surround contact opening 13 from the outside in plan view. The planar shape of first opening 34 is arbitrary. First opening 34 may also be defined as a quadrilateral having four sides parallel to side surfaces 5A to 5D in plan view.

[0095] The first outer wall 33 of the inorganic insulating layer 30 is formed inwardly from the side surfaces 5A to 5D at intervals, exposing the peripheral edge of the main surface insulating layer 12. The inorganic insulating layer 30 defines a portion of the scribe line 25 between the side surfaces 5A to 5D. The first outer wall 33 may also be formed in a rectangular shape having four sides parallel to the side surfaces 5A to 5D when viewed from above.

[0096] The angle formed between the first inner wall 32 (first outer wall 33) and the main surface of the first main surface electrode 21 within the inorganic insulating layer 30 may be greater than 30° and less than 90°. The angle formed between the first inner wall 32 (first outer wall 33) and the main surface of the first main surface electrode 21 within the inorganic insulating layer 30 is preferably greater than 45° and less than 90°. The angle of the first inner wall 32 (first outer wall 33) is defined by the angle formed between the main surface of the first main surface electrode 21 and a straight line connecting the lower and upper ends of the first inner wall 32 (first outer wall 33).

[0097] The inorganic insulating layer 30 has a high adhesion to Ni. The inorganic insulating layer 30 includes at least one of a silicon oxide layer and a silicon nitride layer. The inorganic insulating layer 30 may also have a stacked structure including silicon oxide layers and silicon nitride layers stacked sequentially from the SiC chip 2 side. The inorganic insulating layer 30 may also have a single-layer structure consisting of a silicon oxide layer or a silicon nitride layer. The inorganic insulating layer 30 preferably includes an insulating material different from that of the main surface insulating layer 12. In this embodiment, the inorganic insulating layer 30 has a single-layer structure consisting of a silicon nitride layer.

[0098] The thickness T2 of the inorganic insulating layer 30 is preferably smaller than the thickness T1 of the first main surface electrode 21 (T2 < T1). The thickness T2 may be greater than or equal to 0.1 μm and less than or equal to 10 μm. The thickness T2 may also be greater than or equal to 0.1 μm and less than or equal to 1 μm, greater than or equal to 1 μm and less than or equal to 2 μm, greater than or equal to 2 μm and less than or equal to 4 μm, greater than or equal to 4 μm and less than or equal to 6 μm, greater than or equal to 6 μm and less than or equal to 8 μm, or greater than or equal to 8 μm and less than or equal to 10 μm. The thickness T2 is preferably greater than or equal to 1 μm and less than or equal to 5 μm. The thickness T2 is particularly preferably greater than or equal to 1 μm and less than or equal to 2 μm.

[0099] The organic insulating layer 31 is formed in a film-like shape on the inorganic insulating layer 30. The organic insulating layer 31 includes a second inner wall 35 and a second outer wall 36. The second inner wall 35 of the organic insulating layer 31 defines a second opening 37 that exposes a portion of the first main surface electrode 21. In this embodiment, the second inner wall 35 is formed in a curved shape that is recessed toward the inorganic insulating layer 30.

[0100] Reference Figure 3 Second opening 37 communicates with first opening 34 of inorganic insulating layer 30, forming pad opening 26 between second opening 37 and first opening 34. Second opening 37 is defined within the region surrounded by contact opening 13 in plan view. Second opening 37 may also surround contact opening 13 from outside in plan view. The planar shape of second opening 37 is arbitrary. Second opening 37 may also be defined as a quadrilateral having four sides parallel to side surfaces 5A to 5D in plan view.

[0101] The second opening 37 surrounds the first opening 34 at a distance therefrom and exposes a portion of the inorganic insulating layer 30 . Specifically, the organic insulating layer 31 exposes a portion of the main surface of the inorganic insulating layer 30 as an inner peripheral edge 38 in the region between the first opening 34 and the second opening 37 .

[0102] The width W of the inner peripheral edge 38 of the inorganic insulating layer 30 may be greater than 0 μm and less than 10 μm. The width W may also be greater than 0 μm and less than 1 μm, greater than 1 μm and less than 2 μm, greater than 2 μm and less than 4 μm, greater than 4 μm and less than 6 μm, greater than 6 μm and less than 8 μm, or greater than 8 μm and less than 10 μm. The width W is preferably greater than 1 μm and less than 5 μm. The width W is arbitrary, but is preferably less than or equal to the thickness T2 of the inorganic insulating layer 30 (W≤T2). The width W is particularly preferably greater than or equal to 1 μm and less than 2 μm.

[0103] In this embodiment, the second outer wall 36 of the organic insulating layer 31 is formed in a curved shape that is recessed toward the inorganic insulating layer 30. The second outer wall 36 is formed on the inorganic insulating layer 30 at intervals inward from the side surfaces 5A to 5D, and defines a portion of the scribe line 25 between the side surfaces 5A to 5D. As a result, the organic insulating layer 31 exposes the periphery of the main surface insulating layer 12. The second outer wall 36 can also be formed in a rectangular shape with four sides parallel to the side surfaces 5A to 5D when viewed from above.

[0104] The second outer wall 36 of the organic insulating layer 31 may cross the first outer wall 33 of the inorganic insulating layer 30 and be formed on the main surface insulating layer 12. In this case, the second outer wall 36 of the organic insulating layer 31 defines the dicing street 25.

[0105] The angle formed between the second inner wall 35 (second outer wall 36) of the organic insulating layer 31 and the main surface of the inorganic insulating layer 30 within the organic insulating layer 31 may be greater than 30° and less than 90°. The angle formed between the second inner wall 35 (second outer wall 36) and the main surface of the inorganic insulating layer 30 within the organic insulating layer 31 is preferably greater than 45° and less than 90°. The angle of the second inner wall 35 (second outer wall 36) is defined by the angle formed between the main surface of the inorganic insulating layer 30 and a straight line connecting the lower and upper ends of the second inner wall 35 (second outer wall 36).

[0106] Compared to the inorganic insulating layer 30, the organic insulating layer 31 has lower adhesion to Ni. The organic insulating layer 31 comprises a negative-type or positive-type photosensitive resin. Alternatively, the organic insulating layer 31 may comprise at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 31 comprises polyimide.

[0107] The organic insulating layer 31 preferably has a thickness T3 that exceeds the thickness T2 of the inorganic insulating layer 30 (T2 < T3). The ratio T3 / T2 of the thickness T3 of the organic insulating layer 31 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than 10. The ratio T3 / T2 may also be greater than 1 and less than 2, greater than 2 and less than 4, greater than 4 and less than 6, greater than 6 and less than 8, or greater than 8 and less than 10. The ratio T3 / T2 is preferably greater than 2 and less than 6.

[0108] Thickness T3 may be 1 μm to 50 μm. Thickness T3 may be 1 μm to 10 μm, 10 μm to 20 μm, 20 μm to 30 μm, 30 μm to 40 μm, or 40 μm to 50 μm. Thickness T3 is preferably 5 μm to 30 μm.

[0109] Semiconductor device 1 includes a rough surface region 39 formed on the surface of first main surface electrode 21 that is exposed from pad opening 26 (first opening 34 of inorganic insulating layer 30). Rough surface region 39 includes a recess formed in a region directly below first inner wall 32 of inorganic insulating layer 30. As a result, first inner wall 32 of inorganic insulating layer 30 includes a portion that protrudes into rough surface region 39.

[0110] Semiconductor device 1 includes a pad electrode 40 formed within pad opening 26. Pad electrode 40 includes a Ni plating layer 41 formed on first main surface electrode 21 within pad opening 26. Ni plating layer 41 covers first main surface electrode 21 within first opening 34 and covers inner periphery 38 of inorganic insulating layer 30 within second opening 37. Ni plating layer 41 has an outer surface formed with a gap from the main surface of organic insulating layer 31 (insulating layer 24) toward first main surface electrode 21. In this embodiment, Ni plating layer 41 covers organic insulating layer 31 within second opening 37.

[0111] Reference Figure 3 The Ni plating layer 41 includes a first portion 41A that covers the first main surface electrode 21 and a second portion 41B that covers the inner periphery 38 of the inorganic insulating layer 30. The first portion 41A of the Ni plating layer 41 fills the rough surface region 39 within the first opening 34 and covers the first main surface electrode 21. The first portion 41A covers the entire first inner wall 32 of the inorganic insulating layer 30 and protrudes from the opening end of the first opening 34 toward the opening end of the second opening 37. The first portion 41A is connected to the first inner wall 32 of the inorganic insulating layer 30 and has a first connection portion that extends in the thickness direction of the inorganic insulating layer 30.

[0112] Second portion 41B of Ni plating layer 41 is drawn from first portion 41A toward organic insulating layer 31 in second opening 37 . Second portion 41B is formed in an arc shape extending from the opening end of first opening 34 toward organic insulating layer 31 .

[0113] The second portion 41B covers the inner peripheral edge 38 of the inorganic insulating layer 30 within the second opening 37. Thus, the second portion 41B faces the first main surface electrode 21 across the inner peripheral edge 38 of the inorganic insulating layer 30. The second portion 41B is connected to the main surface of the inorganic insulating layer 30 and has a second connection portion extending in the width direction of the inorganic insulating layer 30.

[0114] In this embodiment, the second portion 41B also covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37. The second portion 41B covers the area on the inorganic insulating layer 30 side relative to the middle portion of the second inner wall 35 of the organic insulating layer 31. In other words, the second portion 41B covers the organic insulating layer 31 so that the exposed area of ​​the second inner wall 35 (organic insulating layer 31) exceeds the concealed area of ​​the second inner wall 35 (organic insulating layer 31). In this manner, the Ni plating layer 41 is formed so that the first portion 41A and the second portion 41B engage with the opening end of the first opening 34 from two different directions.

[0115] The Ni plating layer 41 has a thickness T4 that exceeds the thickness T2 of the inorganic insulating layer 30 (T2 < T4). Thickness T4 is less than thickness T3 of the organic insulating layer 31 (T4 < T3). Thickness T4 exceeds the value obtained by adding the width W of the inner peripheral edge 38 to the thickness T2 of the inorganic insulating layer 30 (T2 + W) (T2 + W < T4). This is a condition for the Ni plating layer 41 to be in contact with the second inner wall 35 of the organic insulating layer 31. Thickness T4 is defined by the thickness of the Ni plating layer 41 relative to the main surface of the first main surface electrode 21.

[0116] The ratio T4 / T2 of the thickness T4 of the Ni plating layer 41 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than 5. The ratio T4 / T2 may be greater than 1 and less than 2, greater than 2 and less than 3, greater than 3 and less than 4, or greater than 4 and less than 5.

[0117] Thickness T4 may be 0.1 μm to 15 μm. Thickness T4 may be 0.1 μm to 1 μm, 1 μm to 3 μm, 3 μm to 6 μm, 6 μm to 9 μm, 9 μm to 12 μm, or 12 μm to 15 μm. Thickness T4 is preferably 2 μm to 8 μm.

[0118] The pad electrode 40 is made of a different metal material than the Ni plating layer 41 and includes an outer surface plating layer 42 that covers the outer surface of the Ni plating layer 41 within the second opening 37. The outer surface plating layer 42 has a thickness T5 that is less than the thickness T4 of the Ni plating layer 41 (T5 < T4). The outer surface plating layer 42 covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37.

[0119] The outer surface plating layer 42 has a terminal surface 42A for external connection via a conductive bonding material (e.g., solder). The terminal surface 42A is located on the Ni plating layer 41 side relative to the main surface (opening end of the second opening 37) of the organic insulating layer 31. Thus, the outer surface plating layer 42 exposes a portion of the second inner wall 35 of the organic insulating layer 31.

[0120] In this embodiment, the outer surface plating layer 42 has a laminated structure including a Pd plating layer 43 and an Au plating layer 44 stacked in order from the Ni plating layer 41 side. The Pd plating layer 43 is formed in a film-like shape along the outer surface of the Ni plating layer 41. The Pd plating layer 43 covers the Ni plating layer 41 from the opening end of the second opening 37 toward the inorganic insulating layer 30 side with a gap. The Pd plating 43 covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37.

[0121] The Pd plating layer 43 has a thickness smaller than the thickness T4 of the Ni plating layer 41. The thickness of the Pd plating layer 43 may be 0.01 μm to 1 μm. The thickness of the Pd plating layer 43 may be 0.01 μm to 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.4 μm, 0.4 μm to 0.6 μm, 0.6 μm to 0.8 μm, or 0.8 μm to 1 μm.

[0122] The Au plating layer 44 is formed in a film shape along the outer surface of the Pd plating layer 43. The Au plating layer 44 covers the Pd plating layer 43 with a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. The Au plating layer 44 covers the second inner wall 35 of the organic insulating layer 31 in the second opening 37.

[0123] The Au plating layer 44 has a thickness smaller than the thickness T4 of the Ni plating layer 41. The thickness of the Au plating layer 44 may be 0.01 μm to 1 μm. The thickness of the Au plating layer 44 may be 0.01 μm to 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.4 μm, 0.4 μm to 0.6 μm, 0.6 μm to 0.8 μm, or 0.8 μm to 1 μm.

[0124] The outer surface coating 42 can be Figures 4A to 4D Various ways shown.

[0125] Figure 4A yes Figure 3 , which is an enlarged view showing the outer surface plating layer 42 of the second embodiment. Hereinafter, the portions of the outer surface plating layer 42 that are different from those of the first embodiment will be described.

[0126] Reference Figure 4A In this embodiment, the outer surface plating layer 42 has a single-layer structure composed of an Au plating layer 44. The Au plating layer 44 is formed in a film-like shape along the outer surface of the Ni plating layer 41. The Au plating layer 44 covers the Ni plating layer 41 from the opening end of the second opening 37 toward the inorganic insulating layer 30, with a gap therebetween. The Au plating 44 covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37.

[0127] Figure 4B yes Figure 3 , which is an enlarged view showing the outer surface plating layer 42 of the third embodiment. Hereinafter, the parts of the outer surface plating layer 42 that are different from those of the first embodiment will be described.

[0128] Reference Figure 4B In this embodiment, the outer surface plating layer 42 has a single-layer structure consisting of a Pd plating layer 43. The Pd plating layer 43 is formed in a film-like shape along the outer surface of the Ni plating layer 41. The Pd plating layer 43 covers the Ni plating layer 41 from the opening end of the second opening 37 toward the inorganic insulating layer 30, with a gap therebetween. The Pd plating 43 covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37.

[0129] Figure 4C yes Figure 3 , which is an enlarged view showing the outer surface plating layer 42 of the fourth embodiment. Hereinafter, the parts of the outer surface plating layer 42 that are different from those of the first embodiment will be described.

[0130] Reference Figure 4C In this embodiment, the outer surface plating layer 42 has a single-layer structure composed of an Ag plating layer 45. The Ag plating layer 45 is formed in a film-like shape along the outer surface of the Ni plating layer 41. The Ag plating layer 45 covers the Ni plating layer 41 from the opening end of the second opening 37 toward the inorganic insulating layer 30, with a gap therebetween. The Ag plating 45 covers the second inner wall 35 of the organic insulating layer 31 within the second opening 37.

[0131] The Ag plating layer 45 has a thickness smaller than the thickness T4 of the Ni plating layer 41. The thickness of the Ag plating layer 45 may be 0.01 μm to 1 μm. The thickness of the Ag plating layer 45 may be 0.01 μm to 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.4 μm, 0.4 μm to 0.6 μm, 0.6 μm to 0.8 μm, or 0.8 μm to 1 μm.

[0132] Figure 4D yes Figure 3 , which is an enlarged view showing the outer surface plating layer 42 of the fifth embodiment. Hereinafter, the portions of the outer surface plating layer 42 that are different from those of the first embodiment will be described.

[0133] Reference Figure 4D The outer surface plating layer 42 has a stacked structure including a Pd plating layer 43 , an Au plating layer 44 , and an Ag plating layer 45 stacked in this order from the Ni plating layer 41 side.

[0134] The Pd plating layer 43 is formed in a film shape along the outer surface of the Ni plating layer 41. The Pd plating layer 43 covers the Ni plating layer 41 with a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. The Pd plating layer 43 covers the second inner wall 35 of the organic insulating layer 31 in the second opening 37.

[0135] The Au plating layer 44 is formed in a film shape along the outer surface of the Pd plating layer 43. The Au plating layer 44 covers the Pd plating layer 43 with a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. The Au plating layer 44 covers the second inner wall 35 of the organic insulating layer 31 in the second opening 37.

[0136] The Ag plating layer 45 is formed in a film shape along the outer surface of the Au plating layer 44. The Ag plating layer 45 covers the Au plating layer 44 with a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. The Ag plating layer 45 covers the second inner wall 35 of the organic insulating layer 31 in the second opening 37.

[0137] Refer again Figure 2 The semiconductor device 1 includes a second main surface electrode 46 formed on the second main surface 4. The second main surface electrode 46 covers the entire area of ​​the second main surface 4. The second main surface electrode 46 forms an ohmic contact with the second main surface 4. The second main surface electrode 46 forms a cathode electrode of the SBD.

[0138] The second main surface electrode 46 includes at least one of a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer. The second main surface electrode 46 may also have a stacked structure in which at least two of the Ti layer, the Ni layer, the Pd layer, the Au layer, and the Ag layer are stacked in any order. The second main surface electrode 46 may also have a single-layer structure consisting of a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer. The second main surface electrode 46 preferably includes a Ti layer as an ohmic electrode. In this embodiment, the second main surface electrode 46 has a stacked structure including a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer stacked in sequence from the second main surface 4 side.

[0139] Figures 5A to 5O Is used to illustrate Figure 1A cross-sectional view showing an example of a method for manufacturing the semiconductor device 1 is shown.

[0140] Reference Figure 5A First, a SiC epitaxial wafer 50 is prepared to serve as the base of the SiC chip 2. The SiC epitaxial wafer 50 has a stacked structure including a SiC wafer 51 and a SiC epitaxial layer 52. The SiC wafer 51 serves as the base of the SiC substrate 6. The SiC epitaxial layer 52 serves as the base of the SiC epitaxial layer 7. The SiC epitaxial layer 52 is formed by epitaxially growing SiC from the main surface of the SiC wafer 51.

[0141] The SiC epitaxial wafer 50 has a first wafer principal surface 53 on one side and a second wafer principal surface 54 on the other side. The first wafer principal surface 53 and the second wafer principal surface 54 correspond to the first principal surface 3 and the second principal surface 4 of the SiC chip 2, respectively.

[0142] The SiC epitaxial wafer 50 is provided with a plurality of device regions 55 corresponding to the semiconductor devices 1, and predetermined cutting lines 56 for dividing the plurality of device regions 55. Figure 5A In the figure, one device area 55 is shown, and illustration of other areas is omitted (hereinafter, in Figure 5B to Figure 5O The plurality of device regions 55 are arranged in rows and columns along the first direction X and the second direction Y. The planned cutting lines 56 are arranged in a grid pattern extending along the first direction X and the second direction Y.

[0143] Next, refer to Figure 5B , forming the main part of the functional device in each device region 55. In this method, n-type impurities and / or p-type impurities are selectively introduced into the surface portion of the first wafer main surface 53 to form the n-type diode region 10 and the p-type protective member region 11. The n-type impurities and / or p-type impurities are introduced into the surface portion of the first wafer main surface 53 by ion implantation through an ion implantation mask (not shown).

[0144] Next, refer to Figure 5C A main surface insulating layer 12 is formed on the first wafer main surface 53. The main surface insulating layer 12 may also be formed by a CVD (Chemical Vapor Deposition) method and / or an oxidation treatment method (eg, a thermal oxidation treatment method).

[0145] Next, refer to Figure 5DA resist mask 57 having a predetermined pattern is formed on the main surface insulating layer 12. The resist mask 57 exposes the area where the contact opening 13 is to be formed in the main surface insulating layer 12, while covering the remaining area. Next, unnecessary portions of the main surface insulating layer 12 are removed by etching through the resist mask 57. The etching method may be wet etching and / or dry etching. As a result, contact openings 13 are formed in the main surface insulating layer 12.

[0146] Next, refer to Figure 5E A base electrode layer 58 serving as the base of the first main surface electrode 21 is formed on the main surface insulating layer 12. The base electrode layer 58 has a stacked structure including the barrier electrode 22 and the main electrode 23 stacked in this order from the main surface insulating layer 12 side. The barrier electrode 22 and the main electrode 23 can also be formed by sputtering and / or vapor deposition.

[0147] Next, refer to Figure 5F A resist mask 59 having a predetermined pattern is formed on the base electrode layer 58. The resist mask 59 exposes the area of ​​the base electrode layer 58 where the first main surface electrode 21 is to be formed, while covering the remaining area. Next, unnecessary portions of the base electrode layer 58 are removed by etching through the resist mask 59. The etching method may be wet etching and / or dry etching. As a result, the first main surface electrode 21 is formed on the main surface insulating layer 12.

[0148] Next, refer to Figure 5G An inorganic insulating layer 30 is formed on the main surface insulating layer 12 so as to cover the first main surface electrode 21. In this embodiment, the inorganic insulating layer 30 has a single-layer structure composed of a silicon nitride layer. The inorganic insulating layer 30 may also have a stacked structure including a silicon oxide layer and a silicon nitride layer stacked in sequence from the SiC epitaxial wafer 50 side. The inorganic insulating layer 30 may also be formed by CVD.

[0149] Next, refer to Figure 5H A resist mask 60 having a predetermined pattern is formed on the inorganic insulating layer 30. The resist mask 60 exposes regions of the inorganic insulating layer 30 where the first openings 34 and the dicing streets 25 are to be formed, and covers other regions.

[0150] Next, unnecessary portions of the inorganic insulating layer 30 are removed by etching through the resist mask 60. The etching method may be wet etching and / or dry etching. As a result, first openings 34 exposing the first main surface electrodes 21 and dicing streets 25 extending in a grid pattern along the planned cutting lines 56 are formed in the inorganic insulating layer 30.

[0151] Next, refer to Figure 5IAn organic insulating layer 31 is formed on the main surface insulating layer 12 so as to cover the first main surface electrode 21 and the inorganic insulating layer 30. The organic insulating layer 31 is formed by applying polyimide, an example of a photosensitive resin, to the first wafer main surface 53 side.

[0152] Next, refer to Figure 5J The organic insulating layer 31 is exposed to light in a pattern corresponding to the second openings 37 and the scribe lines 25 and then developed. Thus, the organic insulating layer 31 has second openings 37 exposing the first main surface electrodes 21 and scribe lines 25 extending in a grid pattern along the planned cutting lines 56.

[0153] The second opening 37 of the organic insulating layer 31 is formed to surround the first opening 34 of the inorganic insulating layer 30 at a distance therefrom.

[0154] Next, refer to Figure 5K The portion of the first principal surface electrode 21 exposed from the first opening 34 and the second opening 37 forms a rough surface region 39. The rough surface region 39 is formed by zincate treatment (zinc substitution treatment) of the exposed portion of the first principal surface electrode 21.

[0155] Next, refer to Figure 5L , a Ni plating layer 41 is formed on the portion of the first main surface electrode 21 exposed from the first opening 34 and the second opening 37. The Ni plating layer 41 is formed by forming a Ni film from the first main surface electrode 21 using an electrolytic plating method or an electroless plating method (in this embodiment, an electroless plating method). Thus, the Ni plating layer 41 is formed, covering the first main surface electrode 21 in the first opening 34 and covering the inner peripheral edge 38 of the inorganic insulating layer 30 in the second opening 37. The specific structure of the Ni plating layer 41 is as described above, so its description is omitted.

[0156] Next, refer to Figure 5M An outer surface plating layer 42 is formed in the second opening 37 and on the outer surface of the Ni plating layer 41. The outer surface plating layer 42 includes at least one of a Pd plating layer 43, an Au plating layer 44, and an Ag plating layer 45. The outer surface plating layer 42 is formed by forming a film of any of Pd, Au, and Ag from the first main surface electrode 21 using electrolytic plating or electroless plating (electroless plating in this embodiment).

[0157] Next, refer to Figure 5NBy polishing the second wafer main surface 54, the SiC epitaxial wafer 50 is thinned to a desired thickness. The second wafer main surface 54 can also be polished using CMP (Chemical Mechanical Polishing). After the polishing step of the second wafer main surface 54, the second wafer main surface 54 can also be annealed. The annealing process can also be performed using laser irradiation. As a result, the second wafer main surface 54 (second main surface 4) becomes an ohmic surface.

[0158] Next, refer to Figure 5O , forming a second main surface electrode 46 on the second wafer main surface 54. The second main surface electrode 46 can also be formed by sputtering, vapor deposition, and / or electroplating. Subsequently, the SiC epitaxial wafer 50 is cut or cleaved along the dicing streets 25 to produce a plurality of semiconductor devices 1. Through the above steps, the semiconductor device 1 is manufactured.

[0159] As described above, the semiconductor device 1 includes a SiC chip 2, a first main surface electrode 21, an inorganic insulating layer 30, an organic insulating layer 31, and a Ni plating layer 41. The first main surface electrode 21 is formed on the SiC chip 2. The inorganic insulating layer 30 covers the first main surface electrode 21 and has a first opening 34 that exposes the first main surface electrode 21. The organic insulating layer 31 covers the inorganic insulating layer 30 and has a second opening 37 that surrounds the first opening 34 with a gap therebetween, and the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed in the area between the first opening 34 and the second opening 37. The Ni plating layer 41 is connected to the first main surface electrode 21 in the first opening 34 and covers the inner peripheral edge 38 of the inorganic insulating layer 30 in the second opening 37.

[0160] The inorganic insulating layer 30 has high adhesion to Ni, while the organic insulating layer 31 has low adhesion to Ni compared to the inorganic insulating layer 30. Therefore, for example, when the inorganic insulating layer 30 is not present or when the organic insulating layer 31 and the inorganic insulating layer 30 are formed on the same surface, a gap extending toward the first main surface electrode 21 is formed between the Ni plating layer 41 and the organic insulating layer 31. As a result, the connection between the Ni plating layer 41 and the first main surface electrode 21 is insufficient, and the reliability of the Ni plating layer 41 is reduced.

[0161] Therefore, in the semiconductor device 1, the organic insulating layer 31 is formed so as to expose the inner peripheral edge 38 of the inorganic insulating layer 30, which has a high adhesion to Ni, and the Ni plating layer 41 covers the inner peripheral edge 38 of the inorganic insulating layer 30. In this case, the Ni plating layer 41 forms a first connecting portion extending in the thickness direction of the inorganic insulating layer 30 and a second connecting portion extending in the width direction of the inorganic insulating layer 30 between the Ni plating layer 41 and the inorganic insulating layer 30.

[0162] This allows the gap formation region to be distanced from the first main surface electrode 21, while appropriately suppressing the formation of a gap extending toward the first main surface electrode 21. Furthermore, compared to a case where the inner peripheral edge 38 of the inorganic insulating layer 30 is absent, the gap formation region with the organic insulating layer 31 can be reduced. Consequently, the reliability of the Ni plating layer 41 can be improved.

[0163] In semiconductor device 1, second portion 41B of Ni plating layer 41 covers the area on the inorganic insulating layer 30 side relative to the middle portion of second inner wall 35 of organic insulating layer 31. In other words, second portion 41B of Ni plating layer 41 surrounds organic insulating layer 31 so that the concealed area of ​​second inner wall 35 (organic insulating layer 31) is smaller than the exposed area of ​​second inner wall 35 (organic insulating layer 31). This Ni plating layer 41 can appropriately reduce the area where gaps are formed.

[0164] The semiconductor device 1 further includes an outer surface plating layer 42 that covers the outer surface of the Ni plating layer 41. This structure can suppress the formation of a gap between the organic insulating layer 31 and the Ni plating layer 41, and can inhibit the intrusion of the plating solution into the gap. As a result, abnormal film formation of the outer surface plating layer 42 starting from the gap can be suppressed. As a result, poor connection of the Ni plating layer 41 caused by abnormal film formation of the outer surface plating layer 42 can be suppressed, and peeling (poor connection) of the outer surface plating layer 42 can be suppressed.

[0165] Specifically, the outer surface plating layer 42 can include at least one of the Pd plating layer 43, the Au plating layer 44, and the Ag plating layer 45. Therefore, it is possible to suppress poor connection of the Ni plating layer 41 caused by abnormal film formation of the Pd plating layer 43, the Au plating layer 44, and the Ag plating layer 45. At the same time, it is possible to suppress peeling (poor connection) of the Pd plating layer 43, the Au plating layer 44, and the Ag plating layer 45.

[0166] Figure 6 yes Figure 2 , which corresponds to FIG. 1 , is a cross-sectional view showing a semiconductor device 61 according to a second embodiment of the present invention together with the outer surface plating layer 42 of the first embodiment. Figure 7 yes Figure 6 Hereinafter, structures corresponding to those described for the semiconductor device 1 are denoted by the same reference numerals and their descriptions are omitted.

[0167] Reference Figure 6 as well as Figure 7 The organic insulating layer 31 exposes the inner periphery 38 of the inorganic insulating layer 30 in the region between the first opening 34 and the second opening 37. The width W of the inner periphery 38 of the inorganic insulating layer 30 is arbitrary, but preferably exceeds the thickness T2 of the inorganic insulating layer 30 (T2<W).

[0168] The ratio W / T2 of the width W of the inner peripheral edge 38 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than 10. The ratio W / T2 may be greater than 1 and less than 2, greater than 2 and less than 4, greater than 4 and less than 6, greater than 6 and less than 8, or greater than 8 and less than 10. The ratio W / T2 is preferably greater than 2 and less than 5. The width W may be greater than 0 μm and less than 10 μm. The width W may be greater than 0 μm and less than 2 μm, greater than 2 μm and less than 4 μm, greater than 4 μm and less than 6 μm, greater than 6 μm and less than 8 μm, or greater than 8 μm and less than 10 μm.

[0169] Ni plating 41 is formed on first main surface electrode 21 within pad opening 26. Ni plating 41 covers first main surface electrode 21 within first opening 34 and covers inner periphery 38 of inorganic insulating layer 30 within second opening 37. Ni plating 41 has an outer surface formed with a gap from the main surface of organic insulating layer 31 (insulating layer 24) toward first main surface electrode 21. Ni plating 41 covers inner periphery 38 of inorganic insulating layer 30 within second opening 37, with a gap from organic insulating layer 31.

[0170] Specifically, the Ni plating layer 41 includes a first portion 41A that covers the first principal surface electrode 21 and a second portion 41B that covers the inner peripheral edge 38 of the inorganic insulating layer 30. The first portion 41A of the Ni plating layer 41 fills the roughened region 39 within the first opening 34 and covers the first principal surface electrode 21. The first portion 41A covers the entire first inner wall 32 of the inorganic insulating layer 30 within the first opening 34 and protrudes from the opening end of the first opening 34 toward the opening end of the second opening 37. The first portion 41A is connected to the first inner wall 32 of the inorganic insulating layer 30 and has a first connection portion that extends in the thickness direction of the inorganic insulating layer 30.

[0171] Second portion 41B of Ni plating layer 41 is drawn from first portion 41A toward organic insulating layer 31 in second opening 37. Second portion 41B is formed in an arc shape starting from the opening end of first opening 34 toward second inner wall 35 of organic insulating layer 31.

[0172] The second portion 41B covers the inner peripheral edge 38 of the inorganic insulating layer 30 within the second opening 37. In this manner, the second portion 41B partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 from the second inner wall 35 of the organic insulating layer 31 toward the first inner wall 32 of the inorganic insulating layer 30 with a gap in the second opening 37, so that a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed.

[0173] Thus, the Ni plating layer 41 exposes a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire area of ​​the second inner wall 35 of the organic insulating layer 31. The second portion 41B faces the first main surface electrode 21 across the inner peripheral edge 38 of the inorganic insulating layer 30. The second portion 41B is connected to the main surface of the inorganic insulating layer 30 and has a second connection portion extending in the width direction of the inorganic insulating layer 30.

[0174] The Ni plating layer 41 has a thickness T4 that exceeds the thickness T2 of the inorganic insulating layer 30 (T2 < T4). Thickness T4 is less than thickness T3 of the organic insulating layer 31 (T4 < T3). Thickness T4 is less than the value obtained by adding the width W of the inner peripheral edge 38 to the thickness T2 of the inorganic insulating layer 30 (T2 + W) (T4 < T2 + W). This is a condition for the Ni plating layer 41 to expose the second inner wall 35 of the organic insulating layer 31. Thickness T4 is defined by the thickness of the Ni plating layer 41 relative to the main surface of the first main surface electrode 21.

[0175] The ratio T4 / T2 of the thickness T4 of the Ni plating layer 41 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than 5. The ratio T4 / T2 may be greater than 1 and less than 2, greater than 2 and less than 3, greater than 3 and less than 4, or greater than 4 and less than 5. The thickness T4 may be greater than 0.1 μm and less than 10 μm. The thickness T4 may be greater than 0.1 μm and less than 1 μm, greater than 1 μm and less than 2 μm, greater than 2 μm and less than 4 μm, greater than 4 μm and less than 6 μm, greater than 6 μm and less than 8 μm, or greater than 8 μm and less than 10 μm.

[0176] The outer surface plating layer 42 covers the outer surface of the Ni plating layer 41 within the second opening 37. The outer surface plating layer 42 has a thickness T5 that is less than the thickness T4 of the Ni plating layer 41 (T5 < T4). In this embodiment, the outer surface plating layer 42 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 within the second opening 37, extending from the second inner wall 35 of the organic insulating layer 31 toward the first inner wall 32 of the inorganic insulating layer 30, with a gap therebetween.

[0177] The outer surface plating layer 42 has a terminal surface 42A for external connection via a conductive bonding material (e.g., solder). The terminal surface 42A is located on the Ni plating layer 41 side relative to the main surface (opening end of the second opening 37) of the organic insulating layer 31. Thus, the outer surface plating layer 42 exposes a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire second inner wall 35 of the organic insulating layer 31 within the second opening 37.

[0178] Specifically, the outer surface plating 42 has a laminated structure including a Pd plating 43 and an Au plating 44 stacked in sequence from the Ni plating 41 side. The Pd plating 43 is formed in a film-like shape along the outer surface of the Ni plating 41. The Pd plating 43 covers the Ni plating 41 with a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30 side. The Pd plating 43 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 from the second inner wall 35 of the organic insulating layer 31 toward the first inner wall 32 of the inorganic insulating layer 30 within the second opening 37, with a gap, so that a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. As a result, the Pd plating 43 exposes a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire area of ​​the second inner wall 35 of the organic insulating layer 31 within the second opening 37.

[0179] The Pd plating layer 43 has a thickness smaller than the thickness T4 of the Ni plating layer 41. The thickness of the Pd plating layer 43 may be 0.01 μm to 1 μm. The thickness of the Pd plating layer 43 may be 0.01 μm to 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.4 μm, 0.4 μm to 0.6 μm, 0.6 μm to 0.8 μm, or 0.8 μm to 1 μm.

[0180] The Au plating layer 44 is formed in a film-like shape along the outer surface of the Pd plating layer 43. The Au plating layer 44 covers the Pd plating layer 43 with a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. The Au plating 44 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 from the second inner wall 35 of the organic insulating layer 31 toward the first inner wall 32 of the inorganic insulating layer 30 within the second opening 37, so that a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. As a result, the Au plating 44 exposes a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire area of ​​the second inner wall 35 of the organic insulating layer 31 within the second opening 37.

[0181] The Au plating layer 44 has a thickness smaller than the thickness T4 of the Ni plating layer 41. The thickness of the Au plating layer 44 may be 0.01 μm to 1 μm. The thickness of the Au plating layer 44 may be 0.01 μm to 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.4 μm, 0.4 μm to 0.6 μm, 0.6 μm to 0.8 μm, or 0.8 μm to 1 μm.

[0182] In this embodiment, an example is described in which the outer surface plating layer 42 is formed so as to expose the entire area of ​​the second inner wall 35 of the organic insulating layer 31. However, the outer surface plating layer 42 may be formed to cover a portion of the second inner wall 35 of the organic insulating layer 31. In this case, at least one of the Pd plating layer 43 and the Au plating layer 44 may also cover a portion of the second inner wall 35 of the organic insulating layer 31. The outer surface plating layer 42 may be formed to cover a portion of the second inner wall 35 of the organic insulating layer 31. Figures 8A to 8D Various ways shown.

[0183] Figure 8A yes Figure 7 , which is an enlarged view showing the outer surface plating layer 42 of the second embodiment. Hereinafter, the portions of the outer surface plating layer 42 that are different from those of the first embodiment will be described.

[0184] Reference Figure 8A In this embodiment, the outer surface plating layer 42 has a single-layer structure composed of an Au plating layer 44. The Au plating layer 44 is formed in a film-like shape along the outer surface of the Ni plating layer 41. The Au plating layer 44 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 from the second inner wall 35 of the organic insulating layer 31 toward the first inner wall 32 of the inorganic insulating layer 30 within the second opening 37, with a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 exposed.

[0185] The Au plating layer 44 covers the Ni plating layer 41 with a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. Thus, the Au plating layer 44 exposes a portion of the inner periphery 38 of the inorganic insulating layer 30 and the entire second inner wall 35 of the organic insulating layer 31 within the second opening 37. The Au plating layer 44 may also cover a portion of the second inner wall 35 of the organic insulating layer 31.

[0186] Figure 8B yes Figure 7 , which is an enlarged view showing the outer surface plating layer 42 of the third embodiment. Hereinafter, the parts of the outer surface plating layer 42 that are different from those of the first embodiment will be described.

[0187] Reference Figure 8B In this embodiment, the outer surface plating layer 42 has a single-layer structure composed of a Pd plating layer 43. The Pd plating layer 43 is formed in a film-like shape along the outer surface of the Ni plating layer 41. The Pd plating layer 43 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 from the second inner wall 35 of the organic insulating layer 31 toward the first inner wall 32 of the inorganic insulating layer 30 within the second opening 37, with a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 exposed.

[0188] The Pd plating layer 43 covers the Ni plating layer 41 with a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. Thus, the Pd plating layer 43 exposes a portion of the inner periphery 38 of the inorganic insulating layer 30 and the entire second inner wall 35 of the organic insulating layer 31 within the second opening 37. The Pd plating layer 43 may also cover a portion of the second inner wall 35 of the organic insulating layer 31.

[0189] Figure 8C and Figure 7 , which is an enlarged view showing the outer surface plating layer 42 of the fourth embodiment. Hereinafter, the parts of the outer surface plating layer 42 that are different from those of the first embodiment will be described.

[0190] Reference Figure 8C In this embodiment, the outer surface plating layer 42 has a single-layer structure composed of an Ag plating layer 45. The Ag plating layer 45 is formed in a film-like shape along the outer surface of the Ni plating layer 41. The Ag plating layer 45 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 from the second inner wall 35 of the organic insulating layer 31 toward the first inner wall 32 of the inorganic insulating layer 30 within the second opening 37, with a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 exposed.

[0191] The Ag plating layer 45 covers the Ni plating layer 41 with a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. Thus, the Ag plating layer 45 exposes a portion of the inner periphery 38 of the inorganic insulating layer 30 and the entire second inner wall 35 of the organic insulating layer 31 within the second opening 37. The Ag plating layer 45 may also cover a portion of the second inner wall 35 of the organic insulating layer 31.

[0192] The Ag plating layer 45 has a thickness smaller than the thickness T4 of the Ni plating layer 41. The thickness of the Ag plating layer 45 may be 0.01 μm to 1 μm. The thickness of the Ag plating layer 45 may be 0.01 μm to 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.4 μm, 0.4 μm to 0.6 μm, 0.6 μm to 0.8 μm, or 0.8 μm to 1 μm.

[0193] Figure 8D yes Figure 7 , which is an enlarged view showing the outer surface plating layer 42 of the fifth embodiment. Hereinafter, the portions of the outer surface plating layer 42 that are different from those of the first embodiment will be described.

[0194] Reference Figure 8D The outer surface plating layer 42 has a stacked structure including a Pd plating layer 43 , an Au plating layer 44 , and an Ag plating layer 45 stacked in this order from the Ni plating layer 41 side.

[0195] The Pd plating layer 43 is formed in a film-like shape along the outer surface of the Ni plating layer 41. The Pd plating layer 43 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30, leaving a gap from the second inner wall 35 of the organic insulating layer 31 toward the first inner wall 32 of the inorganic insulating layer 30 within the second opening 37, so that a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. The Pd plating 43 covers the Ni plating 41, leaving a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. Thus, the Pd plating 43 exposes a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire second inner wall 35 of the organic insulating layer 31 within the second opening 37.

[0196] The Au plating layer 44 is formed in a film-like shape along the outer surface of the Pd plating layer 43. The Au plating layer 44 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30, leaving a gap from the second inner wall 35 of the organic insulating layer 31 toward the first inner wall 32 of the inorganic insulating layer 30 within the second opening 37, so that a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. The Au plating layer 44 covers the Pd plating layer 43, leaving a gap from the opening end of the second opening 37 toward the inorganic insulating layer 30. Thus, the Au plating layer 44 exposes a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire second inner wall 35 of the organic insulating layer 31 within the second opening 37.

[0197] The Ag plating layer 45 is formed in a film-like shape along the outer surface of the Au plating layer 44. The Ag plating layer 45 partially covers the inner peripheral edge 38 of the inorganic insulating layer 30 within the second opening 37, extending from the second inner wall 35 of the organic insulating layer 31 toward the first inner wall 32 of the inorganic insulating layer 30, with a gap therebetween. The Ag plating 45 covers the Au plating 44 from the opening end of the second opening 37 toward the inorganic insulating layer 30, with a gap therebetween. Thus, the Ag plating 45 exposes a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 and the entire second inner wall 35 of the organic insulating layer 31 within the second opening 37. At least one of the Pd plating layer 43, the Au plating layer 44, and the Ag plating 45 may also cover a portion of the second inner wall 35 of the organic insulating layer 31.

[0198] As described above, semiconductor device 61 can also achieve the same effects as those described for semiconductor device 1. In particular, Ni plating layer 41 of semiconductor device 61 covers inner peripheral edge 38 of inorganic insulating layer 30 within second opening 37, leaving a gap from organic insulating layer 31. This prevents the formation of an undesirable gap between organic insulating layer 31 and Ni plating layer 41. Consequently, the reliability of Ni plating layer 41 can be reliably improved.

[0199] Furthermore, the semiconductor device 61 includes an outer surface plating layer 42 that covers the outer surface of the Ni plating layer 41. With this structure, no gap is formed between the organic insulating layer 31 and the Ni plating layer 41, so the outer surface plating layer 42 can be properly formed along the outer surface of the Ni plating layer 41. Therefore, while properly suppressing poor connection of the Ni plating layer 41 due to abnormal film formation of the outer surface plating layer 42, it is also possible to properly suppress peeling (poor connection) of the outer surface plating layer 42.

[0200] Specifically, the outer surface plating layer 42 can include at least one of the Pd plating layer 43, the Au plating layer 44, and the Ag plating layer 45. Therefore, it is possible to suppress poor connection of the Ni plating layer 41 caused by abnormal film formation of the Pd plating layer 43, the Au plating layer 44, and the Ag plating layer 45. At the same time, it is possible to suppress peeling (poor connection) of the Pd plating layer 43, the Au plating layer 44, and the Ag plating layer 45.

[0201] Figure 9 It is a plan view showing a semiconductor device 101 according to a third embodiment. Figure 10 Yes Figure 9 Magnified view of area X. Figure 11 It is along Figure 10 A cross-sectional view taken along line XI-XI is shown. Figure 12 It is along Figure 9 A cross-sectional view taken along line XII-XII is shown. Figure 13 yes Figure 12 An enlarged view of region XIII is shown. Figure 14 yes Figure 12 Hereinafter, structures corresponding to those described for the semiconductor device 1 are denoted by the same reference numerals and their descriptions are omitted.

[0202] Reference Figures 9 to 14 The semiconductor device 101 is a SiC semiconductor device in which a MISFET (Metal Insulator Semiconductor Field Effect Transistor), which is an example of a functional device, is formed in the source region 8 instead of an SBD.

[0203] The semiconductor device 101 includes a SiC chip 2, a main surface insulating layer 12, a first main surface electrode 21, an insulating layer 24, a pad electrode 40, and a second main surface electrode 46. Figure 9 In FIG, the insulating layer 24 is shown by hatching. The first main surface 3 and the second main surface 4 of the SiC chip 2 are formed to have a quadrilateral shape (a rectangular shape in this embodiment) in a plan view.

[0204] The first side surface 5A and the second side surface 5B extend along the first direction X and oppose each other in a second direction Y intersecting the first direction X. The first side surface 5A and the second side surface 5B form short sides of the SiC chip 2. The third side surface 5C and the fourth side surface 5D extend along the second direction Y and oppose each other in the first direction X. The third side surface 5C and the fourth side surface 5D form long sides of the SiC chip 2.

[0205] The length of the first side surface 5A (second side surface 5B) may be greater than or equal to 0.1 mm and less than or equal to 8 mm. The length of the first side surface 5A (second side surface 5B) is preferably greater than or equal to 0.1 mm and less than or equal to 2.5 mm. The length of the third side surface 5C (fourth side surface 5D) may be greater than or equal to 0.2 mm and less than or equal to 16 mm. The length of the third side surface 5C (fourth side surface 5D) is preferably greater than or equal to 0.5 mm and less than or equal to 5 mm.

[0206] As in the first embodiment, the SiC chip 2 has a stacked structure including a SiC substrate 6 and a SiC epitaxial layer 7. The SiC substrate 6 is formed as a drain region of the MISFET, and the SiC epitaxial layer 7 is formed as a drift region of the MISFET.

[0207] In this embodiment, the SiC epitaxial layer 7 has different n-type impurity concentrations along the normal direction Z. Specifically, the SiC epitaxial layer 7 includes a high-concentration region 102 having a high n-type impurity concentration and a low-concentration region 103 having a lower n-type impurity concentration than the high-concentration region 102 .

[0208] High-concentration region 102 is formed in a region on the side of first main surface 3. Low-concentration region 103 is formed in a region on the side of second main surface 4 relative to high-concentration region 102. The thickness of high-concentration region 102 is smaller than the thickness of low-concentration region 103. The thickness of high-concentration region 102 is less than half the total thickness of SiC epitaxial layer 7.

[0209] The n-type impurity concentration of the high-concentration region 102 may also be 1.0×10 16 cm -3 Above and 1.0×10 18 cm -3 The n-type impurity concentration of the low-concentration region 103 may be 1.0×10 15 cm -3 Above and 1.0×10 16 cm -3 Of course, the n-type impurity concentration of the SiC epitaxial layer 7 can also be 1.0×10 15 cm -3 Above and 1.0×10 18 cm -3The following range has a concentration gradient in which the n-type impurity concentration gradually decreases from the SiC substrate 6 toward the first main surface 3 .

[0210] Active region 8 is formed in the center of SiC chip 2, spaced inward from side surfaces 5A to 5D in plan view. Active region 8 is formed in a rectangular shape with four sides parallel to side surfaces 5A to 5D in plan view. Meanwhile, outer region 9 is formed in a rectangular ring shape surrounding active region 8 in plan view.

[0211] The semiconductor device 101 includes a plurality of trench gate structures 104 formed on the first main surface 3 in the active region 8. The plurality of trench gate structures 104 are each formed in a stripe shape extending in the first direction X and are formed at intervals in the second direction Y. The plurality of trench gate structures 104 are formed in a stripe shape extending in the first direction X when viewed from above.

[0212] In this embodiment, the plurality of trench gate structures 104 extend in a stripe shape from the peripheral portion on one side (the third side surface 5C side) toward the peripheral portion on the other side (the fourth side surface 5D side) of the active region 8. The plurality of trench gate structures 104 traverse the intermediate portion between the peripheral portion on one side and the peripheral portion on the other side of the active region 8.

[0213] The length of each trench gate structure 104 may also be greater than 1 mm and less than 10 mm. The length of each trench gate structure 104 may also be greater than 1 mm and less than 2 mm, greater than 2 mm and less than 4 mm, greater than 4 mm and less than 6 mm, greater than 6 mm and less than 8 mm, or greater than 8 mm and less than 10 mm. The length of each trench gate structure 104 is preferably greater than 2 mm and less than 6 mm. The total extension per unit area of ​​a trench gate structure 104 may also be 0.5 μm / μm. 2 Above and 0.75μm / μm 2 the following.

[0214] Each trench gate structure 104 includes a gate trench 105, a gate insulating layer 106, and a gate electrode 107. Figure 10 In FIG, the gate insulating layer 106 and the gate electrode 107 are shown by hatching.

[0215] The gate trench 105 is formed in the SiC epitaxial layer 7. The gate trench 105 includes sidewalls and a bottom wall. The sidewalls forming the long sides of the gate trench 105 are formed by the a-plane of the SiC single crystal. The sidewalls forming the short sides of the gate trench 105 are formed by the m-plane of the SiC single crystal.

[0216] The sidewalls of the gate trench 105 may extend along the normal direction Z. In the SiC chip 2, the angle formed by the sidewalls of the gate trench 105 with respect to the first main surface 3 may be greater than or equal to 90° and less than or equal to 95° (e.g., greater than or equal to 91° and less than or equal to 93°). The sidewalls of the gate trench 105 may be formed substantially perpendicular to the first main surface 3. The gate trench 105 may also be formed into a tapered shape with the opening width narrowing from the first main surface 3 toward the bottom wall.

[0217] The bottom wall of the gate trench 105 is located in the high-concentration region 102. The bottom wall of the gate trench 105 faces the c-plane of the SiC single crystal. The bottom wall of the gate trench 105 has an off angle relative to the c-plane of the SiC single crystal, tilted toward the a-axis. The bottom wall of the gate trench 105 can also be formed parallel to the first main surface 3. The bottom wall of the gate trench 105 can also be formed in a curved shape toward the second main surface 4.

[0218] The gate trench 105 has a first depth D1. The first depth D1 may be greater than or equal to 0.5 μm and less than or equal to 3 μm. The first depth D1 may also be greater than or equal to 0.5 μm and less than or equal to 1 μm, greater than or equal to 1 μm and less than or equal to 1.5 μm, greater than or equal to 1.5 μm and less than or equal to 2 μm, greater than or equal to 2 μm and less than or equal to 2.5 μm, or greater than or equal to 2.5 μm and less than or equal to 3 μm.

[0219] The width of the gate trench 105 along the second direction Y may be 0.1 μm to 2 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, or 1.5 μm to 2 μm.

[0220] The opening edge of the gate trench 105 includes an inclined portion that slopes downward from the first main surface 3 toward the interior of the gate trench 105. The opening edge of the gate trench 105 is the portion connecting the first main surface 3 and the sidewall of the gate trench 105. The inclined portion of the gate trench 105 is formed into a curved shape that is recessed toward the SiC chip 2. The inclined portion of the gate trench 105 may also be formed into a curved shape toward the gate trench 105. The inclined portion of the gate trench 105 mitigates electric field concentration relative to the opening edge of the gate trench 105.

[0221] The gate insulating layer 106 includes at least one of silicon oxide, silicon nitride, aluminum oxide, zirconium oxide, and tantalum oxide. The gate insulating layer 106 may have a stacked structure in which a silicon oxide layer and a silicon nitride layer are stacked in any order. The gate insulating layer 106 may also have a single-layer structure consisting of a silicon oxide layer or a silicon nitride layer. In this embodiment, the gate insulating layer 106 has a single-layer structure consisting of a silicon oxide layer.

[0222] The gate insulating layer 106 is formed in a film-like shape along the inner wall of the gate trench 105, defining a recessed space within the gate trench 105. The gate insulating layer 106 includes a first region 108, a second region 109, and a third region 110. The first region 108 is formed along the sidewall of the gate trench 105. The second region 109 is formed along the bottom wall of the gate trench 105. The third region 110 partially covers the first main surface 3 via the opening edge of the gate trench 105.

[0223] The thickness of the first region 108 may be greater than or equal to 0.01 μm and less than or equal to 0.2 μm. The thickness of the second region 109 may be greater than or equal to 0.05 μm and less than or equal to 0.5 μm. The thickness of the second region 109 may also exceed the thickness of the first region 108. The thickness of the third region 110 may also be greater than or equal to 0.05 μm and less than or equal to 0.5 μm. The thickness of the third region 110 may also exceed the thickness of the first region 108.

[0224] The gate insulating layer 106 includes a bulging portion 111 that bulges out toward the inside of the gate trench 105 at the edge of the opening. The bulging portion 111 is formed at the connection between the first region 108 and the third region 110 of the gate insulating layer 106. The bulging portion 111 is formed in a curved shape toward the inside of the gate trench 105. The bulging portion 111 narrows the opening of the gate trench 105 at the edge of the opening. The gate insulating layer 106 may be formed without the bulging portion 111. Alternatively, the gate insulating layer 106 may be formed to have a uniform thickness.

[0225] The gate electrode 107 is embedded in the gate trench 105 via the gate insulating layer 106. Specifically, the gate electrode 107 is embedded in the recessed space defined by the gate insulating layer 106 within the gate trench 105. The gate electrode 107 has an electrode surface exposed from the opening of the gate trench 105. The electrode surface of the gate electrode 107 is formed in a curved shape that is recessed toward the bottom wall of the gate trench 105. The electrode surface of the gate electrode 107 is narrowed by the bulge 111 of the gate insulating layer 106.

[0226] The gate electrode 107 is made of a conductive material other than a metal material. The gate electrode 107 is preferably made of conductive polysilicon. In this embodiment, the gate electrode 107 includes p-type polysilicon to which p-type impurities are added.

[0227] The p-type impurity concentration of the gate electrode 107 may also be 1.0×10 18 cm -3 Above and 1.0×10 22 cm -3The p-type impurity of the gate electrode 107 may include at least one of boron, aluminum, indium, and gallium. The sheet resistance of the gate electrode 107 may be greater than or equal to 10 Ω / □ and less than or equal to 500 Ω / □ (approximately 200 Ω / □ in this embodiment). The thickness of the gate electrode 107 may be greater than or equal to 0.5 μm and less than or equal to 3 μm.

[0228] The semiconductor device 101 includes a first low resistance layer 112 covering the gate electrode 107. The first low resistance layer 112 covers the gate electrode 107 in the gate trench 105. The first low resistance layer 112 forms a portion of the trench gate structure 104.

[0229] The first low-resistance layer 112 includes a conductive material having a sheet resistance lower than that of the gate electrode 107. The sheet resistance of the first low-resistance layer 112 may be greater than or equal to 0.01 Ω / □ and less than or equal to 10 Ω / □. The thickness of the first low-resistance layer 112 may also be greater than or equal to 0.01 μm and less than or equal to 3 μm. The thickness of the first low-resistance layer 112 is preferably less than the thickness of the gate electrode 107.

[0230] Specifically, the first low-resistance layer 112 includes a polycrystalline layer. The polycrystalline layer is formed by silicideing the surface portion of the gate electrode 107 using a metal material. In other words, the electrode surface of the gate electrode 107 is formed by the first low-resistance layer 112. Specifically, the polycrystalline layer is composed of a p-type polycrystalline layer containing p-type impurities added to the gate electrode 107. The polycrystalline layer preferably has a specific resistance of 10 μΩ·cm or more and 110 μΩ·cm or less.

[0231] The sheet resistance within the gate trench 105, where the gate electrode 107 and the first low-resistance layer 112 are embedded, is lower than the sheet resistance of the gate electrode 107 alone. The sheet resistance within the gate trench 105 is preferably lower than the sheet resistance of n-type polysilicon doped with n-type impurities. The sheet resistance within the gate trench 105 is similar to the sheet resistance of the first low-resistance layer 112. The sheet resistance within the gate trench 105 may be greater than 0.01 Ω / □ and less than 10 Ω / □. The sheet resistance within the gate trench 105 is preferably less than 10 Ω / □.

[0232] The first low-resistance layer 112 may also include at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, and WSi2. Among these, NiSi, CoSi2, and TiSi2 are particularly suitable as the polycrystalline layer forming the first low-resistance layer 112 because they have relatively low specific resistance values ​​and temperature dependence. The first low-resistance layer 112 is preferably composed of CoSi2, which has the property of being less diffused into other regions.

[0233] The first low-resistance layer 112 includes a contact portion with the gate insulating layer 106. Specifically, the contact portion of the first low-resistance layer 112 contacts the third region 110 (bulged portion 111) of the gate insulating layer 106. This prevents the current path between the first low-resistance layer 112 and the SiC epitaxial layer 7. In particular, the design in which the contact portion of the first low-resistance layer 112 contacts a relatively thick corner portion of the gate insulating layer 106 is effective in reducing the risk of current paths.

[0234] By embedding p-type polysilicon, which has a different work function than n-type polysilicon, in the gate trench 105, the gate threshold voltage Vth can be increased by approximately 1V. However, p-type polysilicon has a sheet resistance several dozen times (approximately 20 times) higher than that of n-type polysilicon. Therefore, when p-type polysilicon is used as the material for the gate electrode 107, the parasitic resistance (hereinafter referred to as "gate resistance") within the gate trench 105 increases, leading to increased energy loss.

[0235] Therefore, in semiconductor device 101 , first low-resistance layer 112 (p-type polycrystalline) is formed on gate electrode 107 (p-type polysilicon). First low-resistance layer 112 allows an increase in gate threshold voltage Vth and reduces sheet resistance within gate trench 105 .

[0236] For example, a structure including the first low-resistance layer 112 can reduce sheet resistance by less than 1 percent compared to a structure without the first low-resistance layer 112. A structure including the first low-resistance layer 112 can reduce sheet resistance by less than one-fifth compared to a gate electrode 107 made of n-type polysilicon.

[0237] This reduces gate resistance, allowing current to spread efficiently along the trench gate structure 104. Specifically, the first low-resistance layer 112 can be formed as a current diffusion layer that diffuses current within the gate trench 105. In particular, in the case of a gate trench 105 having a length on the order of millimeters (a length of 1 mm or greater), current transfer requires time, but the first low-resistance layer 112 can appropriately suppress switching delays.

[0238] The structure including the first low-resistance layer 112 can improve the gate threshold voltage Vth without increasing the p-type impurity concentration in the SiC epitaxial layer 7. Thus, the gate threshold voltage Vth can be appropriately increased while suppressing an increase in channel resistance.

[0239] The semiconductor device 101 includes a plurality of trench source structures 121 formed in regions between adjacent trench gate structures 104. The plurality of trench source structures 121 are formed at intervals in the second direction Y so as to sandwich one trench gate structure 104 therebetween.

[0240] Each of the plurality of trench source structures 121 is formed in a stripe shape extending in the first direction X. Each of the plurality of trench source structures 121 is formed in a stripe shape extending in the first direction X in a plan view.

[0241] The pitch PS between the central portions of adjacent trench source structures 121 in the second direction Y may be 1 μm to 5 μm. The pitch PS may be 1 μm to 2 μm, 2 μm to 3 μm, 3 μm to 4 μm, or 4 μm to 5 μm. The pitch PS is preferably 1.5 μm to 3 μm.

[0242] Each trench source structure 121 includes a source trench 122, a source insulating layer 123 and a source electrode 124. Figure 10 , the source electrode 124 is shown by hatching.

[0243] Source trench 122 is formed in SiC epitaxial layer 7. Source trench 122 includes sidewalls and a bottom wall. The sidewalls forming the long sides of source trench 122 are formed by the a-plane of SiC single crystal, while the sidewalls forming the short sides of source trench 122 are formed by the m-plane of SiC single crystal.

[0244] The bottom wall of the source trench 122 is located in the high-concentration region 102. The bottom wall of the source trench 122 is located in the region on the second main surface 4 side relative to the bottom wall of the gate trench 105. The bottom wall of the source trench 122 is located in the region between the bottom wall of the gate trench 105 and the low-concentration region 103 in the normal direction Z.

[0245] The bottom wall of source trench 122 faces the c-plane of the SiC single crystal. The bottom wall of source trench 122 has an off angle relative to the c-plane of the SiC single crystal, tilted toward the a-axis. The bottom wall of source trench 122 may be formed parallel to first principal surface 3. The bottom wall of source trench 122 may also be formed in a curved shape toward second principal surface 4.

[0246] The source trench 122 has a second depth D2 exceeding the first depth D1 of the gate trench 105. The ratio DS / DG of the second depth D2 to the first depth D1 may be 1.5 or greater when the source trench 122 is located within the high-concentration region 102. The ratio DS / DG is preferably 2 or greater.

[0247] The second depth D2 may be greater than or equal to 0.5 μm and less than or equal to 10 μm. The second depth D2 may be greater than or equal to 0.5 μm and less than or equal to 1 μm, greater than or equal to 1 μm and less than or equal to 2 μm, greater than or equal to 2 μm and less than or equal to 4 μm, greater than or equal to 4 μm and less than or equal to 6 μm, greater than or equal to 6 μm and less than or equal to 8 μm, or greater than or equal to 8 μm and less than or equal to 10 μm. The source trench 122 may also be formed to have a second depth D2 that is substantially equal to the first depth D1.

[0248] The source trench 122 includes a first trench portion 125 and a second trench portion 126. The first trench portion 125 is formed on the opening side of the source trench 122. The first trench portion 125 has a first width W1 in the second direction Y. The first trench portion 125 may be formed in a tapered shape in which the first width W1 gradually narrows from the first main surface 3 toward the bottom wall.

[0249] The first trench portion 125 is preferably formed in a region on the first main surface 3 side relative to the bottom wall of the gate trench 105. That is, the depth of the first trench portion 125 is preferably less than the first depth D1 of the gate trench 105. The first trench portion 125 may be formed to extend across the bottom wall of the gate trench 105. That is, the depth of the first trench portion 125 may exceed the first depth D1 of the gate trench 105.

[0250] The depth of the first groove portion 125 may be 0.1 μm to 2 μm, 0.5 μm to 1 μm, 1 μm to 1.5 μm, or 1.5 μm to 2 μm.

[0251] The first width W1 of the first trench portion 125 may be greater than or less than the width of the gate trench 105. The first width W1 preferably exceeds the width of the gate trench 105. The first width W1 may be greater than or equal to 0.1 μm and less than or equal to 2 μm. The first width W1 may also be greater than or equal to 0.1 μm and less than or equal to 0.5 μm, greater than or equal to 0.5 μm and less than or equal to 1 μm, greater than or equal to 1 μm and less than or equal to 1.5 μm, or greater than or equal to 1.5 μm and less than or equal to 2 μm.

[0252] The second trench portion 126 is formed on the bottom wall side of the source trench 122. The second trench portion 126 is formed in the region between the first trench portion 125 and the bottom of the SiC epitaxial layer 7 in the normal direction Z, and crosses the bottom wall of the gate trench 105. In the normal direction Z, the depth of the second trench portion 126 relative to the first trench portion 125 preferably exceeds the first depth D1 of the gate trench 105.

[0253] The second trench portion 126 has a second width W2 smaller than the first width W1 in the second direction Y. The second width W2 may be larger than or smaller than the width of the gate trench 105 while being smaller than the first width W1 .

[0254] The second width W2 may be greater than or equal to 0.1 μm and less than 2 μm. The second width W2 may be greater than or equal to 0.1 μm and less than 2 μm. The second width W2 may be greater than or equal to 0.1 μm and less than 0.5 μm, greater than or equal to 0.5 μm and less than 1 μm, greater than or equal to 1 μm and less than 1.5 μm, or greater than or equal to 1.5 μm and less than 2 μm. Of course, the second groove portion 126 may also be formed to have a second width W2 that is substantially equal to the first width W1.

[0255] The overall opening width of the source trench 122 is preferably approximately the same as the opening width of the gate trench 105. The opening width of the source trench 122 being approximately the same as the opening width of the gate trench 105 means that the opening width of the source trench 122 is within a range of ±20% of the opening width of the gate trench 105.

[0256] The sidewalls of the second groove portion 126 may extend along the normal direction Z. In the SiC chip 2, the angle formed by the sidewalls of the second groove portion 126 with respect to the first main surface 3 may be greater than or equal to 90° and less than or equal to 95° (e.g., greater than or equal to 91° and less than or equal to 93°). The sidewalls of the second groove portion 126 may be formed substantially perpendicular to the first main surface 3. The second groove portion 126 may be formed into a tapered shape in which the second width W2 gradually narrows from the first groove portion 125 toward the bottom wall.

[0257] Source insulating layer 123 includes at least one of silicon oxide, silicon nitride, aluminum oxide, zirconium oxide, or tantalum oxide. Source insulating layer 123 may also have a stacked structure comprising silicon oxide layers and silicon nitride layers stacked in any order. Source insulating layer 123 may also have a single-layer structure consisting of a silicon oxide layer or a silicon nitride layer. In this embodiment, source insulating layer 123 has a single-layer structure consisting of a silicon oxide layer.

[0258] The source insulating layer 123 is formed in a film shape along the inner wall of the source trench 122 to define a recessed space in the source trench 122. Specifically, the source insulating layer 123 is formed in a film shape along the inner wall of the source trench 122 to expose the first trench portion 125 and cover the second trench portion 126.

[0259] Thus, the source insulating layer 123 defines a recessed space within the second trench portion 126. The source insulating layer 123 has a sidewall window portion 127 that exposes the first trench portion 125.

[0260] Source insulating layer 123 includes a first region 128 and a second region 129. First region 128 is formed along the sidewalls of source trench 122. Second region 129 is formed along the bottom wall of source trench 122. The thickness of first region 128 is smaller than the thickness of second region 129. The thickness of first region 128 may be greater than 0.01 μm and less than 0.2 μm. The thickness of second region 129 may be greater than 0.05 μm and less than 0.5 μm.

[0261] The thickness of the first region 128 may be substantially equal to the thickness of the first region 128 of the gate insulating layer 106. The thickness of the second region 129 may be substantially equal to the thickness of the second region 129 of the gate insulating layer 106. The source insulating layer 123 may be formed to have a uniform thickness.

[0262] The source electrode 124 is embedded in the source trench 122 via the source insulating layer 123 . Specifically, the source electrode 124 is embedded in the first trench portion 125 and the second trench portion 126 via the source insulating layer 123 .

[0263] Source electrode 124 is embedded in the recessed space defined by second trench portion 126 on the bottom wall side of source trench 122. Source electrode 124 has sidewall contact portion 130 on the opening side of source trench 122 that contacts the sidewall of first trench portion 125 exposed from sidewall window portion 127.

[0264] Source electrode 124 has an electrode surface exposed from the opening of source trench 122. The electrode surface of source electrode 124 is formed in a curved shape recessed toward the bottom wall of source trench 122. The electrode surface of source electrode 124 may be formed parallel to first main surface 3.

[0265] The thickness of the source electrode 124 in the normal direction Z may be greater than or equal to 0.5 μm and less than or equal to 10 μm. The thickness of the source electrode 124 may be greater than or equal to 0.5 μm and less than or equal to 1 μm, greater than or equal to 1 μm and less than or equal to 2 μm, greater than or equal to 2 μm and less than or equal to 4 μm, greater than or equal to 4 μm and less than or equal to 6 μm, greater than or equal to 6 μm and less than or equal to 8 μm, or greater than or equal to 8 μm and less than or equal to 10 μm.

[0266] The source electrode 124 is made of a conductive material other than a metal material. The source electrode 124 is preferably made of conductive polysilicon. In this embodiment, the source electrode 124 includes p-type polysilicon to which p-type impurities are added.

[0267] The p-type impurity concentration of the source electrode 124 may also be 1.0×10 18 cm -3 Above and 1.0×10 22 cm -3The p-type impurity concentration of the source electrode 124 is preferably equal to the p-type impurity concentration of the gate electrode 107. The p-type impurity of the source electrode 124 may include at least one of boron, aluminum, indium, and gallium.

[0268] Semiconductor device 101 includes a second low-resistance layer 131 that covers source electrode 124. Second low-resistance layer 131 covers source electrode 124 within source trench 122. Second low-resistance layer 131 forms a portion of trench source structure 121. Second low-resistance layer 131 has the same structure as first low-resistance layer 112. The description of second low-resistance layer 131 is based on the description of first low-resistance layer 112.

[0269] The semiconductor device 101 includes a p-type body region 141 formed in the surface portion of the first main surface 3 in the active region 8. The body region 141 defines the active region 8. The p-type impurity concentration in the body region 141 is lower than the p-type impurity concentration in the gate electrode 107 and the source electrode 124. The peak value of the p-type impurity concentration in the body region 141 may be 1.0×10 17 cm -3 1.0×10 19 cm -3 the following.

[0270] The body region 141 covers the sidewalls of the gate trench 105 and the sidewalls of the source trench 122 on the surface of the first main surface 3. The body region 141 is formed in a region on the first main surface 3 side relative to the bottom wall of the gate trench 105. The body region 141 faces the gate electrode 107 with the gate insulating layer 106 interposed therebetween.

[0271] The body region 141 is formed in a region on the side of the first trench 125 relative to the second trench 126. The body region 141 covers the first trench 125. The body region 141 is connected to the sidewall contact 130 of the source electrode 124 exposed from the first trench 125. Thus, the body region 141 serves as a source ground within the SiC chip 2. The body region 141 may also cover a portion of the second trench 126. In this case, the body region 141 may face the source electrode 124 via a portion of the source insulating layer 123.

[0272] The semiconductor device 101 includes a n-type semiconductor layer formed on the surface portion of the body region 141. + The source region 142 is formed by the gate trench 105. The peak value of the n-type impurity concentration of the source region 142 exceeds the peak value of the n-type impurity concentration of the high-concentration region 102. The peak value of the n-type impurity concentration of the source region 142 may also be 1.0×10 18 cm -3 Above and 1.0×10 21 cm-3 the following.

[0273] The source region 142 covers the sidewalls of the gate trench 105 and the source trench 122 on the surface of the body region 141. The source region 142 faces the gate electrode 107 via the gate insulating layer 106. The source region 142 preferably faces the first low-resistance layer 112 via the gate insulating layer 106.

[0274] The source region 142 is also formed in a region on the first trench portion 125 side relative to the second trench portion 126. The source region 142 covers the first trench portion 125. The source region 142 is connected to the sidewall contact portion 130 of the source electrode 124 exposed from the first trench portion 125. Thus, the source region 142 is source-grounded within the SiC chip 2.

[0275] In this embodiment, the source region 142 has a shielded portion shielded by the third region 110 of the gate insulating layer 106 and an exposed portion exposed from the third region 110 on the first main surface 3. Alternatively, the entire source region 142 may be covered by the third region 110.

[0276] The portion of the source region 142 along the sidewall of the gate trench 105 defines a channel of the MISFET within the body region 141 and between the source region 142 and the high-concentration region 102. The gate electrode 107 controls the on / off state of the channel.

[0277] The semiconductor device 101 includes a p-type transistor formed on a surface portion of the first main surface 3 in the active region 8. + The peak value of the p-type impurity concentration of each contact region 143 exceeds the peak value of the p-type impurity concentration of the body region 141. The peak value of the p-type impurity concentration of each contact region 143 may also be 1.0×10 18 cm -3 Above and 1.0×10 21 cm -3 the following.

[0278] Multiple contact regions 143 are formed along the multiple source trenches 122. Specifically, the multiple contact regions 143 are formed in a one-to-many relationship with each corresponding source trench 122. The multiple contact regions 143 are formed at intervals along the corresponding source trenches 122. The multiple contact regions 143 are formed at intervals from the gate trench 105.

[0279] Each contact region 143 covers the corresponding first trench portion 125. Each contact region 143 is located between the sidewall contact portion 130 of the source electrode 124 and the source region 142 in the corresponding first trench portion 125. Each contact region 143 is also located between the sidewall contact portion 130 of the source electrode 124 and the body region 141 in the corresponding first trench portion 125.

[0280] Thus, each contact region 143 is electrically connected to the source electrode 124, the body region 141, and the source region 142. Each contact region 143 serves as a source ground in the SiC chip 2.

[0281] The portion of each contact region 143 that surrounds the first trench portion 125 extends toward the gate trench 105. The portion of each contact region 143 that surrounds the first trench portion 125 is formed in a region on the first main surface 3 side relative to the bottom of the body region 141. The portion of each contact region 143 that surrounds the first trench portion 125 may also extend to an intermediate region between the gate trench 105 and the source trench 122.

[0282] Each contact region 143 also covers the corresponding second trench portion 126. Each contact region 143 faces the source electrode 124 in the corresponding second trench portion 126 with the source insulating layer 123 interposed therebetween.

[0283] Each contact region 143 also covers the bottom wall of the corresponding source trench 122. Each contact region 143 faces the source electrode 124 across the bottom wall of the corresponding source trench 122. The bottom of each contact region 143 may also be formed parallel to the bottom wall of the corresponding source trench 122.

[0284] Semiconductor device 101 includes a plurality of p-type deep well regions 144 formed in the surface portion of first main surface 3 in active region 8 . The peak p-type impurity concentration of each deep well region 144 is lower than the peak p-type impurity concentration of contact region 143 .

[0285] The peak value of the p-type impurity concentration in each deep well region 144 may be greater than or less than the peak value of the p-type impurity concentration in the body region 141. The peak value of the p-type impurity concentration in each deep well region 144 may also be 1.0×10 17 cm -3 Above and 1.0×10 19 cm -3 the following.

[0286] A plurality of deep well regions 144 are formed in a one-to-one correspondence with the plurality of source trenches 122. Each deep well region 144 is formed in a strip shape extending along the corresponding source trench 122 in a plan view. Each deep well region 144 forms a high-concentration region 102. Each deep well region 144 is formed in a region on the second main surface 4 side relative to the body region 141. Each deep well region 144 is connected to the body region 141.

[0287] Each deep well region 144 includes a portion covering the corresponding second trench portion 126. Each deep well region 144 includes a portion covering the corresponding second trench portion 126 across the contact region 143. Each deep well region 144 also includes a portion covering the bottom wall of the corresponding source trench 122. Each deep well region 144 includes a portion covering the bottom wall of the corresponding source trench 122 across the contact region 143.

[0288] Each deep well region 144 has a bottom located on the second main surface 4 side relative to the bottom wall of gate trench 105. The bottom of each deep well region 144 may be formed parallel to the bottom wall of each source trench 122. The plurality of deep well regions 144 are preferably formed to a constant depth.

[0289] Each deep well region 144 forms a pn junction with the high concentration region 102. A depletion layer extends from the pn junction toward the gate trench 105. The depletion layer may overlap with the bottom wall of the gate trench 105.

[0290] In semiconductor device 101, which only includes a pn junction diode and lacks a trench structure, electric field concentration within SiC chip 2 is less of a concern. Each deep well region 144 gives the trench-gate MISFET a structure similar to a pn junction diode. This mitigates the electric field within SiC chip 2 in the trench-gate MISFET.

[0291] Deep well region 144 having a bottom on the second main surface 4 side relative to the bottom wall of gate trench 105 can appropriately alleviate the electric field concentration relative to gate trench 105 through the depletion layer. Narrowing the pitch PS between the plurality of source trenches 122 (deep well regions 144) is effective in alleviating electric field concentration and improving the withstand voltage.

[0292] The plurality of deep well regions 144 are preferably formed at a constant depth. This prevents the breakdown voltage (eg, breakdown resistance) of the SiC chip 2 from being limited by the deep well regions 144 , thereby appropriately improving the breakdown voltage.

[0293] By utilizing source trench 122 , deep well region 144 can be appropriately formed in a relatively deep region of SiC chip 2 . Since deep well region 144 can be formed along source trench 122 , variations in depth among multiple deep well regions 144 can be appropriately suppressed.

[0294] In this embodiment, a portion of the high-concentration region 102 is located between the plurality of deep well regions 144. Thus, the resistance of the JFET (Junction Field Effect Transistor) can be reduced in the region between the plurality of deep well regions 144.

[0295] In this configuration, the bottom of each deep well region 144 is located in the high-concentration region 102. This allows the area directly below each deep well region 144 in the high-concentration region 102 to form a current path in a lateral direction parallel to the first principal surface 3. This reduces resistance to current spreading. In this configuration, the low-concentration region 103 improves the withstand voltage of the SiC chip 2.

[0296] The main surface insulating layer 12 covers the entire area of ​​the first main surface 3. The main surface insulating layer 12 covers the source region 142 and the contact region 143 in the active region 8. Specifically, in a cross-section viewed in the second direction Y, the main surface insulating layer 12 covers the entire area of ​​the source region 142 and the entire area of ​​the contact region 143 in the active region 8. The main surface insulating layer 12 covers the entire area of ​​the source region 142 and the entire area of ​​the contact region 143 when viewed from above.

[0297] More specifically, the main surface insulating layer 12 crosses the first trench portion 125 in the active region 8 and covers the source electrode 124. The main surface insulating layer 12 covers the sidewall contact portion 130 of the source electrode 124 on the first main surface 3.

[0298] The main surface insulating layer 12 has a plurality of contact openings 151 that expose the plurality of source electrodes 124 in the active region 8. The plurality of contact openings 151 are formed in a one-to-one correspondence with the plurality of source electrodes 124. Each contact opening 151 may also be formed in a strip shape extending along the trench source structure 121. Each contact opening 151 is formed within a region surrounded by the sidewalls of the source trench 122 (first trench portion 125) when viewed from above.

[0299] Each contact opening 151 exposes the source electrode 124 at intervals from the sidewall of the source trench 122 (first trench portion 125) toward the inside of the source trench 122. The contact opening 151 exposes only the source electrode 124. The opening edge of the contact opening 151 is curved toward the inside of the contact opening 151.

[0300] A recess 152 is formed on the electrode surface of the source electrode 124, recessed toward the bottom wall of the source trench 122. The recess 152 may also be formed in a strip shape extending along the trench source structure 121. The recess 152 is formed in a region surrounded by the sidewalls of the source trench 122 (first trench portion 125) in a plan view.

[0301] The groove 152 is formed at intervals from the sidewall of the source trench 122 (first trench portion 125) toward the inside of the source trench 122. The groove 152 exposes the second low-resistance layer 131. The groove 152 may also penetrate the second low-resistance layer 131. The contact opening 151 communicates with the groove 152 of the source electrode 124.

[0302] The periphery of the main surface insulating layer 12 is exposed from the side surfaces 5A to 5D. In this embodiment, the periphery of the main surface insulating layer 12 is continuous with the side surfaces 5A to 5D. Alternatively, the periphery of the main surface insulating layer 12 may be formed with a gap inward from the side surfaces 5A to 5D. In this case, the main surface insulating layer 12 is exposed in the portion located in the outer region 9 of the first main surface 3.

[0303] The thickness of the main surface insulating layer 12 may be 0.1 μm to 10 μm. The thickness of the main surface insulating layer 12 may be 0.1 μm to 1 μm, 1 μm to 2 μm, 2 μm to 4 μm, 4 μm to 6 μm, 6 μm to 8 μm, or 8 μm to 10 μm. The thickness of the main surface insulating layer 12 is preferably 0.5 μm to 5 μm.

[0304] The first main surface electrode 21 is formed on the main surface insulating layer 12. The thickness T1 of the first main surface electrode 21 may be greater than or equal to 1 μm and less than or equal to 100 μm. The thickness T1 may also be greater than or equal to 1 μm and less than or equal to 10 μm, greater than or equal to 10 μm and less than or equal to 20 μm, greater than or equal to 20 μm and less than or equal to 40 μm, greater than or equal to 40 μm and less than or equal to 60 μm, greater than or equal to 60 μm and less than or equal to 80 μm, or greater than or equal to 80 μm and less than or equal to 100 μm. The thickness T1 is preferably greater than or equal to 20 μm and less than or equal to 60 μm.

[0305] The first main surface electrode 21 includes a gate main surface electrode 153, a gate wiring electrode 154, and a source main surface electrode 155. A gate voltage is applied to the gate main surface electrode 153 (gate wiring electrode 154). The gate voltage may be greater than 10V and less than 50V (e.g., approximately 30V). A source voltage is applied to the source main surface electrode 155. The source voltage may also be a reference voltage (e.g., GND voltage).

[0306] The gate main surface electrode 153 is formed in the active region 8. When viewed from above, the gate main surface electrode 153 is formed in the region on the first side surface 5A side. Specifically, the gate main surface electrode 153 is formed in the center portion of the first side surface 5A when viewed from above. The gate main surface electrode 153 may also be formed at a corner connecting any two of the side surfaces 5A to 5D when viewed from above. The gate main surface electrode 153 may also be formed in a quadrilateral shape when viewed from above.

[0307] The gate wiring electrode 154 extends from the gate main surface electrode 153 and extends in a strip shape along the periphery of the active area 8. In this embodiment, the gate wiring electrode 154 extends along the first side surface 5A, the third side surface 5C, and the fourth side surface 5D, dividing the inner side of the active area 8 from three directions. The gate wiring electrode 154 is electrically connected to the gate electrode 107 via the main surface insulating layer 12. The electrical signal from the gate main surface electrode 153 is transmitted to the gate electrode 107 via the gate wiring electrode 154.

[0308] The source main surface electrode 155 is formed in the active region 8 at a distance from the gate main surface electrode 153 and the gate wiring electrode 154. The source main surface electrode 155 covers the region partitioned by the gate main surface electrode 153 and the gate wiring electrode 154 and has a C-shape in plan view.

[0309] The source main surface electrode 155 is electrically connected to the source electrode 124 via the contact opening 151. That is, in this embodiment, the source main surface electrode 155 made of a metal material is electrically connected to the source electrode 124 made of conductive polysilicon.

[0310] The first main surface electrodes 21 (the gate main surface electrode 153 , the gate wiring electrode 154 , and the source main surface electrode 155 ) each have a stacked structure including a barrier electrode 22 and a main electrode 23 stacked in this order from the SiC chip 2 side.

[0311] In this embodiment, the barrier electrode 22 includes at least one of a Ti layer and a TiN layer. The barrier electrode 22 preferably has a stacked structure including Ti layers and TiN layers stacked in order from the SiC chip 2 side. Alternatively, the barrier electrode 22 may have a single-layer structure consisting of a Ti layer or a TiN layer.

[0312] The thickness of the barrier electrode 22 may be 0.01 μm to 1 μm. The thickness of the barrier electrode 22 may be 0.01 μm to 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.4 μm, 0.4 μm to 0.6 μm, 0.6 μm to 0.8 μm, or 0.8 μm to 1 μm.

[0313] The main electrode 23 is formed in a film-like shape on the barrier electrode 22. The main electrode 23 covers the entire main surface of the barrier electrode 22. The main electrode 23 has a resistance value lower than that of the barrier electrode 22. The main electrode 23 is composed of an Al-based metal layer. Specifically, the main electrode 23 includes at least one of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer.

[0314] The main electrode 23 may have a stacked structure comprising two or more of a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, and an AlSiCu alloy layer stacked in any order. The main electrode 23 may also have a single-layer structure comprising a pure Al layer, an AlSi alloy layer, an AlCu alloy layer, or an AlSiCu alloy layer. The main electrode 23 preferably has a single-layer structure comprising an AlSi alloy layer, an AlCu alloy layer, or an AlSiCu alloy layer.

[0315] The thickness of the main electrode 23 exceeds the thickness of the barrier electrode 22. The thickness of the main electrode 23 may be greater than 10 μm and less than 100 μm. The thickness of the main electrode 23 may be greater than 10 μm and less than 20 μm, greater than 20 μm and less than 40 μm, greater than 40 μm and less than 60 μm, greater than 60 μm and less than 80 μm, or greater than 80 μm and less than 100 μm. The thickness of the main electrode 23 is preferably greater than 20 μm and less than 60 μm. The thickness of the barrier electrode 22 is extremely small compared to the thickness of the main electrode 23, so the thickness T1 of the first main surface electrode 21 is approximately the same as the thickness of the main electrode 23.

[0316] The insulating layer 24 covers the first main surface electrode 21 on the first main surface 3. Figure 9 Insulation layer 24 is hatched. Specifically, insulation layer 24 is formed on main surface insulation layer 12. The periphery of insulation layer 24 is formed with spaces inward from side surfaces 5A to 5D. Thus, insulation layer 24 exposes the periphery of main surface insulation layer 12.

[0317] The periphery of the insulating layer 24 defines dicing streets 25 between the side surfaces 5A to 5D. The dicing streets 25 allow the insulating layer 24 to be physically cut when the semiconductor device 101 is cut from the wafer. This allows for smooth cutting of the semiconductor device 101 from the wafer while suppressing delamination and degradation of the insulating layer 24. Consequently, the insulating layer 24 can appropriately protect the SiC chip 2, first main surface electrode 21, and other protected objects.

[0318] The width of the dicing street 25 may be greater than or equal to 1 μm and less than or equal to 25 μm. The width of the dicing street 25 is the width in a direction perpendicular to the direction in which the dicing street 25 extends. The width of the dicing street 25 may be greater than or equal to 1 μm and less than or equal to 5 μm, greater than or equal to 5 μm and less than or equal to 10 μm, greater than or equal to 10 μm and less than or equal to 15 μm, greater than or equal to 15 μm and less than or equal to 20 μm, or greater than or equal to 20 μm and less than or equal to 25 μm.

[0319] Insulating layer 24 has a pad opening 26 that exposes first main surface electrode 21. In this embodiment, pad opening 26 includes a gate pad opening 161 that exposes gate main surface electrode 153 and a source pad opening 162 that exposes source main surface electrode 155. Gate pad opening 161 may be formed into a polygonal shape having four sides parallel to side surfaces 5A to 5D when viewed from above. Source pad opening 162 may be formed into a polygonal shape having four sides parallel to side surfaces 5A to 5D when viewed from above. The planar shapes of gate pad opening 161 and source pad opening 162 are arbitrary.

[0320] Specifically, the insulating layer 24 has a laminated structure comprising an inorganic insulating layer 30 and an organic insulating layer 31, stacked sequentially from the SiC chip 2 side. The inorganic insulating layer 30 is formed in a film-like shape along the main surface insulating layer 12, the gate main surface electrode 153, and the source main surface electrode 155. The inorganic insulating layer 30 includes a first gate inner wall 163, a first source inner wall 164, and a first outer wall 165. Hereinafter, the first gate inner wall 163, the first source inner wall 164, and the first outer wall 165 may be collectively referred to as the first wall surface.

[0321] First gate inner wall 163 defines a first gate opening 166 that exposes a portion of gate main surface electrode 153. First gate opening 166 forms a portion of gate pad opening 161. First gate opening 166 has a planar shape similar to that of gate main surface electrode 153 and exposes the inner portion of gate main surface electrode 153. The planar shape of first gate opening 166 is arbitrary. First gate opening 166 may also be defined as a polygonal shape having four sides parallel to side surfaces 5A to 5D when viewed from above.

[0322] First source inner wall 164 defines a first source opening 167 that exposes a portion of source main surface electrode 155. First source opening 167 forms a portion of source pad opening 162. First source opening 167 has a planar shape similar to that of source main surface electrode 155 and exposes the inner portion of source main surface electrode 155. The planar shape of first source opening 167 is arbitrary. First source opening 167 may also be defined as a polygonal shape having four sides parallel to side surfaces 5A to 5D when viewed from above.

[0323] First outer wall 165 of inorganic insulating layer 30 is formed inwardly from side surfaces 5A to 5D at intervals, and defines a portion of scribe line 25 between side surfaces 5A to 5D. Thus, inorganic insulating layer 30 exposes the periphery of main surface insulating layer 12. First outer wall 165 may also be formed in a rectangular shape having four sides parallel to side surfaces 5A to 5D in plan view.

[0324] The angle formed between the first wall surface of the inorganic insulating layer 30 and the main surface of the first main surface electrode 21 within the inorganic insulating layer 30 may be greater than 30° and less than 90°. The angle formed between the first wall surface and the main surface of the first main surface electrode 21 within the inorganic insulating layer 30 is preferably greater than 45° and less than 90°. The angle of the first wall surface is defined by the angle formed by the straight line connecting the lower end and the upper end of the first wall surface and the main surface of the first main surface electrode 21.

[0325] The inorganic insulating layer 30 has a high adhesion to Ni. The inorganic insulating layer 30 includes at least one of a silicon oxide layer and a silicon nitride layer. The inorganic insulating layer 30 may also have a stacked structure including silicon oxide layers and silicon nitride layers stacked sequentially from the SiC chip 2 side. The inorganic insulating layer 30 may also have a single-layer structure consisting of a silicon oxide layer or a silicon nitride layer. The inorganic insulating layer 30 preferably includes an insulating material different from that of the main surface insulating layer 12. In this embodiment, the inorganic insulating layer 30 has a single-layer structure consisting of a silicon nitride layer.

[0326] The thickness T2 of the inorganic insulating layer 30 is preferably smaller than the thickness T1 of the first main surface electrode 21 (T2 < T1). The thickness T2 may be greater than or equal to 0.1 μm and less than or equal to 10 μm. The thickness T2 may also be greater than or equal to 0.1 μm and less than or equal to 1 μm, greater than or equal to 1 μm and less than or equal to 2 μm, greater than or equal to 2 μm and less than or equal to 4 μm, greater than or equal to 4 μm and less than or equal to 6 μm, greater than or equal to 6 μm and less than or equal to 8 μm, or greater than or equal to 8 μm and less than or equal to 10 μm. The thickness T2 is preferably greater than or equal to 1 μm and less than or equal to 5 μm. The thickness T2 is particularly preferably greater than or equal to 1 μm and less than or equal to 2 μm.

[0327] The organic insulating layer 31 is formed in a film-like shape on the inorganic insulating layer 30. The organic insulating layer 31 includes a second gate inner wall 168, a second source inner wall 169, and a second outer wall 170. Hereinafter, the second gate inner wall 168, the second source inner wall 169, and the second outer wall 170 may be collectively referred to as a second wall surface.

[0328] Reference Figure 13 In this embodiment, the second gate inner wall 168 is formed into a curved shape that is recessed toward the inorganic insulating layer 30. The second gate inner wall 168 defines a second gate opening 171 that exposes a portion of the gate main surface electrode 153. The second gate opening 171 has a planar shape similar to that of the gate main surface electrode 153 and exposes the inner portion of the gate main surface electrode 153. The planar shape of the second gate opening 171 is arbitrary. The second gate opening 171 may also be defined into a polygonal shape having four sides parallel to the side surfaces 5A to 5D when viewed from above.

[0329] Second gate opening 171 communicates with first gate opening 166 of inorganic insulating layer 30, and gate pad opening 161 is formed between second gate opening 171 and first gate opening 166. Second gate opening 171 surrounds first gate opening 166 with a gap therebetween, exposing a portion of inorganic insulating layer 30. Specifically, organic insulating layer 31 exposes a portion of the main surface of inorganic insulating layer 30 as gate inner periphery 172 in the region between first gate opening 166 and second gate opening 171.

[0330] The width WG of the gate inner periphery 172 may be greater than 0 μm and less than 10 μm. The width WG may also be greater than 0 μm and less than 1 μm, greater than 1 μm and less than 2 μm, greater than 2 μm and less than 4 μm, greater than 4 μm and less than 6 μm, greater than 6 μm and less than 8 μm, or greater than 8 μm and less than 10 μm. The width WG is preferably greater than 1 μm and less than 5 μm. The width WG is arbitrary, but is preferably less than or equal to the thickness T2 of the inorganic insulating layer 30 (WG ≤ T2). The width WG is particularly preferably greater than or equal to 1 μm and less than 2 μm.

[0331] Reference Figure 14 In this embodiment, the second source inner wall 169 is formed into a curved shape that is recessed toward the inorganic insulating layer 30. The second source inner wall 169 defines a second source opening 173 that exposes a portion of the source main surface electrode 155. The second source opening 173 has a planar shape similar to that of the source main surface electrode 155 and exposes the inner portion of the source main surface electrode 155. The planar shape of the second source opening 173 is arbitrary. The second source opening 173 may also be defined into a polygonal shape having four sides parallel to the side surfaces 5A to 5D when viewed from above.

[0332] Second source opening 173 communicates with first source opening 167 of inorganic insulating layer 30, and forms source pad opening 162 between second source opening 173 and first source opening 167. Second source opening 173 surrounds first source opening 167 with a gap therebetween, exposing a portion of inorganic insulating layer 30. Specifically, organic insulating layer 31 exposes a portion of the main surface of inorganic insulating layer 30 as source inner peripheral edge 174 in the region between first source opening 167 and second source opening 173.

[0333] The width WS of the source inner peripheral edge 174 may be greater than 0 μm and less than 10 μm. The width WS may also be greater than 0 μm and less than 1 μm, greater than 1 μm and less than 2 μm, greater than 2 μm and less than 4 μm, greater than 4 μm and less than 6 μm, greater than 6 μm and less than 8 μm, or greater than 8 μm and less than 10 μm. The width WS is preferably greater than 1 μm and less than 5 μm. The width WS is arbitrary, but is preferably less than or equal to the thickness T2 of the inorganic insulating layer 30 (WS ≤ T2). The width WS is particularly preferably greater than or equal to 1 μm and less than 2 μm.

[0334] In this embodiment, the second outer wall 170 of the organic insulating layer 31 is formed in a curved shape that is recessed toward the inorganic insulating layer 30. The second outer wall 170 is formed on the inorganic insulating layer 30 at intervals inward from the side surfaces 5A to 5D, and defines a portion of the scribe line 25 between the side surfaces 5A to 5D. As a result, the organic insulating layer 31 exposes the periphery of the main surface insulating layer 12. Alternatively, the second outer wall 170 may be formed in a rectangular shape with four sides parallel to the side surfaces 5A to 5D when viewed from above.

[0335] The second outer wall 170 of the organic insulating layer 31 may also cross the first outer wall 165 of the inorganic insulating layer 30 and be formed on the main surface insulating layer 12. In this case, the second outer wall 170 of the organic insulating layer 31 defines the dicing street 25.

[0336] The angle formed between the second wall surface of the organic insulating layer 31 and the main surface of the inorganic insulating layer 30 within the organic insulating layer 31 may be greater than 30° and less than 90°. The angle formed between the second wall surface within the organic insulating layer 31 and the main surface of the inorganic insulating layer 30 is preferably greater than 45° and less than 90°. The angle of the second wall surface is defined by the angle formed between the main surface of the inorganic insulating layer 30 and a straight line connecting the lower and upper ends of the second wall surface.

[0337] Compared to the inorganic insulating layer 30, the organic insulating layer 31 has lower adhesion to Ni. The organic insulating layer 31 comprises a negative-type or positive-type photosensitive resin. Alternatively, the organic insulating layer 31 may comprise at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 31 comprises polyimide.

[0338] The organic insulating layer 31 preferably has a thickness T3 that exceeds the thickness T2 of the inorganic insulating layer 30 (T2 < T3). The ratio T3 / T2 of the thickness T3 of the organic insulating layer 31 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than 10. The ratio T3 / T2 is preferably greater than 1 and less than 2, greater than 2 and less than 4, greater than 4 and less than 6, greater than 6 and less than 8, or greater than 8 and less than 10. The ratio T3 / T2 is preferably greater than 2 and less than 6.

[0339] Thickness T3 may be 1 μm to 50 μm. Thickness T3 may be 1 μm to 10 μm, 10 μm to 20 μm, 20 μm to 30 μm, 30 μm to 40 μm, or 40 μm to 50 μm. Thickness T3 is preferably 5 μm to 30 μm.

[0340] In this embodiment, the rough surface region 39 of the first main surface electrode 21 includes a gate rough surface region 175 and a source rough surface region 176. Gate rough surface region 175 is formed on the surface of gate main surface electrode 153 that is exposed from gate pad opening 161 (first gate opening 166 of inorganic insulating layer 30). Gate rough surface region 175 includes a recess formed in the area directly below first gate inner wall 163. As a result, first gate inner wall 163 includes a portion that protrudes toward gate rough surface region 175.

[0341] Source rough surface region 176 is formed on the surface of source main surface electrode 155 that is exposed from source pad opening 162 (first source opening 167 in inorganic insulating layer 30). Source rough surface region 176 comprises a recess formed in the area directly below first source inner wall 164. As a result, first source inner wall 164 includes a portion that protrudes toward source rough surface region 176.

[0342] In this embodiment, pad electrode 40 includes gate pad electrode 181 and source pad electrode 182. Gate pad electrode 181 includes first Ni plating layer 183 formed on gate main surface electrode 153 within gate pad opening 161. First Ni plating layer 183 corresponds to Ni plating layer 41 of the first embodiment.

[0343] First Ni plating layer 183 covers gate main surface electrode 153 within first gate opening 166 and covers gate inner periphery 172 of inorganic insulating layer 30 within second gate opening 171. First Ni plating layer 183 has an outer surface formed with a gap from the main surface of organic insulating layer 31 (insulating layer 24) toward gate main surface electrode 153. First Ni plating layer 183 covers organic insulating layer 31 within second gate opening 171.

[0344] Reference Figure 13 Specifically, the first Ni plating layer 183 includes a first portion 183A covering the gate main surface electrode 153 and a second portion 183B covering the gate inner peripheral edge 172 of the inorganic insulating layer 30 .

[0345] First portion 183A of first Ni plating layer 183 fills gate rough surface region 175 within first gate opening 166 and covers gate main surface electrode 153. First portion 183A covers the entire first gate inner wall 163 of inorganic insulating layer 30 and protrudes from the opening end of first gate opening 166 toward the opening end of second gate opening 171. First portion 183A is connected to first gate inner wall 163 of inorganic insulating layer 30 and has a first connection portion extending in the thickness direction of inorganic insulating layer 30.

[0346] Second portion 183B of first Ni plating layer 183 extends from first portion 183A toward organic insulating layer 31 within second gate opening 171. Second portion 183B is formed in an arc shape extending from the opening end of first gate opening 166 toward organic insulating layer 31.

[0347] The second portion 183B covers the gate inner periphery 172 of the inorganic insulating layer 30 within the second gate opening 171. Thus, the second portion 183B faces the gate main surface electrode 153 across the gate inner periphery 172 of the inorganic insulating layer 30. The second portion 183B is connected to the main surface of the inorganic insulating layer 30 and has a second connection portion extending in the width direction of the inorganic insulating layer 30.

[0348] In this embodiment, the second portion 183B also covers the second gate inner wall 168 of the organic insulating layer 31 within the second gate opening 171. The second portion 183B covers the area on the inorganic insulating layer 30 side relative to the middle portion of the second gate inner wall 168 of the organic insulating layer 31. In other words, the second portion 183B covers the organic insulating layer 31 such that the exposed area of ​​the second gate inner wall 168 (organic insulating layer 31) exceeds the concealed area of ​​the second gate inner wall 168 (organic insulating layer 31). In this manner, the first Ni plating layer 183 is formed so that the first portion 183A and the second portion 183B engage with the opening end of the first gate opening 166 from two different directions.

[0349] The first Ni plating layer 183 has a thickness T4 that exceeds the thickness T2 of the inorganic insulating layer 30 (T2 < T4). Thickness T4 is less than the thickness T3 of the organic insulating layer 31 (T3 < T4). Thickness T4 exceeds the value obtained by adding the width WG of the gate inner periphery 172 to the thickness T2 of the inorganic insulating layer 30 (T2 + WG) (T2 + WG < T4). This is a condition for the first Ni plating layer 183 to be in contact with the second gate inner wall 168 of the organic insulating layer 31. Thickness T4 is defined by the thickness of the first Ni plating layer 183 relative to the main surface of the gate main surface electrode 153.

[0350] The ratio T4 / T2 of the thickness T4 of the first Ni plating layer 183 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than 5. The ratio T4 / T2 may be greater than 1 and less than 2, greater than 2 and less than 3, greater than 3 and less than 4, or greater than 4 and less than 5.

[0351] Thickness T4 may be 0.1 μm to 15 μm. Thickness T4 may be 0.1 μm to 1 μm, 1 μm to 3 μm, 3 μm to 6 μm, 6 μm to 9 μm, 9 μm to 12 μm, or 12 μm to 15 μm. Thickness T4 is preferably 2 μm to 8 μm.

[0352] Gate pad electrode 181 is made of a different metal material from first Ni plating layer 183 and includes first outer surface plating layer 184 covering the outer surface of first Ni plating layer 183 in second gate opening 171. First outer surface plating layer 184 corresponds to outer surface plating layer 42 of the first embodiment.

[0353] The first outer surface plating layer 184 has a thickness T5 smaller than the thickness T4 of the first Ni plating layer 183 ( T5 < T4 ). The first outer surface plating layer 184 covers the second gate inner wall 168 of the organic insulating layer 31 in the second gate opening 171 .

[0354] First outer surface plating layer 184 includes a gate terminal surface 185A for external connection via a conductive bonding material (e.g., solder). Gate terminal surface 185A is located on the first Ni plating layer 183 side relative to the main surface (opening end of second gate opening 171) of organic insulating layer 31. Thus, first outer surface plating layer 184 exposes a portion of second gate inner wall 168 of organic insulating layer 31.

[0355] Specifically, the first outer surface plating layer 184 has a laminated structure including a first Pd plating layer 185 and a first Au plating layer 186 laminated in order from the first Ni plating layer 183. The first Pd plating layer 185 and the first Au plating layer 186 correspond to the Pd plating layer 43 and the Au plating layer 44 of the first embodiment, respectively.

[0356] The first Pd plating layer 185 is formed in a film-like shape along the outer surface of the first Ni plating layer 183. The first Pd plating layer 185 covers the first Ni plating layer 183 from the opening end of the second gate opening 171 toward the inorganic insulating layer 30, leaving a gap therebetween. The first Pd plating layer 185 covers the second gate inner wall 168 of the organic insulating layer 31 within the second gate opening 171.

[0357] The first Pd plating layer 185 has a thickness smaller than the thickness T4 of the first Ni plating layer 183. The thickness of the first Pd plating layer 185 may be 0.01 μm to 1 μm. The thickness of the first Pd plating layer 185 may be 0.01 μm to 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.4 μm, 0.4 μm to 0.6 μm, 0.6 μm to 0.8 μm, or 0.8 μm to 1 μm.

[0358] The first Au plating layer 186 is formed in a film-like shape along the outer surface of the first Pd plating layer 185. The first Au plating layer 186 covers the first Pd plating layer 185 from the opening end of the second gate opening 171 toward the inorganic insulating layer 30, leaving a gap therebetween. The first Au plating layer 186 covers the second gate inner wall 168 of the organic insulating layer 31 within the second gate opening 171.

[0359] The first Au plating layer 186 has a thickness smaller than the thickness T4 of the first Ni plating layer 183. The thickness of the first Au plating layer 186 may be greater than or equal to 0.01 μm and less than or equal to 1 μm. The thickness of the first Au plating layer 186 may be greater than or equal to 0.01 μm and less than or equal to 0.1 μm, greater than or equal to 0.1 μm and less than or equal to 0.2 μm, greater than or equal to 0.2 μm and less than or equal to 0.4 μm, greater than or equal to 0.4 μm and less than or equal to 0.6 μm, greater than or equal to 0.6 μm and less than or equal to 0.8 μm, or greater than or equal to 0.8 μm and less than or equal to 1 μm.

[0360] In this embodiment, the first outer surface plating layer 184 has a laminated structure including the first Pd plating layer 185 and the first Au plating layer 186. However, a laminated structure having the same structure as described above may also be used. Figures 4A to 4D The first outer surface plating layer 184 is the same as any of the outer surface plating layers 42 of the second to fourth embodiments shown.

[0361] Source pad electrode 182 includes second Ni plating layer 193 formed on source main surface electrode 155 within source pad opening 162. Second Ni plating layer 193 corresponds to Ni plating layer 41 of the first embodiment.

[0362] Second Ni plating layer 193 covers source main surface electrode 155 within first source opening 167 and covers source inner periphery 174 of inorganic insulating layer 30 within second source opening 173. Second Ni plating layer 193 has an outer surface formed with a gap from the main surface of organic insulating layer 31 (insulating layer 24) toward source main surface electrode 155. Second Ni plating layer 193 covers organic insulating layer 31 within second source opening 173.

[0363] Reference Figure 14Specifically, the second Ni plating layer 193 includes a first portion 193A covering the source main surface electrode 155 and a second portion 193B covering the source inner peripheral edge 174 of the inorganic insulating layer 30 .

[0364] First portion 193A of second Ni-plated layer 193 fills source rough surface region 176 within first source opening 167 and covers source main surface electrode 155. First portion 193A covers the entire first source inner wall 164 of inorganic insulating layer 30 and protrudes from the opening end of first source opening 167 toward the opening end of second source opening 173. First portion 193A is connected to first source inner wall 164 of inorganic insulating layer 30 and has a first connection portion extending in the thickness direction of inorganic insulating layer 30.

[0365] Second portion 193B of second Ni plating layer 193 extends from first portion 193A toward organic insulating layer 31 within second source opening 173 . Second portion 193B is formed in an arc shape extending from the opening end of first source opening 167 toward organic insulating layer 31 .

[0366] The second portion 193B covers the source inner peripheral edge 174 of the inorganic insulating layer 30 within the second source opening 173. Thus, the second portion 193B faces the source main surface electrode 155 across the source inner peripheral edge 174 of the inorganic insulating layer 30. The second portion 193B is connected to the main surface of the inorganic insulating layer 30 and has a second connection portion extending in the width direction of the inorganic insulating layer 30.

[0367] In this embodiment, second portion 193B also covers second source inner wall 169 of organic insulating layer 31 within second source opening 173. Second portion 193B covers the area on the inorganic insulating layer 30 side relative to the middle portion of second source inner wall 169 of organic insulating layer 31. In other words, second portion 193B covers organic insulating layer 31 such that the exposed area of ​​second source inner wall 169 (organic insulating layer 31) exceeds the concealed area of ​​second source inner wall 169 (organic insulating layer 31). In this manner, second Ni plating layer 193 is formed so that first portion 193A and second portion 193B engage with the opening end of first source opening 167 from two different directions.

[0368] The second Ni plating layer 193 has a thickness T4 that exceeds the thickness T2 of the inorganic insulating layer 30 (T2 < T4). Thickness T4 is less than thickness T3 of the organic insulating layer 31 (T3 < T4). Thickness T4 exceeds the value obtained by adding the width WS of the source inner periphery 174 to the thickness T2 of the inorganic insulating layer 30 (T2 + WS) (T2 + WS < T4). This is a condition for the second Ni plating layer 193 to be in contact with the second source inner wall 169 of the organic insulating layer 31. Thickness T4 is defined by the thickness of the second Ni plating layer 193 relative to the main surface of the source main surface electrode 155.

[0369] The ratio T4 / T2 of the thickness T4 of the second Ni plating layer 193 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than 5. The ratio T4 / T2 may be greater than 1 and less than 2, greater than 2 and less than 3, greater than 3 and less than 4, or greater than 4 and less than 5.

[0370] Thickness T4 may be 0.1 μm to 15 μm. Thickness T4 may be 0.1 μm to 1 μm, 1 μm to 3 μm, 3 μm to 6 μm, 6 μm to 9 μm, 9 μm to 12 μm, or 12 μm to 15 μm. Thickness T4 is preferably 2 μm to 8 μm.

[0371] Source pad electrode 182 is made of a metal material different from second Ni plating layer 193 and includes second outer surface plating layer 194 covering the outer surface of second Ni plating layer 193 in second source opening 173. Second outer surface plating layer 194 corresponds to outer surface plating layer 42 of the first embodiment.

[0372] The second outer surface plating layer 194 has a thickness T5 smaller than the thickness T4 of the second Ni plating layer 193 ( T5 < T4 ). The second outer surface plating layer 194 covers the second source inner wall 169 of the organic insulating layer 31 in the second source opening 173 .

[0373] Second outer surface plating layer 194 includes a source terminal surface 194A for external connection via a conductive bonding material (e.g., solder). Source terminal surface 194A is located on the second Ni plating layer 193 side relative to the main surface (opening end of second source opening 173) of organic insulating layer 31. Thus, second outer surface plating layer 194 exposes a portion of second source inner wall 169 of organic insulating layer 31.

[0374] Specifically, the second outer surface plating layer 194 has a laminated structure including a second Pd plating layer 195 and a second Au plating layer 196 laminated in order from the second Ni plating layer 193. The second Pd plating layer 195 and the second Au plating layer 196 correspond to the Pd plating layer 43 and the Au plating layer 44 of the first embodiment, respectively.

[0375] Second Pd plating layer 195 is formed in a film-like shape along the outer surface of second Ni plating layer 193. Second Pd plating layer 195 covers second Ni plating layer 193 from the opening end of second source opening 173 toward inorganic insulating layer 30, leaving a gap therebetween. Second Pd plating layer 195 covers second source inner wall 169 of organic insulating layer 31 within second source opening 173.

[0376] The second Pd plating layer 195 has a thickness smaller than the thickness T4 of the second Ni plating layer 193. The thickness of the second Pd plating layer 195 may be 0.01 μm to 1 μm. The thickness of the second Pd plating layer 195 may be 0.01 μm to 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.4 μm, 0.4 μm to 0.6 μm, 0.6 μm to 0.8 μm, or 0.8 μm to 1 μm.

[0377] Second Au plating layer 196 is formed in a film-like shape along the outer surface of second Pd plating layer 195. Second Au plating layer 196 covers second Pd plating layer 195 from the opening end of second source opening 173 toward inorganic insulating layer 30, leaving a gap therebetween. Second Au plating layer 196 covers second source inner wall 169 of organic insulating layer 31 within second source opening 173.

[0378] The second Au plating layer 196 has a thickness smaller than the thickness T4 of the second Ni plating layer 193. The thickness of the second Au plating layer 196 may be 0.01 μm to 1 μm. The thickness of the second Au plating layer 196 may be 0.01 μm to 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.4 μm, 0.4 μm to 0.6 μm, 0.6 μm to 0.8 μm, or 0.8 μm to 1 μm.

[0379] In this embodiment, the second outer surface plating layer 194 has a laminated structure including the second Pd plating layer 195 and the second Au plating layer 196. However, a laminated structure having the same structure as described above may also be used. Figures 4A to 4D The second outer surface plating layer 194 is the same as any of the outer surface plating layers 42 of the second to fourth embodiments shown.

[0380] The second main surface electrode 46 covers the entire area of ​​the second main surface 4. The second main surface electrode 46 forms an ohmic contact with the second main surface 4. The second main surface electrode 46 is formed as a drain electrode.

[0381] The second main surface electrode 46 includes at least one of a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer. The second main surface electrode 46 may also have a stacked structure in which at least two of the Ti layer, the Ni layer, the Pd layer, the Au layer, and the Ag layer are stacked in any order. The second main surface electrode 46 may also have a single-layer structure consisting of a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer. The second main surface electrode 46 preferably includes a Ti layer as an ohmic electrode. In this embodiment, the second main surface electrode 46 has a stacked structure including a Ti layer, a Ni layer, a Pd layer, an Au layer, and an Ag layer stacked in sequence from the second main surface 4 side.

[0382] As described above, according to the semiconductor device 101 including MISFETs instead of SBDs, the same effects as those described for the semiconductor device 1 can be achieved.

[0383] Figure 15 yes Figure 12 The corresponding figure is a cross-sectional view showing a semiconductor device 201 according to a fourth embodiment of the present invention. Figure 16 yes Figure 15 An enlarged view of region XVI is shown. Figure 17 yes Figure 15 The following is an enlarged view of the region XVII shown in FIG. Figures 9 to 14 ) The structures corresponding to the structures described in the preceding paragraph are marked with the same reference symbols and the description is omitted.

[0384] Reference Figures 15 to 17 The organic insulating layer 31 exposes the gate inner periphery 172 of the inorganic insulating layer 30 in the region between the first gate opening 166 and the second gate opening 171. The width WG of the gate inner periphery 172 preferably exceeds the thickness T2 of the inorganic insulating layer 30 (T2<WG).

[0385] The ratio WG / T2 of the width WG of the gate inner peripheral edge 172 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than 10. The ratio WG / T2 may be greater than 1 and less than 2, greater than 2 and less than 4, greater than 4 and less than 6, greater than 6 and less than 8, or greater than 8 and less than 10. The ratio WG / T2 is preferably greater than 2 and less than 5. The width WG may be greater than 0 μm and less than 10 μm. The width WG may be greater than 0 μm and less than 2 μm, greater than 2 μm and less than 4 μm, greater than 4 μm and less than 6 μm, greater than 6 μm and less than 8 μm, or greater than 8 μm and less than 10 μm.

[0386] First Ni plating layer 183 is formed on gate main surface electrode 153 within gate pad opening 161. First Ni plating layer 183 covers gate main surface electrode 153 within first gate opening 166 and covers gate inner periphery 172 of inorganic insulating layer 30 within second gate opening 171. First Ni plating layer 183 has an outer surface formed with a gap from the main surface of organic insulating layer 31 (insulating layer 24) toward gate main surface electrode 153. First Ni plating layer 183 covers gate inner periphery 172 of inorganic insulating layer 30 within second gate opening 171, with a gap from organic insulating layer 31.

[0387] Reference Figure 16 Specifically, the first Ni plating layer 183 includes a first portion 183A covering the gate main surface electrode 153 and a second portion 183B covering the gate inner peripheral edge 172 of the inorganic insulating layer 30 .

[0388] First portion 183A of first Ni-plated layer 183 fills gate rough surface region 175 within first gate opening 166 and covers gate main surface electrode 153. First portion 183A covers the entire first gate inner wall 163 of inorganic insulating layer 30 within first gate opening 166 and protrudes from the opening end of first gate opening 166 toward the opening end of second gate opening 171. First portion 183A is connected to first gate inner wall 163 of inorganic insulating layer 30 and has a first connection portion extending in the thickness direction of inorganic insulating layer 30.

[0389] Second portion 183B of first Ni plating layer 183 extends from first portion 183A toward organic insulating layer 31 in second gate opening 171. Second portion 183B is formed in an arc shape starting from the opening end of first gate opening 166 toward second gate inner wall 168 of organic insulating layer 31.

[0390] The second portion 183B covers the gate inner peripheral edge 172 of the inorganic insulating layer 30 within the second gate opening 171. In this manner, the second portion 183B partially covers the gate inner peripheral edge 172 of the inorganic insulating layer 30 from the second gate inner wall 168 of the organic insulating layer 31 toward the first gate inner wall 163 of the inorganic insulating layer 30 with a gap in the second gate opening 171, such that a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed.

[0391] Thus, the first Ni plating layer 183 exposes a portion of the gate inner peripheral edge 172 of the inorganic insulating layer 30 and the entire area of ​​the second gate inner wall 168 of the organic insulating layer 31. The second portion 183B faces the gate main surface electrode 153 across the gate inner peripheral edge 172 of the inorganic insulating layer 30. The second portion 183B is connected to the main surface of the inorganic insulating layer 30 and has a second connection portion extending in the width direction of the inorganic insulating layer 30.

[0392] The first Ni plating layer 183 has a thickness T4 that exceeds the thickness T2 of the inorganic insulating layer 30 (T2 < T4). Thickness T4 is less than the value obtained by adding the width WG of the gate inner periphery 172 to the thickness T2 of the inorganic insulating layer 30 (T2 + WG) (T4 < T2 + WG). This is a condition for the first Ni plating layer 183 to expose the second gate inner wall 168 of the organic insulating layer 31. Thickness T4 is defined by the thickness of the first Ni plating layer 183 relative to the main surface of the gate main surface electrode 153.

[0393] The ratio T4 / T2 of the thickness T4 of the first Ni plating layer 183 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than 5. The ratio T4 / T2 may be greater than 1 and less than 2, greater than 2 and less than 3, greater than 3 and less than 4, or greater than 4 and less than 5. The thickness T4 may be greater than 0.1 μm and less than 10 μm. The thickness T4 may be greater than 0.1 μm and less than 1 μm, greater than 1 μm and less than 2 μm, greater than 2 μm and less than 4 μm, greater than 4 μm and less than 6 μm, greater than 6 μm and less than 8 μm, or greater than 8 μm and less than 10 μm.

[0394] The first outer surface plating layer 184 covers the outer surface of the first Ni plating layer 183 within the second gate opening 171. The first outer surface plating layer 184 has a thickness T5 that is less than the thickness T4 of the first Ni plating layer 183 (T5 < T4). In this embodiment, the first outer surface plating layer 184 partially covers the gate inner periphery 172 of the inorganic insulating layer 30, extending from the second gate inner wall 168 of the organic insulating layer 31 toward the first gate inner wall 163 of the inorganic insulating layer 30 within the second gate opening 171, with a portion of the inner periphery 38 of the inorganic insulating layer 30 exposed.

[0395] The first outer surface plating layer 184 includes a gate terminal surface 184A for external connection via a conductive bonding material (e.g., solder). The gate terminal surface 184A is located on the first Ni plating layer 183 side relative to the main surface (opening end of the second gate opening 171) of the organic insulating layer 31. Thus, the first outer surface plating layer 184 exposes a portion of the gate inner periphery 172 of the inorganic insulating layer 30 and the entire second gate inner wall 168 of the organic insulating layer 31 within the second gate opening 171.

[0396] Specifically, the first outer surface plating layer 184 has a laminated structure including a first Pd plating layer 185 and a Pd plating layer 186 stacked in sequence from the first Ni plating layer 183. The first Pd plating layer 185 is formed in a film-like shape along the outer surface of the first Ni plating layer 183. The first Pd plating layer 185 covers the first Ni plating layer 183 from the opening end of the second gate opening 171 toward the inorganic insulating layer 30, with a gap therebetween.

[0397] The first Pd plating layer 185 partially covers the gate inner peripheral edge 172 of the inorganic insulating layer 30, leaving a gap from the second gate inner wall 168 of the organic insulating layer 31 toward the first gate inner wall 163 of the inorganic insulating layer 30, in the second gate opening 171, so that a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. Thus, the first Pd plating layer 185 exposes a portion of the gate inner peripheral edge 172 of the inorganic insulating layer 30 and the entire second gate inner wall 168 of the organic insulating layer 31 within the second gate opening 171.

[0398] The first Pd plating layer 185 has a thickness smaller than the thickness T4 of the first Ni plating layer 183. The thickness of the first Pd plating layer 185 may be 0.01 μm to 1 μm. The thickness of the first Pd plating layer 185 may be 0.01 μm to 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.4 μm, 0.4 μm to 0.6 μm, 0.6 μm to 0.8 μm, or 0.8 μm to 1 μm.

[0399] The Pd plating layer 186 is formed in a film shape along the outer surface of the first Pd plating layer 185. The Pd plating layer 186 covers the first Pd plating layer 185 with a gap from the opening end of the second gate opening 171 toward the inorganic insulating layer 30 side.

[0400] The Pd plating layer 186 partially covers the gate inner peripheral edge 172 of the inorganic insulating layer 30, leaving a gap from the second gate inner wall 168 of the organic insulating layer 31 toward the first gate inner wall 163 of the inorganic insulating layer 30, in the second gate opening 171, so that a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. Thus, the Pd plating layer 186 exposes a portion of the gate inner peripheral edge 172 of the inorganic insulating layer 30 and the entire second gate inner wall 168 of the organic insulating layer 31 within the second gate opening 171.

[0401] The Pd plating layer 186 has a thickness smaller than the thickness T4 of the first Ni plating layer 183. The thickness of the Pd plating layer 186 may be 0.01 μm to 1 μm. The thickness of the Pd plating layer 186 may be 0.01 μm to 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.4 μm, 0.4 μm to 0.6 μm, 0.6 μm to 0.8 μm, or 0.8 μm to 1 μm.

[0402] In this embodiment, the first outer surface plating layer 184 has a laminated structure including the first Pd plating layer 185 and the Pd plating layer 186. However, a laminated structure having the same structure as described above may also be used. Figures 8A to 8D The first outer surface plating layer 184 is the same as any of the outer surface plating layers 42 of the second to fourth embodiments shown.

[0403] The organic insulating layer 31 exposes the source inner periphery 174 of the inorganic insulating layer 30 in the region between the first source opening 167 and the second source opening 173. In this embodiment, the width WS of the source inner periphery 174 exceeds the thickness T2 of the inorganic insulating layer 30 (T2<WS).

[0404] The ratio WS / T2 of the width WS of the gate inner peripheral edge 172 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than 10. The ratio WS / T2 may be greater than 1 and less than 2, greater than 2 and less than 4, greater than 4 and less than 6, greater than 6 and less than 8, or greater than 8 and less than 10. The ratio WS / T2 is preferably greater than 2 and less than 5. The width WS may be greater than 0 μm and less than 10 μm. The width WS may be greater than 0 μm and less than 2 μm, greater than 2 μm and less than 4 μm, greater than 4 μm and less than 6 μm, greater than 6 μm and less than 8 μm, or greater than 8 μm and less than 10 μm.

[0405] Second Ni plating layer 193 is formed on source main surface electrode 155 within source pad opening 162. Second Ni plating layer 193 covers source main surface electrode 155 within second source opening 173 and covers source inner peripheral edge 174 of inorganic insulating layer 30 within second source opening 173. Second Ni plating layer 193 has an outer surface formed with a gap from the main surface of organic insulating layer 31 (insulating layer 24) toward source main surface electrode 155. Second Ni plating layer 193 covers source inner peripheral edge 174 of inorganic insulating layer 30 within second source opening 173, with a gap from organic insulating layer 31.

[0406] Reference Figure 17Specifically, the second Ni plating layer 193 includes a first portion 193A covering the source main surface electrode 155 and a second portion 193B covering the source inner peripheral edge 174 of the inorganic insulating layer 30 .

[0407] First portion 193A of second Ni-plated layer 193 fills source rough surface region 176 within first source opening 167 and covers source main surface electrode 155. First portion 193A covers the entire first source inner wall 164 of inorganic insulating layer 30 within first source opening 167 and protrudes from the opening end of first source opening 167 toward the opening end of second source opening 173. First portion 193A is connected to first source inner wall 164 of inorganic insulating layer 30 and has a first connection portion extending in the thickness direction of inorganic insulating layer 30.

[0408] Second portion 193B of second Ni plating layer 193 extends from first portion 193A toward organic insulating layer 31 in second source opening 173. Second portion 193B is formed in an arc shape starting from the opening end of first source opening 167 toward second source inner wall 169 of organic insulating layer 31.

[0409] The second portion 193B covers the source inner peripheral edge 174 of the inorganic insulating layer 30 within the second source opening 173. In this manner, the second portion 193B partially covers the source inner peripheral edge 174 of the inorganic insulating layer 30 with a gap from the second source inner wall 169 of the organic insulating layer 31 toward the first source inner wall 164 of the inorganic insulating layer 30 within the second source opening 173, such that a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed.

[0410] As a result, second Ni plating layer 193 exposes a portion of source inner peripheral edge 174 of inorganic insulating layer 30 and the entire region of second source inner wall 169 of organic insulating layer 31. Second portion 193B faces source main surface electrode 155 across source inner peripheral edge 174 of inorganic insulating layer 30. Second portion 193B is connected to the main surface of inorganic insulating layer 30 and has a second connection portion extending in the width direction of inorganic insulating layer 30.

[0411] The second Ni plating layer 193 has a thickness T4 that exceeds the thickness T2 of the inorganic insulating layer 30 (T2 < T4). Thickness T4 is less than the thickness T3 of the organic insulating layer 31 (T3 < T4). Thickness T4 is less than the value obtained by adding the width WS of the source inner periphery 174 to the thickness T2 of the inorganic insulating layer 30 (T2 + WS) (T4 < T2 + WS). This is the condition for the second Ni plating layer 193 to expose the second source inner wall 169 of the organic insulating layer 31. Thickness T4 is defined by the thickness of the second Ni plating layer 193 relative to the main surface of the source main surface electrode 155.

[0412] The ratio T4 / T2 of the thickness T4 of the second Ni plating layer 193 to the thickness T2 of the inorganic insulating layer 30 may be greater than 1 and less than 5. The ratio T4 / T2 may be greater than 1 and less than 2, greater than 2 and less than 3, greater than 3 and less than 4, or greater than 4 and less than 5. The thickness T4 may be greater than 0.1 μm and less than 10 μm. The thickness T4 may be greater than 0.1 μm and less than 1 μm, greater than 1 μm and less than 2 μm, greater than 2 μm and less than 4 μm, greater than 4 μm and less than 6 μm, greater than 6 μm and less than 8 μm, or greater than 8 μm and less than 10 μm.

[0413] The second outer surface plating layer 194 covers the outer surface of the second Ni plating layer 193 within the second source opening 173. The second outer surface plating layer 194 has a thickness T5 that is less than the thickness T4 of the second Ni plating layer 193 (T5 < T4). In this manner, the second outer surface plating layer 194 partially covers the source inner periphery 174 of the inorganic insulating layer 30, leaving a gap from the second source inner wall 169 of the organic insulating layer 31 toward the first source inner wall 164 of the inorganic insulating layer 30 within the second source opening 173, with a portion of the inner periphery 38 of the inorganic insulating layer 30 exposed.

[0414] Second outer surface plating layer 194 includes a source terminal surface 194A for external connection via a conductive bonding material (e.g., solder). Source terminal surface 194A is located on the second Ni plating layer 193 side relative to the main surface of organic insulating layer 31 (the opening end of second source opening 173). Thus, second outer surface plating layer 194 exposes a portion of source inner periphery 174 of inorganic insulating layer 30 and the entire second source inner wall 169 of organic insulating layer 31 within second source opening 173.

[0415] Specifically, the second outer surface plating layer 194 has a laminated structure including a second Pd plating layer 195 and a second Au plating layer 196, which are laminated in this order from the second Ni plating layer 193. The second Pd plating layer 195 is formed in a film shape along the outer surface of the second Ni plating layer 193. The second Pd plating layer 195 covers the second Ni plating layer 193 from the opening end of the second source opening 173 toward the inorganic insulating layer 30, with a gap therebetween.

[0416] The second Pd plating layer 195 partially covers the source inner peripheral edge 174 of the inorganic insulating layer 30, leaving a gap from the second source inner wall 169 of the organic insulating layer 31 toward the first source inner wall 164 of the inorganic insulating layer 30, in the second source opening 173, so that a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. Thus, the second Pd plating layer 195 exposes a portion of the source inner peripheral edge 174 of the inorganic insulating layer 30 and the entire region of the second source inner wall 169 of the organic insulating layer 31 within the second source opening 173.

[0417] The second Pd plating layer 195 has a thickness smaller than the thickness T4 of the second Ni plating layer 193. The thickness of the second Pd plating layer 195 may be 0.01 μm to 1 μm. The thickness of the second Pd plating layer 195 may be 0.01 μm to 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.4 μm, 0.4 μm to 0.6 μm, 0.6 μm to 0.8 μm, or 0.8 μm to 1 μm.

[0418] The second Au plating layer 196 is formed in a film shape along the outer surface of the second Pd plating layer 195 . The second Au plating layer 196 covers the second Pd plating layer 195 with a gap from the opening end of the second source opening 173 toward the inorganic insulating layer 30 .

[0419] The second Au plating layer 196 partially covers the source inner peripheral edge 174 of the inorganic insulating layer 30, leaving a gap from the second source inner wall 169 of the organic insulating layer 31 toward the first source inner wall 164 of the inorganic insulating layer 30, in the second source opening 173, so that a portion of the inner peripheral edge 38 of the inorganic insulating layer 30 is exposed. Thus, the second Au plating layer 196 exposes a portion of the source inner peripheral edge 174 of the inorganic insulating layer 30 and the entire region of the second source inner wall 169 of the organic insulating layer 31 within the second source opening 173.

[0420] The second Au plating layer 196 has a thickness smaller than the thickness T4 of the second Ni plating layer 193. The thickness of the second Au plating layer 196 may be 0.01 μm to 1 μm. The thickness of the second Au plating layer 196 may be 0.01 μm to 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.4 μm, 0.4 μm to 0.6 μm, 0.6 μm to 0.8 μm, or 0.8 μm to 1 μm.

[0421] In this embodiment, the second outer surface plating layer 194 has a laminated structure including the second Pd plating layer 195 and the second Au plating layer 196. However, a laminated structure having the same structure as described above may also be used. Figures 8A to 8D The second outer surface plating layer 194 is the same as any of the outer surface plating layers 42 of the second to fourth embodiments shown.

[0422] As described above, the semiconductor device 201 can also achieve the same effects as those described for the semiconductor device 101. The semiconductor device 201 can also achieve the same effects as those described for the semiconductor device 61.

[0423] Figure 18This is a plan view of a semiconductor package 301 incorporating the semiconductor devices (reference numerals omitted) according to the first to fourth embodiments, as viewed from one side. Figure 19 Observing from the other side Figure 18 FIG. 3 is a top view of a semiconductor package 301 . Figure 20 yes Figure 18 FIG. 3 is a perspective view of a semiconductor package 301 . Figure 21 yes Figure 18 An exploded perspective view of a semiconductor package 301 is shown. Figure 22 It is along Figure 18 A cross-sectional view taken along line XXII-XXII is shown. Figure 23 yes Figure 18 FIG. 3 is a circuit diagram of a semiconductor package 301 .

[0424] Reference Figures 18 to 23 In this embodiment, semiconductor package 301 has a form factor known as a power protector. Semiconductor package 301 includes a resin package body 302. Package body 302 is formed from a molded resin containing a filler (e.g., an insulating filler) and a matrix resin. The matrix resin is preferably an epoxy resin.

[0425] The package body 302 has a first main surface 303 (first surface) on one side, a second main surface 304 (second surface) on the other side, and side surfaces 305A to 305D connecting the first main surface 303 and the second main surface 304. The first main surface 303 and the second main surface 304 are formed into a quadrilateral shape (a rectangular shape in this embodiment) when viewed from above in the normal direction Z thereof.

[0426] The side surfaces 305A to 305D include a first side surface 305A, a second side surface 305B, a third side surface 305C, and a fourth side surface 305D. The first side surface 305A and the second side surface 305B extend along a first direction X and are opposed to each other in a second direction Y that intersects the first direction X. The first side surface 305A and the second side surface 305B form the long sides of the package body 302. The third side surface 305C and the fourth side surface 305D extend along a second direction Y and are opposed to each other in the first direction X. The third side surface 305C and the fourth side surface 305D form the short sides of the package body 302. Specifically, the second direction Y is orthogonal to the first direction X.

[0427] The semiconductor package 301 includes a first metal plate 310 disposed within the package body 302. The first metal plate 310 is disposed on the first principal surface 303 side of the package body 302 and integrally includes a first heat dissipation portion 311 and a first terminal portion 312. The first heat dissipation portion 311 is disposed within the package body 302 so as to be exposed from the first principal surface 303. The first heat dissipation portion 311 is formed into a rectangular shape extending in the first direction X when viewed from above. The first heat dissipation portion 311 has a planar surface area smaller than the planar surface area of ​​the first principal surface 303 and is exposed from the first principal surface 303 at intervals inward from the side surfaces 305A to 305D.

[0428] The first terminal portion 312 is exposed from the first side surface 305A. Specifically, the first terminal portion 312 extends in a strip shape from the first heat dissipation portion 311 toward the first side surface 305A, penetrates the first side surface 305A, and is led out of the package body 302. When a center line LC is defined that passes through the center of the first side surface 305A (second side surface 305B) along the second direction Y, the first heat dissipation portion 311 is located on the fourth side surface 305D side relative to the center line LC.

[0429] The first terminal portion 312 has a first length L1 in the second direction Y. The width of the first terminal portion 312 in the first direction X is smaller than the width of the first heat dissipation portion 311 in the first direction X. The first terminal portion 312 is connected to the first heat dissipation portion 311 within the package body 302 via a bent portion 313 that bends from the first principal surface 303 toward the second principal surface 304. As a result, the first terminal portion 312 is exposed from the first side surface 305A with a gap between the first principal surface 303 and the second principal surface 304.

[0430] The semiconductor package 301 includes a second metal plate 320 disposed within the package body 302. The second metal plate 320 is disposed on the second principal surface 304 side of the package body 302, spaced apart from the first metal plate 310. It integrally includes a second heat dissipation portion 321 and a second terminal portion 322. The second heat dissipation portion 321 is disposed within the package body 302 so as to be exposed from the second principal surface 304. The second heat dissipation portion 321 is formed into a rectangular shape extending in the first direction X when viewed from above. The second heat dissipation portion 321 has a planar surface area smaller than that of the second principal surface 304 and is exposed inwardly from the side surfaces 305A to 305D.

[0431] The second terminal portion 322 is exposed from the first side surface 305A. Specifically, the second terminal portion 322 extends in a strip shape from the second heat dissipation portion 321 toward the first side surface 305A, passes through the first side surface 305A, and is led out of the package body 302. The second terminal portion 322 is located on the third side surface 305C side relative to the center line LC.

[0432] In this embodiment, the second terminal portion 322 has a second length L2 in the second direction Y that is different from the first length L1 of the first terminal portion 312. The first terminal portion 312 and the second terminal portion 322 are distinguished by their shape (length). The second length L2 of the second terminal portion 322 can be longer than the first length L1 or shorter than the first length L1. Of course, the second terminal portion 322 can also be formed to have a second length L2 equal to the first length L1.

[0433] The width of the second terminal portion 322 in the first direction X is smaller than the width of the second heat dissipating portion 321 in the first direction X. The second terminal portion 322 is connected to the second heat dissipating portion 321 within the package body 302 via a bent portion 323 that bends from the second principal surface 304 toward the first principal surface 303. As a result, the second terminal portion 322 is exposed from the second side surface 305B with a gap between the second principal surface 304 and the first principal surface 303.

[0434] The second terminal portion 322 extends from a different thickness position than the first terminal portion 312 in the normal direction Z. In this embodiment, the second terminal portion 322 is formed spaced apart from the first terminal portion 312 toward the second main surface 304. The second terminal portion 322 does not face the first terminal portion 312 in the first direction X.

[0435] Semiconductor package 301 includes one or more (five in this embodiment) control terminals 330 disposed within package body 302. Multiple control terminals 330 are exposed from second side surface 305B, opposite first side surface 305A, where first terminal portion 312 and second terminal portion 322 are exposed. Multiple control terminals 330 are located on third side surface 305C relative to center line LC. Multiple control terminals 330 are located on the same straight line as second terminal portion 322 of second metal plate 320 when viewed from above. The arrangement of multiple control terminals 330 is arbitrary.

[0436] The plurality of control terminals 330 are each formed in a strip shape extending along the second direction Y. Specifically, the plurality of control terminals 330 each include an internal connection portion 331, an external connection portion 332, and a strip portion 333. The internal connection portion 331 is disposed within the package body 302. The external connection portion 332 is disposed outside the package body 302.

[0437] The strip portion 333 extends from the internal connecting portion 331 through the second side surface 305B and toward the external connecting portion 332 in a strip-like shape. The strip portion 333 may also have a bent portion 334 that is recessed toward the second main surface 304 in a portion located outside the package body 302. Alternatively, the strip portion 333 may be formed without the bent portion 334.

[0438] The plurality of control terminals 330 extend from positions different in thickness from the first heat sink 311 and the second heat sink 321 in the normal direction Z. In this embodiment, the plurality of control terminals 330 are arranged in the region between the first heat sink 311 and the second heat sink 321 at intervals.

[0439] The semiconductor package 301 includes an SBD chip 341 and a MISFET chip 342 disposed within a package body 302. The SBD chip 341 is formed of any of the semiconductor devices (reference numerals omitted) of the first and second embodiments. The MISFET chip 342 is formed of any of the semiconductor devices (reference numerals omitted) of the third and fourth embodiments.

[0440] The SBD chip 341 is disposed within the package body 302 in a space between the first heat sink 311 and the second heat sink 321. The SBD chip 341 is disposed on the fourth side surface 305D of the package body 302 relative to the center line LC. The SBD chip 341 is disposed on the second heat sink 321 such that the second principal surface electrode 46 faces the second heat sink 321.

[0441] The MISFET chip 342 is disposed within the package body 302, spaced apart from the SBD chip 341, in a space between the first heat sink 311 and the second heat sink 321. The MISFET chip 342 is disposed on the third side surface 305C of the package body 302 relative to the center line LC. The MISFET chip 342 is disposed on the second heat sink 321 such that the second main surface electrode 46 faces the second heat sink 321.

[0442] The semiconductor package 301 includes a first conductive bonding material 343 and a second conductive bonding material 344. The first conductive bonding material 343 and the second conductive bonding material 344 each comprise solder or metal paste. The first conductive bonding material 343 is interposed between the second main surface electrode 46 of the SBD chip 341 and the second heat sink 321, thermally, mechanically, and electrically connecting the SBD chip 341 and the second heat sink 321. The second conductive bonding material 344 is interposed between the second main surface electrode 46 of the MISFET chip 342 and the second heat sink 321, thermally, mechanically, and electrically connecting the MISFET chip 342 and the second heat sink 321.

[0443] This electrically connects the cathode of the SBD chip 341 to the drain of the MISFET chip 342. That is, the second metal plate 320 (second heat dissipation portion 321) functions as cathode and drain terminals for the SBD chip 341 and the MISFET chip 342.

[0444] The semiconductor package 301 includes a first metal pad 351 and a second metal pad 352. In this embodiment, the first metal pad 351 and the second metal pad 352 are each formed of a plate-shaped member containing copper. The second metal pad 352 has a thickness equal to that of the first metal pad 351.

[0445] The first metal pad 351 is interposed between the SBD chip 341 and the first heat sink 311, separating the first heat sink 311 from the SBD chip 341. The second metal pad 352 is interposed between the MISFET chip 342 and the first heat sink 311, separating the first heat sink 311 from the MISFET chip 342. In this embodiment, the first metal pad 351 and the second metal pad 352 are separate components, but the first metal pad 351 and the second metal pad 352 can also be formed integrally.

[0446] The semiconductor package 301 includes a third conductive bonding material 353 and a fourth conductive bonding material 354 .

[0447] The third conductive bonding material 353 and the fourth conductive bonding material 354 each include solder or metal paste.

[0448] The third conductive bonding material 353 and the fourth conductive bonding material 354 are preferably each made of solder.

[0449] The third conductive bonding material 353 is interposed between the pad electrode 40 of the SBD chip 341 and the first metal pad 351, thermally, mechanically, and electrically connecting the SBD chip 341 and the first metal pad 351. The fourth conductive bonding material 354 is interposed between the source pad electrode 182 of the MISFET chip 342 and the second metal pad 352, thermally, mechanically, and electrically connecting the MISFET chip 342 and the second metal pad 352.

[0450] Semiconductor package 301 includes a fifth conductive bonding material 355 and a sixth conductive bonding material 356. The fifth conductive bonding material 355 and the sixth conductive bonding material 356 each comprise solder or metal paste. The fifth conductive bonding material 355 is interposed between the first heat sink 311 and the first metal pad 351, thermally, mechanically, and electrically connecting the first heat sink 311 and the first metal pad 351. The sixth conductive bonding material 356 is interposed between the first heat sink 311 and the second metal pad 352, thermally, mechanically, and electrically connecting the first heat sink 311 and the second metal pad 352.

[0451] This electrically connects the anode of the SBD chip 341 to the source of the MISFET chip 342. That is, the first metal plate 310 (first heat dissipation portion 311) functions as an anode terminal and a source terminal for the SBD chip 341 and the MISFET chip 342.

[0452] Semiconductor package 301 includes one or more (five in this embodiment) wires 357. Wires 357 are also referred to as bonding wires. Wires 357 may also be made of metal wires, copper wires, or aluminum wires. Wires 357 are connected to gate pad electrodes 181 of MISFET chips 342 and internal connection portions 331 of control terminals 330, respectively.

[0453] Thus, the gate of the MISFET chip 342 is electrically connected to the plurality of control terminals 330. In other words, the plurality of control terminals 330 each function as a gate terminal of the MISFET chip 342. The wire 357 does not need to connect all of the control terminals 330 to the gate pad electrode 181. Any of the control terminals 330 may be electrically open.

[0454] As described above, according to the semiconductor package 301, the first conductive bonding material 343 is connected to the pad electrode 40 of the SBD chip 341. As described in the first and second embodiments, the pad electrode 40 of the SBD chip 341 includes the Ni plating layer 41 and the outer surface plating layer 42. This allows for proper connection between the first conductive bonding material 343 and the pad electrode 40 of the SBD chip 341. Consequently, the SBD chip 341 can be properly connected to the first heat sink 311 and the second heat sink 321 thermally, mechanically, and electrically.

[0455] If the SBD chip 341 lacks an organic insulating layer 31, filler contained in the package body 302 may cause cracks or peeling in the pad electrodes 40 and other components of the SBD chip 341. This problem, known as filler erosion, is a major factor in reducing the reliability of the pad electrodes 40 and other components. Therefore, an organic insulating layer 31 is formed on the inorganic insulating layer 30 within the SBD chip 341. This acts as a buffer against the filler, effectively protecting the pad electrodes 40 and other components from filler erosion.

[0456] Furthermore, in the SBD chip 341, as described in the first and second embodiments, the organic insulating layer 31 is provided with a structure in which the Ni plating layer 41 is connected to the inner peripheral edge 38 of the inorganic insulating layer 30. This structure also appropriately suppresses cracks and peeling of the Ni plating layer 41 (outer surface plating layer 42) caused by filler corrosion.

[0457] According to the semiconductor package 301, the second conductive bonding material 344 is connected to the source pad electrode 182 of the MISFET chip 342. As described in the third and fourth embodiments, the source pad electrode 182 of the MISFET chip 342 includes the second Ni plating layer 193 and the second outer surface plating layer 194. This allows the second conductive bonding material 344 to be properly connected to the source pad electrode 182 of the MISFET chip 342. Consequently, the MISFET chip 342 can be properly connected to the first heat sink 311 and the second heat sink 321 thermally, mechanically, and electrically.

[0458] If the MISFET chip 342 does not include an organic insulating layer 31, the filler contained in the package body 302 may cause cracks or peeling in the source pad electrode 182 and other components of the MISFET chip 342. This problem is known as filler erosion and is a major factor in reducing the reliability of the source pad electrode 182 and other components. Therefore, in the MISFET chip 342, an organic insulating layer 31 is formed on the inorganic insulating layer 30. This organic insulating layer 31 acts as a buffer against the filler, effectively protecting the source pad electrode 182 and other components from filler erosion.

[0459] Furthermore, in the MISFET chip 342, as described in the third and fourth embodiments, the second Ni plating layer 193 is connected to the first source inner wall 164 of the inorganic insulating layer 30 in a structure including the organic insulating layer 31. This structure also appropriately suppresses cracks and peeling of the second Ni plating layer 193 (second outer surface plating layer 194) caused by filler erosion. In the MISFET chip 342, the gate pad electrode 181 side also achieves the same effects as those on the source pad electrode 182 side.

[0460] In this embodiment, the semiconductor package 301 is described as including an SBD chip 341 and a MISFET chip 342. However, a semiconductor package 301 may include only one of the SBD chip 341 and the MISFET chip 342. A semiconductor package 301 may also include multiple SBD chips 341 and / or multiple MISFET chips 342.

[0461] The embodiments of the present invention can also be implemented in other ways.

[0462] In the third and fourth embodiments described above, when increasing the gate threshold voltage Vth is not important, the gate electrode 107 may comprise n-type polysilicon doped with n-type impurities instead of p-type polysilicon. In this case, a first low-resistance layer 112 composed of n-type polycrystalline is formed. With this structure, the gate resistance can be further reduced.

[0463] In the third and fourth embodiments described above, n-type polysilicon doped with n-type impurities may be included instead of p-type polysilicon. In the third and fourth embodiments described above, a structure may be adopted in which either or both of the first low-resistance layer 112 and the second low-resistance layer 131 are not formed.

[0464] In the third to fourth embodiments described above, it is also possible to adopt p + Type collector region to replace n + This structure allows for an IGBT (Insulated Gate Bipolar Transistor) to be used instead of a MISFET. In this case, in the third and fourth embodiments described above, the MISFET's "source" is replaced by the IGBT's "emitter," and the MISFET's "drain" is replaced by the IGBT's "collector."

[0465] In each of the above embodiments, a Si chip made of Si single crystal can be used in place of the SiC chip 2. That is, the semiconductor devices (not shown) in each of the above embodiments can also be Si semiconductor devices. In each of the above embodiments, a structure in which the conductivity type of each semiconductor portion is reversed can also be used. That is, a p-type portion can be n-type, and vice versa.

[0466] Examples of features extracted from this specification and the accompanying drawings are shown below: [A1] to [A20] provide a semiconductor device having a structure in which a Ni plating layer is formed on an electrode exposed from an opening in an organic insulating layer, and in which the reliability of the Ni plating layer can be improved.

[0467] [A1] A semiconductor device comprising: a chip; an electrode formed on the chip; an inorganic insulating layer covering the electrode and having a first opening for exposing the electrode; an organic insulating layer covering the inorganic insulating layer and having a second opening surrounding the first opening at a distance from the first opening, with the inner peripheral edge of the inorganic insulating layer exposed in a region between the first opening and the second opening; and a Ni plating layer covering the electrode in the first opening and covering the inner peripheral edge of the inorganic insulating layer in the second opening.

[0468] [A2] In the semiconductor device according to A1, the Ni plating layer covers the organic insulating layer in the second opening.

[0469] [A3] The semiconductor device according to A2, wherein the Ni plating layer is formed with a gap from the opening end of the second opening toward the inorganic insulating layer.

[0470] [A4] According to the semiconductor device described in A2 or A3, the Ni plating layer covers the organic insulating layer in the second opening so that the exposed area of ​​the organic insulating layer exceeds the concealed area of ​​the organic insulating layer.

[0471] [A5] The semiconductor device according to any one of A2 to A4, wherein the inner peripheral edge of the inorganic insulating layer has a width that is less than or equal to the thickness of the inorganic insulating layer.

[0472] [A6] The semiconductor device according to any one of A2 to A5, further comprising an outer surface plating layer covering an outer surface of the Ni plating layer in the second opening.

[0473] [A7] In the semiconductor device according to A6, the outer surface plating layer covers the organic insulating layer in the second opening.

[0474] [A8] The semiconductor device according to A6 or A7, wherein the outer surface plating layer covers the Ni plating layer with a gap from the opening end of the second opening toward the inorganic insulating layer.

[0475] [A9] The semiconductor device according to any one of A6 to A8, wherein the outer surface plating layer has a thickness smaller than that of the Ni plating layer.

[0476] [A10] The semiconductor device according to A1, wherein the Ni plating layer covers the inner peripheral edge of the inorganic insulating layer in the second opening with a gap therebetween from the organic insulating layer.

[0477] [A11] The semiconductor device according to A10, wherein the Ni plating layer is formed with a gap from the opening end of the second opening toward the inorganic insulating layer.

[0478] [A12] The semiconductor device according to A10 or A11, wherein the inner peripheral edge of the inorganic insulating layer has a width exceeding the thickness of the inorganic insulating layer.

[0479] [A13] The semiconductor device according to any one of A10 to A12, further comprising an outer surface plating layer covering an outer surface of the Ni plating layer in the second opening.

[0480] [A14] According to the semiconductor device described in A13, the above-mentioned outer surface plating layer covers the above-mentioned inner peripheral edge of the above-mentioned inorganic insulating layer.

[0481] [A15] The semiconductor device according to A13 or A14, wherein the outer surface plating layer covers the Ni plating layer with a gap between the organic insulating layer and the outer surface plating layer.

[0482] [A16] The semiconductor device according to any one of A13 to A15, wherein the outer surface plating layer covers the Ni plating layer with a gap from the opening end of the second opening toward the inorganic insulating layer.

[0483] [A17] The semiconductor device according to any one of A13 to A16, wherein the outer surface plating layer has a thickness smaller than that of the Ni plating layer.

[0484] [A18] The semiconductor device according to any one of A1 to A17, wherein the chip is composed of a SiC chip.

[0485] [A19] Provided is a semiconductor package, comprising: a package body made of resin, having a first surface on one side, a second surface on the other side, and a side surface; a first metal plate, having a first heat dissipation portion exposed from the first surface and a first terminal portion exposed from the side surface, and arranged in the package body; a second metal plate, having a second heat dissipation portion exposed from the second surface and a second terminal portion exposed from the side surface, and arranged in the package body with a gap from the first metal plate toward the second surface; and a semiconductor device as described in any one of claims 1 to 18, which is arranged in the package body in a space sandwiched between the first heat dissipation portion and the second heat dissipation portion.

[0486] This application corresponds to Japanese Patent Application No. 2019-180861 filed with the Japan Patent Office on September 30, 2019, and all disclosures of this application are incorporated herein by reference. Although the embodiments of the present invention are described in detail, these are merely specific examples for clarifying the technical content of the present invention, and the present invention should not be construed as being limited to these specific examples. The scope of the present invention is limited only by the scope of protection attached.

[0487] Explanation of symbols

[0488] 1—semiconductor device, 2—SiC chip (chip), 21—first main surface electrode (electrode), 30—inorganic insulating layer, 31—organic insulating layer, 34—first opening, 37—second opening, 38—inner periphery of inorganic insulating layer, 41—Ni plating, 42—outer surface plating, 61—semiconductor device, 101—semiconductor device, 153—gate main surface electrode (electrode), 155—source main surface electrode (electrode), 166—first gate opening (first opening), 167—first source opening (first opening), 171—second gate opening (second opening), 172—inner periphery of gate of inorganic insulating layer, 173—second source opening (second opening), 174—inner periphery of source of inorganic insulating layer, 183—first Ni plating, 184—first outer surface plating, 193—second Ni plating, 194—second outer surface plating, 2 01—semiconductor device, 301—semiconductor package, 302—package body, 303—first main surface (first surface), 304—second main surface (second surface), 305A—side surface, 305B—side surface, 305C—side surface, 305D—side surface, 310—first metal plate, 311—first heat dissipation portion, 312—first terminal portion, 320—second metal plate, 321—second heat dissipation portion, 322—second terminal portion, 341—SBD chip (semiconductor device), 342—MISFET chip (semiconductor device), 351—first metal gasket, 352—second metal gasket, T2—thickness of inorganic insulating layer, T4—thickness of Ni plating, T5—thickness of outer surface plating, W—width of inner periphery of inorganic insulating layer, WG—width of inner periphery of gate of inorganic insulating layer, WS—width of inner periphery of source of inorganic insulating layer.

Claims

1. A semiconductor device, characterized in that: include: a chip having a side surface; an electrode formed on the chip; an inorganic insulating layer covering the electrode and exposing the electrode from the first opening; an organic insulating layer covering the inorganic insulating layer and having a second opening having an opening end spaced apart from the opening end of the first opening, wherein the inner peripheral edge of the inorganic insulating layer is exposed in a region between the first opening and the second opening; and a Ni plating layer covering the electrode in the first opening and covering the inner periphery of the inorganic insulating layer in the second opening; The organic insulating layer has a second outer wall located inside the first outer wall of the inorganic insulating layer. The second outer wall is formed along the cutting line at intervals inward from the side surface.

2. The semiconductor device according to claim 1, wherein The first outer wall of the inorganic insulating layer is formed with a gap inward from the side surface.

3. The semiconductor device according to claim 1, wherein The Ni plating layer is formed with a gap from the opening end of the second opening toward the inorganic insulating layer.

4. The semiconductor device according to claim 1, wherein It also includes an outer surface plating layer covering the outer surface of the Ni plating layer in the second opening.

5. The semiconductor device according to claim 4, wherein The outer surface plating layer has a thickness smaller than that of the Ni plating layer.

6. The semiconductor device according to any one of claims 1 to 5, wherein: The inner peripheral edge of the inorganic insulating layer has a width exceeding the thickness of the inorganic insulating layer.

7. The semiconductor device according to any one of claims 1 to 5, wherein: The second outer wall of the organic insulating layer is formed in a curved shape that is recessed toward the inorganic insulating layer.

8. The semiconductor device according to any one of claims 1 to 5, wherein: The above-mentioned chip is composed of a SiC chip.

9. The semiconductor device according to any one of claims 1 to 5, wherein: Also included are transistors formed on the above chip.

10. The semiconductor device according to claim 9, wherein The transistor includes a plurality of unit cells extending in a stripe shape.

11. The semiconductor device according to claim 10, wherein The transistor includes a plurality of trench gate structures extending in a stripe shape along the plurality of unit cells.

12. The semiconductor device according to claim 11, wherein The chip has a rectangular shape when viewed from above. The plurality of trench gate structures extend along the short sides of the chip.

13. The semiconductor device according to any one of claims 1 to 5, wherein: The chip has a rectangular shape in a plan view.

14. The semiconductor device according to any one of claims 1 to 5, wherein: The chip has a first main surface covered by the electrode and a second main surface on the opposite side. It also includes a back electrode covering the second main surface, The back electrode includes a Ti layer.

15. The semiconductor device according to any one of claims 1 to 5, wherein: The chip has a first main surface covered by the electrode and a second main surface on the opposite side. It also includes a back electrode covering the second main surface, The back electrode includes a Ni layer.

16. A semiconductor package, characterized in that: include: a resin package body; a plate-shaped member disposed in the package body and comprising copper; as well as The semiconductor device according to any one of claims 1 to 15, wherein the semiconductor device is disposed in the package body, wherein the electrode includes a source pad electrode. The plate-shaped member is electrically connected to the source pad electrode.

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