Package substrate and manufacturing method for improving warpage thereof

Abstract

The invention relates to the technical field of high-density packaging substrates, in particular to a packaging substrate and a manufacturing method of the packaging substrate for improving warpage, the packaging substrate comprises metal layers and dielectric layers, a plurality of metal layers and a plurality of dielectric layers are alternately connected at intervals to form the substrate, and the topmost layer and the bottommost layer of the substrate are the metal layers; a plurality of through holes are formed in the substrate, gold plating layers are plated in the through holes, the through holes are filled with the gold plating layers, and the multiple metal layers and the dielectric layer are connected; the problems that after an existing substrate is thinned, the flexural rigidity of the substrate is reduced, the substrate is prone to warping, and the surface mounting yield and reliability of a chip and the substrate can be affected by warping of substrate strips exceeding a certain limit are solved; after the substrate is thinned, the flexural rigidity of the substrate is improved, the substrate is not easy to warp, and the mounting yield and reliability of the substrate are greatly improved.

Description

Technical Field

[0001] The present invention relates to the technical field of high-density packaging substrates, and in particular to a packaging substrate and a method for manufacturing an improved warpage thereof. Background Art

[0002] High-density packaging substrates are a core component of modern electronic packaging technology, primarily used to achieve high-reliability electrical interconnection and mechanical support between chips and external circuits. As a key carrier of advanced packaging architectures, they utilize micron-level routing and high-precision via technology to enable complex interconnection of numerous I / O ports within a limited space, while simultaneously fulfilling multiple functions including signal transmission, power distribution, thermal management, and physical protection.

[0003] With the advancement of heterogeneous integration technology, the next generation of high-density packaging substrates is exhibiting three key technical characteristics: first, embedded passive component technology, which further increases integration density by integrating capacitors and inductors within the substrate; second, the hybrid application of silicon interposers, enabling ultra-high-frequency signal transmission in 2.5D / 3D packaging; and third, innovative thermal management materials, such as thermally conductive adhesives infused with diamond particles or graphene heat dissipation layers, which increase thermal conductivity by 5-8 times that of traditional materials. These technological advances enable modern packaging substrates to support high-speed signal transmission exceeding 10Gbps while maintaining a thin and lightweight design (down to 50μm) and meeting the stringent power density requirements (>100W / cm²) of high-performance devices such as artificial intelligence chips.

[0004] As a core component of integrated circuit (IC) packaging, high-density packaging substrates play a key role in forming a first-level interconnect with the chip. Thinner packaging substrates help reduce package size and achieve better electrical performance.

[0005] However, as existing substrates become thinner, their bending stiffness decreases and they are prone to warping. If the substrate warping exceeds a certain limit, it will affect the yield and reliability of chip and substrate mounting. Summary of the Invention

[0006] The purpose of the present invention is to solve the problem that after the existing substrate is thinned, its own bending rigidity decreases and it is easy to warp. The warping of the substrate strip exceeding a certain limit will affect the mounting yield and reliability of the chip and the substrate. After the substrate is thinned, its own bending rigidity is improved and it is not easy to warp, which greatly improves the mounting yield and reliability of the substrate.

[0007] In order to solve the above technical problems, the present invention provides the following technical solutions: A packaging substrate, comprising: a metal layer and a dielectric layer, wherein a plurality of the metal layers and the dielectric layers are alternately connected with each other to form a substrate, and the topmost layer and the bottommost layer of the substrate are metal layers; The substrate is provided with a plurality of through holes, and a gold-plated layer is plated in the plurality of through holes. The through holes are filled with the gold-plated layer to connect the multiple metal layers and the dielectric layer.

[0008] As a preferred solution of the packaging substrate and the method for manufacturing the improved warpage thereof described in the present invention, a metal grid is provided in the ineffective substrate area on the edge of the substrate, and the plurality of through holes are located in the ineffective substrate area within the metal grid holes.

[0009] As a preferred solution of the packaging substrate and the method for manufacturing the improved warpage thereof according to the present invention, the hole pitch of the plurality of through holes in the X-axis direction and the Y-axis direction is between 60um and 150um.

[0010] As a preferred solution of the packaging substrate and the method for manufacturing the improved warpage thereof according to the present invention, the depth of the through hole is between 25um and 90um.

[0011] As a preferred solution of the packaging substrate and the method for manufacturing the improved warpage thereof according to the present invention, the through hole is a circular hole, and the diameter of the circular hole is between 60um and 200um.

[0012] As a preferred solution of the packaging substrate and the method for manufacturing the improved warpage thereof according to the present invention, the through hole is an SPV slot, and the size of the SPV slot is between 100*155um and 100*400um.

[0013] As a preferred solution of the packaging substrate and the method for manufacturing the improved warpage thereof according to the present invention, the metal grid is a copper mesh.

[0014] As a preferred solution of the packaging substrate and the method for manufacturing the improved warpage thereof according to the present invention, the metal layer and the gold-plated layer are both made of copper.

[0015] As a preferred solution of the packaging substrate and the method for manufacturing the improved warpage thereof according to the present invention, the dielectric layer is PP.

[0016] A method for improving warpage comprises the following steps: S1: Multiple metal layers and multiple dielectric layers are alternately and tightly connected by pressing; S2: setting a metal grid on the ineffective substrate area on the edge of the substrate; S3: opening a plurality of through holes in the metal mesh hole; S4: Plating gold in multiple through holes; S5: Repeat steps S1 to S4 to continue adding layers.

[0017] Beneficial effects of the present invention: 1. The present invention opens through holes of different sizes and shapes in the ineffective base material area on the edge of the substrate, and plates a gold layer inside the through holes, so that the gold layer penetrates the metal layer and the dielectric layer, fixes all the metal layers and the dielectric layer, improves the connection between all the metal layers and the dielectric layer, prevents the metal layers and the dielectric layer from delamination, and at the same time, prevents the substrate from warping, thereby greatly improving the substrate mounting yield and reliability.

[0018] 2. The present invention designs the through holes into different shapes, such as circular holes or SPV slots. The shapes and sizes of the through holes are different. The size of the circular holes or SPV slots is selected according to actual needs. The number of circular holes or SPV slots can be determined according to the size of the ineffective substrate area on the edge of the substrate, thereby maximally fixing the ineffective substrate area on the edge of the substrate, improving the rigidity of the substrate, preventing delamination or warping of the substrate, and improving the assembly yield and reliability between the substrate and the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of a substrate in an embodiment of the present disclosure.

[0020] Figure 2 1 is a top view of the substrate in an embodiment of the present disclosure.

[0021] Figure 3 In the embodiment of the present disclosure Figure 2 Enlarged view of point A above.

[0022] Figure 4 Schematic diagram of a through hole in an embodiment of the present disclosure being a stacked hole.

[0023] Figure 5 Schematic diagram of a metal grid on an inactive substrate area in an embodiment of the present disclosure.

[0024] Reference numerals: 1. metal layer; 2. dielectric layer; 3. substrate; 4. through hole; 5. gold-plated layer; 6. metal grid. DETAILED DESCRIPTION

[0025] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0026] Example 1:

[0027] Reference Figures 1 to 3 As shown, this embodiment provides a packaging substrate and a method for improving warpage thereof. A packaging substrate, comprising: a metal layer 1 and a dielectric layer 2, wherein a plurality of metal layers 1 and a plurality of dielectric layers 2 are alternately connected to form a substrate 3, and the topmost and bottommost layers of the substrate 3 are the metal layers 1; Reference Figure 1 and Figure 3 As shown, a plurality of through holes 4 are provided on the substrate 3 , and a gold-plated layer 5 is plated inside the plurality of through holes 4 . The gold-plated layer 5 is used to fill the through holes 4 , thereby connecting the multi-layer metal layer 1 and the dielectric layer 2 .

[0028] The size of the through hole 4 also needs to be designed according to actual needs, and the gold-plated layer 5 is copper, which can fix the multi-layer structure and ensure that the gold-plated layer 5 can fix all layers to the greatest extent.

[0029] By opening a plurality of through holes 4 on the substrate 3 and plating a gold layer 5 in the through holes 4, the overall rigidity of the substrate 3 is improved, and the connection between the metal layer 1 and the dielectric layer 2 is strengthened, thereby preventing delamination or warping between the metal layer 1 and the dielectric layer 2.

[0030] Specifically, the alternatingly connected metal layers and dielectric layers 2 constitute the main body of the substrate 3. The metal layer is distributed in the outermost layer to enhance the surface rigidity. The stress distribution of different materials is balanced through the alternating layout between the layers to avoid deformation caused by the concentration of a single material. A through hole 4 is opened inside the substrate 3 and a metal layer is plated, so that a mechanical anchor point penetrating the structure is formed between the metal layers. The metallurgical bonding between the metal plating layer and each layer of material enhances the interlayer fixing effect, and suppresses delamination or warping caused by differences in thermal expansion coefficients or external forces. The through holes are densely distributed in the invalid area of ​​the substrate 3, which not only avoids interference with the effective circuit area, but also achieves uniform support of the overall structure through a grid layout, further improving the planar stability of the packaging substrate.

[0031] Through-holes 4 of various sizes and shapes are precisely designed and opened within the inactive substrate area at the edge of substrate 3. Advanced electroplating processes are then used to form a continuous, complete gold-plated layer 5 within the holes. This gold-plated layer 5 penetrates the entire metal layer 1 and dielectric layer 2 of substrate 3, forming a three-dimensional interconnect network. This achieves the following technological breakthroughs: First, the mechanical anchoring effect of the gold-plated layer 5 significantly enhances the bonding strength between each metal layer 1 and dielectric layer 2, effectively resolving the interlayer separation issue common in traditional substrates 3. Second, this through-hole metal connection structure evenly distributes thermal stress, significantly reducing the risk of warping and deformation of substrate 3 during temperature cycling. Finally, this structural optimization significantly improves the flatness and stability of substrate 3 during subsequent chip placement, thereby increasing placement yield by over 30% and extending the product's service life and reliability.

[0032] Reference Figure 2 and Figure 3As shown, a metal grid 6 is provided in the inactive substrate area at the edge of the substrate 3, and multiple through-holes 4 are located in the inactive substrate area within the holes of the metal grid 6. Furthermore, a metal grid 6 is provided in the inactive substrate area around the edge of the substrate 3, and through-holes 4 are provided within the holes of the metal grid 6. The entire through-hole 4 will be plated with a gold layer 5 that penetrates the interior of the through-hole 4, thereby connecting the entire metal layer 1 and the dielectric layer 2.

[0033] By setting a metal grid 6 in the ineffective substrate area at the edge of the substrate 3, and the metal grid 6 set in the ineffective substrate area on the edge of the substrate 3 can have different shapes, the metal grid 6 can be changed according to actual needs, and the structural characteristics of the metal grid 6 are used to disperse the mechanical stress generated during processing, thereby reducing the risk of local stress concentration. The through hole 4 is limited to the ineffective substrate area within the hole of the metal grid 6, which not only ensures the function of the through hole 3 to fix the metal layer and the dielectric layer, but also avoids the decrease in structural strength of the edge area caused by the dense arrangement of the through holes through the constraint effect of the grid on the surrounding materials. The introduction of the metal grid 6 forms a physical support network, which enhances the deformation resistance of the edge area of ​​the board. At the same time, the coordinated layout of the through hole 4 and the grid can balance the difference in thermal expansion coefficient of different areas of the substrate 3, thereby suppressing the occurrence of warping from both structural and material dimensions.

[0034] It should be noted that the through hole 4 is opened in the invalid base material area on the substrate 3. This is also to open the through hole 4 on the edge of the substrate 3 without affecting the function of the middle part of the substrate 3, and to plate metal copper in the through hole 4, so as to fix all the metal layers 1 and the dielectric layer 2, and prevent delamination or warping between the metal layers 1 or the dielectric layers 2, thereby affecting the mounting yield and reliability between the entire substrate 3 and the chip.

[0035] The metal grid 6 is provided in the ineffective substrate area. After the through holes 4 in the metal grid 6 are copper plated, the metal grid 6 can further enhance the stability of the ineffective substrate area on the edge of the substrate 3 .

[0036] The hole pitch of the plurality of through holes 4 in the X-axis direction and the Y-axis direction is between 60 μm and 150 μm.

[0037] By controlling the pitch of through-holes 4 in the X- and Y-axis directions to between 60 μm and 150 μm, the spatial distribution density of through-holes 4 is optimized. Limiting the pitch range in the X-axis ensures the continuity of the lateral structural support and avoids localized rigidity loss due to excessive pitch. Simultaneously constraining the pitch in the Y-axis balances the longitudinal stress distribution and prevents deformation of substrate 3 due to anisotropy. This spacing range avoids the increased processing difficulty and weakening of the material caused by too small a pitch, while also preventing the insufficient bonding between the metal layer and dielectric layer 2 caused by too large a pitch, thereby improving the overall bending stiffness of substrate 3.

[0038] The depth of the through hole 4 is between 25um and 90um. By limiting the specific range of the depth of the through hole 4, the mechanical properties of the interlayer fixing structure of the substrate 3 are optimized. Controlling the depth of the through hole 4 in the range of 25um-90um not only ensures that the gold-plated layer 5 can form a sufficient anchoring depth to enhance the interlayer bonding force, but also avoids the degradation of the mechanical strength of the dielectric layer 2 caused by the overly deep hole structure. Specifically, the setting of the lower limit of 25um ensures that the vertical fixing force of the metal plating layer can effectively offset the deformation stress of the substrate 3, while the upper limit of 90um prevents the destruction of the continuity of the dielectric layer by over-deep drilling. This coordinated control of the depth range enables the through hole 4 structure to maintain the overall structural integrity of the substrate 3 while enhancing the interlayer constraint, thereby effectively suppressing warping deformation under thinning conditions.

[0039] The through hole 4 can be opened by drilling. The required depth of the through hole 4 is determined according to actual needs and the thickness of the substrate 3. After the drilling is completed, a gold-plated layer 5 can be plated in the through hole 4 to fix the metal layer 1 and the dielectric layer 2, thereby preventing the substrate 3 from delamination and warping, and further improving the rigidity of the substrate 3.

[0040] It should be noted that the hole pitch of the through hole 4 in the X-axis direction and the Y-axis direction is coordinated with the size of the through hole 4. The hole pitch of the through hole 4 changes with the size of the through hole 4. Similarly, the depth of the through hole 4 will also change with the size of the through hole 4. It is determined according to actual needs and the size of the ineffective substrate area on the substrate 3, so as to maximize the fixed connection between the metal layer 1 and the dielectric layer 2 to prevent the substrate 3 from delamination or warping.

[0041] The through hole 4 is a circular hole, and the diameter of the circular hole is between 60um and 200um.

[0042] By limiting the through hole 4 to a circular hole and controlling its diameter range, the structure of the through hole 4 is optimized from both geometric shape and size dimensions. Compared to irregular holes, the circular hole structure can avoid stress concentration, and the evenly distributed circular holes are conducive to forming a symmetrical metal reinforcement network in the substrate 3, thereby improving the deformation resistance. The diameter range is limited to between 60um and 200um, which not only ensures that the through hole 4 has sufficient cross-sectional area to accommodate the gold-plated layer 5 for reliable connection, but also avoids excessive weakening of the local stiffness of the substrate 3 due to a large diameter or difficulty in filling the metal plating due to a small diameter. This size range selection fully balances mechanical strength and processing feasibility. While meeting the lightweight requirements of the packaging substrate, it ensures that the fixing effect of the plating metal on the alternating layer structure reaches the optimal balance through precise aperture control.

[0043] The through holes 4 are circular holes. Circular holes of different diameters can be provided according to actual needs. The number of circular holes provided is determined according to the spacing between the circular holes and the size of the ineffective substrate area.

[0044] The metal grid 6 is made of copper mesh, which can increase the stability of the ineffective substrate area on the edge of the substrate 3 and prevent the edge of the substrate 3 from being delaminated or warped.

[0045] Both the metal layer 1 and the gold-plated layer 5 are made of copper. The metal grid 6 is made of high-purity electrolytic copper mesh. The copper mesh has excellent electrical conductivity, thermal conductivity, and mechanical strength. Its mesh structure can evenly disperse stress, thereby significantly increasing the structural stability of the ineffective substrate area on the edge of the substrate 3. This design can effectively prevent the edge of the substrate 3 from delamination or warping under thermal cycling or mechanical stress. At the same time, the thermal expansion coefficient of the copper mesh matches that of the substrate 3 material, which can reduce deformation caused by thermal stress. In addition, the flexibility of the copper mesh enables it to adapt to slight deformation of the substrate during manufacturing and use, further improving the reliability of the product.

[0046] Among them, the metal layer 1 serves as a functional conductive layer, responsible for signal transmission and current conduction when the substrate 3 is working normally. Its thickness and pattern design are precisely calculated to meet the electrical performance requirements. The gold-plated layer 5 mainly serves as a structural reinforcement layer. Through its evenly distributed metal properties, it effectively balances the stress distribution of various parts of the substrate 3. Especially in high-temperature processes or changes in ambient temperature, it can significantly suppress the risk of delamination at the edge of the substrate 3. The synergistic effect of the two metal layers not only prevents warping and deformation at the edge of the substrate 3, but also greatly enhances the overall rigidity and dimensional stability of the substrate 3, enabling it to withstand greater mechanical stress and more harsh working environments. This dual-metal layer structural design is particularly suitable for application scenarios with strict requirements on dimensional stability, such as high-density interconnect boards and high-frequency circuit boards.

[0047] The dielectric layer 2 is made of polypropylene (PP). PP has excellent dielectric properties, thermal stability, and adhesive strength, effectively isolating the various circuit layers of the metal layer 1 while providing good interlayer bonding. The dielectric layer 2 and the metal layer 1 (copper foil) are laminated in an alternating fashion. After high-temperature and high-pressure curing, a complete multilayer substrate 3 is formed. This structural design not only ensures signal transmission integrity but also maintains the dimensional stability of the substrate 3 under thermal stress.

[0048] The dielectric layer 2 and the metal layer 1 are alternately stacked one by one to form a complete substrate 3, and the edge of the entire substrate 3 is connected and fixed by the gold-plated layer 5 to avoid delamination or warping, thereby improving the mounting yield and reliability between the substrate 3 and the chip.

[0049] The metal layer 1 is made of copper foil, while the gold-plated layer 5 is copper. Through a copper plating process, copper is plated inside the through-holes 4, thereby increasing the rigidity of the entire substrate 3. The copper foil and dielectric layer 2PP are connected to each other at intervals. The copper plating thickness needs to penetrate all layers at the same location, further securing the entire substrate 3. The overall process follows the normal drilling-copper plating-copper plating process to complete the production of the entire substrate 3.

[0050] To further enhance the mechanical strength of substrate 3 and prevent edge delamination or warping, a gold-plated layer 5 is added to the outermost layer of substrate 3, formed using a copper plating process. The gold-plated layer 5 is interconnected through through-holes 4, allowing the copper layer to penetrate the entire thickness of substrate 3. This design evenly distributes stress and enhances overall rigidity. It effectively suppresses deformation of substrate 3, particularly under high temperature or mechanical shock conditions, thereby improving chip placement yield and long-term reliability.

[0051] Metal layer 1, made of copper foil, serves as the signal transmission layer. Its thickness and pattern must meet the requirements of high-frequency or high-power applications. Gold-plated layer 5, made of electroplated copper, achieves vertical interconnection through vias 4. The copper plating thickness must be uniform and sufficient to ensure mechanical support. The copper foil is alternately laminated with the PP dielectric layer 2, with the copper plating extending through all layers to form a three-dimensional reinforced structure, significantly enhancing the overall rigidity and thermal stability of the substrate 3.

[0052] A method for improving warpage comprises the following steps: S1: Multiple metal layers 1 and multiple dielectric layers 2 are alternately spaced and tightly connected by pressing; Through the hot pressing process, the alternating metal layers 1 and dielectric layers 2 are aligned and stacked, and pressed and cured under the conditions of 10-30 MPa pressure and 180-220°C to form a multi-layer composite substrate 3 with high density, ensuring that both the top and bottom layers are metal layers 1 to meet surface mounting requirements.

[0053] S2: a metal grid 6 is provided on the ineffective substrate area on the edge of the substrate 3; A periodic copper metal grid 6 is formed in the non-functional edge region of substrate 3 (i.e., the inactive substrate area at the edge of the substrate, with a width of 2-5 mm) using photolithography-etching or direct laser patterning technology. The grid line width is 50-100 μm, the grid cell size is 0.5-2 mm², and the grid aperture ratio is 60-80%, balancing structural strength and stress relief requirements.

[0054] S3: Opening a plurality of through holes 4 in the metal mesh 6; Mechanically controlled depth drilling is used to form an array of through-holes 4 within the unit openings of the metal grid 6. These through-holes 4 can be blind, buried, or through-holes, with diameters ranging from 60-200 μm and depths from 25-90 μm. The center-to-center spacing of these holes is equidistant or staggered along the X / Y axis, with a spacing of 60-150 μm to optimize interlayer interconnect density and stress distribution.

[0055] S4: A gold plating layer 5 is plated in the plurality of through holes 4 .

[0056] Using a combination of chemical copper plating and electrolytic copper plating, a dense gold-plated layer 5 (actually a copper layer with a thickness of 15-30μm) is deposited on the inner walls and bottom of the through-hole 4, achieving both metallization and full hole filling. The metallurgical bonding of the gold-plated layer with the metal layer 1 forms a vertical interconnect structure, simultaneously strengthening the mechanical anchoring between the layers and suppressing interlayer separation and warping caused by CTE mismatch.

[0057] Multilayer Lamination: Multiple metal layers 1 and multiple dielectric layers 2 are spaced apart and tightly bonded together through a high-temperature, high-pressure lamination process to form the initial substrate 3 structure. The dielectric layer 2 is typically made of high-performance organic materials to ensure excellent dielectric properties and mechanical strength, while the metal layer 1 (such as copper foil) is used to construct the basic circuit wiring. Metal Grid 6: A metal grid 6 is formed on the inactive substrate area (i.e., non-functional area, typically not used for signal transmission) at the edge of the substrate 3 through photolithography, etching, or laser processing. This metal grid 6 enhances the structural stability of the substrate 3 edge, prevents warping, and provides a positioning reference for subsequent through-hole processing. Hole Processing: Multiple through-holes 4 are created within the grid holes of the metal grid 6 using laser drilling or mechanical drilling. These through-holes 4 are used for subsequent metallization interconnection. A gold layer 5 is deposited within the through-holes 4 through copper electroplating, further interconnecting the metal layer 5 and the dielectric layer 2. This improves the rigidity of the entire substrate 3 and prevents delamination or warping.

[0058] S5: Repeat steps S1 to S4 to continue adding layers.

[0059] like Figure 4 As shown, it should be noted that in the MSAP process, pressing is performed after each layer is added, and then holes are drilled together with the board, and then copper plating is performed, and the through holes 4 between each layer can form mutually staggered through holes 4 or mutually superimposed through holes 4.

[0060] like Figure 5 As shown, on the ineffective substrate area at the edge of the substrate 3, there is no limit on the metal grid 6 between each layer, and dummy pad copper of different shapes or full copper can be used to meet the requirements of interlayer interconnection density and stress distribution optimization.

[0061] Example 2:

[0062] The through hole 4 is an SPV slot, and the size of the SPV slot is between 100*155um and 100*400um.

[0063] By designing the through-hole 4 as an SPV slot structure of a specific size, stress distribution is optimized while enhancing interlayer bonding. Compared to conventional circular holes, the SPV slot increases the contact area between the metal plating and the dielectric layer 2 by extending the hole edge length, enhancing the mechanical anchoring effect. Limiting the slot width to 100 μm and the length to 155-400 μm ensures sufficient fixing strength while avoiding the loss of effective substrate support area caused by overly large holes and preventing insufficient plating filling caused by undersized holes. This size range balances warpage resistance and processing feasibility, allowing the slot to form an effective stress-dispersing structure without affecting production yield due to insufficient processing precision.

[0064] Different from Example 1, the through hole 4 in this embodiment is an SPV slot, and the sizes of the SPV slots are 100*155um, 100*160um, and 100*400um. In actual hole opening, the number of SPV slots can be determined according to the size of the SPV slots, the spacing between the SPV slots, and the ineffective substrate area.

[0065] The SPV slots are copper plated to fix the metal layer 1 and the dielectric layer 2 to the maximum extent possible, thereby preventing delamination or warping between the metal layer 1 and the dielectric layer 2, which would affect the mounting yield and reliability between the chip and the substrate 3.

[0066] Table 1 below shows experimental data of warping of the substrate 3 when the through hole 4 is provided and when the through hole 4 is not provided; Table 1: This table shows the warping test data of substrate 3 As shown in Table 1 above, by opening a through hole 4 in the ineffective substrate area on the edge of the substrate 3 and copper plating the inside of the through hole 4, the connection between each first metal and the dielectric layer 2 can be greatly improved, thereby greatly improving the rigidity of the substrate 3 and reducing warpage. The extent of warpage is also within the specification requirements, which greatly improves the placement yield and reliability of the substrate 3. In contrast, in the comparison experiment, the substrate 3 without holes has no holes in the ineffective base material area on the edge of the substrate 3. Therefore, the overall rigidity of the substrate 3 is low, and the warping amplitude is large, exceeding the specification requirements, reducing the assembly yield and reliability of the substrate 3.

[0067] The embodiments of the present application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of this application.

Claims

1. A packaging substrate, comprising: A metal layer (1) and a dielectric layer (2), wherein a plurality of the metal layers (1) and a plurality of the dielectric layers (2) are alternately connected with each other at intervals to form a substrate (3), and the topmost layer and the bottommost layer of the substrate (3) are the metal layers (1); The invention is characterized in that: a plurality of through holes (4) are provided on the substrate (3), a gold-plated layer (5) is plated in the plurality of through holes (4), and the through holes (4) are filled with the gold-plated layer (5) to connect the multi-layer metal layer (1) and the dielectric layer (2).

2. The packaging substrate according to claim 1, wherein: A metal grid (6) is provided in the invalid substrate area on the upper edge of the substrate (3), and the plurality of through holes (4) are located in the invalid substrate area within the holes of the metal grid (6).

3. The packaging substrate according to claim 1, wherein: The hole pitch of the plurality of through holes (4) in the X-axis direction and the Y-axis direction is between 60 μm and 150 μm.

4. The packaging substrate according to claim 1, wherein: The depth of the through hole (4) is between 25um and 90um.

5. The packaging substrate according to claim 1, wherein: The through hole (4) is a circular hole, and the diameter of the circular hole is between 60um and 200um.

6. The packaging substrate according to claim 1, wherein: The through hole (4) is an SPV slot, and the size of the SPV slot is between 100*155um and 100*400um.

7. The packaging substrate according to claim 2, wherein: The metal grid (6) is made of copper mesh.

8. The packaging substrate according to claim 1, wherein: The metal layer (1) and the gold-plated layer (5) are both made of copper.

9. The packaging substrate according to claim 1, wherein: The medium layer (2) is PP.

10. A method for improving warpage manufacturing, using a packaging substrate according to any one of claims 1 to 9, characterized in that: The steps include: S1: alternately and spaced apart from each other, the plurality of metal layers (1) and the plurality of dielectric layers (2) are tightly connected by pressing; S2: Arranging a metal grid (6) on an ineffective substrate area on the upper edge of the substrate (3); S3: opening a plurality of through holes (4) in the metal mesh (6); S4: Plating a gold layer (5) in the plurality of through holes (4); S5: Repeat steps S1 to S4 to continue adding layers.

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