Semiconductor device and method of manufacturing semiconductor device

Abstract

The invention provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a base layer and an interconnect structure on the base layer, the interconnect structure including: a first metal line on the base layer; a first top via vertically protruding from the first metal line, without a connection surface between the first top via and the first metal line; an isolation layer on the first metal line and the first top via; and a planarization stop layer vertically and laterally on the isolation layer.

Description

Technical Field

[0001] Apparatuses and methods consistent with example embodiments of the present disclosure relate to a semiconductor device including an interconnect structure in which a planarization stop layer is formed on a metal line. Background Art

[0002] The performance of semiconductor devices is affected by how the interconnect structures are formed in the semiconductor devices. The interconnect structures include back-end-of-line (BEOL) structures (such as metal lines and vias), which connect front-end-of-line (FEOL) structures to voltage sources or other circuit elements through middle-of-line (MOL) structures. The interconnect structures also include dielectric layers surrounding the metal lines and vias to electrically isolate these metal structures from each other or from other circuit elements. The FEOL structures include transistor structures (such as channel structures, source / drain regions, and gate structures), and the MOL structures include contact plugs formed on the source / drain regions and gate structures.

[0003] As semiconductor devices are developed to have high device density and performance, the design and formation of interconnect structures of semiconductor devices have become more difficult and complex, while improved resistance-capacitance (RC) characteristics are required for semiconductor devices.

[0004] The information disclosed in this background section was known to the inventors before implementing the embodiments of this application, or was technical information acquired during the implementation of the embodiments described herein. Therefore, it may contain information that does not form prior art already known to the public. Summary of the Invention

[0005] The present disclosure provides a method for forming an interconnect structure through two planarization operations to avoid possible via loss in an intermetal dielectric (IMD) layer surrounding metal lines and vias formed thereon and recesses on the IMD layer, thereby improving the connection performance of the interconnect structure and preventing short circuit risks.

[0006] According to an aspect of one or more embodiments, a semiconductor device is provided, comprising a base layer and an interconnect structure on the base layer, the interconnect structure comprising: a first metal line on the base layer; a first top via protruding vertically from the first metal line, with no connection surface between the first top via and the first metal line; an isolation layer on the first metal line and the first top via; and a planarization stop layer vertically and laterally on the isolation layer.

[0007] According to an aspect of one or more embodiments, there is provided a semiconductor device including a base layer and an interconnect structure on the base layer, the interconnect structure including: a metal line on the base layer; a top via protruding vertically from the metal line, with no connection surface between the top via and the metal line; an isolation layer vertically on the metal line and laterally on the top via; and an open area on the base layer, in which no metal line is formed at a level where the metal line is provided, wherein the open area includes at least two dielectric layers, the at least two dielectric layers including the isolation layer vertically on the base layer.

[0008] According to an aspect of one or more embodiments, there is provided a method for manufacturing a semiconductor device, the method comprising: patterning an initial metal structure to form a metal line and a top via on the metal line such that the top via protrudes from the metal line; forming at least two dielectric layers vertically stacked on the metal line having the top via thereon; performing a first planarization such that the first planarization stops at a level above a top surface of the top via; and performing a second planarization such that the top surface of the top via is exposed. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0010] Figure 1A-Figure 1C A semiconductor device including an interconnect structure according to one or more embodiments is shown.

[0011] Figure 2 A semiconductor device is shown including an interconnect structure in which a top via has experienced via loss.

[0012] Figure 3 A semiconductor device including an interconnect structure in which IMD recess has occurred is shown.

[0013] Figure 4A-Figure 4R A side cross-sectional view of a semiconductor device including an intermediate interconnect structure in which a planarization stop layer is formed in an isolation layer is shown after respective steps of fabricating the semiconductor device according to one or more embodiments.

[0014] Figures 5A-5I A side cross-sectional view of a semiconductor device including an intermediate interconnect structure is shown after respective steps of fabricating the semiconductor device including the interconnect structure in which the isolation layer itself serves as a planarization stop layer in accordance with one or more embodiments.

[0015] Figure 6A Reference to one or more embodiments is shown Figure 4A-Figure 4RA flow chart of a method of manufacturing a semiconductor device including an interconnect structure in which a planarization stop layer is formed in an isolation layer.

[0016] Figure 6B Reference to one or more embodiments is shown Figures 5A-5I A flow chart of a method of manufacturing a semiconductor device including an interconnect structure in which an isolation layer serves as a planarization stop layer.

[0017] Figure 7 is a block diagram of a system on chip (SoC) 1000 including a semiconductor device in which a Figure 4N The interconnect structure 40 and Figure 5E At least one of the interconnect structures 50 shown in FIG. DETAILED DESCRIPTION

[0018] The embodiments of the present disclosure described herein are example embodiments, and therefore, the present disclosure is not limited thereto and may be implemented in various other forms. Each embodiment provided in the following description does not exclude association with one or more features of another example or another embodiment that is also provided here or not provided here but consistent with the present disclosure. For example, even if a matter described in a particular example or embodiment is not described in an example or embodiment different from it, the matter may be understood to be associated with or combined with different examples or embodiments unless otherwise mentioned in its description. In addition, it should be understood that all descriptions of the principles, aspects, examples and embodiments of the present disclosure are intended to cover their structural and functional equivalents. In addition, these equivalents should be understood to include not only currently known equivalents, but also equivalents to be developed in the future, that is, all devices invented for performing the same function, regardless of their structure. For example, the channel layer, sacrificial layer and isolation layer described here may take different types or forms, as long as the present disclosure can be applied thereto.

[0019] It will be understood that when an element, component, layer, pattern, structure, region, etc. of a semiconductor device (hereinafter collectively referred to as an "element") is referred to as being "above," "over," "upper," "below," "under," "down," "connected to," or "coupled to" another element of the semiconductor device, it may be directly above, above, above, below, below, down, directly connected to, or coupled to the other element, or there may be intervening elements. Conversely, when an element of a semiconductor device is referred to as being "directly above," "directly on," "directly below," "directly below," "directly below," "directly below," "directly connected to," or "directly coupled to" another element of the semiconductor device, there are no intervening elements. Throughout this disclosure, like reference numerals refer to like elements.

[0020] For ease of description, spatially relative terms such as "above", "upper", "below", "below", "lower", "left", "right", "lower left", "lower right", "upper left", "upper right", "center", "middle", etc. may be used herein to describe the relationship of one element to another element(s) as shown in the accompanying drawings. It will be understood that spatially relative terms are intended to encompass different orientations of the semiconductor device in use or operation other than the orientation depicted in the accompanying drawings. For example, if the semiconductor device in the accompanying drawings is flipped, an element described as being "below" or "beneath" another element will be oriented "above" the other element. Thus, the term "below" may include both above and below orientations. The semiconductor device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein are interpreted accordingly. As another example, elements referred to as "left" and "right" elements may be "right" and "left" elements when the device or structure including these elements is oriented differently. Thus, in the following description, the "left" and "right" elements may also be referred to as "first" and "second" elements, respectively, as long as their structural relationship is clearly understood in the context of the description. Similarly, the terms "lower" element and "upper" element may be referred to as a "first" element and a "second" element, respectively, with the necessary description to distinguish the two elements.

[0021] It will be understood that although the terms "first," "second," "third," "fourth," "fifth," "sixth," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, the first element discussed below could be termed the second element without departing from the teachings of the present disclosure.

[0022] As used herein, expressions such as "at least one of," when following a list of elements, modify the entire list of elements, rather than modifying the individual elements of the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. Herein, when the terms "same" or "equal" are used to compare the dimensions of two or more elements, the terms may encompass dimensions that are "substantially the same" or "substantially equal." In one or more examples, when a specified parameter X may be "substantially the same" as a parameter Y, the term "substantially" may be understood to mean that X is within 5% of Y. In one or more examples, when a specified parameter is approximately X, the term "approximately" may be understood to mean that X is within 5% of X.

[0023] It will also be understood that even if a step or operation of manufacturing a device or structure is described as occurring later than another step or operation, the step or operation may be performed earlier than the other step or operation unless the other step or operation is described as being performed after the step or operation.

[0024] Many embodiments are described herein with reference to cross-sectional views, which are schematic diagrams of the embodiments (and intermediate structures). Therefore, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments should not be interpreted as limited to the specific shapes of the regions shown here, but rather include shape deviations due to, for example, manufacturing. The various regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of the regions of the device and are not intended to limit the scope of the present disclosure. In addition, in the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

[0025] For the sake of brevity, conventional elements of a semiconductor device may or may not be described in detail herein or shown in the accompanying drawings. For example, MOL or FEOL structures may not be shown or described in detail when these structures are not relevant to the concepts of the present disclosure.

[0026] Hereinafter, various embodiments of the present disclosure are described with reference to the accompanying drawings.

[0027] Figure 1A-Figure 1C A semiconductor device including an interconnect structure according to one or more embodiments is shown.

[0028] Figure 1A is a plan view of a semiconductor device, Figure 1B The semiconductor device is along Figure 1A The side cross-sectional view taken along line II' is shown. Figure 1C The semiconductor device is along Figure 1AA side sectional view taken along line II-II' is shown.

[0029] Reference Figure 1A-Figure 1C The interconnect structure 10 formed in the BEOL process may be disposed on a base layer 100. Here, the base layer 100 may be a BEOL layer including another interconnect structure, a middle of line (MOL) layer, or a front end of line (FEOL) layer forming a transistor structure of a semiconductor device. According to one or more other embodiments, the base layer 100 may be a substrate or a carrier substrate.

[0030] The interconnect structure 10 may include a plurality of M1 metal lines M11-M15 at the M1 level (or M1 metal layer), a plurality of top vias V1-V4 on the M1 metal lines M11, M12, M14, and M15, and a plurality of M2 metal lines M21-M23 at the M2 level (or M2 metal layer) directly above the M1 level in the D3 direction. The M1 metal lines, the top vias, and the M2 metal lines may be surrounded by inter-metal dielectric (IMD) layers 110 and 120, respectively, which are electrically isolated or insulating structures. It will be understood herein that Figure 1A The positional relationship between the M1 metal lines M11-M15 and the M2 metal lines M21-M23 is shown with the top vias V1-V4 therebetween, so for visibility purposes, the IMD layers 110 and 120 are not shown. Figure 1A Shown in.

[0031] The M1 metal lines can be arranged in the D1 direction at a predetermined pitch and extend in the D2 direction. The M2 metal lines formed above the M1 metal lines can be arranged in the D2 direction at a predetermined pitch and extend in the D1 direction. The top vias V1-V4 are between the M1 metal lines and the M2 metal lines. The M1 metal lines can each have the same width in the D1 direction, and the M2 metal lines can each have the same width in the D2 direction. The width of the M2 metal lines can be the same as or different from the width of the M1 metal lines. However, the present disclosure is not limited to this. According to one or more other embodiments, the M1 metal lines and the M2 metal lines can be arranged without the predetermined pitch and can have different widths respectively. The D1 direction and the D2 direction are each horizontal directions and intersect each other. The D3 direction is a vertical direction intersecting the D1 direction and the D2 direction.

[0032] Top via V1 may connect M1 metal wire M11 with M2 metal wire M21 , top via V2 may connect M1 metal wire M12 with M2 metal wire M22 , top via V3 may connect M1 metal wire M14 with M2 metal wire M22 , and top via V4 may connect M1 metal wire M15 with M2 metal wire M23 .

[0033] It should be noted here that the M1 metal line can be formed in the lowest layer among the BEOL layers. However, the present disclosure is not limited thereto, and there may be one or more other metal lines and vias below the M1 metal line to form an extended interconnect structure of the semiconductor device. In addition, the number of metal lines and top vias is not limited to Figure 1A Those shown to form the interconnect structure 10 .

[0034] The interconnect structure 10 can be formed by a top via process, wherein top vias V1-V4 are respectively formed from underlying metal lines. For example, top via V1 can be formed from M1 metal line M11, top via V2 can be formed from M1 metal line M12, top via V3 can be formed from M1 metal line M14, and top via V4 can be formed from M1 metal line M15. Thus, each of the top vias V1-V4 can be part of the corresponding underlying M1 metal line itself, and each of the top vias V1-V4 and the corresponding underlying M1 metal line can be a single continuous structure with no boundaries, connecting surfaces, or interfaces between them, unlike a damascene metal line and a damascene via formed thereon by a corresponding damascene process. Each of these top vias V1-V4 can take the form of a pillar-like protrusion on the underlying metal line.

[0035] Via structures like each of the top vias V1-V4 are introduced to reduce the contact resistance between the metal lines and vias formed thereon using conventional damascene processes, which adversely affect at least the connectivity performance of semiconductor devices including the metal lines and vias. For at least the aforementioned purposes and to facilitate the top via process, a metal such as ruthenium (Ru) may be patterned to form the M1 metal lines M11-M15 having the top vias V1-V4 thereon. Alternatively, molybdenum (Mo) or cobalt (Co) may be patterned to form the M1 metal lines M11-M15 having the top vias V1-V4 thereon, without limitation.

[0036] A bottom liner 101 may be formed at a bottom surface of each M1 metal line, the bottom liner 101 reducing contact resistance between each M1 metal line and underlying structures in the base layer 100 and providing adhesion properties therebetween. The bottom liner 101 may be formed of a material such as titanium nitride (TiN), tantalum nitride (TaN), or the like, without being limited thereto.

[0037] A sidewall liner 102 may be formed at the side surface of each of the M1 metal line, the M2 metal line, and the top via, and the sidewall liner 102 prevents or reduces electromigration of metal atoms (e.g., Ru) into the IMD layers 110 and 120, which are formed of a low-k material (such as silicon oxide (SiO2), etc., but not limited thereto) to isolate the M1 metal line and the top via from each other and the M2 metal lines from each other. The sidewall liner 102 may also provide adhesion properties between the IMD layers 110 and 120 and the M1 metal line, the M2 metal line, and the top via. The sidewall liner 102 may be formed of a material such as a composite of silicon nitride (e.g., SiCN, SiBCN, etc.), but not limited thereto. It will be understood here that for the purpose of simplicity, Figure 1A The sidewall liner 102 is not shown.

[0038] When the M1 metal line and the M2 metal line and the top via are formed of ruthenium (Ru), which provides lower resistance and reduced electromigration properties than other metal materials such as copper (Cu), sidewall liner 102 may not be formed at the side surfaces of these metal structures. However, in order to more effectively prevent or reduce electromigration of metal atoms, sidewall liner 102 may be formed even at the side surfaces of the metal structure of interconnect structure 10 when the metal structure is formed of ruthenium (Ru).

[0039] Taking advantage of the material properties (e.g., porosity) of low-k materials (e.g., SiO2) and the small pitch of the M1 metal lines, the interconnect structure 10 can also be formed to include one or more air gaps 113 between at least some of the adjacent M1 metal lines in the IMD layer 110. By forming the air gaps 113 in the IMD layer 110, the isolation or insulation properties between adjacent M1 metal lines and between the M1 metal lines and the adjacent top vias can be increased to further improve the interconnect performance of the semiconductor device including the interconnect structure 10. The formation of the air gaps 113 can be further facilitated by the sidewall liners 102, which reduce the already small metal pitch.

[0040] Meanwhile, in the interconnect structure 10, the M1 metal line having the top via thereon may be formed such that: (i) the M1 metal line is first patterned from an initial metal structure (e.g., Ru) by, for example, direct etching thereof; (ii) portions of the M1 metal line where the top via will be formed are masked, and based on the masking, the M1 metal line is recessed to form the top via on the M1 metal line, respectively; (iii) a sidewall liner 102 may be optionally formed to surround the M1 metal line having the top via thereon; (iv) an IMD layer 110 is formed to surround the M1 metal line having the top via thereon; and (v) the IMD layer 110 is planarized by, for example, chemical mechanical polishing (CMP) to expose the top surface of the top via passing through the IMD layer 110 for connection to the M2 metal line above.

[0041] However, since the global density of top vias is typically very low in the interconnect structure 10 (ie, the number of top vias V1-V4 is very small), such as 1-3%, compared to the entire area of ​​the interconnect structure 10, as shown in FIG. Figure 1A As shown, even if the target heights of the top vias V1-V4 are known, it is very difficult to immediately stop the IMD planarization operation (v) applied to the IMD layer 110 after the top surface of the top via is detected or exposed. As a result, at least one of the top vias on the M1 metal line may be over-polished (e.g., over-CMP), resulting in via loss of the at least one of the top vias. For example, Figure 2 As shown, in Figure 1B In interconnect structure 20, which corresponds to interconnect structure 10, path loss may occur in top via V2 on M1 metal line M12, while path loss may not occur in top via V4. In this example, due to over-polishing, a portion of M1 metal line M12, along with IMD layer 110 surrounding M1 metal line M12, is recessed below level L where the M2 metal line is to be formed. When path loss occurs randomly in this manner, the subsequent operation of forming the upper M2 metal line to contact the top via may become incomplete and unreliable due to the varying heights of the top vias.

[0042] In another example, the top via can be detected early in the IMD planarization operation (v) to stop this operation in time and expose the top surface of the top via, thereby preventing via loss. Figure 3 In this example shown, due to the difference in rigidity and etch selectivity between the low-k dielectric material (e.g., SiO2) forming the IMD layer 110 and the metal material (e.g., Ru) forming the top vias V2 and V3, Figure 1BIMD recess may occur in the IMD layer 110 of the interconnect structure 30 corresponding to the interconnect structure 10. When IMD recess occurs, the IMD layer 110 may be overetched outward from the top vias V2 and V3. As a result, the top surface of the IMD layer 110 may become recessed between and at the sides of the top vias V2 and V3. As a result of the IMD recess, the risk of a short circuit between the M1 metal line below the overetched portion of the IMD layer 110 and the M2 metal line above, or any other circuit element that will be formed above the overetched IMD layer 110, may increase.

[0043] The aforementioned problems of via loss and IMD recess, as well as other related problems, may be caused by difficulties in planarization operations (eg, CMP) applied to interconnect structures 20 and 30 including the M1 metal lines with low-density top vias formed thereon.

[0044] The embodiments given below solve the above-mentioned problems in the interconnect structures 20 and 30 of the semiconductor device.

[0045] Figure 4A-Figure 4R A side cross-sectional view of a semiconductor device including an intermediate interconnect structure in which a planarization stop layer is formed in an isolation layer is shown after respective steps of fabricating the semiconductor device according to one or more embodiments.

[0046] It will be understood here that Figure 4A 、 Figure 4C-4E as well as Figure 4G-4N The side cross-sectional view of the semiconductor device shown in FIG is taken in the direction D1 ( Figure 1B The side cross-sectional view of the semiconductor device shown in FIG is taken in the direction D1), Figure 4B 、 Figure 4F 、 Figure 4H and Figure 4P-Figure 4R The side cross-sectional view of the semiconductor device shown in FIG is taken in the direction D2 ( Figure 1C The side cross-sectional view of the semiconductor device shown in FIG is taken in the direction D2).

[0047] It will also be understood that reference will be made to Figure 4A-Figure 4R The described base layer, bottom liner, multiple M1 metal lines and top vias patterned on the base layer, sidewall liner and air gap can be compared with the reference Figure 1A-Figure 1C The described base layer 100, bottom liner 101, M1 metal lines M11-M15 and top vias V2 and V3, sidewall liner 102, and air gap 113 are the same or similar, and therefore, repeated description thereof may be omitted below.

[0048] Reference Figure 4A and Figure 4BInitial metal structure 205 may be formed on base layer 200 of the semiconductor device (with bottom pad 201 therebetween) to form intermediate interconnect structure 40'. Initial metal structure 205 may extend in directions D1 and D2 on base layer 200, which may be at least one of a FEOL layer, a MOL layer, and another BEOL layer. Initial metal structure 205 may be, for example, ruthenium (Ru).

[0049] Before forming the initial metal structure 205 on the base layer 100, the bottom liner 201 (which may be Figure 1A-Figure 1C The base layer 100 may be formed on the top surface of the base layer 100 by, for example, atomic layer deposition (ALD), but is not limited thereto. Then, the initial metal structure 205 may be formed on the base layer 201 by, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or any other deposition process and planarized by, for example, chemical mechanical polishing (CMP).

[0050] A plurality of hard mask patterns H1-H5 may be formed on the top surface of initial metal structure 205 by, for example, photolithography and masking operations at locations on the top surface of initial metal structure 205, under which corresponding M1 metal lines will be formed in the next step ( Figure 4C ) are patterned separately. The hard mask patterns H1-H5 can be arranged in the D1 direction with the same pitch as the corresponding M1 metal line. In addition, each of the hard mask patterns H1-H5 can extend in the D2 direction on the initial metal structure 205, as shown in FIG. Figure 4B As shown, Figure 4B It is along Figure 4A A side sectional view taken along line III-III' is shown.

[0051] The material or material composition forming the hard mask patterns H1 - H5 may be silicon nitride (eg, Si 3 N 4 ) or silicon dioxide (eg, SiO 2 ), without being limited thereto.

[0052] Reference Figure 4C The initial metal structure 205 and the bottom pad 201 thereunder may be patterned based on the hard mask patterns H1 - H5 to form a plurality of M1 metal lines M11 - M15 arranged in the D1 direction and extending in the D2 direction at the M1 layer.

[0053] The formation of the M1 metal lines M11-M15 can be performed by, for example, dry etching (e.g., reactive ion etching, plasma etching, ion beam etching, or laser ablation) as direct etching, but is not limited thereto. Together with the initial metal structure 205, the bottom liner 201 can also be patterned to expose the top surface of the base layer 200 between the M1 metal lines.

[0054] Reference Figure 4D , the hard mask patterns H1 , H3 , and H5 among the hard mask patterns H1 - H5 may be removed from the M1 metal lines M11 , M13 , and M15 , respectively, while the hard mask patterns H2 and H3 remain on the M1 metal lines M12 and M14 , respectively.

[0055] The hard mask patterns H1, H3, and H5 may be selectively removed in this step to expose the top surfaces of the M1 metal lines M11, M13, and M15 so that these M1 metal lines can be removed in the next step ( Figure 4E ) is recessed from its top surface. The selective removal operation of the hard mask patterns H1, H3, and H5 may be performed by, for example, dry etching, ashing, or stripping, without being limited thereto.

[0056] Reference Figure 4E and Figure 4F , the hard mask patterns H2 and H4 on the M1 metal lines M12 and M14 may be patterned so that the hard mask patterns H2 and M4 may remain at positions on the top surfaces of the M1 metal lines M12 and M14, which will be used in the next step ( Figure 4G-4H ) in which corresponding top vias are patterned under the hard mask patterns H2 and M4, respectively.

[0057] For example, the hard mask pattern H2 may be patterned on the M1 metal line M12, as shown in FIG. Figure 4F As shown, Figure 4F It is along Figure 4E The side cross-sectional view taken along line IV-IV' is shown. Figure 4B compared to, Figure 4F The hard mask pattern H2 is shown to be partially removed except for the area underneath which will be removed in the next step ( Figure 4G and Figure 4H ) in addition to the portion forming the top via in the M1 metal line M14. A hard mask pattern H4 may also be patterned on the M1 metal line M14 to take the same shape as the hard mask pattern H2. The patterning of the hard mask patterns H2 and H4 in this step may be performed by, for example, another photolithography and masking operation, without limitation thereto.

[0058] Reference Figure 4G and Figure 4H , can be based on the previous step ( Figure 4E and Figure 4F ) patterned in the hard mask patterns H2 and H4 pattern the M1 metal lines M11-M15 to a predetermined depth Dt.

[0059] Based on the hard mask patterns H2 and H4 , the M1 metal lines M11 - M15 may be directly etched to a predetermined depth Dt by, for example, dry etching (eg, reactive ion etching, plasma etching, ion beam etching, or laser ablation), without limitation.

[0060] As a result of the patterning operation in this step, Figure 4D ), the heights of the M1 metal lines M11, M13, and M15 from which the hard mask patterns H11, H13, and H15 are removed can be shortened by a predetermined depth Dt, and the heights of portions of the M1 metal lines M12 and M14 that are not masked by the hard mask patterns H2 and H4 can also be shortened by a predetermined depth Dt, and thus, two top vias V2 and V3 can be formed on the patterned M1 metal lines M12 and M14, respectively. Here, the top vias V2 and V3 can have a predetermined depth Dt as their heights from the top surfaces TS1 of the M1 metal lines M12 and M14 to the top surfaces TS2 of the top vias V2 and V3, respectively, wherein the heights of the top surfaces TS1 of the M1 metal lines M12 and M14 are shortened by the predetermined depth Dt. For example, the M1 metal line M12 can be patterned to form a top via V2 thereon, as shown in FIG. Figure 4H As shown, Figure 4H It is along Figure 4G The side cross-sectional view taken along line VV' is shown. The M1 metal line M14 may also be patterned to form a top via V3 thereon, which may have the same shape as the top via V2.

[0061] When forming the M1 metal lines M11-M15 and the top vias V2 and V3 in this manner, the M1 metal lines may all have shortened heights and their top surfaces TS1 may all be at the same level, and the top vias V2 and V3 may be formed to protrude from the top surfaces TS1 of the M1 metal lines M12 and M14, respectively. Patterning of the M1 metal lines M11-M15 based on the hard mask patterns H2 and H4 may be performed, for example, by dry etching, without limitation.

[0062] It will be understood here that corresponding to Figure 1A Additional top vias V1 and V4 to those shown may also be formed on the M1 metal lines M11 and M15 that are not shown in FIG. Figure 4G Therefore, even though the two top passages are not mentioned below, Figure 4H The description of the top vias V2 and V3 shown can also be applied to the top vias V1 and V4.

[0063] Reference Figure 4I , a sidewall liner 202 may be formed on an outer surface of each of the M1 metal lines M11 - M15 and the top vias V2 - V3 .

[0064] As mentioned above Figure 1A-Figure 1CAs described above, the sidewall liner 202 can prevent or reduce the electromigration of metal atoms of the M1 metal lines M11-M15 and the top vias V2 and V3 to the metal electrodes to be used in the next step ( Figure 4J ) in the isolation layer of low-k material formed in order to isolate the M1 metal line and the top via from each other and from other circuit elements. The sidewall liner 202 can also provide adhesion properties between the isolation layer and the M1 metal line and the top via.

[0065] The formation of the sidewall liner 202 may be performed by, for example, atomic layer deposition (ALD) of a silicon nitride compound (eg, SiCN, SiBCN, etc.), but not limited thereto, on the top and side surfaces of the M1 metal line and the top via.

[0066] Alternatively, as above referenced Figure 1A-Figure 1C As described, when the initial metal structure 205 from which the M1 metal line and the top via are formed is ruthenium (Ru), which provides lower resistance and reduced electromigration properties than other metal materials such as copper (Cu), the sidewall liner 202 may not be formed at the side surface of the M1 metal line and the side surface of the top via.

[0067] Reference Figure 4J , an isolation layer 210 (which may be an IMD layer) may be formed on the M1 metal lines M11 - M15 and the top vias V2 - V3 to isolate these metal lines and the top vias from each other or from other circuit elements.

[0068] Isolation layer 210 can be formed by, for example, depositing a first isolation material along the outer contours of M1 metal lines M11-M15 and top vias V2 and V3 using at least one of CVD, PVD, PECVD, and ALD to a vertical thickness TH1 in the D3 direction. The first isolation material can be a dielectric material such as silicon oxycarbide (e.g., SiOC with a low-k value) or silicon oxide (e.g., SiO2), but is not limited thereto. Therefore, the outer contour of isolation layer 210 can have a shape similar to that of the M1 metal lines and the top vias thereon.

[0069] For example, first portion 210V of isolation layer 210 (which is the upper portion of isolation layer 210 and corresponds to and is similar to the profile of each top via) can take the form of a protrusion from second portion 210M of isolation layer 210 (which is the lower portion of isolation layer 210 and corresponds to and is similar to the profile of the M1 metal line). Thus, recess R1 can be formed between two adjacent protrusions (i.e., first portion 210V). Furthermore, the number of protrusions (i.e., first portion 210V) of isolation layer 210 can be equal to the number of top vias formed in intermediate interconnect structure 40'. Therefore, in a plan view, the global density of protrusions in the entire area of ​​isolation layer 210 can be very low compared to the entire area of ​​isolation layer 210, similar to the global density of top vias (e.g., 1-3%).

[0070] Due to this protruding form, the top surface of the first portion 210V of the isolation layer 210 may be at a higher level than the top surface of the second portion 210M of the isolation layer 210. Since the first portion 210V is formed to surround each top via, the width of the first portion 210V may be greater than the width of the top via in the D1 direction.

[0071] Furthermore, the isolation layer 210 can be formed such that one or more air gaps 213 can be formed in the second portion 210M of the isolation layer 210 between at least some of the adjacent M1 metal lines, taking advantage of the material properties (e.g., porosity) of the low-k material and the small pitch of the M1 metal lines. The air gaps 213 formed in the isolation layer 210 can increase the isolation or insulation properties between adjacent M1 metal lines and between an M1 metal line and an adjacent top via to further improve the interconnect performance of a semiconductor device including an interconnect structure formed by the intermediate interconnect structure 40'. The formation of the air gaps 213 can be further facilitated by the sidewall liner 202, which reduces the already small metal pitch. According to one or more other embodiments, the air gaps can be formed in the form of a single void or a plurality of voids or holes. Furthermore, according to one or more other embodiments, the air gaps may not be formed in the spaces between some of the M1 metal lines.

[0072] Additionally, even when sidewall liner 202 is not formed to surround the M1 metal line and the top via, isolation layer 210 may be formed to surround the M1 metal line and the top via so that air gap 213 is still formed as described above.

[0073] Reference Figure 4K , a planarization stop layer 220 may be formed on the isolation layer 210 .

[0074] The planarization stop layer 220 may be so called because this layer will be used in the following steps ( Figure 4M) stops the planarization operation applied to the intermediate interconnect structure 40'.

[0075] The formation of the planarization stop layer 220 can be performed along the outer contour of the isolation layer 210 using at least one of CVD, PVD, PECVD, and ALD, for example, through a second isolation material (which can be a dielectric material such as silicon nitride (e.g., SiN, Si3N4, etc.), which is different from the first isolation material forming the isolation layer 210), without being limited thereto. Therefore, the outer contour of the planarization stop layer 220 can take a shape similar to that of the isolation layer 210 on the M1 metal line and the top via.

[0076] For example, the first portion 220V of the planarization stop layer 220 formed around the first portion 210V of the isolation layer 210 may be in the form of a protrusion from the second portion 220V of the planarization stop layer 220 formed on the second portion 210M of the isolation layer 210. Thus, the recess R2 may be formed between two adjacent protrusions (i.e., the first portion 220V). Furthermore, the number of protrusions (i.e., the first portion 220V) of the planarization stop layer 220 may be equal to the number of the first portion 210V of the isolation layer 210 and the number of top vias formed in the intermediate interconnect structure 40'. Thus, the global density of the protrusions in the entire area of ​​the planarization stop layer 220 may be the same as or similar to the global density of the protrusions in the entire area of ​​the isolation layer 210.

[0077] Due to this protruding form, the top surface of the first portion 220V of the planarization stop layer 220 can be at a higher level than the top surface TS3 of the second portion 220M of the planarization stop layer 220. When the first portion 220V of the planarization stop layer 220 is formed to surround the first portion 210V of the isolation layer 210, the width of the first portion 220V in the D1 direction can be greater than the width of the first portion 210V. Therefore, the recess R2 formed between two adjacent first portions 220V can also be smaller in width along the D1 direction and in height along the D3 direction than the recess R1 formed between the two adjacent first portions 210V.

[0078] The planarization stop layer 220 may be formed such that the top surface TS3 of the second portion 220M is at a higher level than the top surface TS2 of the top via for planarization stop purposes, which will be referred to later. Figure 4M To describe.

[0079] Reference Figure 4L , a capping layer 230 may be formed on the planarization stop layer 220 .

[0080] The capping layer 230 may be formed by, for example, depositing a third isolation material (which may be a dielectric material such as silicon oxide (e.g., SiO2, etc.), which is different from the isolation materials forming the isolation layer 210 and the planarization stop layer 220) on the planarization stop layer 220 using at least one of CVD, PVD, PECVD, and ALD, without limitation thereto. However, unlike the planarization stop layer 220, the capping layer 230 may not necessarily be formed to have an outer profile similar to that of the underlying structure (i.e., the planarization stop layer 220), which has an outer profile similar to that of the isolation layer 210. This is at least because the recess R2 formed between two adjacent protrusions (i.e., the first portion 220V) of the planarization stop layer 220 is smaller than the recess R1 formed between two adjacent protrusions (i.e., the first portion 210V) of the isolation layer 210. Therefore, when deposited on the planarization stop layer 220 , the third isolation material for the capping layer 230 may simply fill the recess R2 without taking the form of a protrusion on the first portion 220V of the planarization stop layer 220 .

[0081] According to one or more other embodiments, when the first isolation material is silicon oxide (eg, SiO 2 ), the third isolation material for the capping layer 230 may be the same as the first isolation material for the isolation layer 210 .

[0082] Reference Figure 4M , we can use the Figure 4L ), the intermediate interconnect structure 40′ obtained in the process of FIG. 1 is subjected to a first planarization until the top surface TS3 of the second portion 220M of the planarization stop layer 220 is exposed.

[0083] As mentioned above Figure 2 and Figure 3 As described above, when a single IMD layer is formed around the M1 metal line, the planarization operation is very difficult and risks of via loss and via recessing. However, when planarization is performed on the intermediate interconnect structure 40′ including the planarization stop layer 220 as described above, the first planarization operation can be controlled to stop at the top surface of the second portion 220M of the planarization stop layer 220. Because the global density of the second portion 220M is much higher than the global density of the first portion 220V of the planarization stop layer 220, it is much easier to detect the second portion 220M than the first portion 220V in the first planarization operation.

[0084] For example, due to the very low density of the first portion 220V, the CMP operation for planarization starting from the top of the capping layer 230 may not stop at the top surface of the first portion 220V of the planarization-stop layer 220. However, when the CMP operation reaches the top surface TS3 of the second portion 220M, the CMP operation may detect a significant change in the spectrum of the isolation material (from the third isolation material to the second isolation material), and therefore, the CMP operation may be controlled to stop at the top surface TS3 of the second portion 220M of the planarization-stop layer 220, which is at a higher level than the top surface TS2 of the top vias V2 and V3.

[0085] Reference Figure 4N-Figure 4R , you can do the previous step ( Figure 4M ) performs a second planarization on the intermediate interconnect structure 40' to obtain the interconnect structure 40 in a completed form, which includes the M1 metal line with the top via thereon, the isolation layer 210, the planarization stop layer 220 and the capping layer 230.

[0086] Since the height of the intermediate interconnect structure 40′ has become sufficiently reduced above the top surfaces TS2 of the top vias V2 and V3 in the previous step, a second planarization such as a CMP operation can be easily performed to obtain the interconnect structure 40, which exposes the top surfaces TS2 of the top vias V2 and V3 without Figure 2 and Figure 3 The second planarization in this step can be performed based on at least one of the height of the top via and the M1 metal line, which can be determined from the design specifications and Figure 4G The measurements at the steps are known in advance.

[0087] As a result of the second planarization, the exposed top surface TS2 of the top vias V2 and V3 may be horizontally (in the D1 and D2 directions) coplanar or aligned with the top surfaces of the first portion 210V of the isolation layer 210 and the second portion 220M of the planarization stop layer 220 in the interconnect structure 40. Here, the top surface of the second portion 220M of the planarization stop layer 220 after the second planarization may be at a lower level than the top surface TS3 of the second portion 220M before the second planarization.

[0088] According to one or more other embodiments, a non-selective dry etch (instead of a CMP operation) may be performed as the second planarization operation to obtain the interconnect structure 40 .

[0089] Figure 4O In addition to the isolation layer 210, the planarization stop layer 220 and the capping layer 230 Figure 4NIn the plan view of FIG, the isolation layer 210, the planarization stop layer 220, and the capping layer 230 may obscure the locations of the M1 metal lines M11-M15 and the top vias V1-V4 in the interconnect structure 40. For the sake of simplicity, the sidewall liner 202 is also omitted. Figure 4P-4R are respectively along Figure 4N and Figure 4O Side cross-sectional views taken along lines VI-VI', VII-VII', and VIII-VIII' are shown.

[0090] Figure 4N-Figure 4R The interconnect structure 40 in its finished form obtained after the second planarization is shown and may comprise, in addition to the isolation layer 210 , a planarization stop layer 220 and a capping layer 230 .

[0091] Reference Figure 4N 、 Figure 4P and Figure 4Q When isolation layer 210 may be formed on M1 metal lines M11-M15 and top vias V2 and V3 to surround these metal structures, second portion 220M of planarization stop layer 220 may be formed vertically (in the D3 direction) on second portion 210M of isolation layer 210 and laterally (in the D1 and D2 directions) on first portion 210V of isolation layer 210. Therefore, in interconnect structure 40, height Dt of top vias V2 and V3 may be the sum of vertical thickness TH1 of second portion 210M of isolation layer 210 vertically on each M1 metal line and vertical thickness TH2 of second portion 220M of planarization stop layer 220 vertically on second portion 210M of isolation layer 210. Furthermore, first portion 210V of isolation layer 210 may laterally surround at least upper portions of top vias V2 and V3, and second portion 220M of planarization stop layer 220 may laterally surround first portion 210V of isolation layer 210. The planarization stop layer 220 and the isolation layer 210 may not be vertically formed over the top surface TS2 of each of the top vias V2 and V3 , and the top surface TS2 of each of the top vias V2 and V3 is exposed to be connected to another metal line or circuit element.

[0092] Reference Figure 4R (This is a side cross-sectional view taken along line VIII-VIII' of a wide open area in the interconnect structure 40 where no M1 metal line is formed), the isolation layer 210, the planarization stop layer 220, and the capping layer 230 may all be formed on the base layer 200. This is because no M1 metal line is formed in this area, and therefore, the isolation layer 210, the planarization stop layer 220, and the capping layer 230 may be stacked in sequence. In this wide open area, the second portion 210M of the isolation layer 210 may remain with a thickness TH1 vertically above the M1 metal line without being planarized (e.g., Figure 4N 、 Figure 4P and Figure 4Q As shown in FIG. 2 , the second portion 220M of the planarization stop layer 220 may also remain on the second portion 210M of the isolation layer 210 without being planarized. However, the capping layer 230 may have been planarized at least to a minimum extent by the first planarization. Here, similar to FIG. Figure 1C As shown, the IMD is recessed, and during the first planarization, the capping layer 230 may have been recessed. However, still due to the first and second planarization operations, the top edge or top surface of the capping layer 230 may be formed to be lower than the top surface TS2 of the top via in the interconnect structure 40.

[0093] In the above embodiment, three layers 210, 220, and 230 are used to prevent path loss or planarization recess that may occur in the formation of metal lines in the BEOL structure. However, the present disclosure is not limited thereto, as more or less than three layers may be used to prevent path loss and planarization recess.

[0094] Figures 5A-5I A side cross-sectional view of a semiconductor device including an intermediate interconnect structure is shown after respective steps of fabricating the semiconductor device including the interconnect structure in which the isolation layer itself serves as a planarization stop layer in accordance with one or more embodiments.

[0095] Reference Figure 5A , the intermediate interconnect structure 50' (which can be Figure 4G The intermediate interconnect structure 40' shown is provided on a base layer 300 having a bottom liner 301. The base layer 300 having a bottom liner 301 may also be the same as the base layer 200 having a bottom liner 201 thereon. Therefore, the following description may be omitted. Figure 5A A description of the formation of intermediate interconnect structure 50 ′ is shown (which is repeated).

[0096] Reference Figure 5B An isolation layer 310 (which may be an IMD layer and a planarization stop layer) may be formed on the M1 metal lines M11-M15 and the top vias V2 and V3 to isolate these metal lines and the top vias from each other or from other circuit elements.

[0097] The formation of the isolation layer 310 may be performed such that a first isolation material (which may be a dielectric material such as silicon oxycarbide (e.g., SiOC, etc., having a low-k value)) is deposited along the outer contours of the M1 metal lines M11-M15 and the top vias V2-V3 in the previous step ( Figure 5A) obtained in the intermediate interconnect structure 50 'is up to a vertical thickness TH3 in the D3 direction, but is not limited thereto. Therefore, the outer profile of the isolation layer 310 can take a shape similar to that of the M1 metal line and the top via thereon.

[0098] For example, first portion 310V of isolation layer 310 (which is the upper portion of isolation layer 310 and corresponds to and is similar to the profile of each top via) can take the form of a protrusion from second portion 310M of isolation layer 310 (which is the lower portion of isolation layer 310 and corresponds to and is similar to the profile of the M1 metal line). Thus, recess R3 can be formed between two adjacent protrusions (i.e., first portion 310V). Furthermore, the number of protrusions (i.e., first portion 310V) of isolation layer 310 can be equal to the number of top vias formed in intermediate interconnect structure 50'. Therefore, in a plan view, the global density of protrusions in the entire area of ​​isolation layer 310 can be very low compared to the entire area of ​​isolation layer 310, similar to the global density of top vias (e.g., 1-3%).

[0099] The top surface of the first portion 310V may be higher than the top surface TS2 of the top via (or the sidewall liner 302 on the top via) by a vertical thickness TH3 and higher than the top surface of the second portion 310M by a height Dt of the top via. In the direction D1, the width of the first portion 310V may be greater than the width of the top via.

[0100] Furthermore, the isolation layer 310 can be formed such that one or more air gaps 313 can be formed in the second portion 310M between at least some of the adjacent M1 metal lines by utilizing the material properties (e.g., porosity) of the low-k material and the small pitch of the M1 metal lines. The air gaps 313 formed in the isolation layer 310 can increase the isolation or insulation properties between adjacent M1 metal lines and between the M1 metal lines and the adjacent top vias to further improve the interconnect performance of the semiconductor device including the interconnect structure formed by the intermediate interconnect structure 50'. The formation of the air gaps 313 can be further facilitated by the sidewall liner 302, which reduces the already small metal pitch. According to one or more other embodiments, the air gaps can be formed in the form of a single void or a plurality of voids or holes. Furthermore, according to one or more other embodiments, air gaps may not be formed in the spaces between some of the M1 metal lines.

[0101] Additionally, even when sidewall liner 302 is not formed to surround the M1 metal line and the top via, isolation layer 310 may be formed to surround the M1 metal line and the top via so that air gap 313 is still formed as described above.

[0102] In the intermediate interconnect structure 50', the isolation layer 310 may also be formed in a later step ( Figure 5D ) is used as a planarization stop layer, which is similar to Figure 4J The isolation layer 210 in the intermediate interconnect structure 40' is shown to be different. For this purpose, an isolation layer 310 may be deposited to surround the intermediate interconnect structure 50' obtained in the previous step by a vertical thickness TH3 of the isolation layer 310, which may be greater than Figure 4J The vertical thickness TH1 of the isolation layer 210 formed in the intermediate interconnect structure 40' is shown. However, the outer profile of the isolation layer 310 can still be similar to Figure 4K The outer profile of the planarization stop layer 220 formed in the intermediate interconnect structure 40' is shown. In addition, the top surface TS4 of the second portion 310M of the isolation layer 310 can be formed at a level above the top surface TS2 of the top via. In addition, the recess R3 formed between the two adjacent first portions 310V of the isolation layer 310 corresponding to the top vias V2 and V3 can be taken as shown in FIG. Figure 4K The recess R2 formed between two adjacent first portions 220V of the planarization stop layer 220 of the intermediate interconnect structure 40 ′ is shown to have a similar shape.

[0103] Reference Figure 5C , a capping layer 320 may be formed on the isolation layer 310 .

[0104] The formation of the cover layer 320 can be similar to Figure 4L The formation of the capping layer 230 of the intermediate interconnect structure 40 ′ is shown, and therefore, the capping layer 320 may take a similar shape as the capping layer 230 of the intermediate interconnect structure 40 ′.

[0105] The capping layer 320 may be formed by depositing a third isolation material (which may be a dielectric material such as silicon oxide (e.g., SiO2, etc.), which is different from the first isolation material forming the isolation layer 310) on the isolation layer 310 using at least one of CVD, PVD, PECVD, and ALD, without being limited thereto. According to one or more other embodiments, the third isolation material forming the capping layer 320 may be another dielectric material such as silicon nitride (e.g., SiN, Si3N4, etc.), which may be different from the first isolation material forming the isolation layer 310. Figure 4K The second isolation material forming the planarization stop layer 220 of the intermediate interconnect structure 40 ′ is shown to be the same or similar.

[0106] Reference Figure 5D , you can do the Figure 5C ) performs a first planarization on the intermediate interconnect structure 50′ obtained in the embodiment of the present invention until the top surface TS4 of the second portion 310M of the isolation layer 310 is exposed.

[0107] Similar to Figure 4MThe first planarization performed on the intermediate interconnect structure 40 ′ shown in FIG. 5 , may be performed on the intermediate interconnect structure 50 ′ in this step based on the isolation layer 310 serving as a planarization stop layer.

[0108] As previously described, first portion 310V of isolation layer 310 has the same outer profile as top vias V2 and V3. Therefore, the global density of first portion 310V relative to the entire area of ​​isolation layer 310 can be similar to the global density of top vias relative to the entire area of ​​intermediate interconnect structure 50' (which can be very low, for example, 1-3%). Therefore, the first planarization can be controlled to stop at the top surface of second portion 310M of isolation layer 310, which has a much higher density than first portion 310V of isolation layer 310.

[0109] For example, due to the very low density of the first portion 310V, the CMP operation for planarization starting from the top of the capping layer 320 may not stop at the top surface of the first portion 310V of the isolation layer 310. However, when the CMP operation reaches the top surface TS4 of the second portion 310M, the CMP operation may detect a significant change in the spectrum of the dielectric material (from the third isolation material to the first isolation material), and therefore, the CMP operation may be controlled to stop at the top surface TS4 of the second portion 310M of the isolation layer 310.

[0110] Reference Figure 5E-Figure 5I , you can do the previous step ( Figure 5D ) performs a second planarization on the intermediate interconnect structure 50′ in order to obtain the interconnect structure 50 in a completed form including the isolation layer 310 and the capping layer 320.

[0111] Since the height of the intermediate interconnect structure 50′ has become sufficiently reduced above the top surfaces TS2 of the top vias V2 and V3 in the previous step, the second planarization (such as a CMP operation) in this step can be easily performed to obtain the interconnect structure 50, which exposes the top surfaces TS2 of the top vias V2 and V3 without Figure 2 and Figure 3 The second planarization in this step may be performed based on at least one of the heights of the M1 metal lines M11-M15 and the top vias V2 and V3, which may be determined, for example, from the design specifications and Figure 5A The measurements at the steps are known in advance.

[0112] As a result of the second planarization, in the interconnect structure 50, the exposed top surfaces TS2 of the top vias V2 and V3 may be horizontally (in the D1 and D2 directions) coplanar or aligned with the top surface of the second portion 310M of the isolation layer 310. Here, the top surface of the second portion 310M of the isolation layer 310 after the second planarization may be at a lower level than the top surface TS4 of the second portion 310M before the second planarization.

[0113] According to one or more other embodiments, a non-selective dry etch operation may be performed as the second planarization operation to obtain the interconnect structure 50 instead of the CMP operation.

[0114] Figure 5F In addition to the isolation layer 310 and the cover layer 320 Figure 5E In the plan view, the isolation layer 310 and the capping layer 320 may obscure the locations of the M1 metal lines M11-M15 and the top vias V1-V4 in the interconnect structure 50. For the sake of simplicity, the sidewall liner 302 is also omitted. Figure 5G-Figure 5I are respectively along Figure 5E and Figure 5F IX-IX', XX' and XI-XI' are side sectional views taken along the lines shown in FIG.

[0115] Figure 5E-Figure 5I The interconnect structure 50 in its finished form, shown as obtained after the second planarization, may comprise, in addition to the isolation layer 310 , a capping layer 320 .

[0116] Reference Figure 5E 、 Figure 5G and Figure 5H , the M1 metal lines M11 - M15 and the top vias V2 and V3 thereon may be surrounded by the isolation layer 310 .

[0117] Reference Figure 5I (This is a side cross-sectional view taken along line XI-XI' of a wide open area in the interconnect structure 50 where no M1 metal line is formed), the isolation layer 310 and the capping layer 320 may both be formed on the base layer 300. This is because no M1 metal line is formed in this area, and therefore, the isolation layer 310 and the capping layer 320 may be stacked in sequence. In this wide open area, the second portion 310M of the isolation layer 310 may remain without being planarized; however, the capping layer 320 may have been planarized to at least a minimum extent by the first planarization. Here, the capping layer 320 may have been recessed during the first planarization, similar to the example shown in FIG. Figure 1C However, still due to the first and second planarization operations, the top edge or top surface of capping layer 320 may be formed to be lower than the level of top surface TS2 of the top via in interconnect structure 50 .

[0118] Figure 6A Reference to one or more embodiments is shown Figure 4A-Figure 4R A flow chart of a method of manufacturing a semiconductor device including an interconnect structure in which a planarization stop layer is formed in an isolation layer.

[0119] In step S10, the initial metal structure may be patterned to form metal lines and top vias thereon, such that the top vias take the form of protrusions from the metal lines without a connecting surface, interface, or barrier layer therebetween, thereby forming an intermediate interconnect structure ( Figures 4A-4I ). The formation of the top via can be performed by directly etching the initial metal structure based on the hard mask pattern. The metal material forming the initial metal structure for direct etching can be ruthenium (Ru).

[0120] In step S20, an isolation layer may be formed on the intermediate interconnect structure such that an upper portion of the isolation layer surrounds the top via and a lower portion of the isolation layer surrounds the metal line ( Figure 4J The isolation layer may be formed by depositing a first dielectric material along an outer contour of a metal line having a top via thereon, whereby a lower portion of the isolation layer may surround the metal line and an upper portion of the isolation layer may take the form of a protrusion surrounding the top via.

[0121] In step S30, a planarization stop layer may be formed on the intermediate interconnect structure including the isolation layer and the metal line having the top via thereon, such that a top surface of a lower portion of the planarization stop layer is at a higher level than a top surface of the top via, while an upper portion of the planarization stop layer surrounds an upper portion of the isolation layer ( Figure 4K The planarization stop layer may be formed by depositing a second dielectric material along the outer contour of the isolation layer. Thus, when the planarization stop layer is formed, the upper portion of the planarization stop layer may surround the upper portion of the isolation layer and the top surface of the lower portion of the planarization stop layer may be at a higher level than the top surface of the top via.

[0122] In step S40, a capping layer ( Figure 4L ). The capping layer may be formed by depositing a third dielectric material on the planarization stop layer. The first to third dielectric materials may be different from each other, or the second dielectric material may be different from the first and third dielectric materials (the first and third dielectric materials may be the same).

[0123] In step S50, a first planarization may be performed on the intermediate interconnect structure including the capping layer, the planarization stop layer, the isolation layer, and the metal line having the top via thereon, such that the first planarization stops at the top surface of the lower portion of the planarization stop layer ( Figure 4M ).

[0124] In step S60, a second planarization may be performed to expose the top surface of the top via to form an interconnect structure ( Figure 4N-Figure 4R ), after the first planarization and the second planarization, the interconnect structure may include a planarization stop layer vertically remaining on the isolation layer, the isolation layer vertically on the metal line.

[0125] Figure 6B Reference to one or more embodiments is shown Figures 5A-5I A flow chart of a method of manufacturing a semiconductor device including an interconnect structure in which an isolation layer serves as a planarization stop layer.

[0126] In step S10, a top via may be patterned on the metal lines without a connecting surface, interface, or barrier layer between them to form an intermediate interconnect structure ( Figure 5A ). The formation of the top via can be performed by directly etching the initial metal structure based on the hard mask pattern. The metal material forming the initial metal structure for direct etching can be ruthenium (Ru).

[0127] In step S20, an isolation layer may be formed on the intermediate interconnect structure such that an upper portion of the isolation layer surrounds the top via, a lower portion of the isolation layer surrounds the metal line, and a top surface of the lower portion is at a higher level than a top surface of the top via ( Figure 5B ). The isolation layer can be formed by depositing a first dielectric material along the outer contour of the metal line having the top via thereon, so that the lower portion of the isolation layer can surround the metal line and the upper portion of the isolation layer can take the form of a protrusion surrounding the top via.

[0128] In step S30, a capping layer ( Figure 5C The capping layer may be formed by depositing a third dielectric material on the isolation layer. The first dielectric material and the third dielectric material may be different from each other.

[0129] In step S40, a first planarization may be performed on the intermediate interconnect structure including the capping layer, the isolation layer, and the metal line having the top via thereon, such that the first planarization stops at the top surface of the lower portion of the isolation layer ( Figure 5D ).

[0130] In step S50, a second planarization may be performed to expose the top surface of the top via to form an interconnect structure ( Figure 5E-Figure 5I ), which may include an isolation layer surrounding a metal line having a top via thereon.

[0131] Figure 7is a block diagram of a system on chip (SoC) 1000 including a semiconductor device in which a Figure 4N The interconnect structure 40 and Figure 5E At least one of the interconnect structures 50 is shown.

[0132] Reference Figure 7 SoC 1000 may be an integrated circuit in which components of a computing system or other electronic system are integrated. As an example of SoC 1000, an application processor (AP) may include at least one processor and components for various functions. SoC 1000 may include a core 1011 (e.g., a processor), a digital signal processor (DSP) 1012, a graphics processing unit (GPU) 1013, an embedded memory 1014, a communication interface 1015, and a memory interface 1016. The components of SoC 1000 may communicate with each other via a bus 1007.

[0133] The core 1011 may process instructions and control the operations of components included in the SoC 1000. For example, the core 1011 may process a series of instructions to run an operating system and execute an application on the operating system. The DSP 1012 may generate useful data by processing digital signals (e.g., digital signals provided from the communication interface 1015). The GPU 1013 may generate data for an image output by a display device from image data provided by the embedded memory 1014 or the memory interface 1016, or may encode the image data.

[0134] Embedded memory 1014 may store data used by core 1011, DSP 1012, and GPU 1013. Communication interface 1015 may provide an interface for a communication network or one-to-one communication. Memory interface 1016 may provide an interface for external memory of SoC 1000 (such as dynamic random access memory (RAM) (DRAM), flash memory, etc.).

[0135] At least one of the core 1011, the DSP 1012, the GPU 1013 and / or the embedded memory 1014 may include a Figure 4N The interconnect structure 40 and Figure 5E The semiconductor device includes at least one of the interconnect structures 50 shown.

[0136] The foregoing is a description of example embodiments and is not to be construed as limiting the present disclosure. Although several example embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made to the above-described embodiments without materially departing from the present disclosure.

[0137] This application is based on and claims priority from U.S. Provisional Application No. 63 / 569,548 filed in the U.S. Patent and Trademark Office on March 25, 2024, and U.S. Non-Provisional Application No. 18 / 886,289 filed in the U.S. Patent and Trademark Office on September 16, 2024, the disclosures of which are incorporated herein by reference in their entirety.

Claims

1. A semiconductor device comprising a substrate and an interconnect structure on the substrate, the interconnect structure comprising: a first metal wire on the base layer; a first top via protruding vertically from the first metal line with no connecting surface between the first top via and the first metal line; an isolation layer on the first metal line and the first top via; as well as A planarization stop layer is vertically and laterally on the isolation layer. 2 . The semiconductor device according to claim 1 , wherein the isolation layer and the planarization stop layer comprise different materials.

3. The semiconductor device according to claim 1 , wherein the isolation layer laterally surrounds the first top via, and The isolation layer is vertically and laterally on the first metal line. 4 . The semiconductor device according to claim 1 , wherein a top surface of the first top via, a top surface of the isolation layer, and a top surface of the planarization stop layer are coplanar in a horizontal direction. 5 . The semiconductor device according to claim 1 , wherein a height of the first top via from a top surface of the first metal line is equal to a sum of vertical thicknesses of the isolation layer and the planarization stop layer vertically on the first metal line.

6. The semiconductor device according to claim 1, further comprising: a second metal line adjacent to the first metal line and at the same level as the first metal line, the isolation layer being between the second metal line and the first metal line; as well as An air gap is formed between the first metal line and the second metal line. The semiconductor device according to claim 1 , wherein the first metal wire comprises ruthenium (Ru).

8. The semiconductor device according to claim 1, further comprising: a second metal line, at the same level as the first metal line, The isolation layer and the planarization stop layer are sequentially on the second metal line in a vertical direction.

9. A semiconductor device comprising a base layer and an interconnection structure on the base layer, the interconnection structure comprising: a metal wire on the base layer; a top via protruding perpendicularly from the metal line with no connecting surface between the top via and the metal line; an isolation layer vertically on the metal lines and laterally on the top via; as well as an open area on the base layer, where no metal line is formed at a level where the metal line is provided, The open area includes at least two dielectric layers, and the at least two dielectric layers include the isolation layer vertically on the base layer.

10. The semiconductor device according to claim 9, wherein the at least two dielectric layers in the open area include a capping layer vertically on the isolation layer, wherein the cover layer and the isolation layer comprise different materials, and The cover layer is not provided perpendicularly to the metal line. 11 . The semiconductor device according to claim 10 , wherein a top surface of the capping layer in the empty region is at a lower level than a top surface of the top via and is recessed toward the isolation layer.

12. The semiconductor device according to claim 9, further comprising: a planarization stop layer vertically and laterally on the isolation layer, wherein the at least two dielectric layers further comprise the planarization stop layer and a capping layer vertically on the planarization stop layer, wherein the planarization stop layer includes a second material different from the first material included in the isolation layer, and the capping layer includes a third material different from the second material, and The cover layer is not provided perpendicularly to the metal line. 13 . The semiconductor device according to claim 12 , wherein a height of the top via from a top surface of the metal line is equal to a sum of vertical thicknesses of the isolation layer and the planarization stop layer vertically on the metal line. 14 . The semiconductor device according to claim 12 , wherein a vertical thickness of the isolation layer vertically on the metal line is the same as a vertical thickness of the isolation layer in the open area. 15 . The semiconductor device according to claim 12 , wherein a top surface of the capping layer in the empty region is lower than a level of a top surface of the top via and is recessed toward the planarization stop layer. 16 . The semiconductor device according to claim 12 , wherein the planarization stop layer comprises silicon nitride. The semiconductor device according to claim 9 , wherein the top via comprises ruthenium (Ru).

18. A method for manufacturing a semiconductor device, the method comprising: patterning the initial metal structure to form a metal line and a top via on the metal line such that the top via protrudes from the metal line; forming at least two dielectric layers vertically stacked on the metal line having the top via thereon; performing a first planarization such that the first planarization stops at a level above a top surface of the top via; as well as A second planarization is performed such that the top surface of the top via is exposed.

19. The method of claim 18, wherein the at least two dielectric layers comprise: an isolation layer comprising a first dielectric material; and a capping layer comprising a second dielectric material different from the first dielectric material, wherein the first planarization is controlled to stop at a surface of the isolation layer, the surface of the isolation layer being at the level above the top surface of the top via.

20. The method of claim 18, wherein the at least two dielectric layers comprise: an isolation layer comprising a first dielectric material; a planarization stop layer comprising a second dielectric material; as well as a capping layer comprising a third dielectric material different from the second dielectric material, wherein the first planarization is controlled to stop at a surface of the planarization stop layer, the surface of the planarization stop layer being at the level above the top surface of the top via.

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