Semiconductor device and radiation hardening method of semiconductor device

Abstract

The invention relates to the field of semiconductors, particularly provides a semiconductor device and a semiconductor device anti-radiation strengthening method, and aims to solve the problem that an anti-radiation process is complex. To this end, the semiconductor device of the present application comprises: a substrate; the isolation region is positioned in the substrate; the active region is defined by the isolation region; the active device is positioned in the active region and the surface of the active region; the first dielectric layer covers the isolation region, the active region and the active device on the surface of the active region; the first-type contact hole penetrates through the first dielectric layer and exposes an electrode of the active device; the second type of contact holes penetrate through the first dielectric layer and are exposed out of the isolation region; the first filling material is filled in the first type of contact holes and the second type of contact holes and is in contact with the electrodes and the isolation regions respectively, and the first filling material is an anti-radiation material; and the first metal layer is positioned on the first type of contact holes and is electrically connected with the first filling material in the first type of contact holes.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and specifically provides a semiconductor device and a method for strengthening the semiconductor device against radiation. Background Art

[0002] In modern aerospace, aviation, space stations and other application scenarios, the support of various electronic system equipment is indispensable. In the radiation environment of outer space, the semiconductor devices (including integrated circuits) in these electronic system equipment will inevitably experience radiation effects. The radiation effects are mainly total dose radiation effects and single particle effects. Among them, the total dose radiation effect is the destruction of silicon dioxide bonds in the thick oxide film (oxide layer formed by shallow trench process, or oxide layer formed by local oxidation) in the device by cosmic rays, resulting in charge accumulation effect, thereby degrading the performance of the circuit or even impairing its function.

[0003] Existing technologies primarily utilize specific ion implantation at the interface between the thick oxide layer and the silicon substrate to increase the turn-on voltage of the product field region, thereby improving the radiation resistance of electronic system equipment. However, ion implantation for radiation resistance hardening requires additional process technology, which inevitably increases the difficulty of product manufacturing, thereby reducing product yield and / or increasing manufacturing costs. Furthermore, ion implantation for radiation resistance hardening can only improve device radiation resistance to a certain extent and cannot completely eliminate the effects of total radiation dose on the device.

[0004] Therefore, in order to solve the above technical problems, it is necessary to provide a new semiconductor device (including integrated circuit) and a corresponding anti-radiation hardening method thereof. Summary of the Invention

[0005] In order to overcome the above-mentioned defects of the prior art, the technical solution of the present application is proposed to solve the technical problem that when injecting radiation-resistant materials, additional process technology needs to be added, which will inevitably increase the difficulty of product manufacturing, thereby reducing product yield and / or increasing manufacturing costs.

[0006] In a first aspect, the present application provides a semiconductor device, comprising:

[0007] substrate;

[0008] an isolation region located in the substrate and an active region defined by the isolation region;

[0009] Active devices located in the active area and on the surface of the active area;

[0010] a first dielectric layer covering the isolation region, the active region, and the active devices on the surface of the active region;

[0011] A first type contact hole, penetrating the first dielectric layer and exposing the electrode of the active device;

[0012] a second type contact hole penetrating the first dielectric layer and exposing the isolation region;

[0013] A first filling material is filled in the first-type contact hole and the second-type contact hole, respectively contacting the electrode and the isolation region, wherein the first filling material is a radiation-resistant material;

[0014] The first metal layer is located on the first-type contact hole and is electrically connected to the first filling material in the first-type contact hole.

[0015] In a technical solution of the above semiconductor device, the orthographic projection of the second-type contact hole on the substrate falls within the range of the orthographic projection of the isolation region on the substrate.

[0016] In a technical solution of the above semiconductor device, the distance between the boundary of the orthographic projection of the second type contact hole on the substrate and the boundary of the orthographic projection of the isolation region on the substrate is more than 5% of the lateral size of the second type contact hole.

[0017] In a technical solution of the above semiconductor device, the second type contact hole includes a plurality of contact holes, and the lateral size of each second type contact hole is equivalent to the lateral size of the first type contact hole.

[0018] In one technical solution of the above-mentioned semiconductor device, the active device is a field effect transistor, and the electrodes include a gate, a source, and a drain; or the active device is a triode, and the electrodes include a base, a collector, and an emitter; or the active device is a diode, and the electrodes include an anode and a cathode.

[0019] In a technical solution of the above semiconductor device, the isolation region is a shallow trench isolation region or a silicon local oxidation isolation region.

[0020] In a technical solution of the above semiconductor device, the first filling material is tungsten.

[0021] In one technical solution of the above semiconductor device, the present invention further comprises:

[0022] a second dielectric layer located on the first dielectric layer;

[0023] a first type of through-hole and a second type of through-hole located in the second dielectric layer, wherein the first type of through-hole exposes the first metal layer, and the orthographic projection of the second type of through-hole on the substrate includes the orthographic projection of the second type of contact hole on the substrate;

[0024] A second filling material and a third filling material are filled in the first type of through-holes and the second type of through-holes, respectively, wherein the second filling material is electrically connected to the first metal layer, and both the third filling material and the second filling material are radiation-resistant materials;

[0025] The second metal layer is located on the first-type through-holes and is electrically connected to the second filling material in the first-type through-holes.

[0026] In a technical solution of the above semiconductor device, the second filling material and the third filling material are both tungsten.

[0027] In a second aspect, the present application provides a method for strengthening a semiconductor device against radiation, comprising:

[0028] forming an isolation region and an active region defined by the isolation region in a substrate;

[0029] forming active devices in the active area and on the surface of the active area;

[0030] forming a first dielectric layer to cover the isolation region, the active region, and the active devices on the surface of the active region;

[0031] forming a first type contact hole penetrating the first dielectric layer to expose the electrode of the active device;

[0032] forming a second type contact hole penetrating the first dielectric layer to expose the isolation region;

[0033] forming a first filling material to fill the first-type contact hole and the second-type contact hole, respectively contacting the electrode and the isolation region, wherein the first filling material is a radiation-resistant material;

[0034] A first metal layer is formed on the first-type contact hole and is electrically connected to the first filling material in the first-type contact hole.

[0035] The present application provides a semiconductor device and a method for strengthening the semiconductor device against radiation. The semiconductor device specifically includes: a substrate; an isolation region located in the substrate and an active region defined by the isolation region; active devices located in the active region and on the surface of the active region; a first dielectric layer covering the isolation region, the active region, and the active devices on the surface of the active region; a first-type contact hole penetrating the first dielectric layer to expose an electrode of the active device; a second-type contact hole penetrating the first dielectric layer to expose the isolation region; a first filling material filled in the first-type contact hole and the second-type contact hole, contacting the electrode and the isolation region, respectively, wherein the first filling material is a radiation-resistant material; and a first metal layer located on the first-type contact hole and electrically connected to the first filling material in the first-type contact hole. Thus, the thick oxide film is subjected to radiation-resistant treatment without increasing the difficulty of product manufacturing process, thereby improving the radiation resistance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The disclosure of this application will be more easily understood with reference to the accompanying drawings. Those skilled in the art will readily appreciate that these drawings are for illustrative purposes only and are not intended to limit the scope of protection of this application. Furthermore, similar numbers in the figures represent similar components, where:

[0037] Figure 1 A schematic diagram of a cross-sectional structure of a semiconductor device provided in an embodiment of the present application;

[0038] Figure 2 is a schematic diagram of a cross-sectional structure of another semiconductor device provided in an embodiment of the present application;

[0039] Figure 3 1 is a flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0040] Figures 4 to 11 This embodiment of the present application provides Figure 3 Schematic diagram of the cross-sectional structure of the semiconductor device formed in the key steps.

[0041] Reference Signs List :

[0042] 1: substrate; 2: active area; 3: shallow trench isolation region; 4: gate; 5: sidewall; 6: gate oxide layer; 7: first dielectric layer; 8: second type contact hole; 9: first type contact hole; 10: first metal layer; 11: second dielectric layer; 12: second metal layer; 13: silicon local oxide isolation region; 14: source; 15: drain; 16: first type through hole; 17: second type through hole. DETAILED DESCRIPTION

[0043] Some embodiments of the present application are described below with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are only used to explain the technical principles of the present application and are not intended to limit the scope of protection of the present application.

[0044] In the description of this application, for ease of description, spatially relative terms such as "below," "beneath," "under," "above," and "upper" may be used to describe the relationship between one element and another. When an element or layer is referred to as being "on," "adjacent to," or "connected to" another element or layer, it may be directly on, adjacent to, or connected to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "directly adjacent to," or "directly connected to" another element or layer, there are no intervening elements or layers.

[0045] It should also be understood that, for ease of description, the term "A and / or B" refers to all possible combinations of A and B, such as just A, just B, or A and B. The term "at least one of A or B" or "at least one of A and B" has a similar meaning to "A and / or B" and may include just A, just B, or A and B. The singular forms "a" and "the" may also include plural forms.

[0046] The specific implementation of the present application will be described in detail below with reference to the accompanying drawings.

[0047] Figure 1 A schematic diagram of a cross-sectional structure of a semiconductor device provided in an embodiment of the present application. Figure 1 As shown, the semiconductor device includes a substrate 1; a plurality of shallow trench isolation regions (STI) 3 located in the substrate 1 and an active region 2 defined by the shallow trench isolation regions 3; a first dielectric layer 7 covering the shallow trench isolation regions 3, the active region 2 and the active device on the surface of the active region; a first type contact hole 9, which penetrates the first dielectric layer 7 and exposes the electrode of the active device (at Figure 1 In the example, the active device is a metal oxide semiconductor field effect transistor, whose electrodes include a source 14, a drain 15 and a gate 4); a second type contact hole 8 penetrates the first dielectric layer 7 and exposes the shallow trench isolation region 3; a first filling material is filled in the first type contact hole 9 and the second type contact hole 8, respectively contacting the electrode and the isolation region 3, wherein the first filling material is an anti-radiation material; a first metal layer 10 is located on the first type contact hole 9 and is electrically connected to the first filling material in the first type contact hole 9.

[0048] This application provides a new contact hole layout structure with radiation resistance reinforcement. As can be seen from the figure, unlike conventional contact hole layouts, this application's solution has two types of contact holes. The first type of contact hole is consistent with existing processes and is mainly used to connect the electrodes of active devices. Specifically, when the active device is a MOS device, the bottom of this type of contact hole mainly contacts the source, drain, or gate of the device. The second type of contact hole is a new contact hole type proposed by this application. The bottom of this type of contact hole mainly stays on the surface of the STI thick oxide layer, so it will not affect device performance.

[0049] In a preferred embodiment, the first filling material is tungsten, and the tungsten material filled in the second type contact hole covers the surface of the STI oxide layer. Since metal tungsten has excellent anti-radiation protection, precise radiation protection of the STI oxide layer is achieved.

[0050] In this embodiment, the substrate 1 may be a semiconductor single-layer structure or a multi-layer structure made of a material containing silicon, such as silicon, silicon carbide, or a material not containing silicon, such as gallium arsenide, gallium nitride, indium phosphide, sapphire, etc.

[0051] In this embodiment, the thickness of the shallow trench isolation region 3 is 2000 angstroms to 4000 angstroms. The distance between adjacent shallow trench isolation regions 3 can be determined according to the size of the active region 2 .

[0052] In the example where the active device is a MOS device, the MOS device further includes a channel region located in the substrate of the active region, with a source electrode 14 and a drain electrode 15 located on either side of the channel region; a gate oxide layer 6 between the gate electrode 4 and the channel region; and a spacer 5 surrounding the gate electrode 4. These are all prior art and will not be described in detail here.

[0053] In a specific example, the thickness of the gate oxide layer 6 may be 10 angstroms to 200 angstroms, the thickness of the gate 4 may be 1000 angstroms to 3000 angstroms, and the thickness of the sidewall spacer 5 may be 200 angstroms to 1000 angstroms.

[0054] Those skilled in the art will appreciate that, although a metal oxide semiconductor field effect transistor is used as an example of an active device in this embodiment, the present application is not limited thereto. Alternatively, a triode may be used, with corresponding electrodes including a base, a collector, and an emitter; or a diode may be used, with corresponding electrodes including an anode and a cathode. In essence, the present invention is applicable to any application requiring radiation protection of shallow trench isolation regions.

[0055] In this embodiment, the material of the first dielectric layer 7 may be an insulating material such as silicon dioxide.

[0056] Generally, for the same process platform, the size of the first-type contact holes is fixed and uniform, while the size of the second-type contact holes is not fixed and is closely related to the size of the shallow trench isolation (STI) region. In one embodiment, the orthographic projection of the second-type contact hole 8 on the substrate 1 falls within the orthographic projection of the isolation region 3 on the substrate 1. In other words, the orthographic projection of the sidewall of the second-type contact hole on the STI surface does not exceed the STI boundary.

[0057] Furthermore, to ensure a sufficient process window, the distance between the orthographic projection boundary of the second type contact hole 8 on the substrate 1 and the orthographic projection boundary of the isolation region 3 on the substrate 1 is more than 5% of the lateral dimension of the second type contact hole 8 .

[0058] When the STI size is large, the size of a single second-type contact hole will also be large. At this time, the size difference between the two types of contact holes is large, and the related contact hole process will have a large local load effect. If the same etching, PVD tungsten filling and planarization process are used, the effects will form a large difference in the first-type contact hole and the second-type contact hole area, which will bring great challenges to the process window. To circumvent this problem, when the lateral size of a single second-type contact hole is more than twice that of the first-type contact hole, the original single second-type contact hole can be split into multiple ones, each with the same (same and close) lateral size as the first-type contact hole. This will reduce the load effect caused by local pattern differences and expand the contact-related process window.

[0059] In this embodiment, the material of the first metal layer 10 can be copper or aluminum. Furthermore, the semiconductor device of the present application also includes: a second dielectric layer 11 located on the first dielectric layer 7; a first type of through hole 16 and a second type of through hole 17 located in the second dielectric layer 11, wherein the first type of through hole 16 exposes the first metal layer 10, and the orthographic projection of the second type of through hole 17 on the substrate 1 includes the orthographic projection of the second type of contact hole 8 on the substrate 1; a second filling material and a third filling material, respectively filled in the first type of through hole 16 and the second type of through hole 17, wherein the second filling material is electrically connected to the first metal layer 10, and the third filling material and the second filling material are radiation-resistant materials; a second metal layer 12, located on the first type of through hole 16, and electrically connected to the second filling material in the first type of through hole 16.

[0060] Preferably, the second filling material and the third filling material are both tungsten.

[0061] By filling the second type of through holes with radiation resistant material, such as tungsten, the total thickness of tungsten above the isolation region is increased, thereby further enhancing the radiation resistance of the isolation region.

[0062] The above embodiment is based on the isolation region being STI. However, those skilled in the art will appreciate that the present application is not limited thereto. The isolation region 3 in the semiconductor may also be a silicon local oxidation isolation region 13, such as Figure 2 In the semiconductor structure given in this embodiment, except for the isolation region, the other structures are the same as Figure 1 The structures in are the same.

[0063] Combine Figure 3 、 Figure 4-11 This application also provides a Figure 1 or Figure 2 Still taking the isolation region as STI as an example, specifically, the preparation method includes steps S101 to S107.

[0064] Step S101: forming a shallow trench isolation region and an active region defined by the shallow trench isolation region in a substrate.

[0065] Figure 4 FIG. 1 shows a cross-sectional view after forming the shallow trench isolation region 3. In this embodiment, the trench of the shallow trench isolation region 3 can be formed by an etching process, and then a layer of silicon dioxide is formed on the inner wall of the trench. The silicon dioxide is then filled using chemical vapor deposition, and finally, excess silicon dioxide is removed from the surface to flatten the surface of the substrate 1, thereby forming the isolation region 3.

[0066] Those skilled in the art will appreciate that the distance between adjacent isolation regions in the cross-sectional view is determined by the size of the active region therebetween.

[0067] Step S102: forming active devices in the active area and on the surface of the active area.

[0068] Next, in a CMOS process, ion implantation is performed in the active region to form a channel region of the MOS device and a gate oxide layer 6, a gate 4 (e.g., polysilicon material) and sidewalls 5 on both sides of the channel region. The sidewalls are then used as masks to form a source 14 and a drain 15 of the MOS device. The structure after formation is as follows: Figure 5 shown.

[0069] Step S103: forming a first dielectric layer to cover the isolation region, the active region and the active devices on the surface of the active region.

[0070] Figure 6 FIG2 shows a cross-sectional view after performing this step. In this embodiment, a first dielectric layer 7 is deposited on substrate 1, covering the isolation region and the MOS device. The deposition method may be chemical vapor deposition, atomic layer deposition, high-density plasma chemical vapor deposition, plasma-enhanced chemical vapor deposition, thermal reaction sub-atmospheric pressure chemical vapor deposition, etc., without limitation herein.

[0071] Step S104: forming a first type contact hole, penetrating the first dielectric layer, and exposing the electrode of the active device.

[0072] Figure 7 In this embodiment, a patterned mask is formed on the first dielectric layer 7 by photolithography, and then the first type contact hole 9 is formed by etching.

[0073] Step S105: forming a second type contact hole, penetrating the first dielectric layer, and exposing the isolation region.

[0074] Figure 8 In this embodiment, a patterned mask is formed on the first dielectric layer 7 by photolithography, and then the second type contact hole 8 is formed by etching.

[0075] Those skilled in the art will appreciate that steps S104 and S105 do not need to be performed separately, but can be implemented in the same process step. The two types of contact holes are formed by a common patterning process of photolithography and etching, without the addition of additional steps.

[0076] Generally speaking, for the same process platform, the size of the first type of contact hole is fixed and uniform, while the size of the second type of contact hole is not fixed and is closely related to the size of the STI trench.

[0077] In one embodiment, the orthographic projection of the second type contact hole 8 on the substrate 1 falls within the orthographic projection of the isolation region 3 on the substrate 1 , that is, the orthographic projection of the sidewall of the second type contact hole on the STI surface does not exceed the boundary of the STI.

[0078] Furthermore, to ensure a sufficient process window, the distance between the orthographic projection boundary of the second type contact hole 8 on the substrate 1 and the orthographic projection boundary of the isolation region 3 on the substrate 1 is more than 5% of the lateral dimension of the second type contact hole 8 .

[0079] In this embodiment, if Figure 9 As shown. When the STI size is large, the size of a single second-class contact hole will also be large. At this time, the size gap between the two types of contact holes is large, and the related contact hole process will have a large local load effect. If the same step of etching, PVD tungsten filling and planarization process is used, the effects will form a large difference in the first-class contact hole and the second-class contact hole area, which will bring great challenges to the process window. In order to circumvent this problem, when the lateral size of a single second-class contact hole is more than twice that of the first-class contact hole, the original single second-class contact hole can be split into multiple ones, each of which has the same (same and close) lateral size as the first-class contact hole. This will reduce the load effect caused by local pattern differences and expand the contact-related process window.

[0080] Step S106: forming a first filling material to fill the first type contact hole and the second type contact hole, respectively contacting the electrode and the isolation region.

[0081] Figure 10 FIG. 3 is a cross-sectional view after performing this step. In this embodiment, the first filling material is a radiation-resistant material, such as tungsten.

[0082] In this embodiment, when the first filling material is tungsten, preferably, 100 to 200 angstroms of Ti and 200 to 500 angstroms of TiN are first deposited by physical vapor deposition. The Ti / TiN layer can prevent tungsten from reacting with silicon and facilitate the adhesion of the subsequent tungsten layer. Then, rapid annealing is used to heat to 600 to 700 degrees Celsius to repair crystal damage on the silicon surface caused by etching, while alloying the Ti / TiN layer with silicon. Then, a tungsten layer is deposited by chemical vapor deposition to fill the first type contact hole and the second type contact hole.

[0083] Step S107 : forming a first metal layer on the first type contact hole, electrically connected to the first filling material in the first type contact hole.

[0084] Figure 11 The figure shows a cross-sectional view after performing this step. The first metal layer 10 only needs to be connected to the first type of contact hole, and the second type of contact hole does not need to be connected to the metal layer. For example, in a CMOS process, the metal layer can be a copper wire or an aluminum wire.

[0085] At this point, the most basic structure of this application has been completed.

[0086] Further, if Figure 1 As shown, the preparation method of the present application also includes:

[0087] forming a second dielectric layer 11 on the first dielectric layer 7;

[0088] A first type of through hole 16 and a second type of through hole 17 are formed in the second dielectric layer 11, wherein the first type of through hole 16 exposes the first metal layer 10, and the orthographic projection of the second type of through hole 17 on the substrate 1 includes the orthographic projection of the second type of contact hole 8 on the substrate 1;

[0089] forming a second filling material and a third filling material to fill the first type through-hole 16 and the second type through-hole 17 respectively, wherein the second filling material is electrically connected to the first metal layer 10, and both the third filling material and the second filling material are radiation-resistant materials;

[0090] A second metal layer 12 is formed on the first type via 16 and is electrically connected to the second filling material in the first type via 16 .

[0091] The number of back-end metal layers depends on the needs of the front-end device and can be one or more layers. The figure uses two layers as an example.

[0092] When the metal layer adopts the aluminum wire process, that is, when the metal layer is made of aluminum, the second filling material and the third filling material both use tungsten, which is a radiation-resistant material. This means that if the second filling material and the third filling material are formed at the same time, the dual effects of satisfying the radiation-resistant function and simplifying the process can be achieved.

[0093] Of course, the third filling material and the second filling material may also be formed separately.

[0094] It should be noted that in CMOS processes, when the metal layer uses a copper wire process, a dual damascene structure is generally adopted. That is, the metal layer and the second filler material are both made of copper. If the third filler material is formed simultaneously with the second filler material, it is also copper. Because copper has weak radiation resistance, the radiation resistance function is mainly provided by the first filler material in the first-type contact hole. Therefore, to enhance the radiation resistance, the third filler material can be a radiation-resistant material, but it needs to be formed separately from the second filler material.

[0095] It should be pointed out that although the various steps in the above embodiments are described in a specific order, those skilled in the art will understand that in order to achieve the effect of the present application, different steps do not have to be performed in such an order. They can be performed simultaneously (in parallel) or in other orders. These changes are within the scope of protection of the present application.

[0096] Thus far, the technical solutions of the present application have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is readily understood by those skilled in the art that the scope of protection of the present application is obviously not limited to these specific embodiments. Without departing from the principles of the present application, those skilled in the art may make equivalent changes or substitutions to the relevant technical features, and the technical solutions after such changes or substitutions will fall within the scope of protection of the present application.

Claims

1. A semiconductor device comprising: substrate; an isolation region in the substrate and an active region defined by the isolation region; Active devices located in the active area and on the surface of the active area; a first dielectric layer covering the isolation region, the active region, and the active devices on the surface of the active region; A first type contact hole, penetrating the first dielectric layer and exposing the electrode of the active device; a second type contact hole penetrating the first dielectric layer and exposing the isolation region; A first filling material is filled in the first-type contact hole and the second-type contact hole, respectively contacting the electrode and the isolation region, wherein the first filling material is a radiation-resistant material; The first metal layer is located on the first-type contact hole and is electrically connected to the first filling material in the first-type contact hole.

2. The semiconductor device according to claim 1, wherein The orthographic projection of the second-type contact hole on the substrate falls within the orthographic projection range of the isolation region on the substrate.

3. The semiconductor device according to claim 2, wherein: A distance between a boundary of an orthographic projection of the second-type contact hole on the substrate and a boundary of an orthographic projection of the isolation region on the substrate is greater than 5% of a lateral dimension of the second-type contact hole.

4. The semiconductor device according to claim 2 or 3, characterized in that The second type contact holes include a plurality of contact holes, and the lateral size of each second type contact hole is equivalent to the lateral size of the first type contact hole.

5. The semiconductor device according to claim 1, wherein The active device is a field effect transistor, and the electrodes include a gate, a source, and a drain; or the active device is a triode, and the electrodes include a base, a collector, and an emitter; or the active device is a diode, and the electrodes include an anode and a cathode. The semiconductor device according to claim 1 , wherein: The isolation region is a shallow trench isolation region or a silicon local oxidation isolation region.

7. The semiconductor device according to claim 1, wherein The first filling material is tungsten.

8. The semiconductor device according to claim 1, wherein Also includes: a second dielectric layer located on the first dielectric layer; a first type of through-hole and a second type of through-hole located in the second dielectric layer, wherein the first type of through-hole exposes the first metal layer, and the orthographic projection of the second type of through-hole on the substrate includes the orthographic projection of the second type of contact hole on the substrate; A second filling material and a third filling material are filled in the first type of through-holes and the second type of through-holes, respectively, wherein the second filling material is electrically connected to the first metal layer, and both the third filling material and the second filling material are radiation-resistant materials; The second metal layer is located on the first-type through-holes and is electrically connected to the second filling material in the first-type through-holes.

9. The semiconductor device according to claim 8, wherein The second filling material and the third filling material are both tungsten.

10. A method for strengthening a semiconductor device against radiation, comprising: forming an isolation region and an active region defined by the isolation region in a substrate; forming active devices in the active area and on the surface of the active area; forming a first dielectric layer to cover the isolation region, the active region, and the active devices on the surface of the active region; forming a first type contact hole penetrating the first dielectric layer to expose the electrode of the active device; forming a second type contact hole penetrating the first dielectric layer to expose the isolation region; forming a first filling material to fill the first-type contact hole and the second-type contact hole, respectively contacting the electrode and the isolation region, wherein the first filling material is a radiation-resistant material; A first metal layer is formed on the first-type contact hole and is electrically connected to the first filling material in the first-type contact hole.

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