Driving circuit, voltage converter, chip and electronic equipment

Abstract

The embodiment of the invention provides a driving circuit, a voltage converter, a chip and electronic equipment, the circuit comprises a low-side turn-off detection circuit, a high-side logic control circuit, a high-side turn-off detection circuit and a low-side logic control circuit, the low-side turn-off detection circuit is configured to judge the state of a low-side power tube, and the high-side turn-off detection circuit is configured to judge the state of the low-side power tube; after it is determined that the low-side power tube is turned off, a high-side turn-on indication signal of the high-side power tube is generated; the high-side logic control circuit is configured to control opening of the high-side power tube according to the high-side opening indication signal and output a control signal of the high-side power tube; the high-side turn-off detection circuit is configured to judge the state of the high-side power tube and generate a low-side turn-on indication signal of the low-side power tube after determining that the high-side power tube is turned off; and the low-side logic control circuit is configured to control opening of the low-side power tube according to the low-side opening indication signal and output a control signal of the low-side power tube. The problems that the dead time of an existing power tube driving scheme is long, and the efficiency is reduced are solved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular, to a driving circuit, a voltage converter, a chip, and an electronic device. Background Art

[0002] As electronic devices become increasingly integrated and complex, higher technical requirements are placed on voltage converter chips. The power stage generally requires sufficient drive capability to quickly turn the power transistor on and off, minimizing dynamic losses during on / off transitions. Furthermore, it must ensure that spikes and glitches caused by parasitic circuits during the on / off switching process do not disrupt the power transistor. Furthermore, to further improve converter efficiency, dead time must be minimized.

[0003] Regarding the drive of the voltage converter power tube, in the existing technical solutions, such as Figure 1 The figure shows the general structure of a driver circuit, which includes a non-overlap clock generation module (non-overlap), a low-voltage domain to high-voltage domain module (LVSH), driver stage circuits D1 and D2, and power transistors M0 and M1. The PWM waveform is a control signal, a pulse-width modulation signal generated by the voltage converter's control loop based on the feedback voltage VFB of the output voltage Vout. PWM is used to control the on / off of the high-side power transistor M0 and the low-side power transistor M1. The non-overlap module's main function is to generate two non-overlapping signals, HS and LS, to control the high-side power transistor M0 and the low-side power transistor M1, respectively, ensuring that the power transistors M0 and M1 are not turned on simultaneously, which would cause crosstalk. Because PWM is generally a low-voltage domain signal within the chip, while the high-side power transistor M0 requires corresponding high-voltage domain control, the non-overlap output signal HS is converted to the high-voltage domain via the LVSH module. D1 and D2 serve as a driver enhancement stage, their function is to quickly turn the power transistors M0 and M1 on or off. Regarding the above-mentioned existing power tube driving solution, the inventors found that this solution has a large dead time, which will reduce efficiency. Summary of the Invention

[0004] The embodiments described in this disclosure provide a driving circuit, a voltage converter, a chip, and an electronic device to reduce dead time and improve efficiency.

[0005] According to a first aspect of the present disclosure, a driving circuit is provided, which is used to drive the high-side power tube and the low-side power tube of the voltage converter to turn on and off. The driving circuit includes: a low-side shutdown detection circuit, a high-side logic control circuit, a high-side shutdown detection circuit, and a low-side logic control circuit; the low-side shutdown detection circuit is coupled to the low-side logic control circuit and is configured to judge the state of the low-side power tube after the low-side logic control circuit receives the low-side shutdown indication signal of the low-side power tube, and generate a high-side start indication signal of the high-side power tube after determining that the low-side power tube is turned off; the high-side logic control circuit is coupled to the low-side shutdown detection circuit and is configured The high-side logic control circuit is configured to receive the high-side start-up indication signal, control the start-up of the high-side power tube according to the high-side start-up indication signal, and output the control signal of the high-side power tube; the high-side shutdown detection circuit is configured to judge the state of the high-side power tube after the high-side logic control circuit receives the high-side shutdown indication signal of the high-side power tube, and generate a low-side start-up indication signal of the low-side power tube after determining that the high-side power tube is shut down; the low-side logic control circuit is coupled to the high-side shutdown detection circuit, and is configured to receive the low-side start-up indication signal, control the start-up of the low-side power tube according to the low-side start-up indication signal, and output the control signal of the low-side power tube.

[0006] Optionally, controlling the turning on of the high-side power tube according to the high-side turning on indication signal includes: controlling the turning on of the high-side power tube in three stages according to different driving currents according to the high-side turning on indication signal.

[0007] Optionally, determining the state of the high-side power tube includes: detecting the voltage of a switch node, and determining whether the high-side power tube is turned off according to the voltage of the switch node, where the switch node is a connection node between the high-side power tube and the low-side power tube.

[0008] Optionally, determining the state of the low-side power tube includes: detecting a preceding signal of a control signal of the low-side power tube, and determining whether the low-side power tube is turned off based on the preceding signal, wherein the preceding signal is a driving voltage signal at a certain level between the low-side shutdown indication signal and the control signal of the low-side power tube.

[0009] Optionally, the three stages include a voltage rise stage, a current conversion stage, and a voltage conversion stage, and the high-side logic control circuit includes: a voltage domain conversion unit, a main control unit, and a first auxiliary control unit. The voltage domain conversion unit is configured to receive the high-side start indication signal or the high-side shutdown indication signal, and perform a conversion process from a low voltage domain to a high voltage domain on the high-side start indication signal or the high-side shutdown indication signal; the main control unit is configured to obtain the control signal of the high-side power tube after logical processing of the converted high-side start indication signal or the converted high-side shutdown indication signal; the first auxiliary control unit is configured to control one or two auxiliary transistors through a delay circuit to increase the driving current of the high-side power tube control signal in the voltage rise stage and the voltage conversion stage.

[0010] Optionally, the low-side logic control circuit includes: an even number of inverters connected in series, wherein the input end of the first inverter receives the low-side shutdown indication signal or the low-side start indication signal, the output end of the last inverter outputs the control signal of the high-side power tube, and the previous stage signal is the output signal of any inverter between the first inverter and the last inverter.

[0011] Optionally, when the serial number of the inverter corresponding to the previous-stage signal is an even number, the low-side shutdown detection circuit includes: a detection unit, wherein the detection unit is configured to collect the previous-stage signal, and when the level of the previous-stage signal is flipped, the previous-stage signal is passed to the high-side logic control circuit as the high-side start-up indication signal.

[0012] Optionally, when the serial number of the inverter corresponding to the previous-stage signal is an odd number, the low-side shutdown detection circuit includes: a detection unit and a logic conversion unit, wherein the detection unit is coupled to the logic conversion unit and is configured to couple the previous-stage signal, and when the level of the previous-stage signal is flipped, the previous-stage signal is passed to the logic conversion unit; the logic conversion unit is configured to invert the output of the detection unit and then output the high-side start-up indication signal.

[0013] Optionally, the main control unit includes: a first buffer, a first transistor, and a second transistor, wherein the input end of the first buffer is coupled to the output end of the voltage domain conversion unit, and the output end of the first buffer is respectively coupled to the control electrode of the first transistor and the control electrode of the second transistor; the first electrode of the first transistor is coupled to the bootstrap voltage, and the second electrode of the first transistor is respectively coupled to the second electrode of the second transistor and the control electrode of the high-side power tube, and the second electrode of the first transistor outputs the control signal of the high-side power tube; the first electrode of the second transistor is coupled to the switching node, and the switching node is the connection node between the high-side power tube and the low-side power tube.

[0014] Optionally, the first auxiliary control unit includes: a first delay unit, a second delay unit, a third transistor, a fourth transistor, a second buffer, and a third buffer. The first delay unit and the second delay unit constitute the delay circuit, and the third transistor and the fourth transistor are both auxiliary transistors. The input end of the first delay unit and the input end of the second delay unit are both coupled to the output end of the voltage domain conversion unit, the output end of the first delay unit is coupled to the input end of the second buffer, and the output end of the second delay unit is coupled to the input end of the third buffer; the output end of the second buffer is coupled to the control electrode of the third transistor, and the output end of the third buffer is coupled to the control electrode of the fourth transistor; the first electrode of the third transistor and the first electrode of the fourth transistor are both coupled to the bootstrap voltage, and the second electrode of the third transistor and the second electrode of the fourth transistor are both coupled to the control electrode of the high-side power tube; the first delay unit controls the third transistor to be in the on state in the voltage rising stage and in the off state in the current conversion stage and the voltage conversion stage; the second delay unit controls the fourth transistor to be in the off state in the voltage rising stage and the current conversion stage, and to be in the on state in the voltage conversion stage.

[0015] Optionally, the first auxiliary control unit includes: a third delay unit, a fourth delay unit, a logic control unit, a fifth transistor, and a fourth buffer, wherein the third delay unit, the fourth delay unit, and the logic control unit constitute the delay circuit, and the fifth transistor is an auxiliary transistor, wherein the input end of the third delay unit and the input end of the fourth delay unit are both coupled to the output end of the voltage domain conversion unit, and the output end of the third delay unit and the output end of the fourth delay unit are respectively coupled to two input ends of the logic control unit; the output end of the logic control unit is coupled to the input end of the fourth buffer, and the output end of the fourth buffer is coupled to the control electrode of the fifth transistor; the first electrode of the fifth transistor is coupled to the bootstrap voltage, and the second electrode of the fifth transistor is coupled to the control electrode of the high-side power tube; the logic control unit selects the third delay unit or the fourth delay unit to control the fifth transistor; the third delay unit controls the fifth transistor to be in the on state in the voltage rising stage and in the off state in the current conversion stage and the voltage conversion stage; the fourth delay unit controls the fifth transistor to be in the off state in the voltage rising stage and the current conversion stage, and to be in the on state in the voltage conversion stage.

[0016] Optionally, the high-side shutdown detection circuit includes: a first resistor, a second resistor, a sixth transistor, a seventh transistor, and a fifth buffer, wherein one end of the first resistor is coupled to the switch node, and the other end of the first resistor is coupled to the second electrode of the sixth transistor; the first electrode of the sixth transistor is coupled to the control electrode of the seventh transistor; the first electrode of the seventh transistor is coupled to the ground end, and the second electrode of the seventh transistor is respectively coupled to one end of the second resistor and the input end of the fifth buffer; the other end of the second resistor is coupled to the power supply voltage; and the output end of the fifth buffer outputs the low-side turn-on indication signal.

[0017] Optionally, the high-side logic control circuit also includes: a second auxiliary control unit, which is configured to control an auxiliary transistor through a fifth delay unit to increase the driving current of the control signal of the high-side power tube during the process of shutting down the high-side power tube.

[0018] Optionally, the second auxiliary control unit includes: a fifth delay unit, a sixth buffer, and an eighth transistor, wherein the eighth transistor is an auxiliary transistor, wherein the input end of the fifth delay unit is coupled to the output end of the voltage domain conversion unit, the output end of the fifth delay unit is coupled to the input end of the sixth buffer, the output end of the sixth buffer is coupled to the control electrode of the eighth transistor, the first electrode of the eighth transistor is coupled to the switching node, the switching node is the connection node between the high-side power tube and the low-side power tube, and the second electrode of the eighth transistor is coupled to the control electrode of the high-side power tube.

[0019] Optionally, the driving circuit also includes a first logic processing circuit and a second logic processing circuit, wherein the first logic processing circuit is configured to output a low-side shutdown indication signal as a valid control signal for shutting down the low-side power tube, and output the low-side startup indication signal as a valid control signal for turning on the low-side power tube, and the low-side shutdown indication signal is generated by a pulse width modulation signal; the second logic processing circuit is configured to output a high-side shutdown indication signal as a valid control signal for shutting down the high-side power tube, and output the high-side startup indication signal as a valid control signal for turning on the high-side power tube, and the high-side shutdown indication signal is generated by the pulse width modulation signal.

[0020] Optionally, the first logic processing circuit is also used to output a start signal for turning on the low-side power tube to the low-side logic control circuit when the maximum dead time is reached if the low-side start indication signal cannot be detected within a preset maximum dead time.

[0021] According to a second aspect of the present disclosure, a voltage converter is provided, comprising the drive circuit according to any one of the first aspects.

[0022] According to a third aspect of the present disclosure, a chip is provided, comprising the voltage converter according to the second aspect.

[0023] According to a fourth aspect of the present disclosure, an electronic device is provided, comprising the chip according to the third aspect.

[0024] In the drive circuit of the embodiment of the present disclosure, when the low-side power tube is turned off and the high-side power tube is turned on, the state of the low-side power tube is judged, and after determining that the low-side power tube is turned off, a high-side turn-on indication signal for the high-side power tube is generated. In addition, when the high-side power tube is turned off and the low-side power tube is turned on, the state of the high-side power tube is judged, and after determining that the high-side power tube is turned off, a low-side turn-on indication signal for the low-side power tube is generated. Compared with the existing solution of controlling the turn-on of the high-side power tube and the low-side power tube through PWM, the dead time can be reduced and the efficiency can be improved. Furthermore, the voltage converter, chip, and electronic device containing the drive circuit of the embodiment of the present disclosure can also improve efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure and are not intended to limit the present disclosure.

[0026] Figure 1 A schematic structural diagram of a conventional voltage converter power tube drive circuit is shown;

[0027] Figure 2-7 Schematic block diagrams of six driving circuits according to embodiments of the present disclosure are shown;

[0028] Figure 8 An exemplary circuit diagram of a high-side logic control circuit according to an embodiment of the present disclosure is shown;

[0029] Figure 9 An exemplary circuit diagram of a high-side logic control circuit according to another embodiment of the present disclosure is shown;

[0030] Figure 10-11 Schematic circuit diagrams showing a low-side logic control circuit and two low-side shutdown detection circuits according to an embodiment of the present disclosure;

[0031] Figure 12 An exemplary circuit diagram of a high-side shutdown detection circuit according to an embodiment of the present disclosure is shown;

[0032] Figure 13 An exemplary circuit diagram of a high-side logic control circuit according to another embodiment of the present disclosure is shown;

[0033] Elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0035] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal manner unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or through one or more intermediate components.

[0036] In all embodiments of the present disclosure, since the source and drain of a metal oxide semiconductor (MOS) transistor are symmetrical, and the directions of the conduction current between the source and drain of an N-type transistor and a P-type transistor are opposite, in the embodiments of the present disclosure, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. In addition, terms such as "first" and "second" are only used to distinguish one component (or a portion of a component) from another component (or another portion of a component).

[0037] In order to solve the problem that the existing power tube driving scheme has a large dead time and reduces efficiency. A new driving circuit for driving the power tube is proposed. In the driving circuit of the embodiment of the present disclosure, when the low-side power tube is turned off and the high-side power tube is turned on, the state of the low-side power tube is judged, and after determining that the low-side power tube is turned off, a high-side turn-on indication signal of the high-side power tube is generated; in addition, when the high-side power tube is turned off and the low-side power tube is turned on, the state of the high-side power tube is judged, and after determining that the high-side power tube is turned off, a low-side turn-on indication signal of the low-side power tube is generated. Compared with the existing scheme of controlling the turning on of the high-side power tube and the low-side power tube through PWM, the dead time can be reduced and the efficiency can be improved. The driving circuit of the present disclosure is described in detail below.

[0038] like Figure 2 FIG. 1 is a schematic block diagram of a driving circuit 100 according to an embodiment of the present disclosure, wherein the driving circuit 100 is used to drive the high-side power tube HS and the low-side power tube LS of the voltage converter to turn on and off. Figure 2The middle driving circuit 100 includes: a low-side shutdown detection circuit 110, a high-side logic control circuit 120, a high-side shutdown detection circuit 130, and a low-side logic control circuit 140.

[0039] The low-side shutdown detection circuit 110 is configured to determine the state of the low-side power tube LS after the low-side logic control circuit 140 receives the low-side shutdown indication signal PWM1 of the low-side power tube LS, and generate the high-side start indication signal C2 of the high-side power tube HS after determining that the low-side power tube LS is turned off. Specifically, the embodiment of the present disclosure provides two methods for determining the state of the low-side power tube LS. The first method is: Figure 3 As shown, by detecting the control signal VGS1 of the low-side power tube LS to determine whether the low-side power tube LS is turned off; the second method: as Figure 4 As shown, by detecting the front-stage signal C1 of the control signal VGS1 of the low-side power tube LS, it is determined whether the low-side power tube LS is turned off. The front-stage signal C1 is a driving voltage signal at a certain level between the low-side shutdown indication signal PWM1 and the control signal VGS1 of the low-side power tube.

[0040] In the first method, when it is detected that VGS1 is less than a certain threshold value (the conduction threshold voltage of the power tube), it can be determined that the low-side power tube LS is turned off. After it is determined to be turned off, the signal can be used as the high-side start-up indication signal C2 of the high-side power tube HS to control the high-side power tube HS to turn on. Compared with the prior art of controlling the high-side power tube HS to turn on through a PWM signal, the dead time can be reduced.

[0041] In the second method, the low-side power tube LS is determined to be off by detecting the precursor signal C1 of the control signal VGS1 of the low-side power tube LS. Compared to the first method of determining whether the low-side power tube LS is off by detecting the control signal VGS1 of the low-side power tube LS, this method can accelerate the detection of the low-side power tube LS off state and reduce the dead time from the low-side off to the high-side on state. This is because after the low-side logic control circuit 140 receives the low-side off indication signal PWM1 of the low-side power tube LS, the precursor signal C1 of the control signal VGS1 of the low-side power tube LS reacts (toggles) more quickly than the control signal VGS1 of the low-side power tube LS. After determining that the low-side power tube LS is off, the high-side on indication signal C2 of the high-side power tube HS is generated based on the precursor signal C1. This reduces the dead time and prevents the high-side power tube HS and the low-side power tube LS from being turned on simultaneously, thereby generating cross-current. It should be noted that the front-stage signal C1 in the embodiment of the present disclosure can be the front-stage, front-two-stage, front-three-stage, etc., as long as it is an intermediate signal of the low-side shutdown detection circuit 110 .

[0042] The high-side logic control circuit 120 is coupled to the low-side shutdown detection circuit 110 and is configured to receive the high-side start-up indication signal C2, and control the start-up of the high-side power tube HS according to the high-side start-up indication signal C2, and output the control signal VGS0 of the high-side power tube HS. The high-side start-up indication signal C2 indicates that the high-side power tube HS can be turned on. After receiving the high-side start-up indication signal C2, the high-side logic control circuit 120 executes the control logic for turning on the high-side power tube HS. Because the high-side power tube HS requires corresponding high-voltage domain control, it is necessary to first perform voltage domain conversion, and then accelerate the start-up of HS through the driver stage circuit (buffer) to generate VGS0. The driver stage circuit here is different from the prior art ( Figure 1 ) is the same as the driving stage circuit D1.

[0043] Furthermore, in order to increase the rising speed of the switch node SW, a control logic for turning on the high-side power transistor HS is also provided. Specifically, after the high-side start-up indication signal C2 is converted into the voltage domain, the start-up of the high-side power transistor HS is controlled in three stages according to different drive currents (three-stage start-up mode), and the control signal VGS0 of the high-side power transistor HS is output. Specifically, the three stages include a voltage rise stage, a current conversion stage, and a voltage conversion stage. The voltage rise stage refers to the stage in which the voltage of the control signal VGS0 of the high-side power transistor HS is rapidly increased. The current conversion stage is the stage in which the voltage of the control signal VGS0 of the high-side power transistor HS reaches the turn-on threshold and current conversion occurs between the high-side power transistor HS and the low-side power transistor LS. The voltage conversion stage is the stage in which the voltage of the control signal VGS0 of the high-side power transistor HS rises to the Miller voltage and current conversion is completed between the high-side power transistor HS and the low-side power transistor LS, and then the voltage conversion stage begins. To accelerate the voltage rise rate at the switch node SW (the node between the high-side power transistor HS and the low-side power transistor LS) while also preventing the power transistor from breaking down, the disclosed embodiment increases the drive capability (drive current) in the first and third stages, accelerating the voltage rise rate. In the second stage, the drive capability is reduced to prevent the power transistor from breaking down. The change in drive capability can be controlled by increasing or decreasing the number of transistors used for driving.

[0044] The high-side shutdown detection circuit 130 is configured to determine the state of the high-side power tube HS after the high-side logic control circuit 120 receives the high-side shutdown indication signal PWM2 of the high-side power tube HS, and generate the low-side start indication signal C3 of the low-side power tube LS after determining that the high-side power tube HS is turned off. Specifically, the embodiment of the present disclosure provides two methods for determining the state of the high-side power tube HS. The first method is: Figure 3 As shown, by detecting the control signal VGS0 of the high-side power tube HS, it is determined whether the high-side power tube HS is turned off; the second method: as Figure 5 or Figure 6 As shown, the voltage of the switch node SW is detected, and whether the high-side power tube HS is turned off is determined according to the voltage of the switch node SW. The switch node SW is a connection node between the high-side power tube HS and the low-side power tube LS.

[0045] In the first method, when it is detected that VGS0 is less than a certain threshold (the conduction threshold voltage of the power tube), it can be determined that the high-side power tube HS is turned off. After it is determined to be turned off, the signal can be used as the high-side start-up indication signal C3 of the low-side power tube LS to control the low-side power tube LS to turn on. Compared with the prior art of controlling the low-side power tube LS to turn on through a PWM signal, the dead time can be reduced.

[0046] In the second approach, after the high-side logic control circuit 120 receives the high-side shutdown indication signal PWM2 of the high-side power transistor HS, it controls the shutdown of the high-side power transistor HS. The corresponding control signal VGS0 of the high-side power transistor HS gradually decreases. After decreasing to the Miller voltage, the voltage of the switch node SW begins to rapidly decrease from the input voltage VIN. When the voltage of the switch node SW decreases to the turn-on threshold of the corresponding transistor in the high-side shutdown detection circuit 130, it indicates that the high-side power transistor HS is turned off, and the low-side turn-on indication signal C3 of the low-side power transistor LS is output. Compared to the first approach of determining whether the high-side power transistor HS is turned off by detecting the control signal VGS0 of the high-side power transistor HS, this method can speed up the detection of the shutdown state of the high-side power transistor HS and reduce the dead time from the high-side turn-off to the low-side turn-on process.

[0047] The low-side logic control circuit 140 is coupled to the high-side shutdown detection circuit 130 , and is configured to control the start of the low-side power transistor LS according to the received low-side start indication signal C3 , and output a control signal VGS1 of the low-side power transistor LS.

[0048] The low-side start-up indication signal C3 indicates that the low-side power transistor LS can be turned on. After receiving the low-side start-up indication signal C3, the low-side logic control circuit 140 executes the control logic for turning on the low-side power transistor LS. In the embodiment of the present disclosure, the control method for turning on the low-side power transistor LS can be any existing implementation method for obtaining the control signal VGS1 of the low-side power transistor LS based on the low-side start-up indication signal C3, and the embodiment of the present disclosure is not limited thereto. For example, a common implementation method is to use multiple inverters connected in series.

[0049] In addition, the low-side shutdown indication signal PWM1 and the high-side shutdown indication signal PWM2 are generated by a pulse width modulation signal PWM, and PWM is a pulse width modulation signal obtained by the feedback voltage VFB of the output voltage Vout in the control loop of the voltage converter. Usually, two non-overlapping signals are generated by PWM to control the high-side power tube HS and the low-side power tube LS respectively, to ensure that the two power tubes are not turned on at the same time to generate a series current. Normally, the two non-overlapping signals generated by PWM can control both the shutdown and the opening of the two power tubes, but in the embodiment of the present disclosure, only the function of controlling the shutdown of the two power tubes is applied, and the opening of the two power tubes is controlled by the high-side opening indication signal C2 and the low-side opening indication signal C3 generated by the low-side shutdown detection circuit 110 and the high-side shutdown detection circuit 130 mentioned above. In order to realize the aforementioned control and avoid control conflicts of multiple control signals, a second logic processing circuit 160 and a first logic processing circuit 150 are added to the front stage of the high-side logic control circuit 120 and the low-side logic control circuit 140, respectively. As Figure 7FIG2 is a schematic block diagram of another driving circuit 100 according to an embodiment of the present disclosure, which shows the connection relationship between the first logic processing circuit 150 and the second logic processing circuit 160 in the circuit. The input end of the first logic processing circuit 150 is coupled to the PWM1 signal and the low-side start indication signal C3, and the output end is the PWM1 signal or the low-side start indication signal C3; the input end of the second logic processing circuit 160 is coupled to the PWM2 signal and the high-side start indication signal C2, and the output end is the PWM2 signal or the high-side start indication signal C2. Specifically, the first logic processing circuit 150 is configured to output the low-side shutdown indication signal PWM1 as the effective control signal for shutting down the low-side power transistor LS, and to output the low-side start indication signal C3 as the effective control signal for turning on the low-side power transistor LS. That is, when shutting down the low-side power transistor LS, the PWM1 signal functions as an effective control signal, and even if the state of the low-side on-indication signal C3 could shut down the low-side power transistor LS, the control signal remains invalid. When turning on the low-side power transistor LS, the low-side on-indication signal C3 functions as an effective control signal, and even if the PWM1 signal could turn on the low-side power transistor LS, the control signal remains invalid. Similarly, the second logic processing circuit 160 is configured to output the high-side shut-down indication signal PWM2 as an effective control signal when shutting down the high-side power transistor HS, and to output the high-side on-indication signal C2 as an effective control signal when turning on the high-side power transistor HS. That is, when shutting down the high-side power transistor HS, the PWM2 signal functions as an effective control signal, and even if the state of the high-side on-indication signal C2 could shut down the high-side power transistor HS, the control signal remains invalid. When turning on the high-side power transistor HS, the high-side on-indication signal C2 functions as an effective control signal, and even if the PWM2 signal could turn on the high-side power transistor HS, the control signal remains invalid.

[0050] From the above description, it can be seen that in the driving circuit 100 of the embodiment of the present disclosure, when the low-side power tube is turned off and the high-side power tube is turned on, the state of the low-side power tube is judged, and a high-side turn-on indication signal of the high-side power tube is generated after determining that the low-side power tube is turned off; in addition, when the high-side power tube is turned off and the low-side power tube is turned on, the state of the high-side power tube is judged, and a low-side turn-on indication signal of the low-side power tube is generated after determining that the high-side power tube is turned off. Compared with the existing solution of controlling the turn-on of the high-side power tube and the low-side power tube through PWM, the dead time can be reduced and the efficiency can be improved.

[0051] Further, such as Figure 8 As shown, a schematic block diagram of a high-side logic control circuit 120 is provided. Figure 8The high-side logic control circuit 120 corresponds to the second method for determining the state of the high-side power transistor HS in the aforementioned embodiment, and includes: a voltage domain conversion unit 121, a main control unit 122, and a first auxiliary control unit 123. Among them, the voltage domain conversion unit 121 is configured to receive the high-side start indication signal C2 or the high-side shutdown indication signal PWM2, and perform a low-voltage domain to high-voltage domain conversion process on the high-side start indication signal C2 or the high-side shutdown indication signal PWM2. The high-side start indication signal C2 and the high-side shutdown indication signal PWM2 are generally low-voltage domain signals, while the high-side power transistor HS requires high-voltage domain control, so the high-side start indication signal C2 or the high-side shutdown indication signal PWM2 needs to be converted to the high-voltage domain through the voltage domain conversion unit 121.

[0052] The main control unit 122 is configured to obtain the control signal VGS0 of the high-side power transistor HS through logic control of the high-side turn-on indication signal C2 after the conversion process or the high-side turn-off indication signal PWM2 after the conversion process; further, as Figure 8 As shown, the main control unit 122 includes: a first buffer B1, a first transistor M1, and a second transistor M2, wherein the input end of the first buffer B1 is coupled to the output end of the voltage domain conversion unit 121, and the output end of the first buffer B1 is respectively coupled to the control electrode of the first transistor M1 and the control electrode of the second transistor M2; the first electrode of the first transistor M1 is coupled to the bootstrap voltage BST, the second electrode of the first transistor M1 is respectively coupled to the second electrode of the second transistor M2 and the control electrode of the high-side power transistor HS, and the second electrode of the first transistor M1 outputs the control signal VGS0 of the high-side power transistor HS; the first electrode of the second transistor M2 is coupled to the switch node SW.

[0053] The first auxiliary control unit 123 is configured to control one or two auxiliary transistors through a delay circuit to increase the driving force (driving current) of the high-side power tube HS control signal VGS0 in the voltage rising stage (first stage) and the voltage conversion stage (third stage). Figure 8As shown, the first auxiliary control unit 123 includes: a first delay unit 1231 and a second delay unit 1232, a third transistor M3, a fourth transistor M4, a second buffer B2, and a third buffer B3. The first delay unit 1231 and the second delay unit 1232 constitute the aforementioned delay circuit. The third transistor M3 and the fourth transistor M4 are both auxiliary transistors. The input end of the first delay unit 1231 and the input end of the second delay unit 1232 are both coupled to the output end of the voltage domain conversion unit 121, the output end of the first delay unit 1231 is coupled to the input end of the second buffer B2, and the output end of the second delay unit 1232 is coupled to the input end of the third buffer B3. input terminal; the output terminal of the second buffer B2 is coupled to the control terminal of the third transistor M3, and the output terminal of the third buffer B3 is coupled to the control terminal of the fourth transistor M4; the first terminal of the third transistor M3 and the first terminal of the fourth transistor M4 are both coupled to the bootstrap voltage BST, and the second terminal of the third transistor M3 and the second terminal of the fourth transistor M4 are both coupled to the control terminal of the high-side power tube HS; the first delay unit 1231 controls the third transistor M3 to be in the on state during the voltage rising stage and to be in the off state during the current conversion stage and the voltage conversion stage, and the second delay unit 1232 controls the fourth transistor M4 to be in the off state during the voltage rising stage and the current conversion stage, and to be in the on state during the voltage conversion stage.

[0054] Further, such as Figure 9 As shown, the embodiment of the present disclosure further provides another circuit structure of the first auxiliary control unit 123, specifically including: a third delay unit 1233, a fourth delay unit 1234, a logic control unit 1235, a fifth transistor M5, and a fourth buffer B4. The third delay unit 1233, the fourth delay unit 1234, and the logic control unit 1235 constitute the aforementioned delay circuit, and the fifth transistor M5 is an auxiliary transistor; wherein the input end of the third delay unit 1233 and the input end of the fourth delay unit 1234 are both coupled to the output end of the voltage domain conversion unit 121, and the output end of the third delay unit 1233 and the output end of the fourth delay unit 1234 are respectively coupled to the two input ends of the logic control unit 1235; The output end of the control unit 1235 is coupled to the input end of the fourth buffer B4, and the output end of the fourth buffer B4 is coupled to the control end of the fifth transistor M5; the first end of the fifth transistor M5 is coupled to the bootstrap voltage BST, and the second end of the fifth transistor M5 is coupled to the control end of the high-side power transistor HS; the logic control unit 1235 selects whether the third delay unit 1233 or the fourth delay unit 1234 controls the fifth transistor M5; the third delay unit 1233 controls the fifth transistor M5 to be in the on state during the voltage rising phase and to be in the off state during the current conversion phase and the voltage conversion phase; the fourth delay unit 1234 controls the fifth transistor M5 to be in the off state during the voltage rising phase and the current conversion phase, and to be in the on state during the voltage conversion phase. Figure 9 The first auxiliary control unit 123 in Figure 8 Compared with the first auxiliary control unit 123 in Figure 9 Two delay units control the same transistor (driver tube) in the first and third stages, simplifying the circuit. Figure 9 The optimization is within the protection scope of the embodiments of the present disclosure.

[0055] Further, such as Figure 10 As shown in FIG11 , the low-side logic control circuit 140 includes an even number of inverters connected in series, wherein the input of the first inverter receives the low-side shutdown indication signal PWM1 or the low-side start indication signal C3, and the output of the last inverter outputs the control signal VGS1 of the high-side power transistor HS. The pre-stage signal C1 is the output signal of any inverter between the first inverter and the last inverter. It should be noted that Figure 10 and Figure 11 The connection method between the low-side logic control circuit 140 and the low-side shutdown detection circuit 110 corresponds to the second method for determining the state of the low-side power tube LS in the aforementioned embodiment; if it is the first method, the VGS1 signal is connected to the low-side shutdown detection circuit 110.

[0056] Furthermore, when the serial number of the inverter corresponding to the front-stage signal C1 is an even number, such as Figure 10 As shown, the low-side shutdown detection circuit 110 includes: a detection unit 111, which is configured to collect the previous stage signal C1, and when the level of the current stage signal C1 is flipped, the previous stage signal C1 is transmitted to the high-side logic control circuit 120 as the high-side start indication signal C2.

[0057] Furthermore, when the serial number of the inverter corresponding to the front-stage signal C1 is an odd number, such as Figure 11 As shown, the low-side shutdown detection circuit 110 includes: a detection unit 111 and a logic conversion unit 112, wherein the detection unit 111 is coupled to the logic conversion unit 112 and is configured to couple to the previous stage signal C1. When the level of the current stage signal C1 is flipped, the previous stage signal C1 is passed to the logic conversion unit 112; the logic conversion unit 112 is configured to invert the output of the detection unit 111 and output the high-side turn-on indication signal C2.

[0058] It should be noted that, for the second method of judging the state of the low-side power tube LS in the above embodiment, Figure 10-11The schematic diagram in FIG. 1 shows two configurations of the low-side shutdown detection circuit 110. One configuration includes only the detection unit 111. In this configuration, the pre-stage signal C1 is output from an even-numbered inverter except the last inverter, that is, the pre-stage signal C1 is in phase with the control signal VGS1 of the low-side power tube LS. The other configuration includes the detection unit 111 and the logic conversion unit 112. In this configuration, the pre-stage signal C1 is output from an odd-numbered inverter except the first inverter, that is, the pre-stage signal C1 is in phase opposite to the control signal VGS1 of the low-side power tube LS.

[0059] In addition, it should be noted that, for the first method of judging the state of the low-side power tube LS in the above embodiment, the shutdown state of the low-side power tube LS is judged by detecting VGS1, and VGS1 and C1 are in phase, so Figure 10 The low-side shutdown detection circuit 110 in FIG. 1 is also applicable to the first method of determining the state of the low-side power tube LS.

[0060] Further, such as Figure 12 As shown, the high-side shutdown detection circuit 130 includes: a first resistor R1, a second resistor R2, a sixth transistor M6, a seventh transistor M7, and a fifth buffer B5, wherein one end of the first resistor R1 is coupled to the switch node SW, and the other end of the first resistor R1 is coupled to the second electrode of the sixth transistor M6; a first electrode of the sixth transistor M6 is coupled to the control electrode of the seventh transistor M7; a first electrode of the seventh transistor M7 is coupled to the ground terminal, and a second electrode of the seventh transistor M7 is respectively coupled to one end of the second resistor R2 and an input terminal of the fifth buffer B5; the other end of the second resistor R2 is coupled to the power supply voltage VDD; and an output terminal of the fifth buffer B5 outputs a low-side turn-on indication signal C3. Figure 12 The high-side shutdown detection circuit 130 compares the voltage of the switch node SW with the threshold voltage of the transistor (M7) to obtain the voltage state information of SW and use it to determine whether the high-side power tube HS is turned off. It should be noted that Figure 12 The high-side shutdown detection circuit 130 in FIG. 1 corresponds to the method of determining whether the high-side is shut down according to the voltage of SW in the aforementioned embodiment.

[0061] Further, in Figure 8 、 Figure 9 On the basis of Figure 13 As shown, the high-side logic control circuit 120 further includes: a second auxiliary control unit 124, which is configured to control an auxiliary transistor through a fifth delay unit to increase the driving force (driving current) of the control signal VGS0 of the high-side power tube HS during the process of turning off the high-side power tube HS. Figure 13As shown, the second auxiliary control unit 124 includes a fifth delay unit 1241, a sixth buffer B6, and an eighth transistor M8 (serving as an auxiliary transistor). The input of the fifth delay unit 1241 is coupled to the output of the voltage domain conversion unit 121, the output of the fifth delay unit 1241 is coupled to the input of the sixth buffer B6, the output of the sixth buffer B6 is coupled to the control electrode of the eighth transistor M8, the first electrode of the eighth transistor M8 is coupled to the switch node SW, and the second electrode of the eighth transistor M8 is coupled to the control electrode of the high-side power transistor HS. The second auxiliary control unit 124 can prevent the high-side power transistor HS from being turned on via the integrated capacitor when the low-power transistor is turned on when the high-side power transistor HS is turned off.

[0062] Further, combined Figure 6 、 8 , 10, and 12 illustrate the working principle of a driving circuit 100 according to an embodiment of the present disclosure: First, it is assumed that the low-side logic control circuit 140 includes four inverters, and the front-stage signal C1 is the output signal of the second inverter. When the low-side logic control circuit 140 receives the low-side shutdown indication signal PWM1, i.e., when PWM1 is at a low level, C1 flips ahead of VGS1. The low-side shutdown detection circuit 110 generates C2, which is also at a low level. After being converted to the high voltage domain by the voltage domain conversion unit 121, the high-side power transistor HS is turned on in a three-stage mode. In the first stage, the first delay unit 1231 controls M3 and M1 to turn on simultaneously, thereby generating a large drive to rapidly increase VGS0. In the second stage, the first delay unit 1231 controls M3 to turn off, leaving only M1 on. This stage is designed to turn off M3 when VGS0 approaches the turn-on threshold of HS (e.g., 80% or 90% of the turn-on threshold). In theory, M3 can be turned off when it reaches the turn-on threshold, but in practice, there may be a delay. To prevent M3 from remaining on in the second stage, M3 is turned off when VGS0 approaches the turn-on threshold of HS. In the second stage, M3 is turned off to reduce the driving force. At this time, there will be current conversion between HS and LS, and the conversion rate is di / dt. Due to the existence of parasitic inductance, di / dt will cause SW to produce burrs. Therefore, the driving capability is made as small as possible in the current conversion stage. Such a smaller di / dt will cause SW to produce smaller burrs and ensure that HS is not broken down. In the third stage, M4 is controlled to turn on through the second delay unit 1232. When VGS0 rises to the Miller platform (reaching the Miller voltage), the current conversion is completed and the voltage conversion begins. At this time, M4 is turned on, and the driving capability increases again, so that SW rises with a larger dv / dt. After the third stage, M4 is controlled to turn off through the second delay unit 1232.

[0063] The above is the process and principle of the transition from the low-side power transistor LS being turned off to the high-side power transistor HS being turned on. The following describes the process and principle of the transition from the high-side power transistor HS being turned off to the low-side power transistor LS being turned on: When the high-side logic control circuit 120 receives the high-side shutdown indication signal PWM2, i.e., when PWM2 is high, the voltage of VGS0 gradually decreases. After reaching the Miller plateau, SW rapidly decreases from VIN. At this time, the high-side shutdown detection circuit 130 detects the voltage of SW. Specifically, when the voltage of SW is high, it remains high after passing through M6, turning on M7. The second electrode (drain) of M7 is pulled low, and the output C3 is also low, indicating that the high-side power transistor HS has not yet been turned off. When the voltage of SW drops to a certain threshold, i.e., below the voltage threshold (turn-on threshold) of M7, the voltage of the second electrode of M7 increases, and the output C3 is also high, indicating that the high-side power transistor HS has been turned off. C3 is then input to the low-side logic control circuit 140, thereby causing VGS1 to turn high and control LS to turn on.

[0064] It can be seen from the working principle of the driving circuit 100 described above that the driving circuit 100 in the embodiment of the present disclosure can reduce the dead time and also ensure that the power tube is not broken down.

[0065] Furthermore, in actual applications, taking into account special circumstances, that is, if the low-side turn-on indication signal C3 output by the high-side shutdown detection circuit 130 cannot be detected, the first logic processing circuit 150 is further configured to output a turn-on signal for turning on the low-side power transistor LS to the low-side logic control circuit 140 when the preset maximum dead time is reached if the low-side turn-on indication signal C3 cannot be detected within the preset maximum dead time. Specifically, a maximum dead time can be generated using a PWM signal to ensure that even if the low-side turn-on indication signal C3 output by the high-side shutdown detection circuit 130 cannot be detected, the low-side power transistor LS can be turned on after the preset maximum dead time.

[0066] The embodiment of the present disclosure further provides a voltage converter, which includes the driving circuit of the embodiment of the present disclosure. The voltage converter is a DCDC converter, which can be a BUCK converter or a Boost converter.

[0067] An embodiment of the present disclosure further provides a chip, which includes a voltage converter according to an embodiment of the present disclosure.

[0068] An embodiment of the present disclosure further provides an electronic device, which includes a chip according to an embodiment of the present disclosure.

[0069] In summary, the driving circuit, voltage converter, chip, and electronic device in the embodiments of the present disclosure can reduce dead time and improve efficiency.

[0070] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular includes the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "include" and "comprising" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a group of terms, "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0071] Further aspects and scope of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present disclosure can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended to be illustrative only and are not intended to limit the scope of the present disclosure.

[0072] Several embodiments of the present disclosure have been described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.

Claims

1. A drive circuit for driving a high-side power tube and a low-side power tube of a voltage converter to turn on and off, characterized in that: The driving circuit includes: a low-side shutdown detection circuit, a high-side logic control circuit, a high-side shutdown detection circuit, and a low-side logic control circuit; The low-side shutdown detection circuit is coupled to the low-side logic control circuit and is configured to, after the low-side logic control circuit receives the low-side shutdown indication signal of the low-side power tube, determine the state of the low-side power tube and generate a high-side start indication signal of the high-side power tube after determining that the low-side power tube is turned off; The high-side logic control circuit is coupled to the low-side shutdown detection circuit, and is configured to receive the high-side start-up indication signal, control the start-up of the high-side power tube according to the high-side start-up indication signal, and output a control signal of the high-side power tube; The high-side shutdown detection circuit is configured to, after the high-side logic control circuit receives the high-side shutdown indication signal of the high-side power tube, determine the state of the high-side power tube, and generate a low-side start indication signal for the low-side power tube after determining that the high-side power tube is turned off; The low-side logic control circuit is coupled to the high-side shutdown detection circuit, and is configured to receive the low-side start-up indication signal, control the start-up of the low-side power tube according to the low-side start-up indication signal, and output the control signal of the low-side power tube.

2. The driving circuit according to claim 1, wherein: The controlling the turning on of the high-side power tube according to the high-side turning on indication signal comprises: According to the high-side start-up indication signal, the start-up of the high-side power tube is controlled in three stages according to different driving currents.

3. The driving circuit according to any one of claims 1 or 2, characterized in that: Determining the state of the high-side power tube includes: Detecting the voltage of a switch node, and determining whether the high-side power tube is turned off according to the voltage of the switch node, wherein the switch node is a connection node between the high-side power tube and the low-side power tube.

4. The driving circuit according to claim 1 or 2, characterized in that: Determining the state of the low-side power tube includes: Detect a preceding signal of the control signal of the low-side power tube, and determine whether the low-side power tube is turned off according to the preceding signal, wherein the preceding signal is a driving voltage signal at a certain level between the low-side shutdown indication signal and the control signal of the low-side power tube.

5. The driving circuit according to claim 2, wherein: The three stages include a voltage rise stage, a current conversion stage, and a voltage conversion stage. The high-side logic control circuit includes: a voltage domain conversion unit, a main control unit, and a first auxiliary control unit. The voltage domain conversion unit is configured to receive the high-side start indication signal or the high-side shutdown indication signal, and perform a low-voltage domain to high-voltage domain conversion process on the high-side start indication signal or the high-side shutdown indication signal; The main control unit is configured to obtain the control signal of the high-side power tube by performing logic processing on the high-side start indication signal after the conversion process or the high-side shut-off indication signal after the conversion process; The first auxiliary control unit is configured to control one or two auxiliary transistors through a delay circuit to increase the driving current of the high-side power tube control signal in the voltage rising stage and the voltage conversion stage.

6. The driving circuit according to claim 4, wherein: The low-side logic control circuit includes: an even number of inverters connected in series, wherein the input end of the first inverter receives the low-side shutdown indication signal or the low-side startup indication signal, the output end of the last inverter outputs the control signal of the high-side power tube, and the previous stage signal is the output signal of any inverter between the first inverter and the last inverter.

7. The driving circuit according to claim 6, wherein: When the serial number of the inverter corresponding to the previous stage signal is an even number, the low-side shutdown detection circuit includes: a detection unit, The detection unit is configured to collect the front-stage signal, and when the level of the front-stage signal is reversed, transmit the front-stage signal as the high-side start indication signal to the high-side logic control circuit.

8. The driving circuit according to claim 6, wherein: When the serial number of the inverter corresponding to the previous stage signal is an odd number, the low-side shutdown detection circuit includes: a detection unit, a logic conversion unit, The detection unit is coupled to the logic conversion unit and is configured to couple to the previous stage signal and transmit the previous stage signal to the logic conversion unit after the level of the previous stage signal is reversed; The logic conversion unit is configured to invert the output of the detection unit and then output the high-side start indication signal.

9. The driving circuit according to claim 5, wherein: The main control unit includes: a first buffer, a first transistor, and a second transistor. The input terminal of the first buffer is coupled to the output terminal of the voltage domain conversion unit, and the output terminal of the first buffer is coupled to the control electrode of the first transistor and the control electrode of the second transistor respectively; The first electrode of the first transistor is coupled to the bootstrap voltage, the second electrode of the first transistor is coupled to the second electrode of the second transistor and the control electrode of the high-side power tube respectively, and the second electrode of the first transistor outputs the control signal of the high-side power tube; A first electrode of the second transistor is coupled to a switch node, and the switch node is a connection node between the high-side power transistor and the low-side power transistor.

10. The driving circuit according to claim 9, wherein: The first auxiliary control unit includes: a first delay unit, a second delay unit, a third transistor, a fourth transistor, a second buffer, and a third buffer. The first delay unit and the second delay unit constitute the delay circuit. The third transistor and the fourth transistor are both auxiliary transistors. The input end of the first delay unit and the input end of the second delay unit are both coupled to the output end of the voltage domain conversion unit, the output end of the first delay unit is coupled to the input end of the second buffer, and the output end of the second delay unit is coupled to the input end of the third buffer; The output terminal of the second buffer is coupled to the control terminal of the third transistor, and the output terminal of the third buffer is coupled to the control terminal of the fourth transistor; The first electrode of the third transistor and the first electrode of the fourth transistor are both coupled to the bootstrap voltage, and the second electrode of the third transistor and the second electrode of the fourth transistor are both coupled to the control electrode of the high-side power transistor; The first delay unit controls the third transistor to be in the on state during the voltage rising stage, and in the off state during the current conversion stage and the voltage conversion stage; the second delay unit controls the fourth transistor to be in the off state during the voltage rising stage and the current conversion stage, and to be in the on state during the voltage conversion stage.

11. The driving circuit according to claim 9, wherein: The first auxiliary control unit includes: a third delay unit, a fourth delay unit, a logic control unit, a fifth transistor, and a fourth buffer. The third delay unit, the fourth delay unit, and the logic control unit constitute the delay circuit. The fifth transistor is an auxiliary transistor. The input end of the third delay unit and the input end of the fourth delay unit are both coupled to the output end of the voltage domain conversion unit, and the output end of the third delay unit and the output end of the fourth delay unit are respectively coupled to the two input ends of the logic control unit; An output terminal of the logic control unit is coupled to an input terminal of the fourth buffer, and an output terminal of the fourth buffer is coupled to a control terminal of the fifth transistor; A first electrode of the fifth transistor is coupled to the bootstrap voltage, and a second electrode of the fifth transistor is coupled to the control electrode of the high-side power transistor; The logic control unit selects the third delay unit or the fourth delay unit to control the fifth transistor; The third delay unit controls the fifth transistor to be in the on state during the voltage rising stage, and in the off state during the current conversion stage and the voltage conversion stage; the fourth delay unit controls the fifth transistor to be in the off state during the voltage rising stage and the current conversion stage, and to be in the on state during the voltage conversion stage.

12. The driving circuit according to claim 10 or 11, characterized in that: The high-side shutdown detection circuit includes: a first resistor, a second resistor, a sixth transistor, a seventh transistor, and a fifth buffer. Wherein, one end of the first resistor is coupled to the switch node, and the other end of the first resistor is coupled to the second electrode of the sixth transistor; The first electrode of the sixth transistor is coupled to the control electrode of the seventh transistor; A first electrode of the seventh transistor is coupled to the ground terminal, and a second electrode of the seventh transistor is respectively coupled to one end of the second resistor and the input terminal of the fifth buffer; The other end of the second resistor is coupled to a power supply voltage; The output end of the fifth buffer outputs the low-side start indication signal.

13. The driving circuit according to claim 5, wherein: The high-side logic control circuit further includes: a second auxiliary control unit, The second auxiliary control unit is configured to control an auxiliary transistor through a fifth delay unit to increase the driving current of the control signal of the high-side power tube when the high-side power tube is turned off.

14. The driving circuit according to claim 13, wherein: The second auxiliary control unit includes: a fifth delay unit, a sixth buffer, and an eighth transistor, wherein the eighth transistor is an auxiliary transistor. Among them, the input end of the fifth delay unit is coupled to the output end of the voltage domain conversion unit, the output end of the fifth delay unit is coupled to the input end of the sixth buffer, the output end of the sixth buffer is coupled to the control electrode of the eighth transistor, the first electrode of the eighth transistor is coupled to the switch node, the switch node is the connection node between the high-side power tube and the low-side power tube, and the second electrode of the eighth transistor is coupled to the control electrode of the high-side power tube.

15. The driving circuit according to claim 1 or 2, characterized in that: The driving circuit further includes a first logic processing circuit and a second logic processing circuit. The first logic processing circuit is configured to output a low-side shutdown indication signal as a valid control signal for shutting down the low-side power tube, and output the low-side start indication signal as a valid control signal for turning on the low-side power tube, wherein the low-side shutdown indication signal is generated by a pulse width modulation signal; The second logic processing circuit is configured to output a high-side shutdown indication signal as a valid control signal for shutting down the high-side power tube, and to output the high-side start-up indication signal as a valid control signal for turning on the high-side power tube, wherein the high-side shutdown indication signal is generated by the pulse width modulation signal.

16. The driving circuit according to claim 15, wherein: The first logic processing circuit is further configured to output a start signal for turning on the low-side power tube to the low-side logic control circuit when the maximum dead time is reached if the low-side start indication signal cannot be detected within a preset maximum dead time.

17. A voltage converter, characterized in that: The voltage converter includes the drive circuit according to any one of claims 1 to 16.

18. A chip, characterized in that: The chip includes the voltage converter according to claim 17.

19. An electronic device, characterized in that: The electronic device comprises the chip according to claim 18.

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