PWM controller based on FPGA parallel-serial conversion and control method thereof
The PWM controller with FPGA parallel-serial conversion solves the wiring error and PLL resource occupation problems of traditional PWM controllers, achieves high-precision PWM wave output, and optimizes FPGA resource utilization.
Patent Information
- Application Number
- CN202510816472.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-18
- Publication Date
- 2025-09-26
AI Technical Summary
The traditional FPGA implementation of PWM controllers has problems such as large wiring errors, low accuracy, and excessive use of PLL resources.
A PWM controller based on FPGA parallel-serial conversion is used. Through the parallel-serial conversion code calculation unit, parallel-serial conversion module and signal output pin, high-precision PWM waves are generated by parallel-serial data conversion, avoiding wiring errors and reducing PLL resource usage.
It achieves high-precision PWM control, reduces wiring errors, optimizes FPGA resource usage, and improves the output accuracy and efficiency of PWM waves.
Smart Images
Figure CN120710484A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the technical field of PWM controllers, and more specifically, relates to a PWM controller based on FPGA parallel-to-serial conversion and a control method thereof. Background Art
[0002] Pulse Width Modulation (PWM) controllers are common peripherals in microcontroller units (MCUs) and digital signal processing (DSPs) devices. Their theoretical accuracy typically reaches 10-5ns, and their channel count is limited. With the rapid development of the power electronics industry, the demand for high-precision PWM controllers, a crucial component of DC-DC (DC-DC) power supply precision control, is growing. Furthermore, as the demand for multiple channels increases in application scenarios, FPGAs are often used as development platforms to implement multi-channel PWM wave control.
[0003] In the existing technology, the traditional method of using FPGA to implement PWM controller is to use a phase-locked loop (PLL) to shift the main frequency clock phase to generate M clocks with different phases but the same frequency. These M derived clocks are then used to oversample the PWM wave in the main clock domain. Subsequently, these derived PWM waves are logically ANDed or logically ORed based on the calculated duty cycle, thereby generating a PWM wave with higher precision than the clock frequency, with a theoretical accuracy of 1 / M times the clock period.
[0004] However, the above-mentioned traditional PWM wave control method uses combinational logic output of signals generated by clocks with different phases, which will cause the actual output PWM wave to have uncertain and irreversible wiring errors, resulting in low accuracy. At the same time, it occupies too many PLL resources.
[0005] Therefore, how to better realize the control of PWM wave has become a technical problem that needs to be solved urgently in the industry. Summary of the Invention
[0006] In response to the defects of the existing technology, the purpose of this application is to better realize the control of PWM waves, aiming to solve the problem that the PWM waves actually output by the traditional PWM wave control method have uncertain and irreversible wiring errors, low accuracy, and at the same time, occupy too many PLL resources.
[0007] To achieve the above objectives, in a first aspect, the present application provides a PWM controller based on FPGA parallel-to-serial conversion, comprising: FPGA; The FPGA includes a parallel-to-serial conversion code calculation unit, a parallel-to-serial conversion module, and a signal output pin connected in sequence; The parallel-to-serial conversion code calculation unit is used to convert the preset PWM wave high-level period data into a maximum number code with a bit width of N of the target period number and a single low-bit mask with a bit width of N; N is the parallel-to-serial conversion ratio of the parallel-to-serial conversion module; The parallel-to-serial conversion module is configured to generate a PWM wave corresponding to the preset PWM wave high-level period data based on the maximum number code of the input target cycle number with a bit width of N and the low-bit mask of the single bit width of N; The signal output pin is used to output the PWM wave.
[0008] Optionally, the parallel-to-serial conversion code calculation unit includes an arithmetic logic module and a parallel-to-serial conversion code calculation module connected in sequence; The arithmetic logic module is used to convert the preset PWM wave high level period data into the corresponding quotient and remainder; The parallel-to-serial conversion code calculation module is used to output the maximum number code of the target cycle number with a bit width of N based on the quotient, and convert the remainder into the single low-bit mask with a bit width of N.
[0009] Optionally, the arithmetic logic module includes an arithmetic logic submodule and a first divider connected in sequence: The arithmetic logic submodule is used to output a calculation result of multiplying the preset PWM wave high-level period data by the parallel-to-serial conversion ratio based on the input preset carrier period, the preset PWM wave duty cycle and the parallel-to-serial conversion ratio; The first divider is configured to perform a division operation based on the operation result and the parallel-to-serial conversion ratio, and output the quotient and the remainder; The preset carrier period and the preset PWM wave duty cycle are determined based on the preset PWM wave high level period data.
[0010] Optionally, the arithmetic logic submodule includes a multiplier and a second divider connected in sequence; The multiplier is used to perform a multiplication operation according to the input preset carrier period, the preset PWM wave high level time and the parallel-to-serial conversion ratio, and output a multiplication result; The second divider is used to perform a division operation based on the multiplication result and the preset PWM wave cycle time, and output the operation result of multiplying the preset PWM wave high level period data and the parallel-to-serial conversion ratio; the preset PWM wave duty cycle is the ratio of the preset PWM wave high level time to the preset PWM wave cycle time.
[0011] Optionally, the parallel-to-serial conversion module is an Oserdes module.
[0012] Optionally, when the FPGA uses a single Oserdes module, the value of N includes 2, 3, 4, 5, 6, 7, and 8; when the FPGA uses two Oserdes modules connected in series, the value of N includes 4, 6, 8, 10, and 14.
[0013] Optionally, the accuracy of the PWM wave is the ratio of the main frequency clock period of the FPGA to N.
[0014] Optionally, the Oserdes module operates in ODDR mode.
[0015] In a second aspect, the present application provides a control method for the PWM controller based on FPGA parallel-to-serial conversion as described above, comprising: Convert the preset PWM wave high-level period data into a maximum number code with a bit width of N for the target number of periods and a single low-bit mask with a bit width of N; N is the parallel-to-serial conversion ratio of the parallel-to-serial conversion module; Generate a PWM wave corresponding to the preset PWM wave high-level period data based on the input maximum number code of the target cycle number with a bit width of N and the single low-bit mask with a bit width of N; Output the PWM wave.
[0016] Optionally, the step of converting the preset PWM wave high-level period data into a maximum number code with a bit width of N of the target period number and a single low-bit mask with a bit width of N includes: Converting the preset PWM wave high level period data into corresponding quotient and remainder; Outputting a maximum number code having a bit width of N of the target number of cycles based on the quotient; The remainder is converted into the single low-bit mask with a bit width of N.
[0017] Optionally, converting the preset PWM wave high-level period data into corresponding quotients and remainders includes: Outputting a calculation result of multiplying the preset PWM wave high-level period data by the parallel-to-serial conversion ratio according to the input preset carrier period, the preset PWM wave duty cycle and the parallel-to-serial conversion ratio; Performing a division operation based on the operation result and the parallel-to-serial conversion ratio, and outputting the quotient and the remainder; The preset carrier period and the preset PWM wave duty cycle are determined based on the preset PWM wave high level period data.
[0018] Optionally, outputting a calculation result of multiplying the preset PWM wave high-level period data by the parallel-to-serial conversion ratio according to the input preset carrier period, the preset PWM wave duty cycle, and the parallel-to-serial conversion ratio includes: Performing a multiplication operation according to the input preset carrier period, the preset PWM wave high level time and the parallel-to-serial conversion ratio, and outputting the multiplication result; Performing a division operation based on the multiplication result and a preset PWM wave cycle time, and outputting an operation result of multiplying the preset PWM wave high-level period data by the parallel-to-serial conversion ratio; The preset PWM wave duty cycle is the ratio of the preset PWM wave high level time to the preset PWM wave cycle time.
[0019] Optionally, the parallel-to-serial conversion module is an Oserdes module.
[0020] In general, the above technical solutions conceived by this application have the following beneficial effects compared with the existing technologies: The present application provides a PWM controller based on FPGA parallel-to-serial conversion and a control method thereof. By using FPGA as a development platform, a parallel-to-serial conversion code calculation unit, a parallel-to-serial conversion module, and a signal output pin connected in sequence are designed. The preset PWM wave high-level period data is converted into a maximum number code with a bit width of N for the target period number and a single low-bit mask with a bit width of N, which are input into the parallel-to-serial conversion module. By using the parallel-to-serial data conversion method, a PWM wave corresponding to the preset PWM wave high-level period data is generated according to the maximum number code with a bit width of N for the target period number and the single low-bit mask with a bit width of N. The output data timing path is reliably determined, and the output of the PWM wave is free from the wiring errors caused by traditional methods. The PWM wave output error can be effectively reduced, and a high-precision PWM controller can be realized. There is no need to change the peripheral hardware of the FPGA, and PLL resources will not be occupied, thereby optimizing the use of FPGA resources. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 This is one of the structural diagrams of the PWM controller based on FPGA parallel-to-serial conversion provided in an embodiment of the present application; Figure 2 This is a schematic diagram of the working principle of the parallel-to-serial conversion module provided in an embodiment of the present application; Figure 3 This is the second structural diagram of the PWM controller based on FPGA parallel-to-serial conversion provided in an embodiment of the present application; Figure 4 This is a flow chart of a control method for a PWM controller based on FPGA parallel-to-serial conversion provided in an embodiment of the present application. DETAILED DESCRIPTION
[0022] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.
[0023] In the specification and claims of this application, the terms "first" and "second" are used to distinguish different objects, rather than to describe a specific order of objects. For example, the terms "first divider" and "second divider" are used to distinguish different dividers, rather than to describe a specific order of dividers.
[0024] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.
[0025] In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more, for example, multiple processing units means two or more processing units, etc.; multiple elements means two or more elements, etc.
[0026] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application.
[0027] Figure 1 This is one of the structural diagrams of the PWM controller based on FPGA parallel-to-serial conversion provided in the embodiment of the present application, such as Figure 1 As shown, including: FPGA 1; The FPGA 1 includes a parallel-to-serial conversion code calculation unit 10, a parallel-to-serial conversion module 20, and a signal output pin 30 connected in sequence; The parallel-to-serial conversion code calculation unit 10 is used to convert the preset PWM wave high-level period data into a maximum number code with a bit width of N of the target period number and a single low-bit mask with a bit width of N; N is the parallel-to-serial conversion ratio of the parallel-to-serial conversion module; The parallel-to-serial conversion module 20 is used to generate a PWM wave corresponding to a preset PWM wave high-level period data based on the maximum number code of the input target cycle number with a bit width of N and a single low-bit mask with a bit width of N; The signal output pin 30 is used to output a PWM wave.
[0028] Specifically, the preset PWM wave high-level period data described in the embodiment of the present application refers to a preset high-level period of the PWM wave to be generated, which can be determined based on the period of the PWM wave to be generated and its set duty cycle.
[0029] The maximum number encoding described in the embodiments of the present application refers to the encoding corresponding to the maximum number represented when the bit width is N. For example, if N is 8, the binary encoding corresponding to the maximum number represented by 8 bits is "8'b1111_1111".
[0030] In the embodiment of the present application, if N is 8, the data represented by the low-order mask with a bit width of 8 is 3, which can be expressed as “8'b0000_0111”.
[0031] The target number of cycles described in the embodiment of the present application refers to the total period of the maximum number encoded with a bit width of N, which can be determined according to the specific value of the preset PWM wave high-level period data.
[0032] In the embodiment of the present application, a high-precision PWM wave is output by introducing a parallel-to-serial conversion code calculation unit, a parallel-to-serial conversion module and a signal output pin on an FPGA development platform to realize a high-precision PWM controller.
[0033] More specifically, the parallel-to-serial conversion code calculation unit, the parallel-to-serial conversion module, and the signal output pin are sequentially connected. The parallel-to-serial conversion code calculation unit is primarily used to convert the preset PWM wave high-level period data into a maximum number code with a bit width of N for the target number of periods and a single low-bit mask with a bit width of N, where N is the parallel-to-serial conversion ratio of the parallel-to-serial conversion module, for example, N = 8.
[0034] The parallel-to-serial conversion module can receive the maximum number code with a bit width of N for the target number of cycles and a single low-bit mask with a bit width of N output by the parallel-to-serial conversion code calculation unit, and through the parallel-to-serial data conversion function, output the maximum number code with a bit width of N for the target number of cycles and the single low-bit mask with a bit width of N according to high and low levels, that is, it can generate a PWM wave corresponding to the preset PWM wave high-level period data.
[0035] In the embodiment of the present application, the parallel-to-serial conversion module may be an Oserdes module or an OSERDESE2 module, wherein the OSERDESE2 module is an upgraded version of the Oserdes module in the FPGA.
[0036] Based on the content of the above embodiment, as an optional embodiment, the parallel-to-serial conversion module may be an Oserdes module.
[0037] Specifically, in this embodiment, the OserDes module hardcore resource can be selected as the core hardware of the PWM controller. The physical characteristics of this hardcore determine the stable and reliable output high and low levels. The device converts the input code (the value has a bit width of N and ranges from 0 to 2^(N-1)) into 0 to N high levels within a CLKDIV cycle, generating a PWM wave.
[0038] Based on the contents of the above embodiments, as an optional embodiment, when the FPGA uses a single Oserdes module as a parallel-to-serial conversion module, the values of the parallel-to-serial conversion ratio N may include 2, 3, 4, 5, 6, 7, and 8; when performing bit width expansion, two Oserdes modules may also be connected in series as a parallel-to-serial conversion module. In this way, when the FPGA uses two Oserdes modules connected in series, the values of the parallel-to-serial conversion ratio N may specifically include 4, 6, 8, 10, and 14.
[0039] Based on the content of the above embodiment, as an optional embodiment, the accuracy of the PWM wave is the ratio of the main frequency clock period of the FPGA to N.
[0040] Specifically, regarding the accuracy of the PWM wave, the traditional way to determine it is through clock shift sampling, and its minimum accuracy (that is, the actual minimum unit high level) is: system clock period / number of shift clocks.
[0041] In an embodiment of the present application, when parallel-to-serial conversion is adopted, the accuracy of the PWM wave is the ratio of the main frequency clock period of the FPGA to the parallel-to-serial conversion ratio N.
[0042] Specifically, assuming the FPGA's main clock period is 10ns (100MHz) and the parallel-to-serial conversion ratio N is set to 8, the PWM wave's precision is equal to the ratio of the main clock period to the parallel-to-serial conversion ratio N, which is 1.25ns. Furthermore, the clock frequency driving the OserDes module is the product of the main clock frequency and the parallel-to-serial conversion ratio N, which is 800MHz.
[0043] Based on the content of the above embodiment, as an optional embodiment, the Oserdes module operates in an (output double data rate mode) ODDR mode.
[0044] Specifically, the PWM controller supports the highest precision. When the OserDes module operates in ODDR mode, it can support a parallel-to-serial conversion ratio of up to 14:1. That is, the parallel-to-serial conversion ratio of the parallel-to-serial conversion module is 14. In this case, the PWM wave's precision can reach a maximum of the ratio of the FPGA's main clock period to 14.
[0045] The PWM controller of the embodiment of the present application can further improve the reliability of the output data timing path by introducing the Oserdes module as a parallel-to-serial conversion module. The process is simple, which is conducive to improving the accuracy and efficiency of the output PWM wave and avoiding the wiring errors caused by the combinational logic of the traditional PWM wave output.
[0046] like Figure 2 As shown in the figure, if the parallel-to-serial conversion module uses the OSERDESE2 module, in DDR mode with a parallel-to-serial conversion ratio of N = 8, the ratio of CLKDIV cycles to CLK cycles is 4. After data bits ABCDEFGH are sampled, data bit A first appears at OQ four CLK cycles later. Therefore, after the data is read from the output to OQ within the CLKDIV cycle, after four CLK cycles, the bit at position D1 is output first, followed by subsequent bits, completing the transmission of N = 8 bits of data within one CLKDIV clock, thereby converting the parallel data into a serial data stream.
[0047] Furthermore, the PWM wave generated by the parallel-to-serial conversion module is output to the peripheral circuit through the signal output pin on the FPGA.
[0048] In the embodiments of the present application, the PWM controller can output a PWM wave with a settable period and duty cycle. The high-level period of the PWM wave can be calculated based on the set PWM wave period and duty cycle, and the PWM wave accuracy (high and low level duration accuracy) is stable and reliable. Therefore, the controller can input the duty cycle and PWM period as needed, and can also set accuracy parameters as needed.
[0049] The PWM controller based on FPGA parallel-to-serial conversion in the embodiment of the present application adopts FPGA as a development platform, designs a parallel-to-serial conversion code calculation unit, a parallel-to-serial conversion module and a signal output pin connected in sequence, converts the preset PWM wave high-level period data into a maximum number code with a bit width of N for the target period number and a single low-bit mask with a bit width of N, and inputs them into the parallel-to-serial conversion module. By using the parallel-to-serial data conversion method, a PWM wave corresponding to the preset PWM wave high-level period data is generated according to the maximum number code with a bit width of N for the target period number and the single low-bit mask with a bit width of N. The output data timing path is reliably determined, and the output of the PWM wave will not have the wiring error caused by the traditional method. The PWM wave output error can be effectively reduced to realize a high-precision PWM controller. There is no need to change the peripheral hardware of the FPGA, and PLL resources will not be occupied, thereby optimizing the use of FPGA resources.
[0050] Figure 3 This is the second structural diagram of the PWM controller based on FPGA parallel-to-serial conversion provided in the embodiment of the present application, as shown in FIG. Figure 3As shown, based on the content of the above embodiment, as an optional embodiment, the parallel-to-serial conversion code calculation unit 10 includes an arithmetic logic module 11 and a parallel-to-serial conversion code calculation module 12 connected in sequence; The arithmetic logic module 11 is used to convert the preset PWM wave high level period data into the corresponding quotient and remainder; The parallel-to-serial conversion code calculation module 12 is used to output a maximum number code with a bit width of N for the target number of cycles based on the quotient, and convert the remainder into a single low-bit mask with a bit width of N.
[0051] Specifically, in the embodiments of the present application, since the FPGA can only implement multiplication and division of a limited number of bits, the parallel-to-serial conversion module, such as the Oserdes module, supports Code input from 0 to N-1. When performing carrier conversion calculations, the arithmetic logic of the FPGA can be cleverly used to introduce an arithmetic logic module to convert the preset PWM wave high-level period data into the corresponding quotient and remainder.
[0052] Continue to refer to Figure 3 Based on the content of the above embodiment, as an optional embodiment, the arithmetic logic module 11 includes an arithmetic logic submodule 111 and a first divider 112 connected in sequence: The arithmetic logic submodule 111 is used to output the calculation result of multiplying the preset PWM wave high level period data and the parallel-to-serial conversion ratio according to the input preset carrier period, preset PWM wave duty cycle and parallel-to-serial conversion ratio; The first divider 112 is used to perform a division operation based on the operation result and the parallel-to-serial conversion ratio, and output a quotient and a remainder; The preset carrier period and the preset PWM wave duty cycle are determined based on the preset PWM wave high level period data.
[0053] Specifically, in an embodiment of the present application, an arithmetic logic module can be constructed using an arithmetic logic submodule and a first divider by cleverly utilizing the logic of a divider. A preset carrier period and a preset PWM wave duty cycle can be determined in advance based on preset PWM wave high-level period data. Here, the preset carrier period can be the PWM wave period. Furthermore, the preset carrier period, preset PWM wave duty cycle, and parallel-to-serial conversion ratio N are input into the arithmetic logic submodule. Through logical operations in the arithmetic logic submodule, a result of multiplying the preset PWM wave high-level period data by the parallel-to-serial conversion ratio N is output.
[0054] Continue to refer to Figure 3 Based on the content of the above embodiment, as an optional embodiment, the arithmetic logic submodule 111 includes a multiplier 1111 and a second divider 1112 connected in sequence; The multiplier 1111 is used to perform multiplication according to the input preset carrier period, preset PWM wave high level time and parallel-to-serial conversion ratio, and output the multiplication result; The second divider 1112 is used to perform a division operation based on the multiplication result and the preset PWM wave cycle time, and output the operation result of multiplying the preset PWM wave high-level period data by the parallel-to-serial conversion ratio; the preset PWM wave duty cycle is the ratio of the preset PWM wave high-level time to the preset PWM wave cycle time.
[0055] Specifically, the preset PWM wave high-level time described in the embodiment of the present application refers to the high-level duration of the PWM wave within a PWM wave cycle time, and this parameter can be preset.
[0056] In the embodiments of this application, considering the case of floating-point calculations, FPGAs can only perform multiplication and division with a limited number of bits, which is not convenient for floating-point calculations. The final output to the OSerDes module can only be values between 0 and 2^(N-1). Therefore, it is necessary to transform the calculation formula as follows and implement it using FPGA resources.
[0057] Assume that the PWM wave duty cycle is η and the carrier period is T0. Theoretically, the number of PWM high-level system cycles in one carrier period, that is, the preset PWM wave high-level period data T, satisfies the following formula: T=η*T0; Here, the implementation method implemented by FPGA is as follows: The input value of the Oserdes module changes once per system clock cycle. Therefore, for the theoretical number of PWM high-level system cycles per carrier cycle (floating point), the integer part of Code is the maximum number, and the decimal part is normalized to 0~2^(N-1); This can be achieved using the quotient and remainder of the divider. To reduce errors, the final calculation prioritizes all multiplications and normalizes 0 to 2^(N-1) for the final calculation. Therefore, the arithmetic logic submodule can include a multiplier and a second divider connected in sequence. The final specific calculation steps are: Step 1: Use the multiplier to calculate all multiplications: perform multiplication based on the input preset carrier period T0, the preset PWM wave high-level time t, and the parallel-to-serial conversion ratio N, and output the multiplication result Temp1; wherein the preset PWM wave high-level time t is equal to the preset PWM wave high-level period data T, that is, t=T. This process can be expressed as follows: Temp1=t*T0*N; Here, the preset PWM wave duty cycle η=t / T0.
[0058] Step 2: Use the second divider to calculate the division: perform a division operation based on the multiplication result and the preset PWM wave cycle time T1, and output the operation result Temp2 of the multiplication of the preset PWM wave high-level cycle data and the parallel-to-serial conversion ratio. This process can be expressed as follows: Temp2≈Temp1 / T1; Here, the preset PWM wave cycle time is the same as the preset carrier cycle, that is, T1=T0.
[0059] Furthermore, in step three, the Code output for each clock cycle is calculated: using the first divider, the result of multiplying the input preset PWM wave high-level period data T by the parallel-to-serial conversion ratio N is divided by the parallel-to-serial conversion ratio N to obtain the operation result Temp3, and finally the corresponding quotient and remainder can be output. This process can be expressed as follows: Temp3=Temp2 / N; Here, for the quotient, the Code inputs the maximum value, that is, the value corresponding to the maximum number code. For the remainder, the Code inputs the value of the remainder converted to the low-bit mask. For the non-duty cycle part of the PWM wave, the Code inputs 0.
[0060] For example, assuming the preset carrier period is 100 cycles, and the preset duty cycle corresponding to the high-level period data T of the PWM wave is 51.5%, then when the parallel-to-serial conversion module inputs the Code code, the first 51 cycles are the maximum value, the 52nd cycle input is the mask corresponding to the calculated remainder, and the remaining 48 cycles input are 0. Through the parallel-to-serial conversion output of the parallel-to-serial conversion module, a complete cycle of the PWM wave can be output. Then, in the same way as above, the output of the next cycle of the PWM wave begins.
[0061] Among them, the value of the Code code is determined by Temp3. According to the specific value of the quotient q, the number N corresponding to the value is output. After outputting the quotient q, a low-bit mask corresponding to the remainder r is output.
[0062] Here, for example, assuming that the parallel-to-serial conversion ratio N is 8, the remainder r is converted to a low-order mask: r[3:0] = 3, its corresponding low-order mask m = 8'b0000_0111; r[3:0] = 6, its corresponding low-order mask m = 8'b0011_1111; r[3:0] = 8, and its corresponding low-order mask m = 8'b1111_1111; The value of r will not be greater than 8 (determined by the calculation of the first divider).
[0063] Furthermore, in an embodiment of the present application, after the above-mentioned Code code is input into the parallel-to-serial conversion module Oserdes module, for the quotient, the Code code inputs the maximum number code, for the remainder, the Code code inputs the remainder converted to the value of the low-bit mask, and for the non-duty cycle part (i.e., the low-level time of the PWM wave), the Code code inputs 0, which will be serialized and output from left to right, and the PWM wave can be directly output through the signal output pin of the FPGA.
[0064] The PWM controller of the embodiment of the present application utilizes the arithmetic logic function of the FPGA and cleverly uses the logic of the divider to convert the preset PWM wave high-level period data into the corresponding quotient and remainder. The parallel-to-serial serialization generation method of the parallel-to-serial conversion module is used. For the quotient, the Code code inputs the maximum value. For the remainder, the Code code inputs the value of the remainder converted to the low-bit mask. For the non-duty cycle part, the Code code inputs 0, thereby stably outputting the PWM wave. The signal timing path is determined and reliable, and the accuracy can reach below the main frequency clock period, which can effectively realize a high-precision PWM controller.
[0065] The control method of the PWM controller based on FPGA parallel-serial conversion provided in this application is described below. The control method of the PWM controller based on FPGA parallel-serial conversion described below and the PWM controller based on FPGA parallel-serial conversion described above can refer to each other.
[0066] Figure 4 1 is a flow chart of a control method of a PWM controller provided in an embodiment of the present application. It can be understood that it can be applied to any of the aforementioned FPGA-based parallel-to-serial conversion PWM controllers, such as Figure 4 As shown, the method includes: Step S1, converting the preset PWM wave high-level period data into a maximum number code with a bit width of N of the target period number and a single low-bit mask with a bit width of N; N is the parallel-to-serial conversion ratio of the parallel-to-serial conversion module; Step S2, generating a PWM wave corresponding to the preset PWM wave high-level period data based on the maximum number code of the input target cycle number with a bit width of N and a single low-bit mask with a bit width of N; Step S3, output PWM wave.
[0067] It is understandable that the specific implementation of the above-mentioned method steps can be found in the introduction of the detailed functional implementation of each unit / module in the aforementioned FPGA-based parallel-to-serial conversion PWM controller, which will not be repeated here.
[0068] The control method of the PWM controller of the embodiment of the present application adopts FPGA as a development platform, designs a parallel-to-serial conversion code calculation unit, a parallel-to-serial conversion module and a signal output pin connected in sequence, converts the preset PWM wave high-level period data into a maximum number code with a bit width of N for the target period number and a single low-bit mask with a bit width of N, and inputs them into the parallel-to-serial conversion module. By using the parallel-to-serial data conversion method, a PWM wave corresponding to the preset PWM wave high-level period data is generated according to the maximum number code with a bit width of N for the target period number and the single low-bit mask with a bit width of N. The output data timing path is reliably determined, and the output of the PWM wave will not have the wiring error caused by the traditional method. It can effectively reduce the PWM wave output error and realize a high-precision PWM controller. There is no need to change the peripheral hardware of the FPGA, and PLL resources will not be occupied, thereby optimizing the use of FPGA resources.
[0069] Based on the content of the above embodiment, as an optional embodiment, step S1, converting the preset PWM wave high-level period data into a maximum number code with a bit width of N of the target period number and a single low-bit mask with a bit width of N, includes: Convert the preset PWM wave high level period data into the corresponding quotient and remainder; Output the maximum number encoding of the target number of cycles with a bit width of N based on the quotient; Convert the remainder to a single low-bit mask of width N.
[0070] Based on the content of the above embodiment, as an optional embodiment, converting the preset PWM wave high-level period data into the corresponding quotient and remainder includes: According to the input preset carrier period, preset PWM wave duty cycle and parallel-to-serial conversion ratio, output the calculation result of multiplying the preset PWM wave high-level period data by the parallel-to-serial conversion ratio; Perform division operation based on the operation result and the parallel-to-serial conversion ratio, and output the quotient and remainder; The preset carrier period and the preset PWM wave duty cycle are determined based on the preset PWM wave high level period data.
[0071] Based on the content of the above embodiment, as an optional embodiment, according to the input preset carrier period, preset PWM wave duty cycle and parallel-to-serial conversion ratio, outputting the operation result of multiplying the preset PWM wave high-level period data by the parallel-to-serial conversion ratio includes: Perform multiplication operation based on the input preset carrier period, preset PWM wave high level time and parallel-to-serial conversion ratio, and output the multiplication result; Perform division operation on the multiplication result and the preset PWM wave cycle time, and output the operation result of multiplying the preset PWM wave high level cycle data and the parallel-to-serial conversion ratio; The preset PWM wave duty cycle is the ratio of the preset PWM wave high level time to the preset PWM wave cycle time.
[0072] Based on the content of the above embodiment, as an optional embodiment, the parallel-to-serial conversion module is an Oserdes module.
[0073] It is understood that the processor in the embodiments of the present application may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor.
[0074] The method steps in the embodiments of the present application can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, mobile hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be an integral part of the processor. The processor and storage medium can be located in an ASIC.
[0075] The above embodiments can be implemented in whole or in part using software, hardware, firmware, or any combination thereof. When implemented using software, they can be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions. When loaded and executed on a computer, the computer program instructions fully or partially produce the processes or functions described in the embodiments of this application. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted via the computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible by a computer or a data storage device such as a server or data center that integrates one or more available media. The available medium can be magnetic media (e.g., floppy disk, hard disk, tape), optical media (e.g., DVD), or semiconductor media (e.g., solid-state drive (SSD)).
[0076] It will be understood that the various numerical numbers involved in the embodiments of the present application are merely distinctions for the convenience of description and are not intended to limit the scope of the embodiments of the present application.
[0077] It should be understood that expressions such as "include" and "may include" used in this application indicate the existence of the disclosed functions, operations, or constituent elements, and do not limit one or more additional functions, operations, and constituent elements. In this application, terms such as "include" and / or "have" may be interpreted as indicating specific characteristics, numbers, operations, constituent elements, components, or combinations thereof, but may not be interpreted as excluding the existence or possibility of adding one or more other characteristics, numbers, operations, constituent elements, components, or combinations thereof.
[0078] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.
Claims
1. A PWM controller based on FPGA parallel-to-serial conversion, characterized in that: include: FPGA; The FPGA includes a parallel-to-serial conversion code calculation unit, a parallel-to-serial conversion module, and a signal output pin connected in sequence; The parallel-to-serial conversion code calculation unit is used to convert the preset PWM wave high-level period data into a maximum number code with a bit width of N of the target period number and a single low-bit mask with a bit width of N; N is the parallel-to-serial conversion ratio of the parallel-to-serial conversion module; The parallel-to-serial conversion module is configured to generate a PWM wave corresponding to the preset PWM wave high-level period data based on the maximum number code of the input target cycle number with a bit width of N and the low-bit mask of the single bit width of N; The signal output pin is used to output the PWM wave.
2. The PWM controller based on FPGA parallel-to-serial conversion according to claim 1, characterized in that: The parallel-to-serial conversion code calculation unit includes an arithmetic logic module and a parallel-to-serial conversion code calculation module connected in sequence; The arithmetic logic module is used to convert the preset PWM wave high level period data into the corresponding quotient and remainder; The parallel-to-serial conversion code calculation module is used to output the maximum number code of the target cycle number with a bit width of N based on the quotient, and convert the remainder into the single low-bit mask with a bit width of N.
3. The PWM controller based on FPGA parallel-to-serial conversion according to claim 2, characterized in that: The arithmetic logic module includes an arithmetic logic submodule and a first divider connected in sequence: The arithmetic logic submodule is used to output a calculation result of multiplying the preset PWM wave high-level period data by the parallel-to-serial conversion ratio based on the input preset carrier period, the preset PWM wave duty cycle and the parallel-to-serial conversion ratio; The first divider is configured to perform a division operation based on the operation result and the parallel-to-serial conversion ratio, and output the quotient and the remainder; The preset carrier period and the preset PWM wave duty cycle are determined based on the preset PWM wave high level period data.
4. The FPGA-based parallel-to-serial conversion PWM controller according to claim 3, characterized in that: The arithmetic logic submodule includes a multiplier and a second divider connected in sequence; The multiplier is used to perform a multiplication operation according to the input preset carrier period, the preset PWM wave high level time and the parallel-to-serial conversion ratio, and output a multiplication result; The second divider is used to perform a division operation based on the multiplication result and the preset PWM wave cycle time, and output the operation result of multiplying the preset PWM wave high level period data and the parallel-to-serial conversion ratio; the preset PWM wave duty cycle is the ratio of the preset PWM wave high level time to the preset PWM wave cycle time.
5. The FPGA-based parallel-to-serial conversion PWM controller according to any one of claims 1 to 4, characterized in that: The parallel-to-serial conversion module is an Oserdes module.
6. The FPGA-based parallel-to-serial conversion PWM controller according to claim 5, characterized in that: When the FPGA uses a single Oserdes module, the value of N includes 2, 3, 4, 5, 6, 7, and 8; when the FPGA uses two Oserdes modules connected in series, the value of N includes 4, 6, 8, 10, and 14.
7. The FPGA-based parallel-to-serial conversion PWM controller according to claim 5, characterized in that: The accuracy of the PWM wave is the ratio of the main frequency clock period of the FPGA to N.
8. The FPGA-based parallel-to-serial conversion PWM controller according to claim 7, characterized in that: The Oserdes module operates in ODDR mode.
9. A control method for a PWM controller based on FPGA parallel-to-serial conversion according to any one of claims 1 to 8, characterized in that: include: Convert the preset PWM wave high-level period data into the maximum number encoding of the target period number with a bit width of N and a single low-bit mask with a bit width of N; N is the parallel-to-serial conversion ratio of the parallel-to-serial conversion module; Generate a PWM wave corresponding to the preset PWM wave high-level period data based on the input maximum number code of the target cycle number with a bit width of N and the single low-bit mask with a bit width of N; Output the PWM wave.
10. The control method according to claim 9, characterized in that: The method of converting the preset PWM wave high-level period data into a maximum number code with a bit width of N of the target period number and a single low-bit mask with a bit width of N includes: Converting the preset PWM wave high level period data into corresponding quotient and remainder; Outputting a maximum number code having a bit width of N of the target number of cycles based on the quotient; The remainder is converted into the single low-bit mask with a bit width of N.