High-frequency circuit and communication device

Abstract

A high-frequency circuit (1) is provided with: a switching circuit (21) having terminals (21a) and (21b) and switching between connection and disconnection of the terminals (21a) and (21b); and a charge pump circuit (40) configured so as to supply a control voltage to the switching circuit (21), the switching circuit (21) being provided with: an FET (211) having a first gate, a first drain, and a first source, the first control voltage being supplied from the charge pump circuit (40) to the first gate, the first drain being connected to the terminal (21b), and the first source being connected to the terminal (21a); and an FET (217) having a second gate, a second drain, and a second source, the second gate being supplied with a second control voltage from the charge pump circuit (40), the second drain and the second source being connected to a path of the connection terminal (21b), the FET (211), and the terminal (21a), the second drain and the second source being short-circuited.

Description

Technical Field

[0001] The present invention relates to a high-frequency circuit and a communication device. Background Art

[0002] Patent Document 1 discloses a high-frequency circuit module including an RF switch, a level shifter, and a charge pump. The level shifter and the charge pump supply control voltages to the gates of multiple field effect transistors (FETs) constituting the RF switch, thereby controlling the switching operations of the multiple FETs.

[0003] Patent Document 1: International Publication No. 2019 / 009087

[0004] However, in the above-mentioned conventional technology, due to the influence of the load circuit other than the above-mentioned RF switch connected to the charge pump (voltage supply circuit), the control voltage supplied from the charge pump (voltage supply circuit) to the gate of the FET constituting the RF switch (switching circuit) fluctuates in an instantaneous state, thereby causing the terminal voltage (the drain or source of the FET) of the RF switch (switching circuit) to fluctuate in the above-mentioned instantaneous state, and the convergence time until the terminal voltage stabilizes becomes longer. Summary of the Invention

[0005] Therefore, the present invention provides a high-frequency circuit and a communication device capable of suppressing fluctuations in the terminal voltage of a switching circuit.

[0006] In order to achieve the above-mentioned purpose, a high-frequency circuit of one embodiment of the present invention comprises: a first switching circuit, having a first terminal and a second terminal, and switching the connection and non-connection of the first terminal and the second terminal; and a voltage supply circuit, configured to supply a control voltage to the first switching circuit, the first switching circuit comprising: a first FET, having a first gate, a first drain and a first source, a first control voltage being supplied from the voltage supply circuit to the first gate, one of the first drain and the first source being connected to the first terminal, and the other of the first drain and the first source being connected to the second terminal; and a second FET, having a second gate, a second drain and a second source, a second control voltage being supplied from the voltage supply circuit to the second gate, the second drain and the second source being connected to a path connecting the first terminal, the first FET and the second terminal, and the second drain and the second source being short-circuited.

[0007] According to the high-frequency circuit of one aspect of the present invention, it is possible to suppress fluctuations in the terminal voltage of the switching circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a circuit configuration diagram of a communication device according to an embodiment.

[0009] Figure 2It is a circuit configuration diagram of a charge pump circuit and a switch circuit according to an embodiment.

[0010] Figure 3 This is a graph showing the transient response characteristics of the output voltage of the charge pump circuit.

[0011] Figure 4 3 is a circuit configuration diagram of a high-frequency circuit of a comparative example.

[0012] Figure 5 It is a circuit configuration diagram of a high-frequency circuit according to an embodiment.

[0013] Figure 6A Graph showing transient response characteristics of the output voltage of a switching circuit according to a comparative example.

[0014] Figure 6B Graph showing transient response characteristics of the output voltage of the switching circuit according to the embodiment.

[0015] Figure 7 It is a circuit configuration diagram of a high-frequency circuit according to a modified example of the embodiment.

[0016] Description of Reference Numerals

[0017] 1. 1A, 500...high-frequency circuit, 2...antenna, 3...RFIC, 4...communication device, 11...low-noise amplifier circuit, 12...power amplifier circuit, 21. 21A, 22. 23. 43. 44. 521...switching circuit, 21a. 21b. 21c. 21d. 22a. 22b. 22c. 22d. 23a. 23b. 23c. 23d. 43a. 43b. 43c. 43d. 43e. 44a. 44b. 44c. 44d. 44e. 521 a, 521b, 521c, 521d…terminals, 31, 32, 33, 34, 35, 36…filter, 40…charge pump circuit, 41…positive bias circuit, 42…negative bias circuit, 51, 52…level shifter, 61, 62…bias circuit, 71, 72…inductor, 100…antenna connection terminal, 110…high-frequency output terminal, 20…high-frequency input terminal, 211, 212, 213, 214, 215, 216, 217, 218, 219…FET. DETAILED DESCRIPTION

[0018] The following describes embodiments of the present invention in detail using the accompanying drawings. The embodiments described below are generally or specifically examples. The values, shapes, materials, components, configurations of components, and connection methods shown in the following embodiments are examples and do not limit the present invention.

[0019] In addition, the figures are schematic diagrams that have been appropriately emphasized, omitted, or adjusted in proportion to illustrate the present invention, and are not necessarily strictly illustrative. Actual shapes, positional relationships, and proportions may differ. In the figures, identical components may be denoted by the same reference numerals, and duplicate descriptions may be omitted or simplified.

[0020] In the circuit structure of the present invention, "connection" includes not only direct connection through connecting terminals and / or wiring conductors, but also electrical connection via other circuit elements. "C is connected between A and B" means that one end of C is connected to A and the other end of C is connected to B. "Path between A and B" refers to the path formed by the conductor that electrically connects A and B. "Terminal" refers to the point where the conductor in the element ends. In addition, when the impedance of the conductor between the elements is low enough, the terminal is not only a single point, but can also be interpreted as any point on the conductor between the elements or the conductor as a whole.

[0021] Terms such as "parallel" and "perpendicular" that indicate the relationship between elements, terms such as "rectangular" that indicate the shape of elements, and numerical ranges do not have strict meanings but refer to actually equivalent ranges, for example, also including errors of several percent.

[0022] (Implementation Method)

[0023] Hereinafter, embodiments will be described.

[0024] [1 Circuit Structure of Communication Device 4]

[0025] First, refer to Figure 1 The circuit configuration of the communication device 4 according to this embodiment will be described. Figure 1 It is a circuit configuration diagram of the communication device 4 according to the embodiment.

[0026] It should be explained that Figure 1 The circuit configurations of the communication device 4 and the high-frequency circuit 1 are shown as examples. The communication device 4 and the high-frequency circuit 1 can be implemented using any of a variety of circuit implementations and circuit technologies. Therefore, the following description of the communication device 4 and the high-frequency circuit 1 should not be interpreted in a limiting sense.

[0027] Communication device 4 corresponds to a user equipment (UE) in a cellular communication system and is typically a mobile phone, smartphone, tablet computer, wearable device, or the like. Alternatively, communication device 4 may be an IoT (Internet of Things) sensor device, medical / healthcare equipment, a car, an unmanned aerial vehicle (UAV) (so-called drone), or an automated guided vehicle (AGV). Furthermore, communication device 4 may also function as a base station (BS) in a cellular communication system.

[0028] like Figure 1 As shown, the communication device 4 includes a high-frequency circuit 1 , an antenna 2 , and an RFIC (Radio Frequency Integrated Circuit) 3 .

[0029] The high-frequency circuit 1 can transmit a high-frequency signal between the antenna 2 and the RFIC 3. The internal structure of the high-frequency circuit 1 will be described later.

[0030] Antenna 2 is connected to antenna connection terminal 100 of high-frequency circuit 1. Antenna 2 receives high-frequency signals from the outside and outputs them to high-frequency circuit 1, and receives high-frequency signals from high-frequency circuit 1 and outputs them to the outside of communication device 4. Antenna 2 may not be included in communication device 4. In addition, communication device 4 may include one or more antennas in addition to antenna 2.

[0031] RFIC3 is an example of a signal processing circuit that processes high-frequency signals. Specifically, RFIC3 can perform signal processing on a high-frequency reception signal input through the reception path of the high-frequency circuit 1 by down-conversion, etc., and output the reception signal generated by the signal processing to the BBIC (Baseband Integrated Circuit: baseband integrated circuit, not shown). In addition, RFIC3 can also perform signal processing on a transmission signal input from the BBIC by up-conversion, etc., and output the high-frequency transmission signal generated by the signal processing to the high-frequency circuit 1. In addition, RFIC3 may also include a control unit for controlling a switching circuit and a power amplifier circuit, etc., which are possessed by the high-frequency circuit 1. In addition, part or all of the control unit may also be provided outside the RFIC3, for example, it may also be included in the BBIC or the high-frequency circuit 1.

[0032] [2 Circuit Structure of High-Frequency Circuit 1]

[0033] Next, refer to Figure 1The circuit configuration of high-frequency circuit 1 will be described. High-frequency circuit 1 includes a low-noise amplifier circuit 11, a power amplifier circuit 12, switch circuits 21, 22, and 23, a charge pump circuit 40, level shifters 51 and 52, filters 31, 32, 33, 34, 35, and 36, bias circuits 61 and 62, inductors 71 and 72, an antenna connection terminal 100, a high-frequency output terminal 110, and a high-frequency input terminal 120. The components of high-frequency circuit 1 will be described below in order.

[0034] The antenna connection terminal 100 is an external connection terminal of the high-frequency circuit 1. Specifically, the antenna connection terminal 100 is connected to the antenna 2 outside the high-frequency circuit 1 and is connected to the switch circuit 23 inside the high-frequency circuit 1.

[0035] The high-frequency output terminal 110 is an external connection terminal of the high-frequency circuit 1. Specifically, the high-frequency output terminal 110 is connected to the RFIC 3 outside the high-frequency circuit 1 and to the output terminal of the low-noise amplifier circuit 11 inside the high-frequency circuit 1. The high-frequency input terminal 120 is an external connection terminal of the high-frequency circuit 1. Specifically, the high-frequency input terminal 120 is connected to the RFIC 3 outside the high-frequency circuit 1 and to the input terminal of the power amplifier circuit 12 inside the high-frequency circuit 1.

[0036] The low-noise amplifier circuit 11 includes an amplifier transistor. The amplifier transistor is, for example, a bipolar transistor or a FET. The input of the low-noise amplifier circuit 11 is connected to the switch circuit 21 via an inductor 71. The low-noise amplifier circuit 11 can amplify received signals in frequency bands A, B, and C that have passed through filters 31, 33, and 35.

[0037] The power amplifier circuit 12 includes an amplifier transistor. The amplifier transistor is, for example, a bipolar transistor or a FET. The output of the power amplifier circuit 12 is connected to the switch circuit 22 via an inductor 72. The transmission signals in frequency bands A, B, and C, amplified by the power amplifier circuit 12, pass through filters 32, 34, and 36, and are output from the antenna connection terminal 100. The power amplifier circuit 12 may not be included in the high-frequency circuit 1.

[0038] Switch circuit 21 is an example of a first switch circuit and includes terminals 21a (second terminal), 21b (first terminal), 21c, and 21d. Based on a control voltage supplied from charge pump circuit 40, switch between connecting and disconnecting terminal 21a with terminal 21b, connecting and disconnecting terminal 21a with terminal 21c, and connecting and disconnecting terminal 21a with terminal 21d. Terminal 21a is connected to the input of low-noise amplifier circuit 11 via inductor 71, terminal 21b is connected to filter 31, terminal 21c is connected to filter 33, and terminal 21d is connected to filter 35. In other words, switch circuit 21 is capable of connecting and disconnecting low-noise amplifier circuit 11 with filter 31, connecting and disconnecting low-noise amplifier circuit 11 with filter 33, and connecting and disconnecting low-noise amplifier circuit 11 with filter 35. Switch circuit 21 is capable of connecting terminal 21a exclusively to any one of terminals 21b, 21c, and 21d. Furthermore, the switch circuit 21 can simultaneously connect terminal 21a to at least two of terminals 21b, 21c, and 21d. The switch circuit 21 is, for example, an SP3T (Single-Pole 3-Throw) type switch circuit comprising a plurality of FETs. The switch circuit 21 includes, for example, a first FET having a first gate, a first drain, and a first source. A first control voltage is supplied to the first gate from the charge pump circuit 40, the first drain is connected to terminal 21b, and the first source is connected to terminal 21a. The switch circuit 21 switches between connecting and disconnecting terminals 21a and 21b.

[0039] Switch circuit 22 is an example of a second switch circuit and includes terminals 22a (fifth terminal), 22b (fourth terminal), 22c, and 22d. Based on a control voltage supplied from charge pump circuit 40, switch between connecting and disconnecting terminal 22a with terminal 22b, connecting and disconnecting terminal 22a with terminal 22c, and connecting and disconnecting terminal 22a with terminal 22d. Terminal 22a is connected to the output of power amplifier circuit 12 via inductor 72, terminal 22b is connected to filter 32, terminal 22c is connected to filter 34, and terminal 22d is connected to filter 36. In other words, switch circuit 22 is capable of connecting and disconnecting power amplifier circuit 12 with filter 32, connecting and disconnecting power amplifier circuit 12 with filter 34, and connecting and disconnecting power amplifier circuit 12 with filter 36. Switch circuit 22 is capable of connecting terminal 22a exclusively to only one of terminals 22b, 22c, and 22d. Furthermore, the switch circuit 22 can simultaneously connect terminal 22a to at least two of terminals 22b, 22c, and 22d. For example, the switch circuit 22 is comprised of an SP3T-type switch circuit including multiple FETs. For example, the switch circuit 22 includes a seventh FET having a seventh gate, a seventh drain, and a seventh source. The charge pump circuit 40 supplies a seventh control voltage to the seventh gate, the seventh drain is connected to terminal 22b, and the seventh source is connected to terminal 22a. The switch circuit 22 switches between connection and disconnection between terminals 22a and 22b. Furthermore, the switch circuit 22 may not be included in the high-frequency circuit 1.

[0040] Switch circuit 23 is an example of an antenna switch and includes terminals 23a, 23b, 23c, and 23d. It can switch between connecting and disconnecting terminal 23a with terminal 23b, connecting and disconnecting terminal 23a with terminal 23c, and connecting and disconnecting terminal 23a with terminal 23d. Terminal 23a is connected to antenna connection terminal 100, terminal 23b is connected to filters 31 and 32, terminal 23c is connected to filters 33 and 34, and terminal 23d is connected to filters 35 and 36. In other words, switch circuit 23 can switch between connecting and disconnecting antenna 2 with filters 31 and 32, connecting and disconnecting antenna 2 with filters 33 and 34, and connecting and disconnecting antenna 2 with filters 35 and 36. Switch circuit 23 can connect terminal 23a exclusively to only one of terminals 23b, 23c, and 23d. The switch circuit 23 can also simultaneously connect the terminal 23a to at least two of the terminals 23b, 23c, and 23d. The switch circuit 23 is, for example, an SP3T type switch circuit including a plurality of FETs. The switch circuit 23 may not be included in the high-frequency circuit 1.

[0041] The charge pump circuit 40 is an example of a voltage supply circuit, and can supply a control voltage to the switch circuits 21 and 22. Figure 2 The circuit structure of the charge pump circuit 40 will be described later.

[0042] The level shifter 51 is connected between the charge pump circuit 40 and the switch circuit 21, and is configured to receive a control signal from, for example, the RFIC 3, and convert the voltage output from the charge pump circuit 40 into a control voltage (on-state voltage / off-state voltage) supplied to the switch circuit 21. The level shifter 52 is connected between the charge pump circuit 40 and the switch circuit 22, and is configured to receive a control signal from, for example, the RFIC 3, and convert the voltage output from the charge pump circuit 40 into a control voltage (on-state voltage / off-state voltage) supplied to the switch circuit 22. This allows the control voltage output from the charge pump circuit 40 to be converted into a control voltage appropriate for the size and characteristics of the FETs constituting the switch circuits 21 and 22.

[0043] The inductor 71 is connected between the input terminal of the low-noise amplifier circuit 11 and the terminal 21a of the switch circuit 21. The inductor 71 can achieve impedance matching between the low-noise amplifier circuit 11 and the switch circuit 21. The inductor 71 may not be included in the high-frequency circuit 1.

[0044] The inductor 72 is connected between the output terminal of the power amplifier circuit 12 and the terminal 22a of the switch circuit 22. The inductor 72 can achieve impedance matching between the power amplifier circuit 12 and the switch circuit 22. The inductor 72 may not be included in the high-frequency circuit 1.

[0045] Filter 31 is an elastic wave filter connected between switch circuits 21 and 23 and has a passband that includes the receive band (A-Rx) of frequency band A. One end of filter 31 is connected to terminal 21b, and the other end is connected to terminal 23b. Filter 32 is an elastic wave filter connected between switch circuits 22 and 23 and has a passband that includes the transmit band (A-Tx) of frequency band A. One end of filter 32 is connected to terminal 22b, and the other end is connected to terminal 23b. Filters 31 and 32 are frequency division duplex filters, forming a duplexer capable of simultaneously transmitting transmit and receive signals in frequency band A. Filters 31 and 32 may also be time division duplex filters, in which case filters 31 and 32 have passbands that include both the transmit and receive bands of frequency band A. Filters 31 and 32 do not necessarily need to be included in high-frequency circuit 1.

[0046] Filter 33 is an elastic wave filter connected between switch circuits 21 and 23 and has a passband that includes the receive band (B-Rx) of frequency band B. One end of filter 33 is connected to terminal 21c, and the other end of filter 33 is connected to terminal 23c. Filter 34 is an elastic wave filter connected between switch circuits 22 and 23 and has a passband that includes the transmit band (B-Tx) of frequency band B. One end of filter 34 is connected to terminal 22c, and the other end of filter 34 is connected to terminal 23c. Filters 33 and 34 are frequency division duplex filters, forming a duplexer capable of simultaneously transmitting transmit and receive signals in frequency band B. Alternatively, filters 33 and 34 may be time division duplex filters, in which case filters 33 and 34 have passbands that include both the transmit and receive bands of frequency band B. Furthermore, filters 33 and 34 do not necessarily need to be included in high-frequency circuit 1.

[0047] Filter 35 is an elastic wave filter connected between switch circuits 21 and 23 and has a passband that includes the receive band (C-Rx) of band C. One end of filter 35 is connected to terminal 21d, and the other end is connected to terminal 23d. Filter 36 is an elastic wave filter connected between switch circuits 22 and 23 and has a passband that includes the transmit band (C-Tx) of band C. One end of filter 36 is connected to terminal 22d, and the other end is connected to terminal 23d. Filters 35 and 36 are frequency division duplex filters, forming a duplexer capable of simultaneously transmitting transmit and receive signals in band C. Alternatively, filters 35 and 36 may be time division duplex filters, in which case filters 35 and 36 have passbands that include both the transmit and receive bands of band C. Furthermore, filters 35 and 36 do not necessarily need to be included in high-frequency circuit 1.

[0048] Furthermore, the filters 31 to 36 do not need to be elastic wave filters. For example, some or all of the filters 31 to 36 may be LC filters.

[0049] Bands A to C are frequency bands used for communication systems built using radio access technology (RAT), and are predefined by standardization organizations such as 3GPP (registered trademark) (3rd Generation Partnership Project) and IEEE (Institute of Electrical and Electronics Engineers). Examples of communication systems include 5GNR (5th Generation New Radio) systems, LTE (Long Term Evolution) systems, and WLAN (Wireless Local Area Network) systems. In addition, bands A to C can be different frequency bands or the same frequency band. For example, band A and band C can be the same, and band B and band C can be the same.

[0050] The bias circuit 61 can supply a bias signal to the low-noise amplifier circuit 11 based on a control signal supplied from the RFIC 3, for example. The bias circuit 62 can supply a bias signal to the power amplifier circuit 12 based on a control signal supplied from the RFIC 3, for example. The bias circuits 61 and 62 may not be included in the high-frequency circuit 1.

[0051] Furthermore, in this embodiment, the low-noise amplifier circuit 11 , the switch circuit 21 , the charge pump circuit 40 , and the bias circuit 61 may be included in one integrated circuit.

[0052] [3. Circuit Structure of Charge Pump Circuit 40]

[0053] Next, refer to Figure 2 The circuit configuration of the charge pump circuit 40 will be described. Figure 2 2 is a circuit configuration diagram of the charge pump circuit 40 and the switch circuits 21 and 22 according to the embodiment.

[0054] It should be explained that Figure 2 While the circuit configurations of the charge pump circuit 40 and the switch circuits 21 and 22 are illustrative, the charge pump circuit 40 and the switch circuits 21 and 22 can be implemented using any of a variety of circuit implementations and circuit technologies. Therefore, the following description of the charge pump circuit 40 and the switch circuits 21 and 22 should not be interpreted in a limiting sense.

[0055] like Figure 2 As shown, the charge pump circuit 40 includes a positive bias circuit 41 and a negative bias circuit 42 .

[0056] The forward bias circuit 41 includes a boost circuit, a buck circuit, an inverting circuit, or any combination thereof, and is connected to the level shifters 51 and 52. The forward bias circuit 41 outputs a positive bias voltage (on-state voltage) by boosting, bucking, inverting, or any combination thereof, of the input voltage using a pulse wave generated by an oscillator (not shown).

[0057] Negative bias circuit 42 includes a boost circuit, a buck circuit, an inverting circuit, or any combination thereof, and is connected to level shifters 51 and 52. Negative bias circuit 42 outputs a negative bias voltage (off-state voltage) by boosting, bucking, inverting, or any combination thereof, using a pulse wave generated by an oscillator (not shown).

[0058] In addition, the circuit structure of the charge pump circuit 40 is shown as an example and is not limited to the following. Figure 2 For example, the charge pump circuit 40 may not include either the positive bias circuit 41 or the negative bias circuit 42. In this case, the switch circuits 21 and 22 are supplied with either the positive bias circuit 41 or the negative bias circuit 42, and a ground voltage. Furthermore, the charge pump circuit 40 may include a bandgap reference circuit (not shown) and an error amplifier circuit (not shown).

[0059] In addition, in this embodiment, the charge pump circuit 40 is used as the voltage supply circuit, but the voltage supply circuit is not limited to the charge pump circuit. For example, a bootstrap circuit and / or a switched capacitor circuit may be used as the voltage supply circuit.

[0060] Here, the output voltage characteristics of the charge pump circuit 40 will be described. Figure 3 4 is a graph showing the transient response characteristics of the output voltage of the charge pump circuit 40 .

[0061] The charge pump circuit 40 supplies control signals not only to the switch circuit 21 in the receive path but also to the switch circuit 22 in the transmit path. When the FETs in the switch circuit 22 are switched from on to off, or vice versa, the control voltage supplied from the charge pump circuit 40 to the switch circuit 22 may temporarily fluctuate. In particular, the switch circuit 22 in the transmit path is configured with a FET having a larger gate width (gate capacitance) to facilitate the passage of high-output transmit signals. In the high-frequency circuit 1 of this embodiment, the gate width of the seventh FET in the switch circuit 22 is larger than the gate width of the first FET in the switch circuit 21.

[0062] Since the seventh FET of the switch circuit 22 has a large gate capacitance, Figure 3As shown, when the negative bias voltage (off voltage: for example, -3.5V) changes to the positive bias voltage (on voltage: for example, 3.5V), the on voltage output from the charge pump circuit 40 may temporarily decrease ( Figure 3 In addition, when the positive bias voltage (on-state voltage: for example, 3.5V) changes to the negative bias voltage (off-state voltage: for example, -3.5V), the off-state voltage output from the charge pump circuit 40 may temporarily rise ( Figure 3 The period from the temporary decrease in the on-state voltage in case 1 to the stable on-state voltage and the period from the temporary increase in the off-state voltage in case 2 to the stable off-state voltage are approximately several μS.

[0063] The control voltage output from the charge pump circuit 40 to the switch circuit 21 also temporarily fluctuates, as does the control voltage output from the charge pump circuit 40 to the switch circuit 22. This causes the drain potential or source potential of each FET constituting the switch circuit 21 to fluctuate via the gate capacitance of the FETs. Consequently, if a circuit whose high-frequency characteristics are sensitive to this potential fluctuation (e.g., the input terminal of the low-noise amplifier circuit 11) is connected to the terminal 21a of the switch circuit 21, the potential fluctuation takes a long time to converge, potentially significantly degrading the transient response of the circuit (e.g., the low-noise amplifier circuit 11).

[0064] [4. Structure of High-Frequency Circuit 500 of Comparative Example]

[0065] Next, a circuit configuration example of a conventional high-frequency circuit will be described. Figure 4 is a circuit diagram of a high-frequency circuit 500 according to a comparative example. As shown in this figure, the high-frequency circuit 500 according to the comparative example includes a low-noise amplifier circuit 11, a switch circuit 521, a charge pump circuit 40, filters 31, 33, and 35, and an inductor 71. Furthermore, although not shown, the high-frequency circuit 500 may also include a power amplifier circuit 12, level shifters 51 and 52, and a switch circuit 22. The high-frequency circuit 500 according to the comparative example differs from the high-frequency circuit 1 according to the embodiment only in the circuit structure of the switch circuit 521 arranged in the receiving path. The following description of the high-frequency circuit 500 according to the comparative example will omit the same structures as the high-frequency circuit 1 according to the embodiment, and will focus on the structure of the switch circuit 521, which is a different structure.

[0066] The switch circuit 521 includes terminals 521 a , 521 b , 521 c , and 521 d , and FETs 211 , 212 , 213 , 214 , 215 , and 216 .

[0067] The terminal 521 a is connected to the input end of the low-noise amplifier circuit 11 via the inductor 71 , the terminal 521 b is connected to the filter 31 , the terminal 521 c is connected to the filter 33 , and the terminal 521 d is connected to the filter 35 .

[0068] FET 211 is an n-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor) having a gate, a drain, and a source. Its gate is connected to the charge pump circuit 40, its drain is connected to the terminal 521b, and its source is connected to the terminal 521a. FET 212 is an n-channel MOSFET having a gate, a drain, and a source. Its gate is connected to the charge pump circuit 40, its drain is connected to the terminal 521b, and its source is grounded.

[0069] When the charge pump circuit 40 supplies an on-voltage to the gate of FET 211 and an off-voltage to the gate of FET 212, FET 211 is turned on and FET 212 is turned off. As a result, the received signal in frequency band A that has passed through the filter 31 passes through the terminal 521b, FET 211, and the terminal 521a and is input to the low-noise amplifier circuit 11.

[0070] On the other hand, when the charge pump circuit 40 supplies an OFF voltage to the gate of FET 211 and an ON voltage to the gate of FET 212, FET 211 is turned OFF and FET 212 is turned ON. As a result, received signals in bands A, B, and C do not pass through FET 211.

[0071] Alternatively, FETs 211 and 212 may each be a p-channel MOSFET or other FET. If FETs 211 and 212 are each a p-channel MOSFET, the gate of FET 211 is connected to the charge pump circuit 40, the source is connected to the terminal 521 b, and the drain is connected to the terminal 521 a. Furthermore, the gate of FET 212 is connected to the charge pump circuit 40, the source is connected to the terminal 521 b, and the drain is grounded.

[0072] FET 213 is an n-channel MOSFET having a gate, a drain, and a source. The gate is connected to the charge pump circuit 40, the drain is connected to the terminal 521 c, and the source is connected to the terminal 521 a. FET 214 is an n-channel MOSFET having a gate, a drain, and a source. The gate is connected to the charge pump circuit 40, the drain is connected to the terminal 521 c, and the source is grounded.

[0073] When the charge pump circuit 40 supplies an on-voltage to the gate of FET 213 and an off-voltage to the gate of FET 214, FET 213 is turned on and FET 214 is turned off. As a result, the received signal in frequency band B that has passed through the filter 33 passes through the terminal 521c, FET 213, and the terminal 521a and is input to the low-noise amplifier circuit 11.

[0074] On the other hand, when the charge pump circuit 40 supplies an OFF voltage to the gate of FET 213 and an ON voltage to the gate of FET 214, FET 213 is turned OFF and FET 214 is turned ON. As a result, received signals in bands A, B, and C do not pass through FET 213.

[0075] Alternatively, FETs 213 and 214 may each be a p-channel MOSFET or other FET. If FETs 213 and 214 are each a p-channel MOSFET, the gate of FET 213 is connected to the charge pump circuit 40, the source is connected to the terminal 521c, and the drain is connected to the terminal 521a. Furthermore, the gate of FET 214 is connected to the charge pump circuit 40, the source is connected to the terminal 521c, and the drain is grounded.

[0076] FET 215 is an n-channel MOSFET having a gate, a drain, and a source. The gate is connected to the charge pump circuit 40, the drain is connected to the terminal 521d, and the source is connected to the terminal 521a. FET 216 is an n-channel MOSFET having a gate, a drain, and a source. The gate is connected to the charge pump circuit 40, the drain is connected to the terminal 521d, and the source is grounded.

[0077] When the charge pump circuit 40 supplies an on-voltage to the gate of FET 215 and an off-voltage to the gate of FET 216, FET 215 is turned on and FET 216 is turned off. As a result, the received signal in frequency band C that has passed through the filter 35 passes through the terminal 521d, the FET 215, and the terminal 521a and is input to the low-noise amplifier circuit 11.

[0078] On the other hand, when the charge pump circuit 40 supplies an OFF voltage to the gate of FET 215 and an ON voltage to the gate of FET 216, FET 215 is turned OFF and FET 216 is turned ON. As a result, received signals in bands A, B, and C do not pass through FET 215.

[0079] Alternatively, FETs 215 and 216 may each be a p-channel MOSFET or other FET. If FETs 215 and 216 are each a p-channel MOSFET, the gate of FET 215 is connected to the charge pump circuit 40, the source is connected to the terminal 521d, and the drain is connected to the terminal 521a. Furthermore, the gate of FET 216 is connected to the charge pump circuit 40, the source is connected to the terminal 521d, and the drain is grounded.

[0080] In the high frequency circuit 500 having the above structure, the charge pump circuit 40 supplies the switching circuit 521 with Figure 3 In the case of the on-voltage of Case 1 or the off-voltage of Case 2, the source potential of FET 211 may fluctuate via the gate capacitance of FET 211, the source potential of FET 213 may fluctuate via the gate capacitance of FET 213, and the source potential of FET 215 may fluctuate via the gate capacitance of FET 215. Here, the fluctuation in the source potential of the FET turned on among FETs 211, 213, and 215 may be transmitted to the input terminal of the low-noise amplifier circuit 11, and the transient response of the low-noise amplifier circuit 11 may be significantly degraded.

[0081] [Structure of the Switching Circuit 21 of the Fifth Embodiment]

[0082] Next, a circuit configuration example of the high-frequency circuit 1 according to the embodiment will be described. Figure 5 This is a circuit diagram of a high-frequency circuit 1 according to an embodiment. As shown in this figure, the high-frequency circuit 1 according to the embodiment includes a low-noise amplifier circuit 11, a switch circuit 21, a charge pump circuit 40, filters 31, 33, and 35, and an inductor 71. Although not shown, the high-frequency circuit 1 also includes a power amplifier circuit 12, level shifters 51 and 52, and a switch circuit 22. The circuit configuration and switching operation of the switch circuit 21 will be described below.

[0083] The switch circuit 21 includes terminals 21 a (second terminal), 21 b (first terminal), 21 c (third terminal), and 21 d, and FETs 211 , 212 , 213 , 214 , 215 , 216 , 217 , 218 , and 219 .

[0084] The terminal 21 a is connected to the input end of the low-noise amplifier circuit 11 via the inductor 71 , the terminal 21 b is connected to the filter 31 , the terminal 21 c is connected to the filter 33 , and the terminal 21 d is connected to the filter 35 .

[0085] FET 211 is an example of a first FET and is an n-channel MOSFET having a first gate, a first drain, and a first source. A first control voltage is supplied to the first gate from the charge pump circuit 40, the first drain is connected to the terminal 21 b (first terminal), and the first source is connected to the terminal 21 a (second terminal). FET 212 is an example of a third FET and is an n-channel MOSFET having a third gate, a third drain, and a third source. A third control voltage is supplied to the third gate from the charge pump circuit 40, the third drain is connected to the terminal 21 b, and the third source is connected to ground.

[0086] FET217 is an example of a second FET, which is an n-channel MOSFET having a second gate, a second drain and a second source. A second control voltage is supplied to the second gate from the charge pump circuit 40, and the second drain and the second source are connected to the path connecting terminal 21b, FET211 and terminal 21a, and the second drain and the second source are short-circuited.

[0087] When the charge pump circuit 40 supplies a first on-voltage to the first gate and an off-voltage to the third gate, the FET 211 is turned on and the FET 212 is turned off. As a result, the received signal in frequency band A that has passed through the filter 31 passes through the terminal 21b, the FET 211, and the terminal 21a and is input to the low-noise amplifier circuit 11.

[0088] On the other hand, when the charge pump circuit 40 supplies the first off-voltage to the first gate and the on-voltage to the third gate, FET 211 is turned off and FET 212 is turned on. As a result, received signals in bands A, B, and C do not pass through FET 211.

[0089] Alternatively, FETs 211, 212, and 217 may each be a p-channel MOSFET or other FET. If FETs 211, 212, and 217 are each a p-channel MOSFET, the first gate is connected to the charge pump circuit 40, the first source is connected to the terminal 21b, and the first drain is connected to the terminal 21a. Furthermore, the third gate is connected to the charge pump circuit 40, the third source is connected to the terminal 21b, and the third drain is grounded. Furthermore, the second gate is connected to the charge pump circuit 40, the second drain and the second source are connected to a path connecting the terminal 21b, FET 211, and the terminal 21a, and the second drain and the second source are short-circuited.

[0090] FET 213 is an example of a fourth FET and is an n-channel MOSFET having a fourth gate, a fourth drain, and a fourth source. A fourth control voltage is supplied to the fourth gate from the charge pump circuit 40, the fourth drain is connected to the terminal 21 c (third terminal), and the fourth source is connected to the terminal 21 a (second terminal). FET 214 is an example of a sixth FET and is an n-channel MOSFET having a sixth gate, a sixth drain, and a sixth source. A sixth control voltage is supplied to the sixth gate from the charge pump circuit 40, the sixth drain is connected to the terminal 21 c, and the sixth source is grounded.

[0091] FET218 is an example of a fifth FET, which is an n-channel MOSFET having a fifth gate, a fifth drain and a fifth source. A fifth control voltage is supplied to the fifth gate from the charge pump circuit 40, and the fifth drain and the fifth source are connected to the path of the connection terminal 21c, FET213 and the terminal 21a, and the fifth drain and the fifth source are short-circuited.

[0092] When the fourth gate is supplied with a fourth on-voltage and the sixth gate is supplied with an off-voltage from the charge pump circuit 40, the FET 213 is turned on and the FET 214 is turned off. As a result, the received signal in frequency band B that has passed through the filter 33 passes through the terminal 21c, the FET 213, and the terminal 21a and is input to the low-noise amplifier circuit 11.

[0093] On the other hand, when the fourth gate is supplied with a fourth off-voltage and the sixth gate is supplied with an on-voltage from the charge pump circuit 40, FET 213 is turned off and FET 214 is turned on. As a result, received signals in bands A, B, and C do not pass through FET 213.

[0094] Alternatively, FETs 213, 214, and 218 may each be a p-channel MOSFET or other FET. If FETs 213, 214, and 218 are each a p-channel MOSFET, the fourth gate is connected to the charge pump circuit 40, the fourth source is connected to the terminal 21c, and the fourth drain is connected to the terminal 21a. Furthermore, the sixth gate is connected to the charge pump circuit 40, the sixth source is connected to the terminal 21c, and the sixth drain is connected to ground. Furthermore, the fifth gate is connected to the charge pump circuit 40, the fifth drain and the fifth source are connected to the path connecting the terminal 21c, FET 213, and the terminal 21a, and the fifth drain and the fifth source are short-circuited.

[0095] FET 215 is an n-channel MOSFET having a gate, a drain, and a source. A control voltage is supplied to the gate from the charge pump circuit 40, the drain is connected to the terminal 21d, and the source is connected to the terminal 21a. FET 216 is an n-channel MOSFET having a gate, a drain, and a source. A control voltage is supplied to the gate from the charge pump circuit 40, the drain is connected to the terminal 21d, and the source is connected to ground.

[0096] FET219 is an n-channel MOSFET having a gate, a drain, and a source. A control voltage is supplied to the gate from the charge pump circuit 40 , and the drain and source are connected to a path connecting the terminal 21 d , the FET 215 , and the terminal 21 a , and the drain and source are short-circuited.

[0097] When an on-voltage is supplied to the gate of FET 215 and an off-voltage is supplied to the gate of FET 216 from the charge pump circuit 40, FET 215 is turned on and FET 216 is turned off. As a result, the received signal in frequency band C that has passed through the filter 35 passes through the terminal 21d, FET 215, and the terminal 21a and is input to the low-noise amplifier circuit 11.

[0098] On the other hand, when the charge pump circuit 40 supplies an OFF voltage to the gate of FET 215 and an ON voltage to the gate of FET 216, FET 215 is turned OFF and FET 216 is turned ON. As a result, received signals in bands A, B, and C do not pass through FET 215.

[0099] Alternatively, FETs 215, 216, and 219 may each be a p-channel MOSFET or other FET. If FETs 215, 216, and 219 are each a p-channel MOSFET, the gate of FET 215 is connected to the charge pump circuit 40, the source is connected to terminal 21d, and the drain is connected to terminal 21a. Furthermore, the gate of FET 215 is connected to the charge pump circuit 40, the source is connected to terminal 21d, and the drain is grounded. Furthermore, the gate of FET 219 is connected to the charge pump circuit 40, the drain and source of FET 219 are connected to a path connecting terminal 21d, FET 215, and terminal 21a, and the drain and source of FET 219 are short-circuited.

[0100] The instantaneous characteristics of the control voltage output from the charge pump circuit 40 are shown. For example, assume that FET 211 of FETs 211, 213, and 215 is turned on, FETs 213 and 215 are turned off, and a received signal in frequency band A is amplified by the low-noise amplifier circuit 11. In this case, in a first instantaneous state in which the first control voltage output from the charge pump circuit 40 changes from the first off-voltage to the first on-voltage, the first on-voltage temporarily decreases. Simultaneously, the fourth control voltage output from the charge pump circuit 40 changes from the fourth on-voltage to the fourth off-voltage, and the fourth off-voltage temporarily increases. Simultaneously, the control voltage output from the charge pump circuit 40 to FET 215 changes from the on-voltage to the off-voltage, and the off-voltage temporarily increases.

[0101] Thus, in the first transient state, a voltage is applied to the first gate of FET 211, which is a combination of a temporary voltage drop component of the first on-voltage, a temporary voltage increase component of the fourth off-voltage, and a temporary voltage increase component of the off-voltage for turning FET 215 off. Whether the gate voltage of FET 211 temporarily drops or rises is determined by the gate capacitance and characteristics of FETs 211 to 216.

[0102] In the switch circuit 21 that receives the control voltage having the above-described characteristics from the charge pump circuit 40 , a switching operation is performed by any of the following methods.

[0103] (Method 1)

[0104] When the first control voltage output from the charge pump circuit 40 is the first on-state voltage that turns FET211 on, the second control voltage output from the charge pump circuit 40 is set to the second on-state voltage that turns FET217 on when the second drain and the second source of FET217 are not short-circuited.

[0105] According to this, in the first instantaneous state in which the first control voltage changes from the first off-voltage to the first on-voltage, when the voltage of the terminal 21a temporarily rises when the FET 217 is not provided, the voltage between the second gate and the second source of the FET 217 temporarily falls in the first instantaneous state (the FET 217 becomes Figure 3 1), the voltage rise of the terminal 21a caused by the first control voltage can be suppressed.

[0106] As a circuit structure for realizing the above-mentioned method 1, Figure 5 As shown, the second gate of FET 217 is connected to the first gate of FET 211 .

[0107] Accordingly, FET217 operates according to the same logic as FET211, so in the first instantaneous state where the first control voltage changes from the first cut-off voltage to the first on-state voltage, the voltage between the second gate and the second source of FET217 temporarily drops, thereby suppressing the voltage rise of terminal 21a caused by the first control voltage.

[0108] (Method 2)

[0109] When the first control voltage output from the charge pump circuit 40 is the first on-state voltage for turning on the FET 211, the second control voltage output from the charge pump circuit 40 is set to the second on-state voltage for turning on the FET 217 when the second drain and the second source of the FET 217 are not short-circuited. Furthermore, when the fourth control voltage output from the charge pump circuit 40 is the fourth on-state voltage for turning on the FET 213, the fifth control voltage output from the charge pump circuit 40 is set to the fifth on-state voltage for turning on the FET 218 when the fifth drain and the fifth source of the FET 218 are not short-circuited.

[0110] According to this, in the first instantaneous state in which the first control voltage changes from the first off-voltage to the first on-voltage, when the voltage of the terminal 21a temporarily rises when the FET 217 is not provided, the voltage between the second gate and the second source of the FET 217 temporarily falls in the first instantaneous state (the FET 217 becomes Figure 3 The characteristic of Case 1) is obtained, so the voltage rise of the terminal 21a caused by the first control voltage can be suppressed. In addition, in the fourth instantaneous state where the fourth control voltage changes from the fourth off-voltage to the fourth on-voltage, when the voltage of the terminal 21a temporarily rises when the FET 218 is not configured, the voltage between the fifth gate and the fifth source of the FET 218 temporarily drops in the fourth instantaneous state (the FET 218 becomes Figure 3 1), the voltage rise of the terminal 21a caused by the fourth control voltage can be suppressed.

[0111] As a circuit structure for realizing the above-mentioned method 2, Figure 5 As shown, the second gate of FET 217 is connected to the first gate of FET 211 , and the fifth gate of FET 218 is connected to the fourth gate of FET 213 .

[0112] Thus, FET 217 operates according to the same logic as FET 211. Therefore, at the first instant when the first control voltage changes from the first off-voltage to the first on-voltage, the voltage between the second gate and the second source of FET 217 temporarily decreases, thereby suppressing the voltage rise at terminal 21a caused by the first control voltage. Furthermore, FET 218 operates according to the same logic as FET 213. Therefore, at the fourth instant when the fourth control voltage changes from the fourth off-voltage to the fourth on-voltage, the voltage between the fifth gate and the fifth source of FET 218 temporarily decreases, thereby suppressing the voltage rise at terminal 21a caused by the fourth control voltage.

[0113] Figure 6A : is a graph showing the transient response characteristics of the output voltage of the switching circuit 521 of the comparative example. Figure 6B Graph showing transient response characteristics of the output voltage of the switching circuit 21 according to the embodiment.

[0114] More specifically, in Figure 6A FIG. 4 shows the transient characteristics of the voltage at the terminal 521a when the charge pump circuit 40 outputs the first on-state voltage to turn on the FET 211 and simultaneously outputs the fourth off-state voltage to turn on the FET 213 and simultaneously outputs the off-state voltage to turn off the FET 215 in the high-frequency circuit 500 of the comparative example. Figure 6A In the graph shown, a voltage obtained by adding together a temporary voltage drop component of the first on-voltage of the first gate of FET211, a temporary voltage rise component of the fourth off-voltage of the fourth gate of FET213, and a temporary voltage rise component of the off-voltage of the gate of FET215 is applied to the terminal 521a via the gate capacitances of FETs 211, 213, and 215, so that the voltage of the terminal 521a temporarily rises in a transient state.

[0115] In contrast, in Figure 6B FIG. 1 shows the transient characteristics of the voltage at the terminal 21a in the embodiment 1 in the high frequency circuit 1 of the embodiment. In other words, when the voltage at the terminal 21a rises temporarily, the voltage between the second gate and the second source of the FET 217 drops temporarily in the first transient state (the FET 217 becomes Figure 3 Therefore, the voltage rise of the terminal 21a caused by the first control voltage is suppressed.

[0116] [Structure of Switch Circuit 21A of 6th Modification]

[0117] Next, a circuit configuration example of a high-frequency circuit 1A according to a modified example of the embodiment will be described. Figure 7This is a circuit diagram of a high-frequency circuit 1A according to a variation of the embodiment. As shown in this figure, the high-frequency circuit 1A according to this variation includes a low-noise amplifier circuit 11, a switch circuit 21A, a charge pump circuit 40, filters 31, 33, and 35, and an inductor 71. Furthermore, although not shown, the high-frequency circuit 1A includes a power amplifier circuit 12, level shifters 51 and 52, and a switch circuit 22. The high-frequency circuit 1A according to this variation differs from the high-frequency circuit 1 according to the embodiment only in the structure of the switch circuit 21A. The following description of the high-frequency circuit 1A according to this variation will omit the same structures as the high-frequency circuit 1 according to the embodiment, and will focus on the circuit structure and switching operation of the switch circuit 21A, which has a different structure.

[0118] The switch circuit 21A includes terminals 21a (second terminal), 21b (first terminal), 21c (third terminal), and 21d, and FETs 211, 212, 213, 214, 215, 216, 217, 218, and 219. The switch circuit 21A of this modification differs from the switch circuit 21 of the embodiment only in the connection structure of the gates of the FETs 211 to 219. The following description of the switch circuit 21A will omit the same configuration as the switch circuit 21, and will focus on the connection structure of the gates of the FETs 211 to 219.

[0119] (Method 3)

[0120] When the first control voltage output from the charge pump circuit 40 is the first on-state voltage that turns on FET211, the second control voltage output from the charge pump circuit 40 is the second off-state voltage that turns off FET217 when the second drain and the second source of FET217 are not short-circuited.

[0121] According to this, in the first instantaneous state when the first control voltage changes from the first off-voltage to the first on-voltage, when the voltage of the terminal 21a temporarily decreases when the FET 217 is not provided, the voltage between the second gate and the second source of the FET 217 temporarily increases in the second instantaneous state (the FET 217 becomes Figure 3 2), the voltage drop at the terminal 21a caused by the first control voltage can be suppressed.

[0122] As a circuit structure for realizing the above-mentioned method 3, Figure 7 As shown, the second gate of FET 217 is connected to the third gate of FET 212 .

[0123] Accordingly, FET217 operates according to the opposite logic to FET211, so in the first instantaneous state when the first control voltage changes from the first cut-off voltage to the first on-state voltage, the voltage between the second gate and the second source of FET217 temporarily rises, thereby suppressing the voltage drop of terminal 21a caused by the first control voltage.

[0124] In addition, as a circuit configuration for realizing the third embodiment, the second off-voltage may be always applied to the second gate of the FET 217 regardless of whether the first on-voltage is applied to the FET 211 .

[0125] (Method 4)

[0126] When the first control voltage output from the charge pump circuit 40 is the first on-voltage for turning on the FET 211, the second control voltage output from the charge pump circuit 40 is set to the second off-voltage for turning off the FET 217 when the second drain and the second source of the FET 217 are not short-circuited. Furthermore, when the fourth control voltage output from the charge pump circuit 40 is the fourth on-voltage for turning on the FET 213, the fifth control voltage output from the charge pump circuit 40 is set to the fifth off-voltage for turning off the FET 218 when the fifth drain and the fifth source of the FET 218 are not short-circuited.

[0127] According to this, in the first instantaneous state in which the first control voltage changes from the first off-voltage to the first on-voltage, when the voltage of the terminal 21a temporarily decreases when the FET 217 is not provided, the voltage between the second gate and the second source of the FET 217 temporarily increases in the first instantaneous state (the FET 217 becomes Figure 3 2), the voltage drop of the terminal 21a caused by the first control voltage can be suppressed. In addition, in the fourth instantaneous state where the fourth control voltage changes from the fourth off-voltage to the fourth on-voltage, when the voltage of the terminal 21a temporarily drops when the FET 218 is not configured, the voltage between the fifth gate and the fifth source of the FET 218 temporarily rises in the fourth instantaneous state (FET 218 becomes Figure 3 2), the voltage drop at the terminal 21a caused by the fourth control voltage can be suppressed.

[0128] As a circuit structure for realizing the above-mentioned method 4, Figure 7 As shown, the second gate of FET 217 is connected to the third gate of FET 212 , and the fifth gate of FET 218 is connected to the sixth gate of FET 214 .

[0129] Thus, FET 217 operates according to the opposite logic to FET 211. Therefore, at the first instant when the first control voltage changes from the first off-voltage to the first on-voltage, the voltage between the second gate and the second source of FET 217 temporarily increases, thereby suppressing the voltage drop at terminal 21a caused by the first control voltage. Furthermore, FET 218 operates according to the opposite logic to FET 213. Therefore, at the fourth instant when the fourth control voltage changes from the fourth off-voltage to the fourth on-voltage, the voltage between the fifth gate and the fifth source of FET 218 temporarily increases, thereby suppressing the voltage drop at terminal 21a caused by the fourth control voltage.

[0130] In addition, as a circuit structure for implementing the above-mentioned method 4, the second cut-off voltage can be always applied to the second gate of FET217 regardless of whether the first on-voltage is applied to FET211, and the fifth cut-off voltage can be always applied to the fifth gate of FET218 regardless of whether the fourth on-voltage is applied to FET213.

[0131] Furthermore, when the control voltage supplied to at least one of the FETs 211, 213, and 215 constituting the switch circuit 21 is an on-voltage, the gate voltages of the FETs 217 to 219 are temporarily increased or decreased, depending on whether the voltage at the terminal 21a is temporarily decreased or increased in a state where the FETs 217 to 219 are not attached to the switch circuit 21. The switch circuit 21 is configured so that when the gate voltages of the FETs 217 to 219 are temporarily increased, an off-voltage is applied to the gates of the FETs 217 to 219, and when the gate voltages of the FETs 217 to 219 are temporarily decreased, an on-voltage is applied to the gates of the FETs 217 to 219.

[0132] In addition, in the high-frequency circuit 1, when the parameters affecting the switching characteristics such as the gate width of FETs 211 to 213 are the same in each FET, instead of configuring FETs 217 to 219, a FET having the same characteristics as FETs 217 to 219 can be configured in the path between the connection terminal 21a and the inductor 71.

[0133] In the high-frequency circuit 1, the switch circuit 21 only needs to include at least one of the FETs 211 to 213. Furthermore, the high-frequency circuit 1 may include four or more reception paths. In this case, the switch circuit 21 includes a FET arranged in series with the fourth reception path in addition to the FETs 211 to 213 arranged in series with the first to third reception paths, respectively.

[0134] [7 Effects, etc.]

[0135] As described above, the high-frequency circuit 1 of this embodiment includes a switch circuit 21 having terminals 21a and 21b and switching between connection and non-connection of the terminals 21a and 21b, and a charge pump circuit 40 configured to supply a control voltage to the switch circuit 21. The switch circuit 21 includes: an FET 211 having a first gate, a first drain, and a first source, a first control voltage being supplied from the charge pump circuit 40 to the first gate, the first drain being connected to the terminal 21b, and the first source being connected to the terminal 21a; and an FET 217 having a second gate, a second drain, and a second source, a second control voltage being supplied from the charge pump circuit 40 to the second gate, the second drain and the second source being connected to a path connecting the terminal 21b, the FET 211, and the terminal 21a, and the second drain and the second source being short-circuited.

[0136] The control voltage supplied from charge pump circuit 40 may fluctuate undesirably at the timing when it switches between the on-voltage and off-voltage levels. If the control voltage fluctuates at this timing, the fluctuation propagates to terminal 21a via the gate capacitance between the first gate and the first source, causing the voltage at terminal 21a to fluctuate instantaneously. In contrast, by placing FET 217, which short-circuits its source and drain, in the path connecting terminals 21b and 21a, it is possible to suppress transient fluctuations in the voltage at terminal 21a by supplying a second control voltage in accordance with the direction of the control voltage fluctuation without affecting the steady-state conduction and non-conduction of switch circuit 21. This reduces the time it takes for the transient fluctuations in switch circuit 21 to converge.

[0137] For example, in the high-frequency circuit 1 , when the first control voltage is the first on-voltage for turning on the FET 211 , the second control voltage is the second on-voltage for turning on the FET 217 when the second drain and the second source are not short-circuited.

[0138] Accordingly, in the first instantaneous state when the first control voltage changes from the first cut-off voltage to the first on-state voltage, when the voltage of the terminal 21a temporarily rises when FET217 is not configured, the voltage between the second gate and the second source of FET217 temporarily drops in the first instantaneous state, so that the voltage rise of the terminal 21a caused by the first control voltage can be suppressed.

[0139] For another example, in the high-frequency circuit 1 , the second gate is connected to the first gate.

[0140] Accordingly, FET217 operates according to the same logic as FET211, so in the first instantaneous state where the first control voltage changes from the first cut-off voltage to the first on-state voltage, the voltage between the second gate, the second drain, and the second source of FET217 temporarily drops, thereby suppressing the voltage rise of terminal 21a caused by the first control voltage.

[0141] For example, in the high-frequency circuit 1A of the modified example, when the first control voltage is the first on-voltage for turning on the FET 211 , the second control voltage is the second off-voltage for turning off the FET 217 when the second drain and the second source are not short-circuited.

[0142] Accordingly, in the first instantaneous state when the first control voltage changes from the first cut-off voltage to the first on-state voltage, when the voltage of the terminal 21a temporarily drops when FET217 is not configured, the voltage between the second gate and the second source of FET217 temporarily rises in the second instantaneous state, thereby suppressing the voltage drop of the terminal 21a caused by the first control voltage.

[0143] For example, the high-frequency circuit 1A further includes a FET 212 having a third gate, a third drain, and a third source. A third control voltage is supplied to the third gate from the charge pump circuit 40, the third drain is connected to the terminal 21 b, and the third source is grounded. When the FET 211 is in the on state, the FET 212 is in the off state. When the FET 211 is in the off state, the FET 212 is in the on state, and when the FET 211 is in the off state, the FET 212 is in the on state, and the second gate is connected to the third gate.

[0144] Accordingly, FET217 operates according to the opposite logic to FET211, so in the first instantaneous state when the first control voltage changes from the first cut-off voltage to the first on-state voltage, the voltage between the second gate, the second drain and the second source of FET217 temporarily rises, thereby suppressing the voltage drop of terminal 21a caused by the first control voltage.

[0145] For example, in the high-frequency circuits 1 and 1A, in a first instantaneous state in which the first control voltage changes from the cutoff voltage for turning FET 211 into the cutoff state to the on-voltage for turning FET 211 into the on-state, the on-voltage temporarily decreases, and in a second instantaneous state in which the first control voltage changes from the on-voltage to the cutoff voltage, the cutoff voltage temporarily increases.

[0146] Even when the first control voltage output from the charge pump circuit 40 changes in the first instantaneous state, since FET217 is configured on the path connecting terminal 21b and terminal 21a, it is possible to suppress the instantaneous change of the voltage on terminal 21a by supplying the second control voltage according to the direction of change of the control voltage without affecting the conduction and non-conduction of the switching circuit 21 in the stable state.

[0147] In addition, for example, in the high-frequency circuit 1, the switching circuit 21 further includes: a terminal 21c; a FET213 having a fourth gate, a fourth drain, and a fourth source, a fourth control voltage is supplied to the fourth gate from the charge pump circuit 40, the fourth drain is connected to the terminal 21c, and the fourth source is connected to the terminal 21a; and a FET218 having a fifth gate, a fifth drain, and a fifth source, a fifth control voltage is supplied to the fifth gate from the charge pump circuit 40, the fifth drain and the fifth source are connected to the path connecting the terminal 21c, the FET213, and the terminal 21a, and the fifth drain and the fifth source are short-circuited.

[0148] Thus, since FET 217 is arranged on the path connecting terminal 21b and terminal 21a, and FET 218 is arranged on the path connecting terminal 21c and terminal 21a, it is possible to suppress transient fluctuations in the voltage at terminal 21a by supplying control voltages to FETs 217 and 218 in accordance with the direction of fluctuation of the control voltage without affecting the conduction and non-conduction in the stable state of switching circuit 21. This shortens the time it takes for transient fluctuations in switching circuit 21 to converge.

[0149] For example, in the high-frequency circuit 1, when the first control voltage is the first on-state voltage that turns on the FET 211, the second control voltage is the second on-state voltage that turns on the FET 217 when the second drain and the second source are not short-circuited, and when the fourth control voltage is the fourth on-state voltage that turns on the FET 213, the fifth control voltage is the fifth on-state voltage that turns on the FET 218 when the fifth drain and the fifth source are not short-circuited.

[0150] Thus, in the first instantaneous state when the first control voltage changes from the first off-voltage to the first on-voltage, if the voltage at the terminal 21a temporarily increases when the FET 217 is not provided, the voltage between the second gate, the second drain, and the second source of the FET 217 temporarily decreases in the first instantaneous state, thereby suppressing the voltage increase at the terminal 21a caused by the first control voltage. Furthermore, in the fourth instantaneous state when the fourth control voltage changes from the fourth off-voltage to the fourth on-voltage, if the FET 218 is not provided, if the voltage at the terminal 21a temporarily increases, the voltage between the fifth gate, the fifth drain, and the fifth source of the FET 218 temporarily decreases in the fourth instantaneous state, thereby suppressing the voltage increase at the terminal 21a caused by the fourth control voltage.

[0151] For another example, in the high-frequency circuit 1 , the fifth gate is connected to the fourth gate.

[0152] Accordingly, FET218 operates according to the same logic as FET213, so in the fourth instantaneous state where the fourth control voltage changes from the fourth cut-off voltage to the fourth on-state voltage, the voltage between the fifth gate and the fifth drain and the fifth source of FET218 temporarily drops, thereby suppressing the voltage rise of terminal 21a caused by the fourth control voltage.

[0153] For example, in the high-frequency circuit 1A, when the first control voltage is the first on-state voltage that turns on the FET 211, the second control voltage is the second off-state voltage that turns off the FET 217 when the second drain and the second source are not short-circuited, and when the fourth control voltage is the fourth on-state voltage that turns on the FET 213, the fifth control voltage is the fifth off-state voltage that turns off the FET 218 when the fifth drain and the fifth source are not short-circuited.

[0154] Thus, in a first instantaneous state when the first control voltage changes from the first off-voltage to the first on-voltage, if the FET 217 is not provided, while the voltage at the terminal 21a temporarily drops, the voltage between the second gate, the second drain, and the second source of the FET 217 temporarily rises in the first instantaneous state, thereby suppressing the voltage drop at the terminal 21a caused by the first control voltage. Furthermore, in a fourth instantaneous state when the fourth control voltage changes from the fourth off-voltage to the fourth on-voltage, if the FET 218 is not provided, while the voltage at the terminal 21a temporarily drops, the voltage between the fifth gate, the fifth drain, and the fifth source of the FET 218 temporarily rises in the fourth instantaneous state, thereby suppressing the voltage drop at the terminal 21a caused by the fourth control voltage.

[0155] For example, the high-frequency circuit 1A further includes a FET 214, which has a sixth gate, a sixth drain, and a sixth source. A sixth control voltage is supplied to the sixth gate from the charge pump circuit 40, the sixth drain is connected to the terminal 21 c, and the sixth source is grounded. When the FET 213 is in the on state, the FET 214 is in the off state. When the FET 213 is in the off state, the FET 214 is in the on state, and when the FET 213 is in the off state, the FET 214 is in the on state, and the fifth gate and the sixth gate are connected.

[0156] Accordingly, FET218 operates according to the opposite logic to FET213, so in the fourth instantaneous state where the fourth control voltage changes from the fourth cut-off voltage to the fourth on-state voltage, the voltage between the fifth gate and the fifth drain and the fifth source of FET218 temporarily rises, thereby suppressing the voltage drop of terminal 21a caused by the fourth control voltage.

[0157] For example, the high-frequency circuits 1 and 1A further include a level shifter 51 connected between the charge pump circuit 40 and the switch circuit 21 and configured to convert the voltage output from the charge pump circuit 40 into the first control voltage and the second control voltage.

[0158] This allows the voltage output from the charge pump circuit 40 to be converted into a control voltage corresponding to the size and characteristics of each FET constituting the switch circuit 21 .

[0159] For example, the high-frequency circuits 1 and 1A further include a low-noise amplifier circuit 11 whose input end is connected to the terminal 21 a .

[0160] Thus, by placing FET 217 with a source-drain short circuit in the path connecting the input of low-noise amplifier circuit 11 and terminal 21b, transient fluctuations in the voltage at terminal 21a can be suppressed by supplying a second control voltage in accordance with the direction of the control voltage fluctuation without affecting the conduction and non-conduction of switch circuit 21 in its stable state. This shortens the convergence time of transient fluctuations in switch circuit 21, thereby suppressing degradation in the reception performance of low-noise amplifier circuit 11.

[0161] For example, the high-frequency circuits 1 and 1A further include: a power amplifier circuit 12; and a switching circuit 22 having terminals 22a and 22b, with terminal 22a being connected to the output end of the power amplifier circuit 12. The charge pump circuit 40 is configured to supply a control voltage to the switching circuits 21 and 22. The switching circuit 22 includes a seventh FET, the seventh FET having a seventh gate, a seventh drain, and a seventh source. The seventh control voltage is supplied to the seventh gate from the charge pump circuit 40, the seventh drain is connected to the terminal 22b, and the seventh source is connected to the terminal 22a.

[0162] As a result, the control voltage supplied from the charge pump circuit 40 to the switch circuit 22 may fluctuate instantaneously due to instantaneous fluctuations in the control voltage supplied from the charge pump circuit 40. Even in this case, since the FET 217 is disposed on the path connecting the terminal 21b and the terminal 21a, the instantaneous fluctuations in the voltage at the terminal 21a can be suppressed by supplying the second control voltage in accordance with the direction of fluctuation of the control voltage without affecting the conduction and non-conduction of the switch circuit 21 in the stable state.

[0163] For example, in the high-frequency circuits 1 and 1A, the gate width of the seventh FET is larger than the gate width of the FET 211 .

[0164] As a result, due to the large gate capacitance of the seventh FET included in the switch circuit 22, the on-voltage output from the charge pump circuit 40 may temporarily decrease when the off-voltage transitions to the on-voltage. Furthermore, the off-voltage output from the charge pump circuit 40 may temporarily increase when the on-voltage transitions to the off-voltage. Even in this case, since the FET 217 is disposed in the path connecting the terminal 21b and the terminal 21a, transient fluctuations in the voltage at the terminal 21a can be suppressed by supplying the second control voltage in accordance with the direction of fluctuation of the control voltage without affecting the conduction and non-conduction of the switch circuit 21 in the stable state.

[0165] Furthermore, the communication device 4 of the present embodiment includes an RFIC 3 configured to process a high-frequency signal, and a high-frequency circuit 1 configured to transmit the high-frequency signal between the RFIC 3 and the antenna 2 .

[0166] Thus, the communication device 4 can achieve the same effects as those of the high-frequency circuit 1 .

[0167] (Other Embodiments)

[0168] While the high-frequency circuit and communication device of the present invention have been described above based on the embodiments and variations, the high-frequency circuit and communication device of the present invention are not limited to the above-described embodiments and variations. Other embodiments implemented by combining arbitrary components of the above-described embodiments and variations, variations resulting from various modifications conceived by those skilled in the art to the above-described embodiments and variations without departing from the spirit of the present invention, and various devices incorporating the above-described high-frequency circuits are also encompassed by the present invention.

[0169] For example, in the circuit configurations of the high-frequency circuits of the aforementioned embodiments and variations, other circuit elements and wiring may be inserted between the paths connecting the circuit elements and signal paths disclosed in the drawings. For example, an impedance matching circuit may be inserted between the filter and the antenna connection terminal.

[0170] Features of the high-frequency circuit and the communication device described based on the above-mentioned embodiment and modified examples are described below.

[0171] <1> A high-frequency circuit having:

[0172] a first switch circuit having a first terminal and a second terminal, and switching between connection and disconnection of the first terminal and the second terminal; and

[0173] a voltage supply circuit configured to supply a control voltage to the first switch circuit;

[0174] The first switch circuit comprises:

[0175] a first FET having a first gate, a first drain, and a first source, wherein a first control voltage is supplied from the voltage supply circuit to the first gate, one of the first drain and the first source is connected to the first terminal, and the other of the first drain and the first source is connected to the second terminal; and

[0176] The second FET has a second gate, a second drain and a second source. A second control voltage is supplied to the second gate from the voltage supply circuit. The second drain and the second source are connected to a path connecting the first terminal, the first FET and the second terminal. The second drain and the second source are short-circuited.

[0177] <2> According to the high-frequency circuit described in <1>,

[0178] When the first control voltage is a first on-voltage for turning on the first FET, the second control voltage is a second on-voltage for turning on the second FET when the second drain and the second source are not short-circuited.

[0179] <3> According to the high-frequency circuit described in <1> or <2>,

[0180] The second gate is connected to the first gate.

[0181] <4> According to the high-frequency circuit described in <1>,

[0182] When the first control voltage is a first on-voltage for turning on the first FET, the second control voltage is a second off-voltage for turning off the second FET when the second drain and the second source are not short-circuited.

[0183] <5> The high-frequency circuit according to <1> or <2>, further comprising:

[0184] a third FET having a third gate, a third drain, and a third source, wherein a third control voltage is supplied from the voltage supply circuit to the third gate, one of the third drain and the third source is connected to the first terminal, and the other of the third drain and the third source is grounded;

[0185] When the first FET is in the on state, the third FET is in the off state, and when the first FET is in the off state, the third FET is in the on state.

[0186] The second gate is connected to the third gate.

[0187] <6> The high-frequency circuit according to any one of <1> to <5>,

[0188] In a first transient state in which the first control voltage changes from an OFF voltage for turning the first FET into an OFF state to an ON voltage for turning the first FET into an ON state, the ON voltage temporarily drops.

[0189] In a second transient state in which the first control voltage changes from the on-voltage to the off-voltage, the off-voltage temporarily increases.

[0190] <7> The high-frequency circuit according to any one of <1> to <6>,

[0191] The first switch circuit further comprises:

[0192] The third terminal;

[0193] a fourth FET having a fourth gate, a fourth drain, and a fourth source, wherein a fourth control voltage is supplied from the voltage supply circuit to the fourth gate, one of the fourth drain and the fourth source is connected to the third terminal, and the other of the fourth drain and the fourth source is connected to the second terminal; and

[0194] The fifth FET has a fifth gate, a fifth drain and a fifth source. A fifth control voltage is supplied to the fifth gate from the voltage supply circuit. The fifth drain and the fifth source are connected to a path connecting the third terminal, the fourth FET and the second terminal. The fifth drain and the fifth source are short-circuited.

[0195] <8> According to the high-frequency circuit described in <7>,

[0196] When the first control voltage is a first on-state voltage that turns on the first FET, the second control voltage is a second on-state voltage that turns on the second FET when the second drain and the second source are not short-circuited.

[0197] When the fourth control voltage is a fourth on-voltage for turning on the fourth FET, the fifth control voltage is a fifth on-voltage for turning on the fifth FET when the fifth drain and the fifth source are not short-circuited.

[0198] <9> The high-frequency circuit according to <7> or <8>,

[0199] The fifth gate is connected to the fourth gate.

[0200] <10> According to the high-frequency circuit described in <7>,

[0201] When the first control voltage is a first on-voltage that turns the first FET on, the second control voltage is a second off-voltage that turns the second FET off when the second drain and the second source are not short-circuited.

[0202] When the fourth control voltage is a fourth on-voltage for turning on the fourth FET, the fifth control voltage is a fifth off-voltage for turning off the fifth FET when the fifth drain and the fifth source are not short-circuited.

[0203] <11> The high-frequency circuit according to <7> or <8>, further comprising:

[0204] a sixth FET having a sixth gate, a sixth drain, and a sixth source, wherein a sixth control voltage is supplied from the voltage supply circuit to the sixth gate, one of the sixth drain and the sixth source is connected to the third terminal, and the other of the sixth drain and the sixth source is grounded;

[0205] When the fourth FET is in the on state, the sixth FET is in the off state, and when the fourth FET is in the off state, the sixth FET is in the on state.

[0206] The fifth gate is connected to the sixth gate.

[0207] <12> The high-frequency circuit according to any one of <1> to <11>, further comprising:

[0208] The level converter is connected between the voltage supply circuit and the first switch circuit and converts the voltage output from the voltage supply circuit into the first control voltage and the second control voltage.

[0209] <13> The high-frequency circuit according to any one of <1> to <12>, further comprising:

[0210] The low-noise amplifier circuit has an input end connected to the second terminal.

[0211] <14> The high-frequency circuit according to any one of <1> to <13>, further comprising:

[0212] power amplifier circuit; and

[0213] The second switch circuit has a fourth terminal and a fifth terminal, and the fifth terminal is connected to the output end of the power amplifier circuit.

[0214] The voltage supply circuit is configured to supply a control voltage to the first switch circuit and the second switch circuit.

[0215] The second switch circuit comprises:

[0216] The seventh FET has a seventh gate, a seventh drain and a seventh source. A seventh control voltage is supplied to the seventh gate from the voltage supply circuit. One of the seventh drain and the seventh source is connected to the fourth terminal, and the other of the seventh drain and the seventh source is connected to the fifth terminal.

[0217] <15> According to the high-frequency circuit described in <14>,

[0218] The gate width of the seventh FET is larger than the gate width of the first FET.

[0219] <16> A communication device comprising:

[0220] a signal processing circuit configured to process a high-frequency signal; and

[0221] The high-frequency circuit according to any one of <1> to <15> is configured to transmit the high-frequency signal between the signal processing circuit and an antenna.

[0222] The present invention can be widely used in communication devices such as mobile phones as a high-frequency circuit disposed at the front end.

Claims

1. A high-frequency circuit, wherein: have: a first switch circuit having a first terminal and a second terminal, and switching between connection and disconnection of the first terminal and the second terminal; and a voltage supply circuit configured to supply a control voltage to the first switch circuit; The first switch circuit comprises: a first FET having a first gate, a first drain, and a first source, wherein a first control voltage is supplied from the voltage supply circuit to the first gate, one of the first drain and the first source is connected to the first terminal, and the other of the first drain and the first source is connected to the second terminal; as well as The second FET has a second gate, a second drain and a second source. A second control voltage is supplied to the second gate from the voltage supply circuit. The second drain and the second source are connected to a path connecting the first terminal, the first FET and the second terminal. The second drain and the second source are short-circuited.

2. The high-frequency circuit according to claim 1, wherein When the first control voltage is a first on-voltage for turning on the first FET, the second control voltage is a second on-voltage for turning on the second FET when the second drain and the second source are not short-circuited.

3. The high-frequency circuit according to claim 1 or 2, wherein: The second gate is connected to the first gate.

4. The high-frequency circuit according to claim 1, wherein When the first control voltage is a first on-voltage for turning on the first FET, the second control voltage is a second off-voltage for turning off the second FET when the second drain and the second source are not short-circuited.

5. The high-frequency circuit according to claim 1 or 2, wherein: Also features: a third FET having a third gate, a third drain, and a third source, wherein a third control voltage is supplied from the voltage supply circuit to the third gate, one of the third drain and the third source is connected to the first terminal, and the other of the third drain and the third source is grounded; When the first FET is in the on state, the third FET is in the off state, and when the first FET is in the off state, the third FET is in the on state. The second gate is connected to the third gate.

6. The high-frequency circuit according to any one of claims 1 to 5, wherein: In a first transient state in which the first control voltage changes from an OFF voltage for turning the first FET into an OFF state to an ON voltage for turning the first FET into an ON state, the ON voltage temporarily drops. In a second transient state in which the first control voltage changes from the on-voltage to the off-voltage, the off-voltage temporarily increases.

7. The high-frequency circuit according to any one of claims 1 to 6, wherein: The first switch circuit further comprises: The third terminal; a fourth FET having a fourth gate, a fourth drain, and a fourth source, wherein a fourth control voltage is supplied from the voltage supply circuit to the fourth gate, one of the fourth drain and the fourth source is connected to the third terminal, and the other of the fourth drain and the fourth source is connected to the second terminal; as well as The fifth FET has a fifth gate, a fifth drain, and a fifth source. A fifth control voltage is supplied to the fifth gate from the voltage supply circuit. The fifth drain and the fifth source are connected to a path connecting the third terminal, the fourth FET, and the second terminal. The fifth drain and the fifth source are short-circuited.

8. The high-frequency circuit according to claim 7, wherein When the first control voltage is a first on-state voltage for turning on the first FET, the second control voltage is a second on-state voltage for turning on the second FET when the second drain and the second source are not short-circuited. When the fourth control voltage is a fourth on-voltage for turning on the fourth FET, the fifth control voltage is a fifth on-voltage for turning on the fifth FET when the fifth drain and the fifth source are not short-circuited.

9. The high-frequency circuit according to claim 7 or 8, wherein: The fifth gate is connected to the fourth gate.

10. The high-frequency circuit according to claim 7, wherein When the first control voltage is a first on-voltage that turns the first FET on, the second control voltage is a second off-voltage that turns the second FET off when the second drain and the second source are not short-circuited. When the fourth control voltage is a fourth on-voltage for turning on the fourth FET, the fifth control voltage is a fifth off-voltage for turning off the fifth FET when the fifth drain and the fifth source are not short-circuited.

11. The high-frequency circuit according to claim 7 or 8, wherein: Also features: a sixth FET having a sixth gate, a sixth drain, and a sixth source, wherein a sixth control voltage is supplied from the voltage supply circuit to the sixth gate, one of the sixth drain and the sixth source is connected to the third terminal, and the other of the sixth drain and the sixth source is grounded; When the fourth FET is in the on state, the sixth FET is in the off state, and when the fourth FET is in the off state, the sixth FET is in the on state. The fifth gate is connected to the sixth gate.

12. The high-frequency circuit according to any one of claims 1 to 11, wherein: Also features: The level converter is connected between the voltage supply circuit and the first switch circuit and converts the voltage output from the voltage supply circuit into the first control voltage and the second control voltage.

13. The high-frequency circuit according to any one of claims 1 to 12, wherein: Also features: The low-noise amplifier circuit has an input end connected to the second terminal.

14. The high-frequency circuit according to any one of claims 1 to 13, wherein: Also features: power amplifier circuit; and The second switch circuit has a fourth terminal and a fifth terminal, and the fifth terminal is connected to the output end of the power amplifier circuit. The voltage supply circuit is configured to supply a control voltage to the first switch circuit and the second switch circuit. The second switch circuit comprises: The seventh FET has a seventh gate, a seventh drain and a seventh source. A seventh control voltage is supplied to the seventh gate from the voltage supply circuit. One of the seventh drain and the seventh source is connected to the fourth terminal, and the other of the seventh drain and the seventh source is connected to the fifth terminal.

15. The high-frequency circuit according to claim 14, wherein The gate width of the seventh FET is larger than the gate width of the first FET.

16. A communication device, wherein: have: a signal processing circuit configured to process a high-frequency signal; and The high-frequency circuit according to any one of claims 1 to 15 is configured to transmit the high-frequency signal between the signal processing circuit and an antenna.

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