Multi-layer circuit board, multi-layer circuit board assembly and preparation method of multi-layer circuit board

Abstract

The invention discloses a multi-layer circuit board, a multi-layer circuit board assembly and a preparation method of the multi-layer circuit board, and the multi-layer circuit board comprises an insulating substrate, a first circuit layer and a second circuit layer which are located at the same side of the insulating substrate, and a first insulating layer which is used for insulating and separating the first circuit layer and the second circuit layer. The first circuit layer is provided with a plurality of first electric connection parts which are arranged in an exposed mode, the second circuit layer is provided with a plurality of second electric connection parts which are arranged in an exposed mode, and the first electric connection parts and the second electric connection parts are arranged in a spaced mode and used for being electrically connected with semiconductor devices. And the first electric connection part and the second electric connection part are arranged in a staggered manner in the height direction and the horizontal direction respectively. The multi-layer circuit board is used for increasing the number of the electric connecting parts which can be arranged on the multi-layer circuit board and are used for being connected with the semiconductor device, and reducing the risk of short circuit caused by the fact that the electric connecting parts are densely arranged and are connected with the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit boards, and in particular to a multilayer circuit board, a multilayer circuit board assembly, and a method for preparing the multilayer circuit board. Background Art

[0002] A circuit board generally includes a substrate and conductive circuits disposed on the substrate. These conductive circuits have several solder joints. Semiconductor devices, such as chips, can be mounted on the circuit board and soldered to the solder joints of the conductive circuits. Chips and other semiconductor devices have multiple solder pins, and the conductive circuits on the circuit board require a solder joint for each solder pin. Therefore, multiple solder joints are required for the conductive circuits.

[0003] The soldering points of conductive circuits are typically located on the side of a circuit board used to mount semiconductor devices, such as chips. Multiple soldering points need to be spaced apart to ensure mutual insulation. When there are a large number of soldering points, the space available for their placement on the circuit board is limited, and the gaps between adjacent soldering points are small. When adjacent soldering points are connected to semiconductor devices via metal leads, the corresponding metal leads can easily come into contact, causing a short circuit. Alternatively, during processing, machining errors can cause adjacent soldering points to come into contact, potentially creating a short circuit between the chip or other semiconductor device and the soldering points. Summary of the Invention

[0004] The object of the present invention is to provide a multilayer circuit board, a multilayer circuit board assembly and a method for preparing a multilayer circuit board, which are used to increase the number of electrical connection parts that can be provided on the multilayer circuit board for connecting to semiconductor devices and reduce the risk of short circuits caused by overly dense arrangement of electrical connection parts when connected to semiconductor devices.

[0005] The purpose of the present invention is achieved by the following technical solutions:

[0006] A multilayer circuit board comprises an insulating substrate, a first circuit layer and a second circuit layer located on the same side of the insulating substrate, and a first insulating layer for insulating and separating the first circuit layer and the second circuit layer, wherein the first circuit layer is provided with a plurality of exposed first electrical connection portions, and the second circuit layer is provided with a plurality of exposed second electrical connection portions, the first electrical connection portions and the second electrical connection portions are spaced apart and used to electrically connect semiconductor devices, and the first electrical connection portions and the second electrical connection portions are staggered in the height direction and the horizontal direction, respectively.

[0007] Preferably, the first circuit layer and the first insulating layer are respectively arranged on the same surface of the insulating substrate, and the second circuit layer is arranged on the first insulating layer; the height of the first insulating layer is higher than that of the first circuit layer, so that the second circuit layer is spaced apart from the first circuit layer in the height direction;

[0008] The first electrical connection portion is disposed on one side of the first insulating layer, and the first electrical connection portion and the second electrical connection portion form a stepped structure.

[0009] Preferably, the first circuit layer also includes several third electrical connection parts arranged flush with the first electrical connection parts, the first insulating layer is provided with a connection groove stacked with the third electrical connection parts, at least part of the area of ​​the third electrical connection parts is exposed to the connection groove, and a metal connection layer electrically connected to the third electrical connection parts is provided in the connection groove, and the second circuit layer is electrically connected to the third electrical connection parts through the metal connection layer.

[0010] Preferably, the first insulating layer at least covers a portion of the third electrical connection portion, the third electrical connection portion and the second electrical connection portion are partially staggered and overlapped at corresponding positions of the connection groove along the height direction, and the third electrical connection portion and the second electrical connection portion are electrically connected through the metal connection layer.

[0011] Preferably, a fourth circuit layer is further provided on the insulating substrate, and the first circuit layer and the fourth circuit layer are provided on opposite surfaces of the insulating substrate; the first electrical connection portion and the second electrical connection portion are respectively electrically connected to the fourth circuit layer through conductive parts passing through the insulating substrate.

[0012] Preferably, the first circuit layer further comprises a connection sheet for connecting the semiconductor device, and the first electrical connection portion and the second electrical connection portion are respectively arranged on the periphery of the connection sheet and spaced apart from the connection sheet;

[0013] The first electrical connection portion and the second electrical connection portion are adjacent to and arranged side by side along the length direction and / or the width direction of the insulating substrate.

[0014] Preferably, it further comprises a third circuit layer, wherein the third circuit layer is at least arranged on the periphery of the second circuit layer;

[0015] The third circuit layer and the second circuit layer are respectively arranged on the first insulating layer;

[0016] Alternatively, the multilayer circuit board also includes a second insulating layer arranged on the first insulating layer, the second circuit layer is embedded in the second insulating layer, and the second insulating layer insulates and separates adjacent second electrical connection parts, the second electrical connection parts are exposed in the second insulating layer, and the third circuit layer is arranged on the second insulating layer so that the third circuit layer and the second circuit layer are staggered in the height direction.

[0017] Preferably, a fourth circuit layer is further provided on the insulating substrate, and the first circuit layer and the fourth circuit layer are provided on opposite surfaces of the insulating substrate;

[0018] The third circuit layer is insulated and separated from the fourth circuit layer, or the third circuit layer is electrically connected to the fourth circuit layer via a conductive member penetrating the insulating substrate.

[0019] Preferably, the insulating substrate is a ceramic substrate, and the first electrical connection portion and the third electrical connection portion of the first circuit layer are formed on the surface of the insulating substrate by a DPC process. The first electrical connection portion is arranged around the periphery of the semiconductor device and forms a first surrounding area. The third electrical connection portion is horizontally spaced apart from the first electrical connection portion and is arranged around the periphery of the first electrical connection portion to form a third surrounding area. The first insulating layer is formed on the surface of the insulating substrate by deposition and covers the third electrical connection portion. The second electrical connection portion of the second circuit layer is spaced apart on the surface of the first insulating layer by deposition and forms a second surrounding area. The projection of the second surrounding area on the insulating substrate falls between the first surrounding area and the second surrounding area.

[0020] A multilayer circuit board assembly, comprising:

[0021] Any of the above multilayer circuit boards, including a connecting sheet;

[0022] A semiconductor device is mounted on the connecting piece, wherein the semiconductor device is provided with a plurality of connecting pins;

[0023] A plurality of connecting leads, one end of each connecting lead is connected to the connecting pin, and the other end is connected to the first electrical connection portion or the second electrical connection portion, so that the semiconductor device is electrically connected to the first circuit layer and the second circuit layer.

[0024] A method for preparing a multilayer circuit board, the method being used to prepare any of the multilayer circuit boards described above, the method comprising:

[0025] providing an insulating substrate;

[0026] forming a first circuit layer on the surface of the insulating substrate by a DPC process;

[0027] forming a first insulating layer by depositing or screen-printing an insulating paste or laminating a photosensitive film and then exposing and developing the film;

[0028] A second circuit layer is formed on the first insulating layer by deposition, and the first circuit layer and the second circuit layer are insulated and separated by the first insulating layer.

[0029] Preferably, the step of forming the first insulating layer specifically includes: covering the insulating substrate on which the first circuit layer is formed with a covering member to expose the formation position of the first insulating layer, and forming a connection groove in the first insulating layer, with at least part of the third electrical connection portion of the first circuit layer exposed in the connection groove;

[0030] The preparation method further includes: forming a metal connection layer filled in the connection groove by deposition, wherein the metal connection layer is flush with the first insulating layer or protrudes from the first insulating layer.

[0031] Preferably, the second circuit layer and the third circuit layer are formed on the first insulating layer simultaneously by deposition; or,

[0032] forming a second insulating layer on the first insulating layer by depositing, screen-printing an insulating paste, or laminating a photosensitive film and then exposing and developing the film;

[0033] forming the second circuit layer on the first insulating layer by deposition;

[0034] The third circuit layer is formed on the second insulating layer by deposition.

[0035] Compared with the prior art, the beneficial effects of the present invention include at least:

[0036] By providing a first circuit layer and a second circuit layer, the circuit layers on the insulating substrate form a multi-layer structure. The first electrical connection portion of the first circuit layer and the second electrical connection portion of the second circuit layer can be located on different layers, and the first electrical connection portion and the second electrical connection portion can be staggered in both the vertical and horizontal directions. Therefore, the first electrical connection portion and the second electrical connection portion can be arranged in a three-dimensional space, expanding the layout space for the electrical connections to the semiconductor device. A larger layout space can accommodate more electrical connections, and the multiple electrical connections can be sufficiently spaced apart to reduce the risk of short circuits caused by overly dense electrical connection portions when connected to the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 is a schematic structural diagram of a multilayer circuit board and a semiconductor device connected in accordance with an embodiment of the present invention;

[0038] Figure 2 is a schematic structural diagram of a multilayer circuit board according to an embodiment of the present invention;

[0039] Figure 3 is a structural diagram of a multilayer circuit board according to an embodiment of the present invention from another perspective;

[0040] Figure 4 is a partial cross-sectional view of a multilayer circuit board according to an embodiment of the present invention;

[0041] Figure 5 is a schematic structural diagram of an insulating substrate according to an embodiment of the present invention;

[0042] Figure 6 is a structural schematic diagram of an insulating substrate and a first circuit layer according to an embodiment of the present invention;

[0043] Figure 7 This is a structural diagram of the insulating substrate and the first circuit layer in another state according to an embodiment of the present invention;

[0044] Figure 8 is a schematic structural diagram of an insulating substrate and a fourth circuit layer according to an embodiment of the present invention;

[0045] Figure 9 is a schematic structural diagram of an insulating substrate, a first circuit layer, and a first insulating layer according to an embodiment of the present invention;

[0046] Figure 10 This is a schematic structural diagram of the insulating substrate, the first circuit layer, and the first insulating layer in another state according to an embodiment of the present invention;

[0047] Figure 11 This is a partial structural diagram of a multilayer circuit board according to an embodiment of the present invention after a metal connection layer is formed within the first insulating layer;

[0048] Figure 12 This is a partial structural schematic diagram of a multilayer circuit board according to an embodiment of the present invention in another state after a metal connection layer is formed within the first insulating layer;

[0049] Figure 13 is a partial structural schematic diagram of a multilayer circuit board after forming a second insulating layer according to an embodiment of the present invention;

[0050] Figure 14 is a partial structural schematic diagram of a multilayer circuit board according to an embodiment of the present invention in another state after forming a second insulating layer;

[0051] Figure 15 is a partial structural schematic diagram of a multi-layer circuit board after forming a second circuit layer according to an embodiment of the present invention;

[0052] Figure 16 This is a partial structural diagram of a multi-layer circuit board according to an embodiment of the present invention in another state after forming a second circuit layer;

[0053] Figure 17 is a schematic diagram of a portion of the structure of a multi-layer circuit board after forming a third circuit layer according to an embodiment of the present invention;

[0054] Figure 18 is a schematic diagram of a surrounding area formed by a first circuit layer in a multi-layer circuit board according to an embodiment of the present invention;

[0055] Figure 19 is a schematic diagram of a surrounding area formed by the second and third circuit layers in a multi-layer circuit board according to an embodiment of the present invention;

[0056] Figure 20 Schematic diagram of a surrounding area formed by the first, second, and third circuit layers in a multi-layer circuit board according to an embodiment of the present invention.

[0057] In the figure: 100, multi-layer circuit board; 1, insulating substrate; 11, conductive part; 2, first circuit layer; 21, first electrical connection part; 22, third electrical connection part; 3, second circuit layer; 31, second electrical connection part; 4, first insulating layer; 41, connecting groove; 42, first extension section; 43, second extension section; 5, metal connection layer; 6, fourth circuit layer; 7, connecting piece; 8, third circuit layer; 9, second insulating layer; 200, semiconductor device; 300, connecting lead; S1, first surrounding area; S2, second surrounding area; S3, third surrounding area; S4, fourth surrounding area. DETAILED DESCRIPTION

[0058] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the example embodiments to those skilled in the art. Identical reference numerals in the drawings represent identical or similar structures, and thus repeated descriptions thereof will be omitted.

[0059] The words expressing positions and directions described in the present invention are all explained with reference to the accompanying drawings as examples, but can be modified as needed, and all such modifications are within the scope of protection of the present invention.

[0060] like Figures 1 to 20 As shown, the present invention provides a multilayer circuit board 100, including an insulating substrate 1 and a circuit layer and an insulating layer arranged on the insulating substrate 1. The circuit layer may further include a connecting piece 7.

[0061] Reference Figure 1 and Figure 2 The insulating substrate 1 may be a ceramic substrate made of ceramic material. The connecting piece 7 of the circuit layer is disposed on the insulating substrate 1. The connecting piece 7 can be used to connect the semiconductor device 200. Specifically, the connecting piece 7 may be a metal sheet, and the connecting piece 7 and the semiconductor device 200 are welded or bonded to fix the semiconductor device 200 to the insulating substrate 1. The connecting piece 7 may be located in the middle of the insulating substrate 1 and exposed to facilitate connection between the connecting piece 7 and the semiconductor device 200.

[0062] The circuit layers disposed on the insulating substrate 1 are multi-layered, including at least a first circuit layer 2 and a second circuit layer 3, and may also include a third circuit layer 8 and a fourth circuit layer 6. The first circuit layer 2 and the second circuit layer 3 are located on the same side of the insulating substrate 1, for example, both located above the insulating substrate 1. The first circuit layer 2 and the second circuit layer 3 are each used to electrically connect to the semiconductor device 200. Specifically, the first circuit layer 2 is provided with a first electrical connection portion 21 for connecting to the semiconductor device 200, and the second circuit layer 3 is provided with a second electrical connection portion 31 for connecting to the semiconductor device 200. The first circuit layer 2 may have multiple first electrical connections 21, each exposed to the insulating substrate 1 and the insulating layer. The second circuit layer 3 may have multiple second electrical connections 31, each exposed to the insulating substrate 1 and the insulating layer. The multiple first electrical connections 21 in the first circuit layer 2 and the multiple second electrical connections 31 in the second circuit layer 3 may be used to electrically connect to the same semiconductor device 200. The first electrical connection portion 21 and the second electrical connection portion 31 are respectively arranged on the periphery of the connecting piece 7 and are spaced apart from the connecting piece 7. When the connecting piece 7 is connected to the semiconductor device 200, the first electrical connection portion 21 and the second electrical connection portion 31 are located on the periphery of the semiconductor device 200 and are spaced apart from the semiconductor device 200.

[0063] The insulating layer may be provided with one or more layers. When the insulating layer is provided with one layer, the insulating layer may be first insulating layer 4, which is used to insulate and separate the first circuit layer 2 and the second circuit layer 3. When the insulating layer is provided with multiple layers, at least one of the multiple insulating layers serves as first insulating layer 4 to insulate and separate the first circuit layer 2 and the second circuit layer 3.

[0064] In conventional circuit boards, the electrical connectors connected to semiconductor device 200 are arranged on a horizontal plane. This horizontal plane requires space for mounting semiconductor device 200, and the electrical connectors need to be arranged around and adjacent to semiconductor device 200 to facilitate connection between the electrical connectors and semiconductor device 200. However, the space available for arranging the electrical connectors on the horizontal plane is limited. If there are a large number of electrical connectors, the electrical connectors may be arranged too densely. When the circuit board is connected to semiconductor device 200, adjacent electrical connectors may become electrically conductive, causing a short circuit in semiconductor device 200.

[0065] In the present application, by providing a first circuit layer 2 and a second circuit layer 3, the circuit layers on the insulating substrate 1 form a multi-layer structure. The first electrical connection portion 21 of the first circuit layer 2 and the second electrical connection portion 31 of the second circuit layer 3 can be located on different layers, and the first electrical connection portion 21 and the second electrical connection portion 31 can be staggered in the height direction and the horizontal direction, respectively. The height direction can be defined as the thickness direction of the insulating substrate 1, and the horizontal direction is perpendicular to the height direction. Therefore, the first electrical connection portion 21 and the second electrical connection portion 31 can be arranged in a three-dimensional space, expanding the arrangement space for the electrical connection portions connected to the semiconductor device 200. More electrical connections can be arranged in a larger arrangement space, and the multiple electrical connections can be kept sufficiently spaced apart to reduce the risk of short circuits caused by the electrical connection portions being arranged too densely when connected to the semiconductor device 200.

[0066] Reference Figure 2 and Figure 4 In some specific embodiments, the first circuit layer 2 and the first insulating layer 4 can be respectively arranged on the surface of the insulating substrate 1, for example, the first circuit layer 2 and the first insulating layer 4 are respectively arranged on the upper surface of the insulating substrate 1, that is, the first circuit layer 2 and the first insulating layer 4 can both be bonded to the upper surface of the insulating substrate 1. The thickness of the first insulating layer 4 is greater than the thickness of the first circuit layer 2. The first circuit layer 2 and the first insulating layer 4 can be completely staggered in the horizontal direction, and there is no upper and lower overlapping part between the first circuit layer 2 and the first insulating layer 4; or, the first circuit layer 2 and the first insulating layer 4 can partially overlap in the height direction, that is, the first insulating layer 4 covers part of the first circuit layer 2, and the first insulating layer 4 and the first electrical connection portion 21 of the first circuit layer 2 are completely staggered in the horizontal direction, that is, the first electrical connection portion 21 is located on one side of the first insulating layer 4, so as to ensure that the first electrical connection portion 21 is exposed relative to the first insulating layer 4.

[0067] The second circuit layer 3 is disposed on and bonded to the first insulating layer 4. Because the first insulating layer 4 is higher than the first circuit layer 2, the second circuit layer 3, located on the first insulating layer 4, is vertically spaced from the first circuit layer 2 and positioned above the first circuit layer 2. The second circuit layer 3 does not extend horizontally beyond the outer edge of the first insulating layer 4 and is located to one side of the first electrical connection portion 21. The second electrical connection portion 31 of the second circuit layer 3 forms a stepped structure with the first electrical connection portion 21.

[0068] Reference Figure 2 and Figure 9In some specific embodiments, the middle region of the first insulating layer 4 is hollowed out so that the first insulating layer 4 has a hollow ring structure, such as a rectangular hollow ring structure. The inner hollow region of the first insulating layer 4 can be used to dispose the first electrical connection portion 21 and the semiconductor device 200. The second electrical connection portion 31 disposed on the first insulating layer 4 can extend to the inner edge of the first insulating layer 4 or extend to the inner edge of the first insulating layer 4. The first electrical connection portion 21 can be in contact with the inner wall of the first insulating layer 4 or be adjacent to the inner wall of the first insulating layer 4.

[0069] The first electrical connection portion 21 and the second electrical connection portion 31 can be adjacent and arranged side by side along the length and / or width direction of the insulating substrate 1. Specifically, the first insulating layer 4 includes a pair of first extension segments 42 extending along the length direction of the insulating substrate 1, and a pair of second extension segments 43 extending along the width direction of the insulating substrate 1. A portion of the first electrical connection portions 21 are adjacent to or in proximity to the first extension segments 42 and arranged in the same direction as the first extension segments 42. A portion of the first electrical connection portions 21 are adjacent to or in proximity to the second extension segments 43 and arranged in the same direction as the second extension segments 43. A portion of the second electrical connection portions 31 are arranged on the first extension segments 42 and arranged in the same direction as the first extension segments 42. A portion of the second electrical connection portions 31 are arranged on the second extension segments 43 and arranged in the same direction as the second extension segments 43. Among them, the first electrical connection portion 21 that is adjacent to or in contact with the first extension section 42 and the second electrical connection portion 31 located on the first extension section 42 are adjacent to and arranged side by side along the width direction of the insulating substrate 1; the first electrical connection portion 21 that is adjacent to or in contact with the second extension section 43 and the second electrical connection portion 31 located on the second extension section 43 are adjacent to and arranged side by side along the width direction of the insulating substrate 1.

[0070] When the first electrical connection portion 21 and the second electrical connection portion 31 are adjacent and arranged side by side, the horizontal spacing between the first electrical connection portion 21 and the second electrical connection portion 31 can be 0 or close to 0. In this case, the second electrical connection portion 31 is higher than the first electrical connection portion 21 so that the second electrical connection portion 31 is spaced apart from the first electrical connection portion 21 in the height direction and separated by the first insulating layer 4. Therefore, even if the horizontal spacing between the first electrical connection portion 21 and the second electrical connection portion 31 is 0 or close to 0, there is essentially no risk of contact between the first electrical connection portion 21 and the second electrical connection portion 31, which would cause a short circuit after connecting to the semiconductor device 200. In addition, the required horizontal spacing between the first electrical connection portion 21 and the second electrical connection portion 31 is short or no spacing is required, which facilitates the arrangement of more electrical connections on one side of the insulating substrate 1 for connection to the semiconductor device 200.

[0071] Reference Figure 2 and Figure 3In some specific embodiments, the first circuit layer 2 and the fourth circuit layer 6 on the insulating substrate 1 are distributed on opposite sides of the insulating substrate 1, that is, the first circuit layer 2 is provided on the upper surface of the insulating substrate 1, and the fourth circuit layer 6 is provided on the lower surface of the insulating substrate 1. The first circuit layer 2 and the second circuit layer 3 located on the upper surface of the insulating substrate 1 are used to connect to the semiconductor device 200, and the fourth circuit layer 6 located on the lower surface of the insulating substrate 1 can be electrically connected to external circuits such as a PCB (Printed Circuit Board). The first circuit layer 2 and the second circuit layer 3 can be electrically connected to the fourth circuit layer 6, respectively, so that the semiconductor device 200 can be electrically connected to external circuits through multiple circuit layers.

[0072] Reference Figure 4 and Figure 5 To electrically connect the first and second circuit layers 2 and 3 above the insulating substrate 1 with the fourth circuit layer 6 below the insulating substrate 1, the insulating substrate 1 may be provided with a plurality of through-holes extending therethrough. Conductive members 11 may be disposed within the through-holes. Conductive members 11 are made of a conductive material and extend through the insulating substrate 1. The first and second circuit layers 2 and 3 may be electrically connected to the fourth circuit layer 6 via the conductive members 11. The conductive members 11 may be metal pillars, such as copper pillars.

[0073] In some specific embodiments, one end of a portion of the conductive members 11 extends to the first circuit layer 2 and abuts or welds to the first circuit layer 2, and the other end extends to the fourth circuit layer 6 and abuts or welds to the fourth circuit layer 6; one end of a portion of the conductive members 11 extends to the second circuit layer 3 and abuts or welds to the second circuit layer 3, and the other end extends to the fourth circuit layer 6 and abuts or welds to the fourth circuit layer 6.

[0074] Because the plane of the second wiring layer 3 is higher than the plane of the first wiring layer 2, when the second wiring layer 3 is directly connected to the conductive member 11, the conductive member 11 connected to the second wiring layer 3 needs to protrude from the insulating substrate 1, while the conductive member 11 connected to the first wiring layer 2 is flush with the insulating substrate 1. In this case, the sizes of the multiple conductive members 11 vary, making it inconvenient to manufacture the multilayer wiring board 100. Therefore, in other specific embodiments, one end of each conductive member 11 extends to the first wiring layer 2 and abuts or welds to the first wiring layer 2, and the other end extends to the fourth wiring layer 6 and abuts or welds to the fourth wiring layer 6.

[0075] The first circuit layer 2 includes a first electrical connection portion 21 and a third electrical connection portion 22 separated from the first electrical connection portion 21. A portion of the conductive members 11 are electrically connected to the first electrical connection portion 21, and a portion of the conductive members 11 are electrically connected to the third electrical connection portion 22, so that the first electrical connection portion 21 and the third electrical connection portion 22 are respectively electrically connected to the fourth circuit layer 6. The first electrical connection portion 21 is used to connect to the semiconductor device 200, and the third electrical connection portion 22 is used to electrically connect to the second electrical connection portion 31. The second electrical connection portion 31 is electrically connected to the fourth circuit layer 6 via the third electrical connection portion 22. The first electrical connection portion 21 and the third electrical connection portion 22 of the first circuit layer 2 are both disposed on the upper surface of the insulating substrate 1. The conductive members 11 connected to the first electrical connection portion 21 and the conductive members 11 connected to the third electrical connection portion 22 both extend until they are flush with the upper surface of the insulating substrate 1. The conductive members 11 have consistent dimensions, which facilitates the production and preparation of the multilayer circuit board 100.

[0076] It should be noted that the fourth circuit layer 6 can be provided with pads for electrical connection to the conductive member 11, and the multiple pads of the fourth circuit layer 6 can be spaced apart from each other. The fourth circuit layer 6 is provided on the back surface of the insulating substrate 1, and the fourth circuit layer 6 does not need to be connected to the semiconductor device 200 via the connecting leads 300. Not only does it not need to consider the issue of contact between the corresponding connecting leads 300, but it also does not need to provide other functional circuit layers. The back surface of the insulating substrate 1 has sufficient space to arrange the pads of the fourth circuit layer 6. Therefore, all the pads of the fourth circuit layer 6 can be formed on the bottom surface of the insulating substrate 1 and located on the same layer.

[0077] Reference Figure 4 、 Figure 10 and Figure 12 To electrically connect the second electrical connection portion 31 and the third electrical connection portion 22, the first insulating layer 4 may be provided with a connection groove 41. The connection groove 41 penetrates the first insulating layer 4 and is stacked with at least a portion of the second electrical connection portion 31 and at least a portion of the third electrical connection portion 22. That is, one end of the connection groove 41 extends to the second electrical connection portion 31, and the other end of the connection groove 41 extends to the third electrical connection portion 22. At least a portion of the third electrical connection portion 22 is exposed to the connection groove 41. A metal connection layer 5 may be provided in the connection groove 41. One end of the metal connection layer 5 is in electrical contact with the second electrical connection portion 31, and the other end of the metal connection layer 5 is in electrical contact with the third electrical connection portion 22, so that the second electrical connection portion 31 and the third connection portion are electrically connected through the metal connection layer 5.

[0078] There can be multiple second electrical connection parts 31, and there can also be multiple third electrical connection parts 22 and connection grooves 41. Each second connection part corresponds to a third electrical connection part 22 and a connection groove 41, so that each second electrical connection part 31 can be electrically connected to the corresponding third electrical connection part 22 through the metal connection layer 5 in the corresponding connection groove 41.

[0079] To ensure that the third electrical connection portion 22 maintains a sufficient distance from the first electrical connection portion 21, the third electrical connection portion 22 is as far away from the first electrical connection portion 21 as possible. However, due to the limited spatial position of the second electrical connection portion 31 and the fact that the connecting lead 300 cannot be stretched too long, the second electrical connection portion 31 cannot be arranged completely corresponding to the third electrical connection portion 22 in the vertical direction. Therefore, the third electrical connection portion 22 and the second electrical connection portion 31 can be offset and have an overlapping area. Specifically, the end of the third electrical connection portion 22 closest to the first electrical connection portion 21 is stacked with the corresponding end of the second electrical connection portion 31 away from the first connection portion and is electrically connected through the metal connection layer 5. That is, the portion of the third electrical connection portion 22 closest to the first electrical connection portion 21 is located below the end of the second electrical connection portion 31 away from the first electrical connection portion 21, ensuring that the third electrical connection portion 22 and the first electrical connection portion 21 maintain a sufficient distance and are insulated from each other. In other embodiments, the third electrical connection part 22 and the second electrical connection part 31 can also be completely staggered, that is, the third electrical connection part 22 and the second electrical connection part 31 have no overlapping area in the height direction, and the metal connection layer 5 in the connecting groove 41 is connected to the third electrical connection part 22 while protruding out of the connecting groove 41 and connected to the second electrical connection part 31, so that the third electrical connection part 22, the metal connection layer 5 and the second electrical connection part 31 are Z-shaped.

[0080] In some specific embodiments, a third circuit layer 8 is further provided above the insulating substrate 1. The third circuit layer 8 is staggered with the first circuit layer 2 and the second circuit layer 3 along the length and width of the insulating substrate 1. Specifically, the third circuit layer 8 can be provided at the outer edge of the insulating substrate 1, and the first circuit layer 2 and the second circuit layer 3 can be located on the inner side of the insulating substrate 1. The third circuit layer 8 is completely staggered with the second circuit layer 3, that is, the third circuit layer 8 and the second circuit layer 3 are spaced apart along the length and width of the insulating substrate 1, and the third circuit layer 8 is located on the periphery of the first circuit layer 2 and the second circuit layer 3. Alternatively, the third circuit layer 8 and the first circuit layer 2 can be partially stacked, for example, the third circuit layer 8 is partially stacked with the third electrical connection portion 22 in the first circuit layer 2.

[0081] The third circuit layer 8 may not be electrically connected to the fourth circuit layer 6. The third circuit layer 8 may serve as a dam structure for the semiconductor device 200 and be formed by deposition. Alternatively, the third circuit layer 8 may be electrically connected to the fourth circuit layer 6 via a conductive member 11 extending through the insulating substrate 1, and the third circuit layer 8 may be connected to electronic components. The conductive member 11 corresponding to the third circuit layer 8 may extend directly to the third circuit layer 8 to electrically connect to the third circuit layer 8. Alternatively, the first circuit layer 2 may be provided with a fourth electrical connection portion corresponding to the third circuit layer 8, and the conductive member 11 corresponding to the third circuit layer 8 may be connected to the fourth electrical connection portion. The fourth electrical connection portion is then electrically connected to the third circuit layer 8 via a conductive structure passing through the insulating layer.

[0082] In some specific embodiments, the third circuit layer 8 and the second circuit layer 3 can be respectively disposed on the first insulating layer 4, that is, the third circuit layer 8 and the second circuit layer 3 are respectively adhered to the first insulating layer 4. The third circuit layer 8 is spaced apart from the second circuit layer 3 so that the third circuit layer 8 is insulated from the second circuit layer 3.

[0083] In other specific embodiments, the insulating layer may be provided with two layers, namely a first insulating layer 4 and a second insulating layer 9. The second insulating layer 9 is provided on the first insulating layer 4, and the second circuit layer 3 is embedded in the second insulating layer 9, that is, the second insulating layer 9 can cover the side of the second circuit layer 3, and the second insulating layer 9 can be flush with the second circuit layer 3, so that the upper surface of the second circuit layer 3 is exposed to the second insulating layer 9, thereby ensuring that the second electrical connection portion 31 is exposed. By embedding the second circuit layer 3 in the second insulating layer 9, the interval between adjacent second electrical connection portions 31 is filled with the second insulating layer 9, so that adjacent second electrical connection portions 31 are separated by the second insulating layer 9, thereby improving the insulation effect between adjacent second electrical connection portions 31. At this time, the third circuit layer 8 can be provided on the second insulating layer 9, and the third circuit layer 8 is higher than the second circuit layer 3, so that the third circuit layer 8 and the second circuit layer 3 are offset in the height direction.

[0084] The first insulating layer 4 and the second insulating layer 9 can be two independent structures, and the first insulating layer 4 and the second insulating layer 9 are formed separately. Alternatively, the first insulating layer 4 and the second insulating layer 9 can be an integrated structure, and the first insulating layer 4 and the second insulating layer 9 can be integrated into a monolithic insulating layer, and the monolithic insulating layer has a first plane and a second plane higher than the first plane, the first plane serving as the upper surface of the first insulating layer 4, and the first plane being higher than the upper surface of the first electrical connection portion 21; the second circuit layer 3 is disposed on the first plane; the second plane can be flush with the second electrical connection portion 31, and the second plane serves as the upper surface of the second insulating layer 9, and the third circuit layer 8 is disposed on the second plane.

[0085] Reference Figures 18 to 20In some specific embodiments, the plurality of first electrical connection portions 21 of the first circuit layer 2 are arranged around the periphery of the semiconductor device 200, and the plurality of first electrical connection portions 21 in the first circuit layer 2 together form a first surrounding area S1 (e.g. Figure 18 The plurality of third electrical connection portions 22 of the first circuit layer 2 are arranged around the periphery of the first electrical connection portion 21, and the plurality of third electrical connection portions 22 in the first circuit layer 2 together form a third surrounding area S3 (as shown in FIG. Figure 18 The third surrounding area S3 is spaced apart from the first surrounding area S1, and the third surrounding area S3 is located outside the first surrounding area S1. The plurality of second electrical connection portions 31 of the second circuit layer 3 are arranged around the periphery of the semiconductor device 200, and the plurality of second electrical connection portions 31 in the second circuit layer 3 together form a second surrounding area S2 (as shown in FIG. Figure 19 the inner annular shaded area in the figure).

[0086] In the projection of the multiple surrounding areas along the height direction on the insulating substrate 1, the second surrounding area S2 is located between the first surrounding area S1 and the third surrounding area S3. Specifically, the second surrounding area S2 is located between the inner edge of the first surrounding area S1 and the outer edge of the third surrounding area S3. The first surrounding area S1 and the second surrounding area S2 are completely offset, and the third surrounding area S1 and the second surrounding area S2 can be completely offset or partially overlap.

[0087] When the multilayer wiring board 100 is further provided with a third wiring layer 8, the third wiring layer 8 can form a fourth surrounding area S4 (eg, Figure 19 The fourth surrounding area S4 is spaced apart from the second surrounding area S2 and is located outside the second surrounding area S2. In the projection of the multiple surrounding areas along the height direction on the insulating substrate 1, the fourth surrounding area S4 is located at the outermost of the multiple surrounding areas. That is, from the outside to the inside, they are the fourth surrounding area S4, the third surrounding area S3, the second surrounding area S2, and the first surrounding area S1. The fourth surrounding area S4 can be completely offset from the third surrounding area S3 or can partially overlap with the third surrounding area S3.

[0088] Reference Figure 1 The present invention also provides a multilayer circuit board 100 assembly, including a semiconductor device 200, a plurality of connecting leads 300 and the above-mentioned multilayer circuit board 100, wherein the semiconductor device 200 is a chip.

[0089] The semiconductor device 200 is fixed to the connecting piece 7 of the multilayer circuit board 100. The semiconductor device 200 is provided with a plurality of connecting pins for connecting to the electrical connection part of the multilayer circuit board 100. Each connecting pin can be connected to a corresponding electrical connection part through a connecting lead 300. Specifically, one end of the connecting lead 300 is welded to the connecting pin of the semiconductor device 200, and the other end is welded to the corresponding electrical connection part, so that the semiconductor device 200 is electrically connected to the circuit layer on the multilayer circuit board 100. Among them, a part of the connecting pins in the semiconductor device 200 is electrically connected to the first electrical connection part 21 through the connecting lead 300, and a part of the connecting pins is electrically connected to the second electrical connection part 31 through the connecting lead 300. The connecting lead 300 can specifically be a gold wire.

[0090] The present invention further provides a method for preparing a multilayer circuit board 100, which is used to prepare the above-mentioned multilayer circuit board 100. The method for preparing the multilayer circuit board 100 includes steps S01 to S05.

[0091] Step S01: Refer to Figure 5 An insulating substrate 1 is provided. The insulating substrate 1 is pre-formed with a plurality of through holes, and conductive members 11 are provided in the through holes. One end of the conductive member 11 is flush with the upper surface of the insulating substrate 1 , and the other end of the conductive member 11 is flush with the lower surface of the insulating substrate 1 .

[0092] Step S02: Refer to Figure 6 and Figure 7 , forming a first circuit layer 2 on the upper surface of the insulating substrate 1 by a DPC (Direct plating copper, direct copper plating substrate) process, Figure 6 The shaded portion is the first circuit layer 2 formed by the DPC process; and, referring to Figure 3 and Figure 8 The fourth circuit layer 6 is formed on the lower surface of the insulating substrate 1 by the DPC process, and the first circuit layer 2 and the fourth circuit layer 6 are electrically connected through the conductive member 11. Figure 8 The middle shaded portion is the fourth circuit layer 6 formed by the DPC process.

[0093] In step S02, a thin copper layer can be first formed on the surface of the insulating substrate 1 by magnetron sputtering, and then a thickened copper layer can be directly formed on the insulating substrate 1 by a DPC process. Then, a nickel layer and a gold layer can be formed on the copper layer by electroplating or other plating processes. Alternatively, a titanium layer can be first formed on the insulating substrate 1 by magnetron sputtering, and then a copper layer can be formed on the insulating substrate 1 by a DPC process. Then, a nickel layer and a gold layer can be formed on the copper layer by electroplating or other plating processes. That is, the first circuit layer 2 and the fourth circuit layer 6 can respectively include a stacked copper layer, a nickel layer, and a gold layer, or can include a stacked titanium layer, a copper layer, a nickel layer, and a gold layer. The titanium layer is used to increase the bonding strength between the circuit layer and the insulating substrate 1, and the nickel layer and the gold layer are used to improve the welding effect between the circuit layer and components such as the connecting lead 300.

[0094] Step S03: Refer to Figure 9 and Figure 10 The first insulating layer 4 is formed by deposition, such as PVD (Physical Vapor Deposition), screen printing of insulating paste, or lamination of a photosensitive film followed by exposure and development. Figure 9 The shaded area represents the first insulating layer 4 formed by PVD, screen printing of an insulating paste, or lamination of a photosensitive film followed by exposure and development. For example, inorganic insulating materials such as aluminum nitride, silicon dioxide, or silicon nitride can be deposited by PVD. PVD can also be performed by magnetron sputtering or physical deposition methods such as evaporation.

[0095] When forming the first insulating layer 4, a mask is placed above the insulating substrate 1 forming the first circuit layer 2. The mask obscures the portion where the first insulating layer 4 is not required, leaving the portion of the insulating substrate 1 where the first insulating layer 4 is required exposed through the hollow holes created by the mask. The first insulating layer 4 is then formed by PVD or screen printing an insulating paste. If the first insulating layer 4 is formed by laminating a photosensitive film followed by exposure and development, such as when laminating a polyimide film, the mask is not required. A through-hole connection groove 41 is provided in the first insulating layer 4.

[0096] Step S04: Refer to Figure 11 and Figure 12 A metal connection layer 5 filling the connection groove 41 is formed by deposition such as PVD or chemical deposition. The metal connection layer 5 is flush with the first insulating layer 4 or protrudes from the first insulating layer 4. Figure 11 The shaded portion is a metal connection layer 5 formed by PVD or chemical deposition. PVD can also be magnetron sputtering or physical deposition such as evaporation.

[0097] When forming the metal connection layer 5, a covering member is used, and the covering member is hollowed out in the portion corresponding to the connection groove 41, so that after the first insulating layer 4 is formed, only the portion of the insulating substrate 1 corresponding to the connection groove 41 is exposed relative to the covering member, and then the metal connection layer 5 filled in the connection groove 41 is formed by PVD or chemical deposition.

[0098] Step S05: Refer to Figure 15 and Figure 16 The second circuit layer 3 is formed on the first insulating layer 4 by deposition such as PVD or chemical deposition, and the first circuit layer 2 and the second circuit layer 3 are insulated and separated by the first insulating layer 4. Figure 15 The shaded portion is the second circuit layer 3 formed by PVD or chemical deposition.

[0099] In some specific embodiments, step S05 specifically includes: simultaneously forming the second circuit layer 3 and the third circuit layer 8 on the first insulating layer 4 by PVD or chemical deposition. When forming the second circuit layer 3 and the third circuit layer 8, a shielding member is used to shield the portion where the second circuit layer 3 and the third circuit layer 8 are not required to be formed, and the shielding member is hollowed out in the portion of the second circuit layer 3 and the third circuit layer 8 corresponding to the second circuit layer 3 and the third circuit layer 8. Thereafter, the second circuit layer 3 and the third circuit layer 8 are simultaneously formed on the first insulating layer 4 by PVD or chemical deposition, with the spaced-apart arrangement. The second circuit layer 3 and the third circuit layer 8 have the same structural components. The second circuit layer 3 and the third circuit layer 8 can respectively include a stacked copper layer, a nickel layer, and a gold layer, or a stacked nickel layer and a gold layer. The copper layer, the nickel layer, and the gold layer are respectively formed by PVD or chemical deposition.

[0100] In some further specific implementations, step S05 may specifically include steps S51 to S53.

[0101] Step S51: Refer to Figure 13 and Figure 14 The second insulating layer 9 is formed on the first insulating layer 4 by PVD, screen printing of insulating paste or laminating a photosensitive film and then exposing and developing. Figure 13 The middle shaded portion is the second insulating layer 9 formed by PVD, screen printing of insulating paste, or laminating a photosensitive film and then exposing and developing.

[0102] When forming the second insulating layer 9, a mask is used to cover the portion where the second insulating layer 9 is not required, and the mask is hollowed out in the portion corresponding to the second insulating layer 9. Then, the second insulating layer 9 is formed on the first insulating layer 4 by PVD and screen printing of insulating paste.

[0103] Step S52: Refer to Figure 15 and Figure 16The second circuit layer 3 is formed on the first insulating layer 4 by PVD or chemical deposition. A mask is used to cover the portion where the second circuit layer 3 is not required, while the mask is hollowed out in the portion where the second circuit layer 3 is required. The second circuit layer 3 is then formed on the first insulating layer 4 by PVD or chemical deposition. The second circuit layer 3 is embedded in the second insulating layer 9 and is flush with the second insulating layer 9.

[0104] Step S53: Refer to Figure 17 and Figure 2 , a third circuit layer 8 is formed on the second insulating layer 9 by PVD or chemical deposition. Figure 17 The shaded portion is the third circuit layer 8 formed by PVD or chemical deposition.

[0105] A shield is used to cover the portion where the third circuit layer 8 is not required, and the shield is hollowed out in the portion where the third circuit layer 8 is required. PVD or chemical deposition is then used to form the third circuit layer 8 on the second insulating layer 9. The third circuit layer 8 is located above the second circuit layer 3.

[0106] The above-mentioned covering members can all be steel meshes, and the steel meshes are processed so that corresponding positions of the steel meshes are hollowed out.

[0107] In some other specific embodiments, when the first insulating layer 4 and the second insulating layer 9 are an integrated structure, the first insulating layer 4 and the second insulating layer 9 can be formed simultaneously.

[0108] Specifically, in step S03, a monolithic insulating structure comprising a first insulating layer 4 and a second insulating layer 9 is formed by PVD, screen printing an insulating paste, or laminating a photosensitive film followed by exposure and development. When forming this monolithic insulating structure, a mask is placed above the insulating substrate 1 forming the first circuit layer 2. The mask obscures the portion of the insulating substrate 1 where the monolithic insulating structure is not required, while the portion of the insulating substrate 1 where the monolithic insulating structure is required is exposed through the hollow holes created by the mask. The monolithic insulating structure is then formed by PVD, screen printing an insulating paste, or printing a photosensitive ink followed by exposure and development. Step S05 includes the aforementioned steps S52 and S53.

[0109] In the prior art, a multi-layer circuit board is mainly formed by using an LTCC (Low Temperature Co-fired Ceramic) process or welding multiple DPC ceramic substrates.

[0110] Among them, when the LTCC process is adopted, ceramic layers and metal layers are stacked multiple times, and some metal circuits are arranged between adjacent ceramic layers. The multi-layer metal circuits are connected by conductive metal columns that pass through the ceramic layers, and the pads of the metal circuits are arranged above the multi-layer circuit board. After the multi-layer ceramic layers and metal layers are stacked, they will be sintered at a temperature of 800 to 1000°C to form an integral multi-layer circuit board. The process of preparing the multi-layer circuit board prepared by the LTCC process is relatively complicated, and it needs to be fired in an oxidizing atmosphere during low-temperature sintering, which makes the processing more difficult. In addition, the pads of the multi-layer circuit board are still distributed on the same surface (i.e., the upper surface of the multi-layer circuit board), and the space for arranging the pads is limited.

[0111] Alternatively, the HTCC (High Temperature Co-fired Ceramic) process is used to sinter the stacked ceramic and metal layers. This process requires sintering at temperatures exceeding 1500°C in an oxidizing atmosphere, but also presents complex manufacturing processes and high processing difficulty.

[0112] When welding multiple DPC ceramic substrates, the multiple single-layer DPC substrates are interconnected using solder or electroplated copper pillars. This requires a large amount of space, and the multiple DPC substrates must be connected to each other using connecting structures. This results in a larger overall structure and higher costs. Furthermore, poor welding can create gaps at the connection points between the multiple DPC substrates, reducing the airtightness of the multilayer circuit board.

[0113] In the present application, the first circuit layer 2 and the fourth circuit layer 6 are formed using a DPC process. The DPC process achieves high precision, with the line width and line spacing of the metal circuits in the first circuit layer 2 and the fourth circuit layer 6 respectively reaching below 50μm. The second circuit layer 3 and the third circuit layer 8 are formed using deposition methods such as PVD, with their line width and spacing reaching levels of 10μm. Therefore, the circuits in the multilayer circuit board 100 prepared in the present application are highly precise, allowing the line width of the circuit layer to be reduced to improve the accuracy of the circuit layer's graphics. Furthermore, the preparation of the multilayer circuit board 100 does not require high temperatures or an oxidizing atmosphere, resulting in a low processing difficulty and a relatively simple preparation process. The multilayer circuit layers prepared in the present application also do not require multiple DPC ceramic substrates. The multiple layers of circuits are formed on a single insulating substrate 1, resulting in a smaller and less expensive multilayer circuit board 100. Furthermore, the circuit layers and insulating layers are formed using a DPC process or deposition process, resulting in an airtight seal that is superior to soldering methods.

[0114] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limiting the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the invention without departing from the principles and purpose of the present invention. All such changes shall fall within the scope of protection of the claims of the present invention.

Claims

1. A multilayer circuit board, characterized in that: The invention comprises an insulating substrate (1), a first circuit layer (2) and a second circuit layer (3) located on the same side of the insulating substrate (1), and a first insulating layer (4) for insulating and separating the first circuit layer (2) and the second circuit layer (3); the first circuit layer (2) is provided with a plurality of exposed first electrical connection parts (21); the second circuit layer (3) is provided with a plurality of exposed second electrical connection parts (31); the first electrical connection parts (21) and the second electrical connection parts (31) are spaced apart and are used to electrically connect a semiconductor device (200); and the first electrical connection parts (21) and the second electrical connection parts (31) are staggered in the height direction and the horizontal direction, respectively.

2. The multilayer circuit board according to claim 1, wherein The first circuit layer (2) and the first insulating layer (4) are respectively arranged on the same surface of the insulating substrate (1), and the second circuit layer (3) is arranged on the first insulating layer (4); the height of the first insulating layer (4) is higher than the height of the first circuit layer (2), so that the second circuit layer (3) and the first circuit layer (2) are spaced apart in a height direction; The first electrical connection portion (21) is arranged on one side of the first insulating layer (4), and the first electrical connection portion (21) and the second electrical connection portion (31) form a stepped structure.

3. The multilayer circuit board according to claim 2, wherein: The first circuit layer (2) further comprises a plurality of third electrical connection parts (22) arranged flush with the first electrical connection part (21); the first insulating layer (4) is provided with a connection groove (41) stacked with the third electrical connection part (22); at least a portion of the third electrical connection part (22) is exposed to the connection groove (41); a metal connection layer (5) electrically connected to the third electrical connection part (22) is provided in the connection groove (41); and the second circuit layer (3) is electrically connected to the third electrical connection part (22) via the metal connection layer (5).

4. The multilayer circuit board according to claim 3, wherein: The first insulating layer (4) at least partially covers the third electrical connection portion (22); the third electrical connection portion (22) and the second electrical connection portion (31) are partially offset and overlapped at corresponding positions of the connection groove (41) in the height direction; and the third electrical connection portion (22) and the second electrical connection portion (31) are electrically connected via the metal connection layer (5).

5. The multilayer circuit board according to claim 3, wherein: A fourth circuit layer (6) is also provided on the insulating substrate (1); the first circuit layer (2) and the fourth circuit layer (6) are provided on opposite surfaces of the insulating substrate (1); the first electrical connection portion (21) and the second electrical connection portion (31) are electrically connected to the fourth circuit layer (6) via a conductive member (11) passing through the insulating substrate (1), respectively.

6. The multilayer circuit board according to claim 1, wherein: The first circuit layer (2) further comprises a connecting piece (7) for connecting the semiconductor device (200), the first electrical connecting portion (21) and the second electrical connecting portion (31) being respectively arranged on the periphery of the connecting piece (7) and spaced apart from the connecting piece (7); The first electrical connection portion (21) and the second electrical connection portion (31) are adjacent to and arranged side by side along the length direction and / or width direction of the insulating substrate (1).

7. The multilayer circuit board according to claim 1, wherein It also includes a third circuit layer (8), wherein the third circuit layer (8) is at least arranged on the periphery of the second circuit layer (3); The third circuit layer (8) and the second circuit layer (3) are respectively arranged on the first insulating layer (4); Alternatively, the multilayer circuit board further comprises a second insulating layer (9) arranged on the first insulating layer (4), the second circuit layer (3) is embedded in the second insulating layer (9), and the second insulating layer (9) insulates and separates adjacent second electrical connection portions (31), the second electrical connection portions (31) are exposed on the second insulating layer (9), and the third circuit layer (8) is arranged on the second insulating layer (9) so that the third circuit layer (8) and the second circuit layer (3) are displaced in a height direction.

8. The multilayer circuit board according to claim 7, wherein: A fourth circuit layer (6) is further provided on the insulating substrate (1), and the first circuit layer (2) and the fourth circuit layer (6) are provided on opposite surfaces of the insulating substrate (1); The third circuit layer (8) is insulated and separated from the fourth circuit layer (6), or the third circuit layer (8) is electrically connected to the fourth circuit layer (6) via a conductive member (11) penetrating the insulating substrate (1).

9. The multilayer circuit board according to claim 3, wherein: The insulating substrate (1) is a ceramic substrate. The first electrical connection portion (21) and the third electrical connection portion (22) of the first circuit layer (2) are formed on the surface of the insulating substrate (1) by a DPC process. The first electrical connection portion (21) is arranged around the periphery of the semiconductor device (200) and forms a first surrounding area (S1). The third electrical connection portion (22) is arranged horizontally spaced apart from the first electrical connection portion (21) and is arranged around the periphery of the first electrical connection portion (21) to form a third surrounding area (S3). The first insulating layer (4) is formed on the surface of the insulating substrate (1) by deposition and covers the third electrical connection portion (22). The second electrical connection portion (31) of the second circuit layer (3) is arranged at intervals on the surface of the first insulating layer (4) by deposition and surrounds to form a second surrounding area (S2). The projection of the second surrounding area (S2) on the insulating substrate (1) falls between the first surrounding area (S1) and the second surrounding area (S2).

10. A multilayer circuit board assembly, characterized in that: include: The multilayer circuit board (100) according to any one of claims 1 to 9, comprising a connecting piece (7); A semiconductor device (200) is mounted on the connecting piece (7), and the semiconductor device (200) is provided with a plurality of connecting pins; A plurality of connecting leads (300), one end of each connecting lead (300) being connected to the connecting pin, and the other end being connected to the first electrical connection portion (21) or the second electrical connection portion (31), so that the semiconductor device (200) is electrically connected to the first circuit layer (2) and the second circuit layer (3).

11. A method for preparing a multilayer circuit board, characterized in that: The preparation method is used to prepare a multilayer circuit board (100) according to any one of claims 1 to 9, and the preparation method comprises: Providing an insulating substrate (1); forming a first circuit layer (2) on the surface of the insulating substrate (1) through a DPC process; Forming a first insulating layer (4) by depositing or screen-printing an insulating paste or laminating a photosensitive film and then exposing and developing the film; A second circuit layer (3) is formed on the first insulating layer (4) by deposition, and the first circuit layer (2) and the second circuit layer (3) are insulated and separated by the first insulating layer (4).

12. The method for preparing a multilayer circuit board according to claim 11, wherein: The step of forming the first insulating layer (4) specifically includes: covering the insulating substrate (1) on which the first circuit layer (2) is formed by a covering member to expose the formation position of the first insulating layer (4), and forming a connection groove (41) in the first insulating layer (4), and at least a portion of the third electrical connection portion (22) of the first circuit layer (2) is exposed in the connection groove (41); The preparation method further comprises: forming a metal connection layer (5) filled in the connection groove (41) by deposition, wherein the metal connection layer (5) is flush with the first insulating layer (4) or protrudes from the first insulating layer (4).

13. The method for preparing a multilayer circuit board according to claim 11, wherein: The second circuit layer (3) and the third circuit layer (8) are simultaneously formed on the first insulating layer (4) by deposition; or, forming a second insulating layer (9) on the first insulating layer (4) by depositing, screen-printing insulating paste, or laminating a photosensitive film and then exposing and developing; forming the second circuit layer (3) on the first insulating layer (4) by deposition; The third circuit layer (8) is formed on the second insulating layer (9) by deposition.

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