A method for manufacturing a semiconductor device and a semiconductor device

Abstract

The application discloses a semiconductor device manufacturing method and a semiconductor device, and belongs to the technical field of semiconductors. The manufacturing method comprises the following steps: providing a substrate, forming a gate structure on the substrate, etching the substrate on both sides of the gate structure to form a sigma groove, forming a buffer layer on the bottom and the sidewall of the sigma groove, forming a self-aligned barrier layer on part of the buffer layer, etching part of the buffer layer and the self-aligned barrier layer to form a groove, and forming a seed layer in the groove. Through the semiconductor device manufacturing method and the semiconductor device provided by the application, the growth space of the high-stress seed layer can be effectively expanded, the stress effect of the seed layer is maximized, the channel mobility is increased, and the performance of the semiconductor device is improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to a method for manufacturing a semiconductor device and the semiconductor device itself. Background Technology

[0002] With the continuous development of integrated circuit manufacturing technology, in order to achieve faster computing speeds, larger data storage capacities, and more functions, integrated circuit chips are evolving towards higher semiconductor device density and higher integration levels. As the feature size of semiconductor devices continues to shrink, traditional processes struggle to break through their limits. In PMOS transistors, a special silicon-germanium structure is used to apply mechanical stress to the channel between the source and drain, altering the electronic band structure of the silicon atomic lattice and thus changing the carrier mobility. The classic silicon-germanium structure includes a buffer layer, a seed layer, and a silicon cap layer. The buffer layer grows at different rates in different crystal directions, resulting in a V-shaped termination surface. Insufficient growth range of the seed layer limits the stress effect, thus restricting the performance of the semiconductor device. Summary of the Invention

[0003] The purpose of this invention is to provide a method for fabricating a semiconductor device and a semiconductor device. The method and semiconductor device provided by this invention can effectively expand the growth space of the high-stress seed layer, maximize the stress effect of the seed layer, increase the channel mobility, and improve the performance of the semiconductor device.

[0004] To address the aforementioned technical problems, this invention provides a method for fabricating a semiconductor device, comprising the following steps:

[0005] A substrate is provided on which a gate structure is formed;

[0006] The substrates on both sides of the gate structure are etched to form sigma trenches;

[0007] A buffer layer is formed on the bottom and sidewalls of the sigma trench;

[0008] A self-aligned barrier layer is formed on a portion of the buffer layer;

[0009] Etching portions of the buffer layer and the self-aligned barrier layer to form grooves; and

[0010] A seed crystal layer is formed within the groove.

[0011] In one embodiment of the present invention, from the surface of the substrate to the bottom of the sigma trench, the side surfaces of the sigma trench are sequentially an upper tangent, a lower tangent, and a bottom surface, and the upper tangent and the lower tangent are connected by an interface.

[0012] In one embodiment of the present invention, the buffer layer is a boron-doped silicon-germanium layer, and the germanium content increases from the interface between the buffer layer and the substrate, with the germanium content on the surface of the buffer layer being 20% ​​to 30%.

[0013] In one embodiment of the present invention, after the buffer layer is deposited, the ratio of the thickness of the buffer layer on the lower cut surface to the thickness on the interface is 1:1.3-1.8.

[0014] After the groove is formed, the ratio of the thickness of the buffer layer on the lower cut surface to the thickness on the interface is 1:2-4.

[0015] In one embodiment of the present invention, the self-aligned barrier layer is an intrinsic silicon layer and is formed by selective epitaxial growth, wherein the self-aligned barrier layer is grown on the bottom surface of the buffer layer.

[0016] In one embodiment of the present invention, when forming the self-aligned barrier layer, the epitaxial growth gas source includes a mixture of dichlorosilane and hydrogen chloride, and the epitaxial growth temperature is 650°C to 680°C.

[0017] In one embodiment of the present invention, the buffer layer and the self-aligned barrier layer are etched by dry etching, and the etching gas includes hydrogen chloride gas.

[0018] In one embodiment of the present invention, the working temperature of the dry etching is 730°C to 780°C, and the flow rate of hydrogen chloride gas is 50 sccm to 100 sccm.

[0019] In one embodiment of the present invention, during the dry etching process, the etching rate of the buffer layer on the interface is greater than the etching rate of the buffer layer on the upper and lower cut surfaces, and the etching rate of the buffer layer on the upper and lower cut surfaces is greater than the etching rate of the self-aligned barrier layer.

[0020] The present invention also provides a semiconductor device, comprising:

[0021] A substrate on which a gate structure is disposed;

[0022] Sigma trenches are disposed in the substrates on both sides of the gate structure;

[0023] A buffer layer is provided on the bottom and sidewalls of the sigma trench;

[0024] A self-aligned blocking layer is disposed on the buffer layer at the bottom of the sigma trench; and

[0025] A seed layer is disposed on the buffer layer and the self-aligned barrier layer.

[0026] In summary, this invention provides a method for fabricating a semiconductor device and the semiconductor device itself. The unexpected technical effect of this application is that it effectively expands the growth space of the high-stress seed layer, maximizing the stress effect of the seed layer while satisfying the requirements for buffering and blocking leakage current, thereby increasing channel mobility and improving the performance of the semiconductor device. It can also improve lattice mismatch problems; the self-aligned blocking layer can effectively improve the main leakage current problem of the semiconductor device, thus enhancing the electrical performance of the semiconductor device.

[0027] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of a pad oxide layer and a pad nitride layer formed on a substrate in one embodiment of the present invention.

[0030] Figure 2 This is a schematic diagram of a shallow trench isolation structure formed in one embodiment of the present invention.

[0031] Figure 3 This is a schematic diagram of the formation of a trap region in one embodiment of the present invention.

[0032] Figure 4 This is a schematic diagram of the formation of a gate dielectric layer, a gate material layer, and a hard mask layer in one embodiment of the present invention.

[0033] Figure 5 This is a schematic diagram of a gate structure formed in one embodiment of the present invention.

[0034] Figure 6 This is a schematic diagram of a sidewall structure formed in one embodiment of the present invention.

[0035] Figure 7 This is a schematic diagram of the formation of sigma trenches in one embodiment of the present invention.

[0036] Figure 8 This is a schematic diagram of the formation of a buffer layer in one embodiment of the present invention.

[0037] Figure 9 This is a schematic diagram of forming a self-aligned barrier layer in one embodiment of the present invention.

[0038] Figure 10 This is a schematic diagram of the self-aligned barrier layer and buffer layer after etching in one embodiment of the present invention.

[0039] Figure 11 This is a schematic diagram showing the etching rates of different crystal planes of different materials in one embodiment of the present invention.

[0040] Figure 12 This is a schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0041] Label Explanation:

[0042] 10. Substrate; 101. Well region; 11. Pad oxide layer; 12. Pad nitride layer; 13. First photoresist layer; 131. Recess; 14. Shallow trench isolation structure; 15. Gate dielectric layer; 16. Gate material layer; 161. Gate structure; 17. Hard mask layer; 18. Second photoresist layer; 19. Sidewall structure; 20. Sigma trench; 201. Opening; 21. Buffer layer; 22. Self-aligned barrier layer; 202. Groove; 23. Seed layer; 24. Cap layer; 301. Top facet; 302. Bottom facet; 303. Bottom surface; 304. Interface. Detailed Implementation

[0043] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0045] In the description of this specification, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," and "right," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing this solution and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this solution. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0046] This invention provides a method for fabricating a semiconductor device and the semiconductor device itself. When forming a stress structure, it effectively expands the growth space of the high-stress seed layer, maximizing the stress effect of the seed layer while satisfying the requirements of buffering and blocking leakage current, thereby increasing channel mobility and improving the performance of the semiconductor device. Furthermore, the semiconductor device prepared by this invention can be widely used in various fields such as optical communication, digital display, image reception, optical integration, transportation, energy, medicine, home appliances, and aerospace.

[0047] Please see Figure 1 As shown, in one embodiment of the present invention, a substrate 10 is first provided. The substrate 10 can be any material suitable for forming a semiconductor device, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, silicon wafers, or other III / V compound semiconductor materials. It also includes a stacked structure composed of these semiconductor materials, or silicon-on-insulator, silicon-on-insulator, silicon-germanium-on-insulator, and germanium-on-insulator. In this embodiment, the substrate 10 is, for example, a silicon wafer semiconductor substrate, and the substrate 10 is, for example, a P-type substrate.

[0048] Please see Figure 1 As shown, in one embodiment of the present invention, a pad oxide layer 11 is formed on a substrate 10. The pad oxide layer 11 serves as a buffer layer to improve the stress between the substrate 10 and the subsequently formed pad nitride layer 12. The pad oxide layer 11 is, for example, a dense silicon oxide material, and can be formed by any one of the following methods: dry oxygen oxidation, wet oxygen oxidation, or in-situ steam generation (ISSG). In this embodiment, the pad oxide layer 11 is formed, for example, by dry oxygen oxidation. Specifically, the substrate 10 is placed in a furnace tube at a temperature of, for example, 900°C to 1150°C, and oxygen is introduced. The surface of the substrate 10 reacts with the oxygen at a high temperature to generate a dense pad oxide layer 11, and the generated pad oxide layer 11 has good quality. The pad oxide layer 11 is, for example, silicon oxide, and the thickness of the pad oxide layer 11 is, for example, 10nm to 40nm, specifically, 10nm, 20nm, 30nm, or 40nm.

[0049] Please see Figures 1 to 2As shown, in one embodiment of the present invention, a pad nitride layer 12 is formed on the pad oxide layer 11. The pad nitride layer 12 is, for example, silicon nitride or a stack of silicon nitride and silicon oxide. In this embodiment, the pad nitride layer 12 is, for example, silicon nitride, and can be formed, for example, by a method such as low-pressure chemical vapor deposition (LPCVD). Specifically, for example, a substrate 10 with the pad oxide layer 11 is placed in a furnace tube filled with dichlorosilane and ammonia, and reacted at a pressure of, for example, 2T to 10T and a temperature of, for example, 700°C to 900°C to deposit the pad nitride layer 12. The thickness of the pad nitride layer 12 can be adjusted by controlling the heating time. The thickness of the pad nitride layer 12 is, for example, 50 nm to 80 nm, specifically 50 nm, 60 nm, or 70 nm. By setting the pad nitride layer 12, the substrate 10 can be protected from the planarization processes such as chemical mechanical polishing (CMP) involved in the fabrication of the shallow trench isolation structure 14. Furthermore, the pad nitride layer 12 can act as a mask during the subsequent formation of the shallow trench isolation structure, protecting the substrate 10 from damage during etching.

[0050] Please see Figures 1 to 2 As shown, in one embodiment of the present invention, after forming the pad nitride layer 12, a first photoresist layer 13 is formed on the pad nitride layer 12. Through exposure and development processes, a plurality of recesses 131 are formed on the first photoresist layer 13. The recesses 131 are used to define the positions of the shallow trench isolation structure 14. Using the first photoresist layer 13 as a mask, etching is performed to remove the pad nitride layer 12, the pad oxide layer 11, and part of the substrate 10 exposed in the recesses 131, thereby forming shallow trenches. In this embodiment, for example, dry etching is used to form the shallow trenches (not shown in the figure). After etching, the first photoresist layer 13 is removed by ashing or wet etching. After forming the shallow trenches, an insulating medium is deposited in the shallow trenches until the insulating medium in the shallow trenches exceeds the surface of the pad nitride layer 12. In this embodiment, the insulating medium is, for example, silicon oxide. This invention does not limit the deposition method of the insulating medium. For example, high-density plasma chemical vapor deposition (HDP-CVD) or high aspect ratio process chemical vapor deposition (HARP-CVD) can be used to form a high-quality insulating medium. In other embodiments, the insulating medium can also be other insulating materials suitable for insulation and the method of formation thereof.

[0051] Please see Figures 1 to 2As shown, in one embodiment of the present invention, after preparing the insulating dielectric, the insulating dielectric is planarized, for example, using a chemical mechanical polishing process. For example, polishing removes part of the insulating dielectric and part of the pad nitride layer 12, and then removes the pad nitride layer 12 again to obtain a shallow trench isolation structure 14, wherein the shallow trench isolation structure 14, for example, protrudes above the pad oxide layers 11 on both sides. The present invention does not limit the method for removing the pad nitride layer 12; for example, it can be removed using dry etching, wet etching, or a combination of dry and wet etching. In this embodiment, for example, thermal phosphoric acid is used to remove the pad nitride layer 12 to form the shallow trench isolation structure 14 for isolating adjacent semiconductor devices.

[0052] Please see Figures 2 to 3 As shown, in one embodiment of the present invention, after the shallow trench isolation structure 14 is fabricated, the substrate 10 is ion implanted using the pad oxide layer 11 as an ion implantation buffer layer to form a well region 101. In this application, the semiconductor device is, for example, a PMOS transistor, and the dopant ions in the well region 101 are, for example, N-type dopant ions, or phosphorus (P) or arsenic (As). After ion implantation, the well region 101 is subjected to a rapid thermal annealing (RTA) process to allow the implanted ions to diffuse to a suitable depth, thereby improving the avalanche breakdown resistance of the semiconductor device. Alternatively, wet etching can be used to remove the pad oxide layer 11, and the etching solution used for wet etching can be, for example, hydrofluoric acid or buffered oxide etch (BOE).

[0053] Please see Figures 3 to 4 As shown, in one embodiment of the present invention, after removing the pad oxide layer, a gate dielectric layer 15 is formed on the substrate 10. The gate dielectric layer 15 is, for example, a silicon oxide layer or a stack of a silicon oxide layer and a high-dielectric-constant dielectric layer. In this embodiment, the gate dielectric layer 15 is, for example, a silicon oxide layer, and the gate dielectric layer 15 is formed, for example, by in-situ water vapor growth, and the thickness of the gate dielectric layer 15 is, for example, 8 Å to 15 Å. A gate material layer 16 is formed on the gate dielectric layer 15. The gate material layer 16 is, for example, polysilicon or a metal layer, and the gate material layer 16 is prepared, for example, by chemical vapor deposition, and the thickness of the gate material layer 16 is, for example, 50 nm to 200 nm, selected according to the requirements of the semiconductor device. A hard mask layer 17 is formed on the gate material layer 16, wherein the hard mask layer 17 is, for example, silicon nitride or a stack of silicon nitride and silicon oxide, to protect the gate structure when sidewall structures or source / drain structures are subsequently formed. A second photoresist layer 18 is formed on the gate material layer 16, and then the second photoresist layer 18 is exposed and developed to remove the second photoresist layer 18 outside the area forming the gate structure.

[0054] Please see Figures 4 to 5As shown, in one embodiment of the present invention, the second photoresist layer 18 is used as a mask, and the substrate 10 is used as an etch stop layer. The hard mask layer 17, the gate material layer 16, and the gate dielectric layer 15 are etched, for example, by a dry etching process, a wet etching process, or a combination of dry and wet etching processes. The remaining gate material layer 16 is defined as the gate structure 161. In this embodiment, the gate structure 161 is formed, for example, by dry etching.

[0055] Please see Figures 5 to 6 As shown, in one embodiment of the present invention, after forming the gate structure 161, sidewall structures 19 are formed on both sides of the gate structure 161. Specifically, a sidewall dielectric layer (not shown in the figure) is formed on the substrate 10 and the gate structure 161, and then the sidewall dielectric layer is etched, leaving only the sidewall dielectric layers on both sides of the gate structure 161 to form the sidewall structures 19. The sidewall structures 19 are, for example, flush with the gate structure 161, and the sidewall structures 19 are, for example, arc-shaped or L-shaped. The sidewall structures 19 are, for example, a stacked structure. In this embodiment, the sidewall structures 19, starting from the side closest to the gate structure 161, are, for example, a stack of silicon oxide and silicon nitride, improving the stability of the sidewall structures 19, thereby improving the stability of the threshold voltage of the semiconductor device. In other embodiments, the sidewall structures 19 are, for example, other stacked structures.

[0056] Please see Figures 6 to 7 As shown, in one embodiment of the present invention, after forming the sidewall structure 19, the substrate 10 on the side of the sidewall structure 19 away from the gate structure 161 is etched to form a sigma trench 20. Specifically, a U-shaped pre-trench (not shown in the figure) is formed in the substrate 10 on both sides of the gate structure 161 by dry etching, and then the pre-trench is widened by wet etching to form the sigma trench 20. The etching gas used in the dry etching is, for example, at least one of carbon tetrafluoride, sulfur hexafluoride, or chlorine, or a mixture of at least one with oxygen, and the wet etching solution is, for example, tetramethylammonium hydroxide (C4H4H2O). 13 In wet etching, solutions such as NO are used to etch different crystal planes of the substrate at different rates, forming sigma trenches 20 of a predetermined shape. By combining dry and wet etching, the etching amounts of both methods are controlled, thereby controlling the depth, shape, and tilt angle of the formed sigma trenches 20. In this embodiment, the sigma trenches 20 are, for example, pentagons with one open side. After etching, the substrate 10 is cleaned to remove etching byproducts and the native oxide layer within the sigma trenches 20, for example, sequentially cleaned with dilute hydrofluoric acid, an ammonium peroxide mixture (APM), and a mixture of hydrochloric acid and hydrogen peroxide (HPM).

[0057] Please see Figures 7 to 8As shown, in one embodiment of the present invention, after forming the sigma trench 20, from the surface of the substrate 10 to the bottom of the sigma trench 20, there are sequentially an upper slicing surface 301, a lower slicing surface 302, and a bottom surface 303. The upper slicing surface 301 and the lower slicing surface 302 are connected by an interface 304. The upper slicing surface 301 and the lower slicing surface 302 correspond to the first crystal plane of the substrate material, the bottom surface 303 corresponds to the second crystal plane of the substrate material, and the interface 304 corresponds to the third crystal plane of the substrate material. Then, a buffer layer 21 is deposited at the bottom and sidewalls of the sigma trench 20. Because the deposition rate of the buffer layer 21 on different crystal planes is different, an opening 201 is formed in the middle of the buffer layer 21. The opening 201 is, for example, V-shaped. The buffer layer 21 is a boron-doped silicon-germanium layer, and the boron doping concentration in the buffer layer 21 is, for example, 1×10⁻⁶. 20 atoms / cm 3 ~3×10 20 atoms / cm 3 Starting from the interface between the buffer layer 21 and the substrate 10, the germanium content gradually increases towards the surface of the buffer layer 21. For example, the germanium content on the surface of the buffer layer 21 is 20% to 30% to improve lattice mismatch. In this embodiment, the buffer layer 21 is formed, for example, by selective epitaxial growth. The pressure in the deposition chamber is, for example, 10 Torr to 25 Torr. The epitaxial growth gas source includes, for example, a mixture of dichlorosilane (SiH2Cl2), hydrogen chloride (HCl), germanium hydride (GeH4), and diborane (B2H6), and the epitaxial growth temperature is, for example, 650°C to 680°C. Furthermore, during the deposition process, the germanium hydride content is gradually increased to obtain a buffer layer 21 with a germanium gradient content. In this embodiment, the thickness of the buffer layer 21 on the lower cut surface 302 is defined as the thickness of the buffer layer 21 on the first crystal plane, specifically the distance from the lower cut surface 302 to the outline tangent of the buffer layer 21, which is parallel to the lower cut surface 302, denoted as d1; the thickness of the buffer layer 21 on the interface 304 is defined as the thickness of the buffer layer 21 on the third crystal plane, specifically the distance from the interface 304 to the outline tangent of the buffer layer 21, which is parallel to the interface 304, denoted as d2; the thickness of the buffer layer 21 on the bottom surface 303 is defined as the thickness of the buffer layer 21 on the second crystal plane, specifically the distance from the bottom surface 303 to the outline tangent of the buffer layer 21, which is parallel to the bottom surface 303, denoted as d3. With a fixed thickness of the buffer layer 21 on the bottom surface 303, in this embodiment, the ratio (d1 / d2) of the thickness of the buffer layer 21 on the lower cut surface 302 to the thickness on the interface 304 is 1:1.3-1.8, thus forming a V-shaped opening 201. Therefore, after depositing the buffer layer 21, a V-shaped opening 201 is formed. If a seed layer is directly deposited, it will result in insufficient stress effect.

[0058] Please see Figures 8 to 9As shown, in one embodiment of the present invention, after forming the buffer layer 21, a self-aligned barrier layer 22 is formed on the buffer layer 21, wherein the self-aligned barrier layer 22 is, for example, an intrinsic silicon layer. In this embodiment, the self-aligned barrier layer 22 is formed, for example, by selective epitaxial growth, wherein the pressure in the deposition chamber is, for example, 10 Torr to 25 Torr, the epitaxial growth gas source includes, for example, a mixture of dichlorosilane and hydrogen chloride, and the epitaxial growth temperature is, for example, 650°C to 680°C. During deposition, hydrogen chloride can suppress the growth of intrinsic silicon on the first and third crystal planes, that is, suppress the growth of intrinsic silicon on the upper tangent 301, the lower tangent 302, and the interface 304, achieving the purpose that intrinsic silicon grows only on the bottom surface 303 of the buffer layer 21, and the formed intrinsic silicon is the second crystal plane. In this embodiment, the thickness of the self-aligned barrier layer 22 on the buffer layer 21 at the bottom of the opening 201 is, for example, 2 nm to 5 nm.

[0059] Please see Figures 9 to 11 As shown, in one embodiment of the present invention, after forming the self-aligned barrier layer 22, a portion of the self-aligned barrier layer 22 and the buffer layer 21 are removed, for example, by dry etching, to form a groove 202, which is, for example, U-shaped. The dry etching gas is, for example, hydrogen chloride gas, and the etching operating temperature is, for example, 730°C to 780°C, the etching pressure is, for example, 10 Torr to 100 Torr, and the flow rate of the hydrogen chloride gas is, for example, 50 sccm to 100 sccm. Figure 11As shown, in one embodiment of the present invention, the etching conditions are controlled such that the etching rate of intrinsic silicon is less than that of silicon-germanium, and the etching rates of the self-aligned barrier layer or buffer layer on each crystal plane are different. The etching rates of each crystal plane in the self-aligned barrier layer or buffer layer satisfy the condition: second crystal plane > third crystal plane > first crystal plane. That is, in the buffer layer, the etching rate of the second crystal plane is greater than that of the third crystal plane, the etching rate of the third crystal plane is greater than that of the first crystal plane, and the etching rate of the first crystal plane in the buffer layer is greater than that of the second crystal plane in the self-aligned barrier layer. Specifically, the etching rate of the buffer layer 21 on the bottom surface 303 is greater than that of the buffer layer 21 on the interface 304, the etching rate of the buffer layer 21 on the interface 304 is greater than that of the buffer layers 21 on the upper and lower tangent surfaces 301 and 302, and the etching rate of the buffer layers 21 on the upper and lower tangent surfaces 301 and 302 is greater than that of the self-aligned barrier layer 22. Therefore, utilizing the lattice stability of the self-aligned barrier layer 22 relative to the buffer layer, it serves as a hard mask barrier layer to mitigate etching along the second crystal plane. Thus, after etching, the thickness ratio of the buffer layer 21 on the lower cut surface 302 to the thickness on the interface 304 is 1:2-4, forming a U-shaped groove 202. The remaining portion at the bottom of the groove 202 is a self-aligned barrier layer 22, which is an intrinsic silicon layer with high resistance, effectively improving bulk leakage in semiconductor devices. By forming the intrinsic silicon self-aligned barrier layer 22, etching can transform the V-shaped opening 201 after depositing the buffer layer 21 into a U-shaped groove 202, providing sufficient space for seed layer deposition and improving stress on the channel region.

[0060] Please see Figure 10 and Figure 12 As shown, in one embodiment of the present invention, after forming the groove 202, a seed layer 23 is deposited in the U-shaped groove 202. The seed layer 23 is a boron-doped silicon-germanium layer, and the boron doping concentration in the seed layer 23 is, for example, 1×10⁻⁶. 20 atoms / cm 3 ~3×10 20 atoms / cm 3The germanium content in the seed layer 23 is greater than that in the buffer layer 21. In the seed layer 23, the germanium content is, for example, 30% to 50%, to generate mechanical stress on the channel, altering the electronic band structure of the silicon atomic lattice and thereby improving the electron mobility in the channel region. In this embodiment, the seed layer 23 is formed, for example, by selective epitaxial growth, wherein the pressure in the deposition chamber is, for example, 10 Torr to 25 Torr, the epitaxial growth gas source includes, for example, a mixture of dichlorosilane, hydrogen chloride, germanium hydride, and diborane, and the epitaxial growth temperature is, for example, 650°C to 680°C. By controlling the germanium hydride content, the germanium content in the seed layer 23 is increased to enhance the stress on the channel region, thereby improving the electron mobility in the channel region.

[0061] Please see Figure 12 As shown, in one embodiment of the present invention, after forming the seed layer 23, a cap layer 24 is formed on the seed layer 23. The cap layer 24 is, for example, a boron-doped silicon layer, and the boron doping concentration in the cap layer 24 is, for example, 8 × 10⁻⁶. 20 atoms / cm 3 ~3×10 21 atoms / cm 3 In this embodiment, the cap layer 24 is grown using selective epitaxial growth, for example, in the same reaction chamber as the seed layer 23. By changing the epitaxial growth gas source, a boron-doped cap layer 24 is formed. The buffer layer 21, the self-aligned barrier layer 22, the seed layer 23, and the cap layer 24 are defined as stress structures to improve the carrier mobility of the semiconductor device, while also serving as the source and drain of the semiconductor device.

[0062] In summary, this invention provides a method for fabricating a semiconductor device and the semiconductor device itself. Through improvements to the semiconductor device fabrication method, the unexpected technical effect of this application is that by depositing a self-aligned barrier layer and etching part of the self-aligned barrier layer and the seed layer, the growth space of the high-stress seed layer is effectively expanded. This maximizes the stress effect of the seed layer while satisfying the requirements for buffering and blocking leakage current, thereby increasing channel mobility and improving semiconductor device performance. It can also improve lattice mismatch problems, and the self-aligned barrier layer can effectively improve the main leakage current problem of the semiconductor device, thus enhancing the electrical performance of the semiconductor device.

[0063] The above description of the embodiments shown in this invention (including the content set forth in the abstract of the specification) is not intended to be an exhaustive enumeration or to limit the invention to the precise forms disclosed herein. Although specific embodiments and examples of the invention have been described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the invention, as will be recognized and understood by those skilled in the art. As indicated, these modifications can be made to the invention in accordance with the above description of the embodiments described herein, and such modifications will be within the spirit and scope of the invention.

[0064] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to the technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application. Except for the technical features described in the specification, the remaining technical features are known to those skilled in the art. To highlight the innovative features of this invention, the remaining technical features will not be described in detail here.

Claims

1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A substrate is provided on which a gate structure is formed; The substrates on both sides of the gate structure are etched to form sigma trenches; From the surface of the substrate to the bottom of the sigma trench, the sides of the sigma trench are sequentially an upper scissor, a lower scissor, and a bottom surface, and the upper scissor and the lower scissor are connected by an interface; A buffer layer is formed on the bottom and sidewalls of the sigma trench; A self-aligned barrier layer is formed on a portion of the buffer layer; the self-aligned barrier layer is an intrinsic silicon layer and is formed by selective epitaxial growth, and the self-aligned barrier layer is grown on the bottom surface of the buffer layer. Etching portions of the buffer layer and the self-aligned barrier layer to form grooves; and A seed crystal layer is formed within the groove.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The buffer layer is a boron-doped silicon-germanium layer. The germanium content increases from the interface between the buffer layer and the substrate, and the germanium content on the surface of the buffer layer is 20% to 30%.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, After the buffer layer is deposited, the ratio of the thickness of the buffer layer on the lower cut surface to the thickness on the interface is 1:1.3-1.8; After the groove is formed, the ratio of the thickness of the buffer layer on the lower cut surface to the thickness on the interface is 1:2-4.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, When forming the self-aligned barrier layer, the epitaxial growth gas source includes a mixture of dichlorosilane and hydrogen chloride, and the epitaxial growth temperature is 650°C to 680°C.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The buffer layer and the self-aligned barrier layer are etched by dry etching, and the etching gas includes hydrogen chloride gas.

6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The dry etching process operates at a temperature of 730°C to 780°C, and the flow rate of hydrogen chloride gas is 50 sccm to 100 sccm.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, During the dry etching process, the etching rate of the buffer layer on the interface is greater than the etching rate of the buffer layer on the upper and lower cut surfaces, and the etching rate of the buffer layer on the upper and lower cut surfaces is greater than the etching rate of the self-aligned barrier layer.

8. A semiconductor device, characterized in that, include: A substrate on which a gate structure is disposed; A sigma trench is disposed in the substrate on both sides of the gate structure; from the surface of the substrate to the bottom of the sigma trench, the sides of the sigma trench are sequentially an upper scissor, a lower scissor, and a bottom surface, and the upper scissor and the lower scissor are connected by an interface; A buffer layer is provided on the bottom and sidewalls of the sigma trench; A self-aligned barrier layer is disposed on the buffer layer at the bottom of the sigma trench; the self-aligned barrier layer is an intrinsic silicon layer and is obtained by selective epitaxial growth, and the self-aligned barrier layer is disposed on the bottom surface of the buffer layer; and A seed layer is disposed on the buffer layer and the self-aligned barrier layer.

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