Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate and an epitaxial layer of the substrate, the epitaxial layer has a first surface; a plurality of first implantation regions are spaced apart in the epitaxial layer along a first direction, the first implantation region is a region formed by ion implantation on part of the first surface, the epitaxial layer between adjacent first implantation regions is set as a first region, the epitaxial layer on a side of the first region away from the first surface is a first sub-epitaxial layer, the first region and the first sub-epitaxial layer are in contact, and the first implantation region has a second doping type; at least one second implantation region is located in the first sub-epitaxial layer, a projection of the second implantation region on the first surface at least partially overlaps a projection of the first region on the first surface, and the second implantation region has the second doping type; an anode metal layer covers the first surface; and a cathode metal layer covers a second surface of the substrate away from the first surface, thereby solving the problem that the switching speed and the surge resistance of the semiconductor device cannot be considered simultaneously.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to a semiconductor device and a preparation method thereof. BACKGROUND

[0002] A Schottky barrier diode (SBD) is a diode formed by a metal-semiconductor junction generated between a metal layer and a doped semiconductor layer, which has two more excellent characteristics than a traditional PiN diode. A Schottky barrier diode made of silicon carbide (SiC) can withstand a bias voltage as high as 3300V, and there are commercial products with a rated voltage from 650V to 1700V and widely used in the field of power electronics. However, in the prior art, the Schottky diode cannot simultaneously improve the anti-surge capability and the switching performance.

[0003] The above information disclosed in the background section is only used to enhance the understanding of the background of the technology described herein, therefore, the background section can include some information which is not known to those skilled in the art in the prior art in the country. SUMMARY

[0004] The main purpose of the present application is to provide a semiconductor device and a preparation method thereof, so as to solve the problem that the switching speed and the anti-surge capability of the semiconductor device cannot be considered simultaneously.

[0005] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a semiconductor device is provided, comprising: a substrate and an epitaxial layer thereof, the epitaxial layer having a first surface, the substrate and the epitaxial layer having a first doping type; a plurality of first implantation regions spaced apart along a first direction in the epitaxial layer, the first implantation regions extending along a second direction, the first implantation regions being regions formed by ion implantation on part of the first surface, the epitaxial layer between adjacent first implantation regions being a first region, the epitaxial layer on a side of the first region away from the first surface being a first sub-epitaxial layer, the first region and the first sub-epitaxial layer being in contact with each other, the first direction and the second direction being perpendicular to the thickness direction of the device, and the first direction and the second direction having an included angle, the first implantation regions having a second doping type; at least one second implantation region in the first sub-epitaxial layer, a projection of the second implantation region on the first surface at least partially overlapping a projection of the first region on the first surface, the second implantation region having the second doping type; an anode metal layer covering the first surface; and a cathode metal layer covering a second surface of the substrate away from the first surface.

[0006] Optionally, the second implantation region is in contact with the first implantation region.

[0007] Optionally, the second implantation region is spaced apart from the first region in the thickness direction of the substrate.

[0008] Optionally, the second implantation region comprises at least one first sub-implantation region and at least one second sub-implantation region, the at least one first sub-implantation region is spaced apart from the first implantation region away from the first surface, and the at least one second sub-implantation region is spaced apart from the first sub-implantation region away from the first implantation region.

[0009] Optionally, the first sub-implantation region is in contact with the second sub-implantation region.

[0010] Optionally, the first sub-implantation region is spaced apart from the second sub-implantation region in the thickness direction of the device.

[0011] Optionally, the first sub-implantation region is in contact with the first implantation region.

[0012] Optionally, the first sub-implantation region is spaced apart from the first region in the thickness direction of the device.

[0013] Optionally, the anode metal layer further comprises a plurality of first ohmic contact layers, each of the plurality of first ohmic contact layers is located on the first surface of the first implantation region, and the anode metal layer covers the first ohmic contact layers and the first surface not provided with the first ohmic contact layers.

[0014] According to another aspect of the present application, a preparation method of a semiconductor device is provided for preparing the semiconductor device, the preparation method comprising: providing a substrate and a first sub-epitaxial layer, the substrate and the first sub-epitaxial layer having a first doping type; forming at least one second implantation region in the first sub-epitaxial layer and forming a second sub-epitaxial layer having the first doping type on the second implantation region, the first sub-epitaxial layer and the second sub-epitaxial layer constituting an epitaxial layer, a side of the epitaxial layer away from the substrate having a first surface, and the second implantation region having a second doping type; forming a plurality of spaced-apart first implantation regions in the second sub-epitaxial layer along a first direction, the epitaxial layer between adjacent first implantation regions being a first region, part of the first region being located on a side of the second implantation region close to the first surface, and the plurality of first implantation regions extending along a second direction, the first direction and the second direction having an included angle, and the first implantation regions having the second doping type; forming an anode metal layer on the first surface, and forming a cathode metal layer on a side of the substrate away from the epitaxial layer.

[0015] By means of the technical scheme of the present application, at least one second injection region is arranged in the first sub-epitaxial layer of the semiconductor device, thus increasing the area of the injection region with the second doping type, and the breakdown voltage of the device can be improved, and the surge resistance of the device is further improved. Meanwhile, the first region of the epitaxial layer with the first doping type is arranged above the second injection region, and the first region can guide the current flowing out of the Schottky contact region in the forward conduction state, so that the current bypasses the second injection region and flows from the first sub-epitaxial layer and the substrate to the cathode metal layer, and the area of the region for the forward conduction current of the device is ensured, so that the forward conduction voltage drop of the semiconductor device is not affected and remains in the original state, or in some cases, the forward conduction voltage drop can be reduced, and thus the switching speed of the semiconductor device is greater than or equal to the original state, and the problem that the switching speed and the surge resistance of the semiconductor device cannot be considered together is solved. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings, which form a part of the present description, are included to provide a further understanding of the present application, and are incorporated herein for purposes of explaining the present application. The drawings illustrate preferred embodiments of the present application and, together with their description, serve to explain the present application. In the drawings:

[0017] Figure 1 A top view of a semiconductor device according to the present application is shown;

[0018] Figure 2 A cross-sectional structure of the semiconductor device in the first cross-section at two different positions in the semiconductor device is shown; Figure 1

[0019] A cross-sectional structure of the semiconductor device in the second cross-section at two different positions in the semiconductor device is shown; Figure 3 Figure 1 A cross-sectional structure of the semiconductor device in the third cross-section at two different positions in the semiconductor device is shown;

[0020] Figure 4 A cross-sectional structure of the semiconductor device in the fourth cross-section at two different positions in the semiconductor device is shown;

[0021] Figure 5 Figure 1 A cross-sectional structure of the semiconductor device in the fifth cross-section at two different positions in the semiconductor device is shown;

[0022] Figure 6 A cross-sectional structure of the semiconductor device in the sixth cross-section at two different positions in the semiconductor device is shown; Figure 1

[0023] A cross-sectional structure of the semiconductor device in the seventh cross-section at two different positions in the semiconductor device is shown; Figure 7 Figure 1 A cross-sectional structure of the semiconductor device in the eighth cross-section at two different positions in the semiconductor device is shown;​​​

[0024] Figure 8 A cross-sectional structure diagram of a semiconductor device according to the present application is shown;

[0025] Figure 9 A cross-sectional structure diagram of another semiconductor device according to the present application is shown;

[0026] Figure 10 A flow diagram of a method for manufacturing a semiconductor device according to the present application is shown;

[0027] Figure 11 A cross-sectional structure diagram of a substrate after providing a substrate and forming a second implantation region in the substrate in a method for manufacturing a semiconductor device according to the present application is shown;

[0028] Figure 12 A cross-sectional structure diagram of a substrate after forming an epitaxial layer on the second implantation region formed in Figure 11

[0029] Figure 13 A cross-sectional structure diagram of a substrate after forming a first implantation region in the epitaxial layer formed in Figure 12

[0030] Figure 14 A top view structure diagram of a semiconductor device according to the present application is shown.

[0031] Wherein, the above figures include the following reference signs:

[0032] 1, cell structure; 111, first region; 11, substrate; 12, epitaxial layer; 121, first sub-epitaxial layer; 122, second sub-epitaxial layer; 20, first implantation region; 30, second implantation region; 31, first sub-implantation region; 32, second sub-implantation region; 40, Schottky metal layer; 50, second ohmic contact layer; 60, first ohmic contact layer; 70, first buffer metal layer; 80, second buffer metal layer. DETAILED DESCRIPTION

[0033] It should be noted that the following detailed description is exemplary in nature and is intended to provide further description of the application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0034] ​​It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0035] It should be noted that the terms "first", "second", and the like, as used in the specification and in the claims, are intended to modify a respective subject which precedes these terms, and are used merely to distinguish at least one such subject from another. It is, therefore, to be understood that such terms as "first", "second", and the like, can be understood as encompassing a plurality of subjects, unless otherwise expressly subject to an understood limitation to a single subject. Further, the use of the terms "including", "comprising", and "having" as well as any variations thereof, are intended to cover a non-exclusive inclusion, such that any process, method, system, product, or device that includes, or comprises, an item or list of items, without explicitly listing each item or member of the item or list, is still within the scope of those terms as used in the specification and in the claims.

[0036] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements can also be present. In addition, it will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element, or intervening elements can also be present.

[0037] As introduced in the background, the Schottky diode in the prior art will affect its switching performance in the case of improving the surge resistance, and the two cannot be considered, in order to solve the problem that the switching speed and the surge resistance of the semiconductor device cannot be considered, the embodiment of the application provides a semiconductor device and a preparation method.

[0038] The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings in the embodiments of the application.

[0039] According to the embodiments of the application, a semiconductor device is provided, such as Figures 1 to 4As shown, the semiconductor device comprises: a substrate 11 and an epitaxial layer 12, the epitaxial layer 12 has a first surface, the substrate 11 and the epitaxial layer 12 have a first doping type; a plurality of first implantation regions 20 are spaced apart in the epitaxial layer 12 along a first direction X, the first implantation regions 20 extend along a second direction Y, the first implantation regions 20 are formed by ion implantation on part of the first surface, the epitaxial layer 12 between adjacent first implantation regions 20 is set as a first region 111, the epitaxial layer 12 on a side of the first region 111 away from the first surface is set as a first sub-epitaxial layer 121, the first region 111 and the first sub-epitaxial layer 121 are in contact with each other in a vertical direction, the first direction X and the second direction Y are both perpendicular to a thickness direction of the device, and the first direction X and the second direction Y have an included angle, the first implantation regions 20 have a second doping type; at least one second implantation region 30 is located in the first sub-epitaxial layer 121, a projection of the second implantation region 30 on the first surface at least partially overlaps a projection of the first region 111 on the first surface, the second implantation region 30 has the second doping type; an anode metal layer comprises a Schottky metal layer 40 covering the first surface, the Schottky metal layer 40 and a contact part of the first implantation region 20 and the first region 111 form a Schottky contact region of the device; a cathode metal layer comprises a second ohmic contact layer 50 covering a second surface of the substrate 11 away from the first surface, a contact part of the second ohmic contact layer 50 and the substrate 11 forms an ohmic contact region of the device.

[0040] The embodiment increases the area of the implantation region with the second doping type by arranging at least one second implantation region in the first sub-epitaxial layer of the semiconductor device, thereby improving the breakdown voltage of the device and further improving the surge resistance of the device. Moreover, the first region of the epitaxial layer with the first doping type is arranged above the second implantation region, the first region can guide the current flowing out of the Schottky contact region in the forward conduction state, so that the current bypasses the second implantation region and flows from the first sub-epitaxial layer and the substrate to the cathode metal layer, thereby ensuring the area of the region of the forward conduction current of the device, which can maintain the original state of the forward conduction voltage drop of the semiconductor device or reduce the forward conduction voltage drop, thereby making the switching speed of the semiconductor device greater than or equal to the original state, and solving the problem that the switching speed and the surge resistance of the semiconductor device cannot be considered simultaneously.

[0041] In the above embodiment, the material of the substrate can be silicon carbide, so that the device has high thermal conductivity and high breakdown field strength, and is suitable for manufacturing high-performance devices that can work in high-temperature and high-pressure environments. For example, Figures 2 to 7As shown, the doping concentration of the substrate 11 is higher than that of the epitaxial layer 12, and the high doping concentration of the substrate 11 can increase the depth of the depletion layer, thereby improving the reverse breakdown voltage, reducing the risk of device breakdown, and the substrate 11 can also absorb carriers from the epitaxial layer 12, further reducing the on-resistance. The lower doping concentration of the epitaxial layer 12 can provide greater carrier mobility when the device is turned on, thereby reducing the on-resistance.

[0042] In the above embodiment, the first doping type can be N-type doping or P-type doping, and the second doping type can be P-type doping or N-type doping, for example, the first doping type is N-type doping and the second doping type is P-type doping, or the first doping type is P-type doping and the second doping type is N-type doping.

[0043] In the above embodiment, the material of the Schottky metal layer can be any one of Au, Ag, Al, and Mo.

[0044] In the above embodiment, there is a certain distance between the second implantation region and the first surface, which should be greater than twice the width of the depletion layer generated by the corresponding concentration of the second implantation region. This distance can allow the device to still pass current through the Schottky contact area in the forward conduction state, and the semiconductor structure has a larger current-carrying area and lower forward conduction voltage drop under the same chip size.

[0045] As shown in Figure 2 , wherein Figure 2 (a) is Figure 1 a cross-sectional view in the A-A' direction in Figure 2 (b) is Figure 1 a cross-sectional view in the B-B' direction in In some alternative embodiments, the second implantation region 30 and the first region 111 are spaced apart in the thickness direction of the device. Figure 2 The second implantation region 30 and the first region 111 in the device do not contact, and the device can better guide the current flowing out of the Schottky contact area to the first region 111 in the forward conduction state, so that the current can flow through a shorter path around the second implantation region 30 to the cathode metal layer, ensuring the area of the device forward conduction current, and not affecting the forward conduction voltage drop of the device. On the basis of maintaining the original state of the device forward conduction voltage drop, the introduction of the second implantation region 30 also increases the area of the second implantation region with the second doping type, which can improve the breakdown voltage of the device and thereby improve the surge resistance of the device.

[0046] As shown in Figure 3 , wherein Figure 3 (a) is Figure 1 a cross-sectional view in the A-A' direction in Figure 3 (b) is Figure 1The cross-sectional view in the direction of B-B'. In some alternative embodiments, the second implantation region 30 contacts the first implantation region 20, and the projection of the second implantation region 30 on the first surface can have the same or different shape and also have the same or different size. The contact between the second implantation region 30 and the first implantation region 20 can make the second implantation region 30 and the first implantation region 20 both connect with the electrode of the device, and after the second implantation region 30 and the first implantation region 20 are electrified, the holes in the second implantation region 30 and the first implantation region 20 will be injected into the N-type substrate, which will increase the conductivity of the N-type substrate, thereby generating a conductivity modulation effect, which can further reduce the resistance of the device under large current and reduce the generation of heat, reduce the forward conduction voltage drop, and improve the switching speed. And compared with the first region above the second implantation region 30 where there is no epitaxial layer 12, that is, the current-conducting area of the second implantation region 30 also contacts the Schottky metal layer 40, the current-conducting area is larger, and the forward conduction voltage drop can be lower. Therefore, in the case where the second implantation region 30 contacts the first implantation region 20, both the surge resistance of the device and the forward conduction voltage drop can be reduced to improve the switching speed of the device.

[0047] In the above embodiments, as shown in Figure 3 , the different projection sizes can be represented as the width of the projection of the second implantation region 30 on the first surface in the first direction X being greater than the width of the projection of the first implantation region 20 on the first surface in the first direction X, and can also be represented as the width or length of the projection of the second implantation region 30 on the first surface being greater than or less than the width or length of the projection of the first implantation region 20 on the first surface. Alternatively, the projection sizes of the first implantation region 20 and the second implantation region 30 are the same, but the projections of the first implantation region 20 and the second implantation region 30 do not overlap. The shape of the projection can be any one or more of a polygon, a circle, and an ellipse, which is not specifically limited in the present application.

[0048] As shown in Figure 4 , the distribution of the second implantation region 30 can also be Figure 4 As shown in (a), the number of the second implantation region 30 is the same as the number of the first implantation region 20, and the second implantation region 30 contacts the first implantation region 20 one by one. The distribution of the second implantation region 30 can also be Figure 4 As shown in (b), the second implantation region 30 is small in size and is located on the side of the epitaxial layer 12 (the first region) between the two adjacent first implantation regions 20 away from the Schottky metal layer 40. The distribution of the second implantation region 30 can also be Figure 4 As shown in (c), the second implantation region 30 contacts the two adjacent first implantation regions 20. There can be various combinations of the relative positions between the second implantation region 30 and the first implantation region 20, such as Figure 4The three distribution forms can be arbitrarily combined, as long as there is a partial epitaxial layer 12 (this part is the first region) between the second injection region 30 and the first surface, and the current flowing out from the Schottky region can flow through this partial epitaxial layer 12 into other parts of the epitaxial layer 12 and thus bypass the second injection region 30 to reach the back electrode of the device smoothly. This application does not make a specific limitation. The number of second injection regions 30 and the number of first injection regions 20 can also be different.

[0049] like Figure 5 and Figure 6 As shown, where Figure 5 (a) and Figure 6 (a) is Figure 1 Cross-sectional view along the A-A' direction. Figure 5 (b) and Figure 6 (b) is Figure 1 A cross-sectional view along the B-B' direction. In some optional embodiments, the second injection region 30 includes at least one first sub-injection region 31 and at least one second sub-injection region 32. The at least one first sub-injection region 31 is spaced apart on the side of the first injection region 20 away from the first surface, and the at least one second sub-injection region 32 is spaced apart on the side of the first sub-injection region 31 away from the first injection region 20. The first sub-injection region 31 and the second sub-injection region 32 are disposed in the epitaxial layer 12, further increasing the area of ​​the second doped type injection region. The presence of a portion of the epitaxial layer 12 above the first sub-injection region 31 ensures the area of ​​the device's forward conduction current, thereby improving surge resistance while maintaining the forward conduction voltage drop. Figure 5 and Figure 6 Structural references not mentioned in the text Figures 1 to 4 , without repeating the description.

[0050] To make the device structure more flexible, such as Figure 5 As shown, in some optional embodiments, the first sub-injection region 31 contacts the second sub-injection region 32. For example... Figure 6 As shown, in the thickness direction of the device, the first sub-implantation region 31 and the second sub-implantation region 32 are distributed alternately. The first sub-implantation region 31 and the second sub-implantation region 32 can increase the area of ​​the second doped implantation region, which can improve the breakdown voltage of the device and thus improve the surge resistance of the device. The projections of the first sub-implantation region 31 and the second sub-implantation region 32 on the first surface can have the same or different shapes, and can also have the same or different sizes. The combination method is not specifically limited.

[0051] To simultaneously improve the surge immunity and forward voltage drop of the device, in some alternative implementations, such as Figure 5 and Figure 6As shown, the first sub-injection region 31 is in contact with the first injection region 20. This contact allows both the first sub-injection region 31 and the first injection region 20 to be connected to the device's electrodes. After the first sub-injection region 31 and the first injection region 20 are energized, holes in them are injected into the N-type epitaxial layer 12. These holes increase the conductivity of the N-type epitaxial layer 12, thereby generating a conductivity modulation effect. This effect can further reduce the device's resistance under high current and reduce heat generation, lower the forward voltage drop, and improve the switching speed. Therefore, with the first sub-injection region 31 and the first injection region 20 in contact, both the device's surge protection capability and the forward voltage drop can be reduced, thus improving the device's switching speed. Figure 5 As shown, the first sub-injection region 31, the second sub-injection region 32 and the first injection region 20 all provide holes for the Schottky contact region, which further improves the conductivity of the epitaxial layer 12, can quickly dissipate and conduct current, and further improves the surge resistance.

[0052] like Figure 7 (a) and Figure 7 As shown in (b), in some optional embodiments, the first sub-implantation region 31 and the first region 111 are spaced apart in the thickness direction of the device. The first sub-implantation region 31 and the second sub-implantation region 32 are provided in the first sub-epitaxy layer 121, further increasing the area of ​​the second doped type implantation region. The first region 111 is located above the first sub-implantation region 31, ensuring the area of ​​the device's forward conduction current and improving surge resistance while maintaining the forward conduction voltage drop. Figure 7 Structural references not mentioned in the text Figures 1 to 6 , without repeating the description.

[0053] In the embodiments of this application, Figures 5 to 7 The distributions of the first sub-injection region 31 and the second sub-injection region 32 in the middle can be respectively compared with... Figures 2 to 4 The distribution of the second injection region 30 is the same, and the relative positions between the first sub-injection region 31 and the second sub-injection region 32 can be arbitrarily combined. This application does not make specific limitations.

[0054] In some alternative implementations, with Figure 3 Taking the structure of (a) as an example, such as Figure 8As shown, the anode metal layer of the semiconductor device further comprises a plurality of first ohmic contact layers 60, which are located on the first surface of the first implanted region 20 one by one, and the Schottky metal layer 40 covers the first ohmic contact layers 60 and the first surface where no first ohmic contact layer 60 is arranged. The Schottky contact and the ohmic contact are integrated in the front surface of the device, and on the basis of the Schottky contact, the ohmic contact further improves the ohmic contact performance of the device and further enhances the surge current bearing capacity thereof. The material of the first ohmic contact layer 60 can be any one or more of Ni, Cu, Ag, Mo, Ta and Au, which is not limited in the present application. Figure 8 Structural references not mentioned in the Figures 1 to 6 are not repeated.

[0055] In some optional embodiments, as Figure 9 As shown, the anode metal layer of the semiconductor device further comprises a first buffer metal layer 70, and the cathode metal layer further comprises a second buffer metal layer 80, wherein the second ohmic contact layer 50 is located on the side of the substrate 11 away from the first implanted region 20; the first buffer metal layer 70 covers the Schottky metal layer 40; and the second buffer metal layer 80 covers the second ohmic contact layer 50. The first buffer metal layer 70 and the second buffer metal layer 80 can reduce the contact resistance and buffer the contact stress. The second ohmic contact layer 50 is in ohmic contact with the substrate 11 on the back surface of the device, receives the current flowing out of the Schottky metal layer 40, and completes the forward conduction of the device. The material of the second ohmic contact layer 50 can be any one or more of Ni, Cu, Ag, Mo, Ta and Au, which is not limited in the present application. The first buffer metal layer 70 and the second buffer metal layer 80 can be a multilayer film, and the material of the first buffer metal layer 70 and the second buffer metal layer 80 can independently comprise at least one of Ti, Al, Cu and Ag. Figure 9 Structural references not mentioned in the Figures 1 to 8 are not repeated.

[0056] According to the embodiments of the present application, a preparation method of a semiconductor device is also provided, Figure 10 is a flowchart of the preparation method of the semiconductor device according to the embodiments of the present application. As Figure 10 shown, the method comprises the following steps:

[0057] Step S1, as Figure 11 shown, a substrate 11 and a first sub-epitaxial layer 121 are provided, and the substrate and the first sub-epitaxial layer 121 have a first doping type;

[0058] Specifically, the material of the substrate 11 and the first sub-epitaxial layer 121 can be N-type silicon carbide. The substrate 11 and the first sub-epitaxial layer 121 can be prepared by epitaxial growth.

[0059] Step S2, as shown in Figure 11 and Figure 12 At least one second implantation region 30 is formed in the first sub-epitaxial layer 121, and a second sub-epitaxial layer 122 with a first doping type is formed on the second implantation region 30, the first sub-epitaxial layer 121 and the second sub-epitaxial layer 122 constitute the epitaxial layer 12, the epitaxial layer 12 has a first surface away from the substrate 11, and the second implantation region 30 has a second doping type;

[0060] Specifically, as shown in Figure 11 and Figure 12 The second implantation region 30 can be a P-type implantation region. A hard mask is deposited on the first sub-epitaxial layer 121, and a hollow pattern is obtained by performing a photolithography process on the hard mask. The second implantation region 30 is formed by ion implantation into the first sub-epitaxial layer 121 corresponding to the hollow pattern. The epitaxial layer is prepared by epitaxial growth on the first sub-epitaxial layer 121, and the epitaxial layer is the second sub-epitaxial layer 122. The second sub-epitaxial layer 122 can ensure that the second implantation region 30 and the first surface have a certain distance, and the first sub-epitaxial layer 121 and the second sub-epitaxial layer 122 constitute a complete epitaxial layer 12.

[0061] Step S3, as shown in Figure 13 A plurality of first implantation regions 20 are formed in the second sub-epitaxial layer along a first direction X, and the epitaxial layer between adjacent first implantation regions 20 is a first region 111. Part of the first region 111 is located on the side of the second implantation region 30 close to the first surface. The plurality of first implantation regions extend along a second direction Y, and the first direction X and the second direction Y have an included angle. The first implantation region 20 has a second doping type.

[0062] Specifically, the first implantation region can be a P-type implantation region. A hard mask is deposited on the second sub-epitaxial layer 122, and a hollow pattern is obtained by performing a photolithography process on the hard mask. The first implantation region 20 is formed by ion implantation into the second sub-epitaxial layer 122 corresponding to the hollow pattern. Annealing treatment is performed on the implantation region to activate the doping ions.

[0063] The projection pattern of the first implantation region and the second implantation region on the first surface can be any one or more of a polygon, a circle, and an ellipse.

[0064] Step S4, as shown in Figure 8 A Schottky metal layer 40 is formed on the first surface, and a second ohmic contact layer 50 is formed on the side of the substrate 11 away from the epitaxial layer 12.

[0065] Specifically, as shown in Figure 8As shown, a first contact metal material can be deposited on the first surface using a deposition process to form a preliminary first ohmic contact layer. The preliminary first ohmic contact layer is then etched to obtain multiple first ohmic contact layers 60. A Schottky metal material is then deposited on the first ohmic contact layer 60 to form a Schottky metal layer 40.

[0066] The semiconductor device prepared by the above method has at least one second implantation region, which increases the area of ​​the implantation region with the second doping type, thereby improving the breakdown voltage of the device and thus improving its surge resistance. Furthermore, above the second implantation region is a first region of an epitaxial layer with the first doping type. In the forward conduction state, the first region can guide the current flowing from the Schottky contact region, allowing the current to flow from the first sub-epitaxial layer around the second implantation region to the cathode metal layer. This ensures the area of ​​the forward conduction current region, allowing the forward conduction voltage drop of the semiconductor device to remain unaffected and maintain its original state, or to reduce the forward conduction voltage drop. This results in the switching speed of the semiconductor device being greater than or equal to the original state, solving the problem of the inability to simultaneously achieve high switching speed and surge resistance in semiconductor devices.

[0067] like Figure 9 As shown, a second contact metal material is deposited on the back side of the substrate 11 to form a second ohmic contact layer 50, and a buffer metal material is deposited on the Schottky metal layer 40 and the second ohmic contact layer 50 to form a first buffer metal layer 70 and a second buffer metal layer 80, respectively.

[0068] This application also provides a semiconductor device, which may include one or more such semiconductor devices. Figure 1 The cell structure 1 shown is as follows: Figure 14 As shown, the layout of the semiconductor device of this application may include multiple cell structures 1, and the second implantation regions 30 are distributed in an array on the orthographic projection of the first surface. The array distribution is not limited to the form shown in the diagram. Figure 14 The form shown can also be an N×M square matrix, where N is the number of rows and M is the number of columns. N and M can be the same or different, as long as the second injection region 30 is uniformly distributed in the substrate. A uniformly distributed second injection region 30 ensures a uniform current distribution when the device is conducting current, making the device more stable and reliable.

[0069] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0070] The semiconductor device and its fabrication method proposed in this application have the following technical advantages:

[0071] 1) The second implant region is arranged in the semiconductor device, which increases the area of the second implant region with the second doping type, and improves the breakdown voltage of the device, and further improves the surge resistance of the device. The first region of the first doping type is further arranged above the second implant region. In the forward conduction state, the first region can guide the current flowing from the Schottky contact region, so that the current bypasses the second implant region from the first sub-epitaxial layer to the cathode metal layer. The area of the device in the forward conduction state is ensured, which can maintain the original state of the forward conduction voltage drop of the semiconductor device, or can reduce the forward conduction voltage drop, and further make the switching speed of the semiconductor device greater than or equal to the original state, which solves the problem that the switching speed and the surge resistance of the semiconductor device cannot be considered.

[0072] 2) The second implant region and the first implant region in the semiconductor device are in contact with the anode metal layer. After the second implant region and the first implant region are energized, the holes in the second implant region and the first implant region are injected into the N-type epitaxial layer, which increases the conductivity of the N-type epitaxial layer, thereby producing a conductivity modulation effect. This effect can further reduce the resistance of the device under large current and reduce heat generation, reduce the forward conduction voltage drop, and improve the switching speed. Compared with the first region without the substrate above the second implant region, i.e., the second implant region also contacts the anode metal layer, the current-carrying area is larger, and the forward conduction voltage drop is also lower. Therefore, in the case that the second implant region and the first implant region are in contact, the surge resistance of the device can be improved, and the forward conduction voltage drop can be reduced to improve the switching speed of the device.

[0073] The above is only a preferred embodiment of the present application and is not intended to limit the present application. Those skilled in the art can make various modifications and changes to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a substrate and an epitaxial layer of the substrate, the epitaxial layer having a first surface, the substrate and the epitaxial layer having a first doping type; a plurality of first implantation regions spaced apart in a first direction in the epitaxial layer, the first implantation regions extending in a second direction, the first implantation regions being regions formed by ion implantation on part of the first surface, the epitaxial layer between adjacent first implantation regions being a first region, the epitaxial layer on a side of the first region facing away from the first surface being a first sub-epitaxial layer, the first region being in contact with the first sub-epitaxial layer above and below, the first direction and the second direction being perpendicular to a thickness direction of the device, and the first direction and the second direction having an included angle, the first implantation regions having a second doping type; a plurality of second implantation regions arranged in the first sub-epitaxial layer in the first direction and the second direction, the second implantation regions being staggered between adjacent rows in the first direction, the rows being in the first direction, projections of the second implantation regions on the first surface at least partially overlapping projections of the first region on the first surface, the second implantation regions having the second doping type, and a projection of each of the second implantation regions on the first surface partially overlapping projections of two of the first implantation regions on the first surface; an anode metal layer covering the first surface; a cathode metal layer covering a second surface of the substrate facing away from the first surface.

2. The semiconductor device according to claim 1, wherein The second implantation regions are in contact with the first implantation regions.

3. The semiconductor device of claim 1, wherein In the thickness direction of the device, the second implantation regions are spaced apart from the first region.

4. The semiconductor device of claim 1, wherein The second implantation regions comprise at least one first sub-implantation region and at least one second sub-implantation region, the at least one first sub-implantation region being spaced apart on a side of the first implantation region facing away from the first surface, and the at least one second sub-implantation region being spaced apart on a side of the first sub-implantation region facing away from the first implantation region.

5. The semiconductor device according to claim 4, wherein The first sub-implantation regions are in contact with the second sub-implantation regions.

6. The semiconductor device of claim 4, wherein In the thickness direction of the device, the first sub-implantation regions are spaced apart from the second sub-implantation regions.

7. The semiconductor device of claim 4, wherein The first sub-implantation regions are in contact with the first implantation regions.

8. The semiconductor device of claim 4, wherein, In the thickness direction of the device, the first sub-implantation regions are spaced apart from the first region.

9. The semiconductor device of claim 1, wherein, The anode metal layer further comprises a plurality of first ohmic contact layers, each of the plurality of first ohmic contact layers being located on the first surface of a corresponding one of the first implantation regions, the anode metal layer covering the first ohmic contact layers and the first surface not provided with the first ohmic contact layers.

10. A method of manufacturing a semiconductor device, characterized by, A method for manufacturing the semiconductor device of any one of claims 1 to 9, the method comprising: providing a substrate and a first sub-epitaxial layer, the substrate and the first sub-epitaxial layer having a first doping type; forming a plurality of arrayed second implant regions in the first sub-epitaxial layer, and forming a second sub-epitaxial layer with the first doping type on the second implant regions, the first sub-epitaxial layer and the second sub-epitaxial layer constituting an epitaxial layer, the epitaxial layer having a first surface on a side away from the substrate, the second implant regions having a second doping type and being staggered between the second implant regions in adjacent rows, the rows being in the first direction, a projection of each of the second implant regions on the first surface partially overlapping projections of two of the first implant regions on the first surface; forming a plurality of spaced first implant regions in the second sub-epitaxial layer along a first direction, the epitaxial layer between adjacent first implant regions being a first region, part of the first region being on a side of the second implant regions close to the first surface, the first implant regions extending along a second direction, the first direction and the second direction having an included angle, the first implant regions having the second doping type; forming an anode metal layer on the first surface, and forming a cathode metal layer on a side of the substrate away from the epitaxial layer.

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