Semiconductor device and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor device and a manufacturing method thereof, and relates to the technical field of semiconductor. The manufacturing method comprises: forming a gate on a substrate; forming a first doped region in the substrate, the first doped region being located on both sides of the gate; forming a first metal layer on the substrate, the first metal layer being connected with the first doped region; performing a first annealing to form an auxiliary region between the first metal layer and the substrate; forming a second metal layer on the auxiliary region; and performing a second annealing to form a contact region between the second metal layer and the substrate. The material of the substrate comprises silicon, the material of the first metal layer comprises silver, the material of the second metal layer comprises nickel, and the material of the contact region comprises a silver-nickel-silicon compound. During the second annealing, the auxiliary region is used to promote the combination of the second metal layer and the substrate to form the contact region, so as to reduce the annealing temperature for forming the nickel-silicon compound, inhibit the problem of the sharp spike caused by the movement of the nickel element in the silicon, and improve the reliability of the device.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] In integrated circuit processes, nickel silicide (NiSi) is attracting much attention due to its excellent performance, especially in the field of manufacturing advanced metal-oxide-semiconductor field-effect transistors (MOSFETs). Nickel silicide has advantages such as low resistivity, low silicon consumption, low heat budget, and no wire effect, making it one of the ideal silicide materials in high-performance CMOS processes. However, if the formation process of nickel silicide is not properly controlled, not only will it increase the resistance of the silicide, thereby affecting the electrical properties of the device and reducing the sensitivity, but it will also affect the reliability of the device, making the device unable to work normally, thereby reducing the yield.

[0003] Specifically, nickel silicide is not stable at high temperatures, which puts higher requirements on process control and integration. Nickel silicide has different phase compositions as the temperature rises. At low temperatures, the high-resistivity Ni2Si phase is formed first, and as the temperature rises, the low-resistivity NiSi phase that we most want to obtain begins to appear. However, the NiSi phase is not stable at high temperatures and will generate the high-resistivity NiSi2 phase due to agglomeration and phase transition when the temperature is higher than about 700°C. This also limits the maximum temperature of each step in the subsequent back-end process. During high-temperature annealing to form nickel silicide, nickel atoms drill into the deep silicon (mainly the source and drain regions), forming spikes, which increases the contact surface leakage current and greatly affects the performance of the device, and even leads to product failure.

[0004] Therefore, although nickel silicide has become a popular material in advanced integrated circuit processes due to its excellent physical properties, improper control during the manufacturing process can lead to serious performance and reliability problems, thereby affecting the yield and performance of the product. In-depth research and optimization of the nickel silicide process are crucial for improving the performance and reliability of integrated circuits. SUMMARY

[0005] In view of the above problems, a semiconductor device and a manufacturing method thereof are proposed.

[0006] According to an aspect of the present disclosure, a manufacturing method of a semiconductor device is provided, comprising:

[0007] forming a gate on a substrate;

[0008] forming a first doped region in the substrate, the first doped region being located on both sides of the gate;

[0009] forming a first metal layer on the substrate, the first metal layer being connected to the first doped region;

[0010] performing a first anneal to form an auxiliary region between the first metal layer and the substrate;

[0011] forming a second metal layer on the auxiliary region; and

[0012] performing a second anneal to form a contact region between the second metal layer and the substrate,

[0013] wherein the substrate comprises silicon, the first metal layer comprises silver, the second metal layer comprises nickel, and the contact region comprises a silver-nickel-silicon compound.

[0014] during the second anneal, the auxiliary region facilitates bonding of the second metal layer to the substrate to form the contact region.

[0015] Optionally, the second anneal is performed at a temperature less than the first anneal.

[0016] Optionally, the first anneal is performed at a temperature in a range of 300°C to 400°C.

[0017] Optionally, the second anneal is performed at a temperature no less than 400K.

[0018] Optionally, the first anneal and / or the second anneal is a step anneal.

[0019] Optionally, the first metal layer has a thickness in a range of 5 to 15 Angstroms.

[0020] Optionally, prior to forming the second metal layer, the substrate is not pre-processed to facilitate bonding of the second metal layer to the substrate using an ion implantation process.

[0021] Optionally, after forming the contact region, the method further comprises simultaneously removing unreacted first metal layer and second metal layer using a mixture of sulfuric acid and hydrogen peroxide.

[0022] According to another aspect of the disclosure, there is provided a semiconductor device comprising:

[0023] a substrate;

[0024] a gate on the substrate;

[0025] a first doped region in the substrate and on both sides of the gate; and

[0026] a contact region in the first doped region,

[0027] wherein the substrate comprises silicon, and the contact region comprises a silver-nickel-silicon compound.

[0028] Optionally, a second doped region is further included in the substrate and connected with the first doped region,

[0029] The second doped region is located on both sides of the gate and between the first doped region and the gate, and the doping concentration of the second doped region is less than the doping concentration of the first doped region.

[0030] Optionally, a side wall structure is further included and covers at least the sidewall of the gate.

[0031] One of the above technical solutions has the following unexpected technical effects:

[0032] By forming a silver metal layer on the silicon substrate before depositing the nickel metal layer, the silver and silicon are combined to form an Ag-Si bonding interface, i.e., an auxiliary region, through the first annealing, then a nickel metal layer is formed on the auxiliary region, and the second annealing is performed to combine nickel and silicon to form NiSi, wherein during the second annealing, the Ag-Si bonding interface can promote the combination of nickel and silicon, thereby reducing the annealing temperature for forming NiSi, inhibiting the generation of high resistance phase NiSi2, and inhibiting the sharp problem caused by the lateral and longitudinal movement of nickel elements in silicon, thereby improving the reliability of the device.

[0033] Further, the reduction of the annealing temperature is also conducive to strengthening the control of NiSi growth, realizing fine adjustment of the carrier concentration and mobility, and helping to reduce impurities and defects at the interface and improve the interface quality. It can also reduce the thermal stress on the underlying silicon circuit and transistor and reduce the heat accumulation effect.

[0034] In addition, since Ag is the metal with the highest electrical conductivity, the contact region with NiSi also includes Ag, so the present solution can also reduce the on-resistance of the device and improve the response speed of the device.

[0035] In some optional embodiments, since the Ag-Si bonding interface in the auxiliary region has already promoted the combination of nickel and silicon, it is not necessary to use ion implantation process to bombard the substrate to promote the combination of nickel and silicon, thereby reducing the damage to the substrate and preventing the deformation of the device.

[0036] In some optional embodiments, the temperature of the first annealing ranges from 300 to 400℃, and the temperature of the second annealing is less than the temperature of the first annealing, and especially when the Ag-Si bonding interface exists, the temperature of the second annealing needs to reach 400K (127℃), which greatly reduces the annealing temperature, thereby saving the cost.

[0037] In some alternative embodiments, since the temperature required for annealing is low, high-energy consumption rapid thermal annealing (RTA) is not required, only simple rapid thermal processing (RTP) is required, thereby reducing the manufacturing difficulty and further saving the cost. It should be noted that the above general description and the following detailed description are only exemplary and explanatory and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0038] The above and other objects, features and advantages of the present application will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:

[0039] Figures 1 to 3 Cross-sectional views of a method of manufacturing a semiconductor device in the related art are shown at some stages;

[0040] Figures 4 to 8 Cross-sectional views of a method of manufacturing a semiconductor device according to embodiments of the present disclosure are shown at some stages. DETAILED DESCRIPTION

[0041] The present application will be described in more detail by way of example with reference to the accompanying drawings. In the drawings, the same elements are denoted by the same reference numerals to indicate like elements. Each portion in the drawings is not drawn to scale for the sake of clarity. Also, some known portions can not be shown.

[0042] Many specific details of the present disclosure are described below in order to provide a thorough understanding of the present disclosure. As well known to those skilled in the art, however, the present disclosure can be implemented without using these specific details.

[0043] Meanwhile, some words are used in the present patent specification and claims to refer to certain components. It will be appreciated by those of ordinary skill in the art that hardware manufacturers can use different names to refer to the same component. The present patent specification and claims do not use the difference in name as a means to distinguish the components, but rather use the difference in function of the components as a criterion for distinction.

[0044] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0045] This application may be presented in various forms, some of which will be described below.

[0046] Figures 1 to 3 A cross-sectional structural schematic diagram of the semiconductor device formation process in the related technology is shown.

[0047] Prior to the nickel-silicon process, a structure such as... Figure 1 The semiconductor structure shown includes: a silicon substrate 101, a first doped region 111 and a second doped region 112 located in the silicon substrate 101, a gate 120 located on the silicon substrate 101, a first sidewall 131, a second sidewall 132 and a barrier layer 133 surrounding the gate 120, wherein the gate 120 includes a gate dielectric layer 121 and a gate conductor 122 stacked on the silicon substrate 101.

[0048] Next, the silicon nickelation process is performed. First, the silicon substrate 101 is pretreated using an ion implantation process. This step involves, for example, pre-amorphization implantation (PAI) using xenon (Xe) as the implantation species. The purpose of PAI is to improve the agglomeration resistance and physical properties of the final silicide layer. Specifically, since xenon is a heavy ion, when xenon ions are implanted into the silicon wafer, they can cause severe disruption of the silicon lattice, thereby forming amorphous regions. This amorphization treatment facilitates subsequent silicide formation processes and improves device performance.

[0049] Further, a nickel layer 102 is formed covering the silicon substrate 101, such as... Figure 2 As shown. The nickel layer 102 is connected to the first doped region 111 in the silicon substrate 101.

[0050] Further, the nickel and silicon are combined to form the NiSi contact region 140 by a first rapid thermal annealing (RTA). In this step, the annealing temperature is about 400-500℃.

[0051] Further, the unreacted metal nickel layer 102 is removed, and then a second rapid thermal annealing is performed to optimize the electrical properties of the NiSi contact region 140, as shown in FIG. 2C. Figure 3 In this step, the annealing temperature is about 500-700℃. However, since the temperature of the second rapid thermal annealing is too high, the NiSi is not stable at high temperature and is easily formed into high-resistance NiSi2 (nickel disilicide), thereby increasing the resistance. At the same time, the high temperature causes the single-crystal Ni to grow laterally along the surface of the silicon substrate 101 to form spikes, which easily causes the source and drain to be short-circuited. The single-crystal Ni also grows vertically in the silicon substrate 101 to form spikes, which also causes the low-resistance NiSi to grow unevenly, thereby causing the resistance to be unstable, affecting the working frequency of the device, and reducing the reliability of the device.

[0052] In view of the above problems, the present disclosure proposes an improved semiconductor device and a manufacturing method thereof.

[0053] Figures 4 to 8 FIGS. 2A-2C show cross-sectional views of some stages of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0054] As shown in FIG. 2A, a gate 220 is formed on a substrate 201. The material of the substrate 201 includes silicon. The gate 220 includes a gate dielectric layer 221 and a gate conductor 222 stacked on the substrate 201. The substrate 201 includes a single substrate, or a stacked structure of a substrate and an epitaxial layer, or only an epitaxial layer. Figure 4 As shown in FIG. 2A, a gate 220 is formed on a substrate 201. The material of the substrate 201 includes silicon. The gate 220 includes a gate dielectric layer 221 and a gate conductor 222 stacked on the substrate 201. The substrate 201 includes a single substrate, or a stacked structure of a substrate and an epitaxial layer, or only an epitaxial layer.

[0055] Further, a second doped region 212 is formed in the substrate 201. In this step, the second doped region 212 is formed on both sides of the gate 220 by a light-doped ion implantation process, for example. The implantation energy is low, and the doped region is shallow. The second doped region 212 serves as a lightly doped source / drain (LDD) region.

[0056] Further, a first side wall 231 and a second side wall 232 are formed to wrap the gate 220, in sequence. The material of the first side wall 231 is silicon oxide, for example, and the material of the second side wall 232 is silicon nitride, for example.

[0057] Further, a first doped region 211 is formed in the substrate 201. In this step, for example, an ion implantation process is used to form the first doped region 211 on both sides of the gate 220. Compared to the second doped region 212, the first doped region 211 has a higher implantation energy, a higher concentration, and a deeper doped region. The first doped region 211 serves as a source / drain region and is connected to the second doped region 212. Due to the shielding of the first sidewall 231 and the second sidewall 232, the first doped region 211 is further away from the gate 220 than the second doped region 212, that is, the second doped region 212 is located between the first doped region 211 and the gate 220.

[0058] Further, a barrier layer 233 is formed, which is connected to the second sidewall 232 and located on both sides of the gate 220. The barrier layer 233 is a self-aligned silicide block oxide (SAB OX), for example, formed by plasma-enhanced chemical vapor deposition (PECVD) SiO2, and is used to cover the surface of the first doped region 211, which does not require the formation of metal silicides in subsequent steps.

[0059] Next, the silicon nickelation process is performed. First, a first metal layer 202 is formed covering the substrate 201, the barrier layer 233, and the second sidewall 232, and the first metal layer 202 is connected to the first doped region 211. In this embodiment, for example, a very thin first metal layer 202 is grown using a deposition process, with a thickness of approximately 5 to 15 angstroms. The material of the first metal layer 202 includes silver. Those skilled in the art can also adjust the thickness of the first metal layer 202 as needed.

[0060] Further, a first annealing is performed to allow the first metal layer 202 to react with the substrate 201 to form an auxiliary region 203, such as... Figure 5 As shown. In this step, the portion of the thin first metal layer 202 in contact with silicon undergoes a first annealing at a temperature ranging from 300°C to 400°C, thereby ensuring sufficient reaction between the first metal layer 202 and the silicon. An auxiliary region 203 is located within the first doped region 211 and close to the surface of the substrate 201. When the material of the first metal layer 202 includes silver, the formed auxiliary region 203 has an Ag-Si interface. In this embodiment, the first annealing can be performed using a simple rapid thermal processing (RTP) process, such as a low-energy step-through annealing process.

[0061] Further, a second metal layer 204 is formed covering the first metal layer 202 and the substrate 201. For example... Figure 5 As shown, the thin first metal layer 202 reacts completely with the silicon at the contact point, thereby forming the auxiliary region 203, and then... Figure 6As shown, a second metal layer 204 is formed on the surface of the remaining first metal layer 202 and the auxiliary region 203. The second metal layer 204 is connected with the auxiliary region 203, and the material of the second metal layer 204 includes nickel.

[0062] Further, a second annealing is performed to react the second metal layer 204 with the substrate 201 to form a contact region 240, as shown. Figure 7 In this step, the temperature of the second annealing can be lower than that of the first annealing. For example, when the auxiliary region 203 has an Ag-Si interface, the temperature of the second annealing only needs to reach 400K (127℃) to promote the reaction between the metal nickel and silicon to form low-resistance NiSi. When the material of the first metal layer 202 includes silver, the contact region 240 formed includes a silver-nickel-silicon compound. In this embodiment, the second annealing can use a simple rapid thermal processing (RTP) process, such as a low-energy step annealing process.

[0063] Further, the unreacted first metal layer 202 and the second metal layer 204 are removed simultaneously to form a device structure as shown. Figure 8 In this step, the unreacted first metal layer 202 and the second metal layer 204 are removed simultaneously, for example, by using a low-temperature sulfuric acid and hydrogen peroxide mixture (SPM) solution.

[0064] One of the technical solutions in the above technical scheme has the following unexpected technical effects:

[0065] By forming a metal silver layer on the silicon substrate before depositing the metal nickel layer, and then performing a first annealing to combine silver and silicon to form an Ag-Si bond interface, i.e., an auxiliary region, and then forming a nickel metal layer on the auxiliary region and performing a second annealing to combine nickel and silicon to form NiSi, in the second annealing, the Ag-Si bond interface can promote the combination of nickel and silicon, thereby reducing the annealing temperature for forming NiSi, inhibiting the generation of high-resistance phase NiSi2, and inhibiting the problem of spikes caused by the lateral and vertical movement of nickel elements in silicon, thereby improving the reliability of the device.

[0066] Further, the reduction of the annealing temperature is also conducive to strengthening the control of NiSi growth, realizing fine adjustment of the carrier concentration and mobility, and also helping to reduce impurities and defects at the interface and improve the interface quality. It can also reduce the thermal stress on the underlying silicon circuit and transistor, and reduce the heat accumulation effect.

[0067] In addition, since Ag is the metal with the highest electrical conductivity, and Ag is also included in the contact region with NiSi, the present scheme can also reduce the on-resistance of the device and improve the response speed of the device.

[0068] In some alternative embodiments, since the Ag-Si bond interface in the auxiliary region has already promoted the combination of nickel and silicon, there is no need to bombard the substrate with ion implantation process to promote the combination of nickel and silicon, thereby reducing the damage to the substrate and preventing the deformation of the device.

[0069] In some alternative embodiments, the temperature of the first annealing ranges from 300°C to 400°C, and the temperature of the second annealing is less than the temperature of the first annealing, especially when there is an Ag-Si bond interface, the temperature of the second annealing needs to reach 400K (127°C) only, greatly reducing the annealing temperature and thereby saving the cost.

[0070] In some alternative embodiments, since the temperature required for annealing is low, there is no need to use high-energy consumption rapid thermal annealing (RTA), only a low-energy consumption annealing process is needed, thereby reducing the manufacturing difficulty and further saving the cost.

[0071] Compared with the scheme of Figures 1 to 3 The scheme of Figures 4 to 8 The scheme of does not increase the overall process steps and does not increase additional masks, and adjusts the process sequence, which not only improves the thermal stability and reliability of the device, reduces the resistance of the device, enhances the electrical properties such as carrier mobility and conductivity, but also improves the working speed and performance of the device, and greatly improves the yield of the device.

[0072] In accordance with the embodiments of the present disclosure as described above, these embodiments do not describe all the details and do not limit the present disclosure to only specific embodiments. Obviously, many modifications and changes can be made according to the above description. The present description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present disclosure, so that those skilled in the art can well utilize the present disclosure and make modifications and uses on the basis of the present disclosure. The protection scope of the present disclosure should be defined by the scope of the claims of the present disclosure and their equivalents.

Claims

1. A method of fabricating a semiconductor device, comprising: forming a gate on a substrate; forming a first doped region in the substrate, the first doped region being located on both sides of the gate; forming a first metal layer on the substrate, the first metal layer being connected to the first doped region; performing a first anneal to form an auxiliary region between the first metal layer and the substrate; forming a second metal layer on the auxiliary region; and performing a second anneal to form a contact region between the second metal layer and the substrate, wherein a material of the substrate comprises silicon, a material of the first metal layer comprises silver, a material of the second metal layer comprises nickel, and a material of the contact region comprises a silver-nickel-silicon compound, the auxiliary region facilitates the formation of the contact region between the second metal layer and the substrate during the second anneal, the contact region is located in the first doped region. a temperature of the second anneal is less than a temperature of the first anneal.

2. The manufacturing method according to claim 1, wherein, the temperature of the first anneal is in a range of 300 °C to 400 °C.

3. The manufacturing method according to claim 2, wherein, the temperature of the second anneal is not less than 400 K.

4. The production method according to any one of claims 1 to 3, wherein the first anneal and / or the second anneal is a step anneal.

5. The production method according to any one of claims 1 to 3, wherein a thickness of the first metal layer is in a range of 5 to 15 Angstroms.

6. The production method according to any one of claims 1 to 3, wherein 7. The method of claim 1, further comprising removing unreacted first metal layer and second metal layer simultaneously using a mixture solution of sulfuric acid and hydrogen peroxide after the step of forming the contact region.

8. A semiconductor device formed using the method of any one of claims 1 to 7, comprising: a substrate; a gate on the substrate; a first doped region in the substrate and on both sides of the gate; and a contact region in the first doped region, wherein a material of the substrate comprises silicon and a material of the contact region comprises a silver-nickel-silicon compound.

9. The semiconductor device of claim 8, further comprising: a second doped region in the substrate and connected to the first doped region; and a sidewall structure covering at least a sidewall of the gate, wherein the second doped region is located on both sides of the gate and between the first doped region and the gate, and a doping concentration of the second doped region is less than a doping concentration of the first doped region. ​ ​ ​

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