Device structure and method of manufacturing semiconductor device

Abstract

The method includes, for example, forming a nitrogen-free low-k dielectric layer on the source / drain; forming an oxygen treated low-k dielectric layer on the nitrogen-free low-k dielectric layer; and forming a dielectric layer on the oxygen treated low-k dielectric layer to form a three-layer etch stop layer over the source / drain. The nitrogen-free dielectric layer has a first dielectric constant, the oxygen-treated low-k dielectric layer has a second dielectric constant greater than the first dielectric constant, and the dielectric layer has a third dielectric constant greater than the second dielectric constant and the first dielectric constant. The method may also include forming an interlayer dielectric layer over the three-layer etch stop layer; removing a portion of the three-layer etch stop layer and a portion of the ILD layer to form a source / drain contact opening exposing the source / drain; and forming a source / drain contact structure in the source / drain contact opening. The embodiment of the invention also relates to a device structure and a method for manufacturing the semiconductor device.

Description

Technical Field

[0001] Embodiments of the present application relate to device structures and methods of manufacturing semiconductor devices. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. Such shrinking has also increased the complexity of processing and manufacturing ICs, and similar developments in IC materials and manufacturing are needed to achieve these advances. Summary of the Invention

[0003] Some embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: forming a three-layer etch stop layer above a source / drain by the following steps: forming a nitrogen-free low-k dielectric layer on the source / drain, wherein the nitrogen-free dielectric layer has a first dielectric constant; forming an oxygen-treated low-k dielectric layer on the nitrogen-free low-k dielectric layer, wherein the oxygen-treated low-k dielectric layer has a second dielectric constant greater than the first dielectric constant; and forming a dielectric layer on the oxygen-treated low-k dielectric layer, wherein the dielectric layer has a third dielectric constant greater than the second dielectric constant and the first dielectric constant; forming an interlayer dielectric layer above the three-layer etch stop layer; removing portions of the three-layer etch stop layer and portions of the interlayer dielectric layer to form a source / drain contact opening exposing the source / drain; and forming a source / drain contact structure in the source / drain contact opening.

[0004] Other embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: forming a contact etch stop layer above a source / drain by the following steps: depositing a first SiOC layer on the source / drain; depositing a second SiOC layer on the first SiOC layer; performing an oxygen treatment on the second SiOC layer; and depositing a SiN layer on the oxygen-treated second SiOC layer; forming an interlayer dielectric layer on the contact etch stop layer; and forming a source / drain contact to the source / drain, wherein the source / drain contact is formed in the contact etch stop layer and the interlayer dielectric layer.

[0005] Some other embodiments of the present application provide a device structure, including: a gate stack; a gate spacer arranged along the sidewall of the gate stack; a source / drain arranged adjacent to the gate spacer; a source / drain contact structure arranged on the source / drain; and a contact etch stop layer arranged between the gate spacer and the source / drain contact structure, wherein the contact etch stop layer has a nitrogen-free portion that interfaces with the source / drain and the gate spacer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The presently disclosed embodiments are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with standard industry practice, various components are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a flowchart of part or all of a method for manufacturing a source / drain contact structure according to various aspects of an embodiment of the present disclosure.

[0008] Figures 2 to 15 The various stages of manufacturing source / drain contact structures (such as with Figure 1 schematic cross-sectional views of part or all of those related to the method).

[0009] Figure 16A and Figure 16B According to various aspects of the embodiments of the present disclosure Figure 15 A schematic cross-sectional view of part or all of a device.

[0010] Figures 17 to 24 The device 100 according to various aspects of the present disclosure is used in the manufacture of source / drain contact structures (such as Figure 1 Schematic cross-sectional views of part or all of different configurations after the method is related to the method. DETAILED DESCRIPTION

[0011] The disclosed embodiments generally relate to fabricating source / drain contacts, and more particularly, to etch stop layers implemented when fabricating source / drain contacts.

[0012] The following disclosure provides many different embodiments or examples for implementing the different features of the embodiments of the present disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments in which the first component and the second component are directly in contact with each other, and may also include embodiments in which additional components may be formed between the first component and the second component so that the first component and the second component are not in direct contact. In addition, spatially relative terms such as "lower," "upper," "horizontal," "vertical," "above," "above," "below," "under," "upward," "downward," "top," "bottom," and their derivatives (e.g., "horizontally," "downwardly," "upwardly," etc.) are used to facilitate understanding the relationship between one component and another component of the embodiments of the present disclosure. Spatially relative terms are intended to cover different orientations of devices including components. The embodiments of the present disclosure may also repeat reference numerals and / or characters in various examples. This repetition is for simplicity and clarity purposes and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, when words like "about," "approximately," and the like are used to describe a value or range of values, such terms are intended to encompass values ​​within a reasonable range, taking into account variations inherently occurring during manufacturing, as understood by one of ordinary skill in the art. For example, a value or range of values ​​encompasses a reasonable range encompassing the described value, such as within + / - 10% of the described value, based on known manufacturing tolerances associated with manufacturing components having the properties associated with the value. For example, a material layer having a thickness of "approximately 5 nm" may encompass a range of dimensions from 4.5 nm to 5.5 nm, where the manufacturing tolerances associated with depositing material layers known to one of ordinary skill in the art are + / - 10%. Furthermore, given the variations inherent in any manufacturing process, when a device component is described as having a property and / or characteristic "substantially," such terms are intended to capture properties and / or characteristics within the tolerances of the manufacturing process. For example, a component that is "substantially vertical" or "substantially horizontal" is intended to capture a component that is approximately vertical and horizontal—but not mathematically or perfectly vertical and horizontal—within the given tolerances of the manufacturing process used to manufacture such component.

[0014] An etch stop layer (ESL), also known as a contact etch stop layer (CESL), is often implemented to protect underlying layers and / or underlying components during semiconductor device fabrication. For example, forming a source / drain contact may include: forming the ESL over the source / drain; forming an interlayer dielectric (ILD) layer over the ESL; forming a source / drain contact opening extending through the ILD layer and the ESL to expose the source / drain; and forming a source / drain contact in the source / drain contact opening. The ESL may protect the source / drain while etching the ILD layer to form the source / drain contact opening therein. Because the ESL typically remains over the source / drain and / or between the source / drain contact and the gate structure (e.g., a gate stack having gate spacers disposed along its sidewalls) of a fabricated semiconductor device (e.g., a transistor including a source / drain and gate structure), ESL design (such as ESL composition and ESL fabrication) needs to consider its impact on the fabricated semiconductor device.

[0015] Embodiments of the present disclosure provide a triple-layer ESL over the source / drain and a method for manufacturing the same that minimizes and / or prevents undesirable oxidation of the source / drain during ESL fabrication and / or subsequent fabrication of the semiconductor device. The disclosed triple-layer ESL and method for manufacturing the same are also configured to minimize the dielectric constant of the dielectric material between conductive components of the semiconductor device (e.g., between the source / drain contacts and their gate stacks and / or between the source / drain and the gate stack), thereby reducing parasitic capacitance therebetween and improving overall device performance (e.g., device speed). Details of the proposed triple-layer etch stop layer over the source / drain and method for manufacturing the same are described herein. Different embodiments may have different advantages, and no particular advantage is required by any embodiment.

[0016] Figure 1Flowchart of part or all of method 10 for fabricating a source / drain contact structure according to various aspects of an embodiment of the present disclosure. In block 15, method 10 includes forming a tri-layer ESL over the source / drain. Block 15 may include: forming a nitrogen-free low-k dielectric layer (e.g., a silicon oxycarbide layer) over the source / drain in block 20; forming an oxygen-treated low-k dielectric layer (e.g., a silicon oxycarbide layer and / or a silicon oxycarbonitride layer) over the nitrogen-free low-k dielectric layer in block 25; and forming a dielectric layer (e.g., a silicon nitride layer) over the oxygen-treated low-k dielectric layer in block 30. The formation of the nitrogen-free low-k dielectric layer, the oxygen-treated dielectric layer, and the dielectric layer may be configured to provide a tri-layer ESL having a dielectric constant that increases from its bottom to its top and having a nitrogen-free low-k dielectric constant portion that interfaces with the source / drain. To prevent oxidation of the source / drain, the nitrogen-free low-k dielectric layer and the oxygen-treated low-k dielectric layer are formed by respective low-temperature, short-duration deposition processes. Forming an oxygen-treated low-k dielectric layer may include: depositing a low-k dielectric layer on the nitrogen-free low-k dielectric layer; and subjecting the low-k dielectric layer to an oxygen treatment after its deposition. To prevent oxidation of the source / drain, no oxygen treatment is applied between depositing the nitrogen-free low-k dielectric layer and depositing the low-k dielectric layer, and the nitrogen-free low-k dielectric layer and the low-k dielectric layer may be deposited in the same process chamber (e.g., to limit and / or prevent exposure of the nitrogen-free dielectric layer to an oxygen environment prior to depositing the low-k dielectric layer, which may occur when transferring the device between process chambers). In block 35, method 10 includes forming an ILD layer over the three-layer ESL. In block 40, method 10 includes removing portions of the three-layer ESL and portions of the ILD layer to form source / drain contact openings exposing the source / drain. In block 45, method 10 includes forming a source / drain contact structure in the source / drain contact openings. Additional steps may be provided before, during, and after method 10, and some of the described steps may be moved, replaced, or eliminated for additional embodiments of method 10. The following discussion describes a device having a source / drain structure fabricated according to method 10.

[0017] Figures 2 to 15 The device 100 according to various aspects of the present disclosure is used in the manufacture of source / drain contact structures (such as Figure 1 Schematic cross-sectional views of part or all of the various stages of method 10). Figure 16A and Figure 16B The device 100 according to various aspects of the embodiment of the present disclosure is respectively along Figure 15 Schematic cross-sectional view of part or all of line AA and line BB. Figures 17 to 24is a schematic cross-sectional view of part or all of various embodiments of different configurations of the device 100 according to various aspects of the present disclosure. The device 100 may include at least one transistor, such as a gate-all-around (GAA) transistor (i.e., a transistor having a gate at least partially surrounding a suspended channel (e.g., a nanowire, nanosheet, nanorod, etc.) extending between a source / drain). The device 100 may be included in a microprocessor, a memory, other integrated circuit (IC) devices, or a combination thereof. In some embodiments, the device 100 is part of an IC chip, a system on a chip (SoC), or a portion thereof, and the device 100 may include various passive electronic devices and / or active electronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs), n-type FETs (NFETs), metal oxide semiconductor FETs (MOSFETs), complementary MOS (CMOS) transistors (including, for example, n-type transistors and p-type transistors), bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or a combination thereof. For reasons of clarity, the following has been simplified. Figures 2 to 15 、 Figure 16A 、 Figure 16B and Figures 17 to 24 , to better understand the inventive concepts of the disclosed embodiments. Additional components may be added to the device 100, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the device 100.

[0018] refer to Figure 2 , a device precursor for device 100 may be formed and / or received, and the device precursor may then be processed as described herein to form source / drain contact structures. Device 100 may include substrate 105, mesa 105′, a multilayer stack 110 (including, for example, mesa 105P′, sacrificial layer 115, and semiconductor layer 120) in a channel region (C) of device 100, substrate isolation structure 125 (see, for example, Figure 16A and Figure 16B ) and a gate structure 128. In the depicted embodiment, the gate structures each include a respective dummy gate stack 130 and a respective gate spacer 132. The device 100 may also include an internal spacer 145 and a source / drain structure 150 disposed in the source / drain region (S / D) of the device 100. Each source / drain structure 150 may be multi-layered, including, for example, a semiconductor layer 152, an insulating layer 154, a semiconductor layer 156, and a semiconductor layer 158.

[0019] The substrate 105 and the mesa 105' (and the mesa 105P') include: an elemental semiconductor such as silicon and / or germanium; a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or a combination thereof; an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof; or a combination thereof. In some embodiments, the substrate 105 is a silicon substrate. In some embodiments, the substrate 105 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The substrate 105 (and the mesa 105') may include various doped regions, such as a p-type doped region (e.g., a p-well), an n-type doped region (e.g., an n-well), or a combination thereof. The n-type doped region includes an n-type dopant such as phosphorus, arsenic, other n-type dopant, or a combination thereof. The p-type doped region includes a p-type dopant, such as boron, indium, gallium, other p-type dopants, or a combination thereof. In some embodiments, the doped region includes a p-type dopant and an n-type dopant. The doped region can be formed on and / or in the substrate 105 and / or the mesa 105', for example, to provide a p-well structure, an n-well structure, a double-well structure, a raised structure, other suitable structures, or a combination thereof. In some embodiments, the substrate 105 and / or the mesa 105' and the semiconductor layers thereon can include an n-well and / or a p-well. For example, the substrate 105, the mesa 105', and / or the mesa 105P' can include a p-well in the n-type transistor region and an n-well in the p-type transistor region.

[0020] The sacrificial layer 115 and the semiconductor layer 120 are stacked vertically (e.g., along the z-direction) in a staggered and / or alternating configuration from the top of the substrate 105. The composition of the sacrificial layer 115 is different from the composition of the semiconductor layer 120 to achieve etch selectivity. For example, the sacrificial layer 115 and the semiconductor layer 120 include different materials, atomic percentages of components, weight percentages of components, other characteristics, or a combination thereof to achieve etch selectivity. In some embodiments, the sacrificial layer 115 includes silicon germanium and the semiconductor layer 120 includes silicon, and the etch rate of the semiconductor layer 120 is different from the etch rate of the sacrificial layer 115 for a given etchant. In some embodiments, the sacrificial layer 115 and the semiconductor layer 120 include the same material, but have different atomic percentages of components. For example, the sacrificial layer 115 and the semiconductor layer 120 may include silicon germanium, but have different atomic percentages of germanium. In some embodiments, the sacrificial layer 115 is a dielectric layer (e.g., the sacrificial layer 115 may be an oxide layer) and the semiconductor layer 120 is a silicon layer to provide etch selectivity. The sacrificial layer 115 and the semiconductor layer 120 may include any combination of materials that provide a desired etch selectivity, a desired oxidation rate difference, a desired performance characteristic, or a combination thereof (eg, a material that maximizes current flow), including any of the materials disclosed herein.

[0021] Semiconductor layer 120 or a portion thereof may form a channel of a transistor of device 100. Figure 2 , the multilayer stack 110 includes three sacrificial layers 115 and three semiconductor layers 120. Thus, the multilayer stack 110 includes three semiconductor layer pairs disposed above the substrate 105, each of which has a corresponding sacrificial layer 115 and a corresponding semiconductor layer 120. After processing the multilayer stack 110, this configuration can produce a transistor with three channels. However, in some embodiments, the multilayer stack 110 includes a different number of semiconductor layers 120, depending on, for example, the number of channels desired for the transistor and / or the design requirements of the device 100. For example, the multilayer stack 110 can include two to six semiconductor layer pairs, each of which can have a corresponding sacrificial layer 115 and a corresponding semiconductor layer 120.

[0022] The substrate isolation structure 125 can be formed adjacent to and surrounding the lower portion of the multilayer stack 110 (e.g., its mesa 105P'), and the device 100 (e.g., the multilayer stack 110 in its channel region and / or the source / drain structure 150 in its source / drain region) can be separated from other devices and / or device regions by the substrate isolation structure 125. The substrate isolation structure 125 can electrically isolate the active device region (e.g., the mesa 105P' and / or the source / drain structure 150) from other device regions. The substrate isolation structure 125 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (including silicon, oxygen, nitrogen, carbon, other suitable isolation components, or combinations thereof), or combinations thereof. The substrate isolation structure 125 can have a multilayer structure. For example, the substrate isolation structure 125 may include a bulk dielectric (e.g., an oxide layer) located above a dielectric liner (e.g., silicon nitride, silicon oxide, silicon oxynitride, silicon carbon oxynitride, or a combination thereof). In another example, the substrate isolation structure 125 may include a bulk dielectric located above a doped liner (e.g., a borosilicate glass (BSG) liner and / or a phosphosilicate glass (PSG) liner). The dimensions and / or characteristics of the substrate isolation structure 125 may be configured to provide a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, a local oxidation of silicon (LOCOS) structure, other suitable isolation structures, or a combination thereof.

[0023] The gate structure 128 can be formed over a channel region (C) of the device 100 (e.g., the multilayer stack 110) and between corresponding source / drain regions (S / D) of the device 100 (e.g., the source / drain structure 150). As noted, the gate structure 128 can include a corresponding dummy gate stack 130 and a corresponding gate spacer 132. The dummy gate stack 130 extends longitudinally in a direction that is different from (e.g., orthogonal to) the longitudinal direction of the multilayer stack 110. For example, the dummy gate stack 130 extends in the y-direction and has a length in the y-direction, a width in the x-direction, and a height in the z-direction. The dummy gate stacks 130 can extend substantially parallel to each other. In Figure 2 In the cross-sectional view along the YZ plane (e.g., the XZ plane), the dummy gate stack 130 is disposed on top of the corresponding channel region of the device 100, and the dummy gate stack 130 is disposed between the respective source / drain regions of the device 100. In a cross-sectional view along the YZ plane, in some embodiments, the dummy gate stack 130 may wrap around the corresponding channel region (e.g., disposed over the top and sidewalls thereof), and the dummy gate stack 130 may be disposed over the top of the substrate isolation structure 125.

[0024] The dummy gate stack 130 may include a dummy gate dielectric and a dummy gate electrode. The dummy gate dielectric includes a dielectric material, such as silicon oxide and / or other suitable dielectric materials. The dummy gate electrode includes a suitable dummy gate material, such as polysilicon. The dummy gate stack 130 may also include a hard mask, which may be configured to protect the dummy gate dielectric and / or dummy gate electrode during processing. For example, the hard mask may include a material that is resistant to etching processes, such as etching associated with forming source / drain grooves and / or etching associated with forming source / drain contact openings, to protect the dummy gate dielectric and / or dummy gate electrode from being affected thereby. In some embodiments, the hard mask has a multilayer structure. The hard mask includes any suitable hard mask material.

[0025] The gate spacers 132 are formed adjacent to and along the sidewalls of the dummy gate stack 130. The gate spacers 132 include a dielectric material that may include silicon, oxygen, carbon, nitrogen, other suitable dielectric components, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxynitride, or combinations thereof). In some embodiments, the gate spacers 132 have a multilayer structure, such as two or more dielectric layers with different compositions. In some embodiments, the gate spacers 132 include more than one spacer group, such as a sealing spacer, an offset spacer, a sacrificial spacer, a dummy spacer, a main spacer, or a combination thereof. In such embodiments, each spacer group may have a different composition.

[0026] The inner spacer 145 is disposed below the gate structure 128 (e.g., below its gate spacer 132) and along the sidewalls of the sacrificial layer 115. The inner spacer 145 is disposed between the sacrificial layer 115 and the source / drain structure 150, between adjacent semiconductor layers 120, and between the bottommost semiconductor layer 120 and the mesa 105P'. The inner spacer 145 comprises a dielectric material comprising silicon, oxygen, carbon, nitrogen, or a combination thereof, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonitride, or the like. In some embodiments, the inner spacer 145 comprises a low-k dielectric material. In some embodiments, dopants (e.g., p-type and / or n-type) are introduced into the dielectric material, and the inner spacer 145 comprises a doped dielectric material.

[0027] The source / drain structure 150 includes a semiconductor material. The source / drain structure 150 may be doped with n-type dopants and / or p-type dopants, and the source / drain structure 150 may have the same or different compositions and / or materials. In some embodiments, the semiconductor material of the source / drain structure 150 is formed by an epitaxial process, and the source / drain structure 150 is formed from epitaxially grown / deposited semiconductor material. In such embodiments, the source / drain structure 150 may be referred to as an epitaxial source / drain. In some embodiments (e.g., when forming part of an n-type transistor), the source / drain structure 150 may include silicon doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof. In some embodiments (e.g., when forming part of a p-type transistor), the source / drain structure 150 may include silicon germanium or germanium doped with boron, other p-type dopants, or combinations thereof. In some embodiments, doped regions, such as heavily doped source / drain (HDD) regions, lightly doped source / drain (LDD) regions, other doped regions, or combinations thereof, are disposed in the source / drain structure 150. In some embodiments, doped regions (such as LDD regions) may extend into the channel region. As used herein, source / drain regions, source / drain, source / drain structure, epitaxial source / drain, epitaxial source / drain component, etc. may refer to the source of the device 100, the drain of the device 100, the source and drain of the device 100, or the source and / or drain of multiple devices.

[0028] Each source / drain structure 150 may include a corresponding semiconductor layer 152, a corresponding insulating layer 154, a corresponding semiconductor layer 156, and a corresponding semiconductor layer 158. The semiconductor layer 152 is disposed on the mesa 105P' and / or the substrate 105. In the depicted embodiment, the semiconductor layer 152 comprises a dopant-free semiconductor material (i.e., substantially free of n-type and p-type dopants). For example, when the semiconductor layer 152 is formed, for example, by an epitaxial growth process, no intentional doping is performed. Thus, the semiconductor layer 152 can provide a high resistance path at the bottom of the source / drain structure 150, thereby preventing leakage current from flowing between the source / drain structures 150 through the mesa 105P' and / or the substrate 105. In some embodiments, the undoped semiconductor layer is formed of silicon, germanium, silicon germanium, other suitable semiconductor materials, or combinations thereof. For example, the semiconductor layer 152 can be an undoped silicon or undoped silicon germanium layer.

[0029] Insulating layer 154 is disposed on semiconductor layer 152 and may be disposed between semiconductor layer 158 and semiconductor layer 152. Insulating layer 154 includes an electrically insulating material, such as a dielectric material, that can also prevent unwanted leakage current from flowing between source / drain structure 150 (e.g., semiconductor layer 158 thereof) through mesa 105P' and / or substrate 105. In some embodiments, insulating layer 154 includes a silicon-containing dielectric material, such as silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon oxycarbide, silicon carbonitride, other silicon-containing dielectric materials (which may include silicon and nitrogen, carbon, oxygen, other suitable dielectric components, or combinations thereof), or combinations thereof. In some embodiments, insulating layer 154 includes a metal-containing dielectric material, such as a metal oxide material (e.g., aluminum oxide and / or hafnium oxide) and / or a metal nitride material. In some embodiments, insulating layer 154 includes a doped semiconductor material that includes a dopant of the opposite type as semiconductor layer 158. For example, when the source / drain structure 150 is a portion of a p-type transistor having a p-type doped semiconductor layer, the insulating layer 154 may include an n-type doped semiconductor material, such as phosphorus-doped silicon. In another example, when the source / drain structure 150 is a portion of an n-type transistor having an n-type doped semiconductor layer, the insulating layer 154 may include a p-type doped semiconductor material, such as boron-doped silicon.

[0030] Semiconductor layer 156 and semiconductor layer 158 are disposed over insulating layer 154 and coupled to semiconductor layer 120. Semiconductor layer 156 may be disposed between semiconductor layer 158 and semiconductor layer 120. In the depicted embodiment, semiconductor layer 156 and semiconductor layer 158 comprise semiconductor materials (e.g., silicon, germanium, silicon germanium, other suitable semiconductor materials, or combinations thereof) doped with n-type dopants and / or p-type dopants. Semiconductor layer 156 and semiconductor layer 158 may have different compositions and / or different sizes / configurations, and the different compositions may be achieved using different semiconductor materials, different dopants, different atomic percentages of components, different dopant concentrations, or combinations thereof. For example, semiconductor layer 158 may be a heavily doped semiconductor layer, and semiconductor layer 156 may be a lightly doped semiconductor layer, wherein the dopant concentration of the heavily doped semiconductor layer is greater than the dopant concentration of the lightly doped semiconductor layer. In some embodiments, semiconductor layer 156 and semiconductor layer 158 may comprise silicon doped with different concentrations of carbon, phosphorus, arsenic, antimony, other n-type dopants, or combinations thereof. In another example, semiconductor layer 156 and semiconductor layer 158 may include silicon germanium doped with different concentrations of boron, gallium, other p-type dopants, or combinations thereof. In some embodiments, semiconductor layer 156 and semiconductor layer 158 include materials and / or dopants that provide desired tensile and / or compressive stress in the channel region.

[0031] Prior to forming the source / drain structure 150, the multilayer stack 110 (e.g., its mesa 105', sacrificial layer 115, and semiconductor layer 120) may be continuous and substantially extend along the x-direction, having a length along the x-direction, a width along the y-direction, and a height along the z-direction. The multilayer stack 110 may be referred to as a fin, a fin structure, a fin element, an active fin region, an active region, etc. In some embodiments, the mesa 105' is a patterned, protruding, and / or extended portion of the substrate 105, and the mesa 105' may be referred to as a substrate extension portion, a substrate fin portion, a fin portion, an etched substrate portion, etc. When forming the source / drain structure 150, the sacrificial layer 115, the semiconductor layer 120, and the mesa 105' may be removed (in some embodiments) to form source / drain recesses in the source / drain region of the device 100, wherein the source / drain structure 150 is formed. After forming the source / drain recesses (which may extend into the mesa 105'), portions of the multilayer stack 110 may remain in the channel region of the device 100, and such portions may include the mesa 105P', the sacrificial layer 115, and the semiconductor layer 120, as depicted.

[0032] refer to Figures 3 to 6 A tri-layer etch stop layer (ESL) 160 is formed over the device 100, such as over its source / drain structure 150. The tri-layer ESL 160 is configured with a combination of dielectric layers and is fabricated in a manner that reduces and / or prevents undesirable oxidation of the source / drain structure 150 during formation of the tri-layer ESL 160 and / or during subsequent processing of the device 100. The tri-layer ESL 160 and its method of formation are also configured to minimize the dielectric constant of the dielectric material between subsequently formed source / drain contacts and the gate stack of the gate structure 128 and / or between the source / drain structure 150 and the gate stack of the gate structure 128, thereby reducing parasitic capacitance. As described herein, the tri-layer ESL 160 includes a nitrogen-free low-k dielectric layer 162, an oxygen-treated low-k dielectric layer 164, and a dielectric layer 166.

[0033] refer to Figure 3 A nitrogen-free low-k dielectric (NFD) layer 162 is formed over the device 100, such as over the gate structures 128 and the source / drain structures 150. In the depicted embodiment, the NFD layer 162 is formed directly over the gate structures 128 and the source / drain structures 150. The NFD layer 162 has a thickness t1. The thickness t1 is less than the spacing between adjacent gate structures 128 (e.g., the distance s between their gate spacers 132), such that the NFD layer 162 partially fills the spacing (and / or distance s). The spacing (and / or distance s) can be approximately the same as the width w1 of the top of the corresponding source / drain structure 150 between adjacent gate structures 128. In some embodiments, the thickness t1 is from about 0.5 nm to about 1.5 nm.

[0034] NFD layer 162 is formed from a nitrogen-free low-k dielectric material. For the purposes of the presently disclosed embodiments, a low-k dielectric material generally refers to a dielectric material having a dielectric constant less than that of silicon dioxide (k≈3.9), and NFD layer 162 is formed from a nitrogen-free dielectric material having a dielectric constant less than approximately 3.9. In some embodiments, NFD layer 162 is formed from a dielectric material having a dielectric constant of at least 3.6 (i.e., 3.6≤k<3.9). In some embodiments, NFD layer 162 includes silicon, oxygen, and carbon. For example, NFD layer 162 is a silicon oxycarbide (SiOC) layer having a dielectric constant of approximately 3.6 to approximately 3.7 (i.e., 3.6≤k≤3.7). In some embodiments, the NFD layer 162 has a silicon content (Si%) of about 25 atomic percent (at%) to about 35 at%, a carbon content (C%) of about 20 at% to about 30 at%, an oxygen content (O%) of about 40 at% to about 50 at%, and a nitrogen content (N%) of less than about 1 at%. For the purposes of the presently disclosed embodiments, a low-k dielectric material having a nitrogen content (N%) of less than about 1 at% is considered nitrogen-free. In other words, nitrogen is not intentionally incorporated into the NFD layer 162 during its formation (e.g., during deposition), but trace / negligible amounts of nitrogen (i.e., less than about 1 at% N%) may be unintentionally incorporated and / or diffused into the NFD layer 162 during fabrication of the device 100. A nitrogen content greater than 1 at % may undesirably provide an NFD layer 162 having a dielectric constant greater than or equal to 3.9, thereby undesirably increasing the effective dielectric constant of the triple-layer ESL 160 and counteracting parasitic capacitance reduction achieved by providing the NFD layer 162 having a dielectric constant less than 3.9.

[0035] Because the NFD layer 162 is formed directly on and interfaces with the source / drain structures 150, oxygen contained in the NFD layer 162 may undesirably react with the source / drain structures 150 (e.g., with the silicon and / or germanium contained therein) during the formation of the NFD layer 162 and / or during subsequent processing of the device 100, thereby undesirably oxidizing the source / drain structures 150. The disclosed embodiments recognize that when forming an ESL over the source / drain, such undesirable reactions and oxidation are more likely to occur when a higher thermal budget (i.e., a temperature greater than or equal to 600° C.) is implemented. Therefore, the disclosed embodiments form the NFD layer 162 using a low-temperature, short-duration deposition process (e.g., a process implementing a deposition temperature of less than about 600° C. and a deposition time of less than about 1 hour). For example, the NFD layer 162 is formed by plasma enhanced chemical vapor deposition (PECVD), which enables low temperature, short duration deposition, such as a deposition temperature of less than about 600° C. and a deposition time of less than about 1 hour. In some embodiments, the PECVD deposition temperature is from about 200° C. to about 600° C. In some embodiments, the PECVD deposition time is from about 6 minutes (0.1 hour) to about 1 hour. Higher deposition temperatures (such as those greater than 600° C.) and / or longer deposition times (such as those greater than 1 hour) may produce undesirable source / drain oxidation. For example, a deposition temperature greater than 600° C. may induce a reaction between oxygen (such as oxygen in the NFD layer 162) and the source / drain structure 150 and / or increase the reaction rate between oxygen and the source / drain structure 150, and a deposition time greater than 1 hour may cause a reaction between oxygen (such as oxygen in the NFD layer 162) and the source / drain structure 150, thereby producing undesirable source / drain oxidation. Thus, the proposed low-temperature, short-duration deposition of the NFD layer 162 reduces the reaction between oxygen and the source / drain structure 150, thereby reducing source / drain oxidation. In some embodiments, PECVD generates a plasma comprising at least silicon, oxygen, and carbon. In some embodiments, the plasma also comprises hydrogen. The plasma can be generated by flowing a deposition precursor gas comprising silicon, carbon, oxygen, or a combination thereof (e.g., trimethylsilane, methyltriethoxysilane, oxygen (O2), other precursors, or a combination thereof) and a carrier gas (e.g., an inert gas) into a process chamber and generating a plasma comprising silicon, carbon, and oxygen therefrom using radio frequency (RF) power and / or direct current (DC) power. PECVD parameters (e.g., deposition temperature, deposition time, deposition gas, pressure, power, bias, etc.) can be adjusted to minimize source / drain oxidation, provide an NFD layer 162 having a dielectric constant of less than about 3.9, provide an NFD layer 162 having an oxygen content of less than about 50 at %, or a combination thereof.

[0036] refer to Figure 4and Figure 5 , in NFD layer 162 ( Figure 4 ) is formed on the low-k dielectric (LKD) layer 164', and the LKD layer 164' is subjected to an oxygen treatment 165 ( Figure 5 ), thereby forming an oxygen-treated LKD layer 164. In the depicted embodiment, the oxygen-treated LKD layer 164 is formed directly on the NFD layer 162. The LKD layer 164' and the oxygen-treated LKD layer 164 have a thickness t2. Thickness t2 is less than the space between adjacent gate structures 128, so that the oxygen-treated LKD layer 164 also partially fills the space (and / or distance s) therebetween. The sum of thickness t2 and thickness t1 is less than the space between adjacent gate structures 128. Thickness t2 can be equal to, greater than, or less than thickness t1. In some embodiments, thickness t2 is approximately 0.5 nm to approximately 1.5 nm.

[0037] The oxygen-treated LKD layer 164 is formed from a low-k dielectric material that may or may not contain nitrogen. In the depicted embodiment, the oxygen-treated LKD layer 164 is formed from a dielectric material having a dielectric constant greater than the dielectric constant of the NFD layer 162. In other words, the dielectric constant of the oxygen-treated LKD layer 164 is greater than the dielectric constant of the NFD layer 162. In some embodiments, the oxygen-treated LKD layer 164 is formed from a dielectric material having a dielectric constant less than approximately 3.9, such as a dielectric constant of approximately 3.6 to approximately 3.9 (i.e., 3.6 ≤ k < 3.9). In such embodiments, the oxygen-treated LKD layer 164 may be a nitrogen-free layer. For example, the oxygen-treated LKD layer 164 includes silicon, oxygen, and carbon, and is a silicon oxycarbide (SiOC) layer. In such embodiments, the oxygen-treated LKD layer 164 has an oxygen content greater than that of the NFD layer 162. In some embodiments, the oxygen-treated LKD layer 164 has a carbon content that is different from (e.g., less than) the carbon content of the NFD layer 162. In some embodiments, the oxygen-treated LKD layer 164 has a silicon content (Si%) of approximately 25 at% to approximately 35 at%, a carbon content (C%) of approximately 5 at% to approximately 15 at%, and an oxygen content (O%) of approximately 55 at% to approximately 70 at%. In such embodiments, the oxygen-treated LKD layer 164 may have a nitrogen content of less than approximately 1 at%. In some embodiments, the oxygen-treated LKD layer 164 includes nitrogen (i.e., the oxygen-treated LKD layer 164 has a nitrogen content greater than 1 at%). For example, the oxygen-treated LKD layer 164 includes silicon, nitrogen, oxygen, and carbon. In such an example, the oxygen-treated LKD layer 164 may be a silicon oxycarbonitride (SiOCN) layer having a dielectric constant greater than 3.9 (e.g., k≈4.3).

[0038] refer to Figure 4To minimize source / drain oxidation, the LKD layer 164' is also formed using a low-temperature, short-duration deposition process (e.g., a process employing a deposition temperature of less than about 600°C and a deposition time of less than about 1 hour). For example, the LKD layer 164' is also formed using PECVD, which enables low-temperature, short-duration deposition. In some embodiments, the PECVD deposition temperature is from about 200°C to about 600°C. In some embodiments, the PECVD deposition time is from about 6 minutes to about 1 hour. Higher deposition temperatures (such as those greater than 600°C) and / or longer deposition times (such as those greater than 1 hour) for the LKD layer 164' may result in undesirable source / drain oxidation. Therefore, the low-temperature, short-duration deposition of the LKD layer 164' reduces and / or prevents reactions between oxygen and the source / drain structure 150, thereby reducing and / or preventing source / drain oxidation. In some embodiments, PECVD generates a plasma comprising at least silicon, oxygen, and carbon. In some embodiments, the plasma also comprises nitrogen and / or hydrogen. The plasma can be generated by flowing a deposition precursor gas comprising silicon, carbon, oxygen, nitrogen, or a combination thereof (e.g., trimethylsilane, methyltriethoxysilane, oxygen (O2), other precursors, or combinations thereof) and a carrier gas (e.g., an inert gas) into a process chamber and generating a plasma containing silicon, carbon, and oxygen therefrom using RF power and / or DC power. PECVD parameters (e.g., deposition temperature, deposition time, deposition gas, pressure, power, bias, etc.) are adjusted to minimize source / drain oxidation, provide an LKD layer 164' having a dielectric constant greater than that of the NFD layer 162, provide an LKD layer 164' having a desired oxygen content, or a combination thereof. In some embodiments, the as-deposited LKD layer 164' has an oxygen content less than that of the oxygen-treated LKD layer 164'. In some embodiments, the oxygen content of the LKD layer 164' is less than approximately 50 at%. In some embodiments, the LKD layer 164' has the same oxygen content as the NFD layer 162. For example, the LKD layer 164 ′ may have an oxygen content of about 40 at % to about 50 at %.

[0039] Sometimes, during processing, as the device 100 is transferred between process systems and / or process chambers, such as from one deposition chamber to another, the exposed surfaces of the device 100 may change when exposed to the external environment. For example, when exposed to an oxygen environment, oxygen may diffuse into and / or react with the NFD layer 162, which may unintentionally increase the oxygen content of the NFD layer 162 (e.g., in some embodiments, to greater than 50 at %). As described herein, this may exacerbate undesirable source / drain oxidation that degrades the performance of the device 100. Therefore, to minimize and / or prevent oxidation of the NFD layer 162 (which may result in unintentional source / drain oxidation), the LKD layer 164' and the NFD layer 162 are deposited in the same process chamber, such as in the same PECVD chamber. In other words, the LKD layer 164' and the NFD layer 162 are formed "in situ."

[0040] refer to Figure 5 The oxygen treatment 165 can drive oxygen into the LKD layer 164' and / or improve (e.g., strengthen) oxygen bonding in the LKD layer 164'. Thus, the oxygen-treated LKD layer 164 has an oxygen content greater than that of the LKD layer 164'. In some embodiments, the LKD layer 164' has an oxygen content less than approximately 50 at%, and the oxygen treatment 165 increases the oxygen content, such that the oxygen-treated LKD layer 164 has an oxygen content greater than or equal to approximately 50 at%. In some embodiments, the oxygen treatment 165 increases the density of the LKD layer 164', such that the density of the oxygen-treated LKD layer 164 is greater than that of the LKD layer 164. In some embodiments, the oxygen treatment 165 increases Si-O bonding, CO bonding, O-O bonding, ON bonding, other types of oxygen bonding, or combinations thereof. For example, the amount and / or strength of oxygen bonding in the oxygen-treated LKD layer 164 can be greater than the amount and / or strength of oxygen bonding in the LKD layer 164'. Increasing the density and enhancing oxygen bonding in the LKD layer 164 ′ (and thus providing a tri-layer ESL 160 with a denser oxygen-treated LKD layer 164 having stronger oxygen bonding) may reduce undesirable oxygen outgassing from the tri-layer ESL 160 during subsequent thermal processes.

[0041] In some embodiments, the oxygen treatment 165 is an oxygen plasma treatment, such as an O2 plasma treatment. In some embodiments, the oxygen plasma treatment includes: flowing an oxygen-containing precursor gas (e.g., O2) and a carrier gas (e.g., He) into a process chamber; thereby generating an oxygen-containing plasma; and bombarding the LKD layer 164' with oxygen-containing species (i.e., active species) excited by the plasma of the oxygen-containing plasma. The active species may include free radicals, ions, neutral particles, electrons, photons, or a combination thereof. The active species may react with the LKD layer 164', for example, by being adsorbed on its surface and triggering a chemical reaction that changes the composition of the LKD layer 164' (e.g., increases its oxygen content) and / or produces a by-product that desorbs from its surface. In some embodiments, the oxygen-containing plasma includes excited neutral atoms and / or molecules (e.g., oxygen radicals, such as O*, O2*, etc.), ionized atoms and / or molecules (e.g., oxygen ions, such as O2+, O2 – 、O+、O – The oxygen-containing gas may include O and / or other suitable oxygen-containing precursors (e.g., O, etc.), atoms and / or molecules (e.g., O, etc.), or combinations thereof. The oxygen-containing gas may include O and / or other suitable oxygen-containing precursors (e.g., the plasma activation process is an O plasma treatment). The carrier gas may be a rare gas and / or an inert gas, such as argon, helium, xenon, neon, krypton, other suitable gases, or combinations thereof. Parameters of the oxygen treatment 165 are adjusted to enhance oxygen incorporation in the LKD layer 164′ (e.g., with silicon, carbon, nitrogen, or a combination thereof), increase the density of the LKD layer 164′, increase the oxygen content in the LKD layer 164′, provide desired oxidation of the LKD layer 164′, or combinations thereof, such as the flow rate and / or concentration of the oxygen-containing precursor gas, the flow rate and / or concentration of the carrier gas, the ratio of the oxygen-containing precursor gas to the carrier gas, temperature, pressure, time, power, bias (voltage) for igniting and / or accelerating the plasma, tilt angle, other suitable parameters, or combinations thereof.

[0042] The disclosed embodiments further recognize that when the oxygen content at the ESL-source / drain interface is greater than 50 at %, undesirable oxidation is more likely to occur between the ESL and the source / drain, and further recognize that oxygen treatments (such as oxygen treatment 165) can improve the quality of the ESL, for example, by increasing its density and / or modifying its composition (e.g., by enhancing and / or increasing oxygen incorporation therein). Thus, a triple-layer ESL 160 is provided with a dual-layer low-k dielectric portion—an NFD layer 162 interfacing with the source / drain structure 150 and an oxygen-treated LKD layer 164 interfacing with the NFD layer 162—wherein the NFD layer 162 is not oxygen-treated, thereby minimizing the oxygen content at the ESL-source / drain interface, and the oxygen-treated LKD layer 164′ is oxygen-treated 165, thereby improving the quality of the dual-layer low-k dielectric portion without substantially increasing the oxygen content at the ESL-source / drain interface. In some embodiments, the oxygen treatment 165 may also increase the density of the NFD layer 162, such that the density of the NFD layer 162 after the oxygen treatment 165 is greater than the density of the NFD layer 162 before the oxygen treatment 165. In some embodiments, the oxygen treatment 165 may also enhance oxygen incorporation in the NFD layer 162, such that the oxygen incorporation in the NFD layer 162 after the oxygen treatment 165 is greater than the oxygen incorporation in the NFD layer 162 before the oxygen treatment 165. However, because the LKD layer 164′ masks the NFD layer 162 during the oxygen treatment 165, any such increase in density and / or improvement in oxygen incorporation is achieved without significantly increasing the oxygen content in the NFD layer 162. For example, the oxygen content at the interface of the NFD layer 162 and the source / drain structure 150 (i.e., at the ESL-source / drain interface) remains less than 50 at % even after the oxygen treatment 165.

[0043] refer to Figure 6 , dielectric layer 166 is formed over oxygen-treated LKD layer 164. In the depicted embodiment, dielectric layer 166 is formed directly on oxygen-treated LKD layer 164. Dielectric layer 166 has a thickness t3 that is less than the spacing between adjacent gate structures 128, such that dielectric layer 166 also partially fills the spacing (and / or distance s) between adjacent gate structures 128. Furthermore, thickness t4 of the three-layer ESL 160 (i.e., the sum of thickness t3, thickness t2, and thickness t1) is less than the spacing between adjacent gate structures 128. Thickness t3 is greater than each of thickness t2 and thickness t1, and thickness t3 can be equal to, greater than, or less than the sum of thickness t2 and thickness t1. In some embodiments, thickness t3 is approximately 2 nm to approximately 3 nm.

[0044] Dielectric layer 166 is formed of a dielectric material having a dielectric constant greater than approximately 3.9, and the dielectric constant of dielectric layer 166 is greater than the dielectric constant of oxygen-treated LKD layer 164. Dielectric layer 166 is also formed of a different dielectric material than a subsequently formed ILD layer (e.g., a silicon oxide layer) to provide sufficient etch selectivity between the tri-layer ESL 160 and the subsequently formed ILD layer. For example, when an etching process is performed on the subsequently formed ILD layer to form source / drain contact openings therein, the etch rate of the dielectric material of dielectric layer 166 for a given etchant of the etching process is sufficiently lower than the etch rate of the subsequently formed ILD layer for the given etchant, so that dielectric layer 166 can serve as an etch stop layer and protect the underlying source / drain structure 150 from the etching process. Without dielectric layer 166, sufficient etch selectivity may not be provided between the ESL located above the source / drain structure 150 and the subsequently formed ILD layer. For example, a given etchant has low etch selectivity between a low-k dielectric ESL (such as the dual-layer low-k dielectric portion of triple-layer ESL 160 (e.g., oxygen-treated LKD layer 164 and / or NFD layer 162)) and a subsequently formed ILD layer, thereby preventing the ESL from acting as an etch stop. In some embodiments, dielectric layer 166 is formed of a dielectric material having a dielectric constant of about 4 to about 10 (i.e., 4≤k≤10). For example, dielectric layer 166 includes silicon and nitrogen, and is a silicon nitride layer. In such an example, the dielectric constant of dielectric layer 166 may be approximately 6.5.

[0045] Dielectric layer 166 is deposited in a different process chamber than oxygen-treated LKD layer 164 and NFD layer 162, and is formed using a different type of deposition process. For example, dielectric layer 166 is formed using atomic layer deposition (ALD) rather than CVD, and is formed in an ALD chamber. In some embodiments, dielectric layer 166 is formed using CVD rather than ALD, but in a different CVD chamber than the one used to form oxygen-treated LKD layer 164 and NFD layer 162. In some embodiments, dielectric layer 166 is formed using another suitable process.

[0046] Thus, the dielectric constant of the tri-layer ESL 160 decreases from the top (e.g., dielectric layer 166) to the bottom (e.g., NFD layer 162). For example, the dielectric constant of the tri-layer ESL 160 can decrease from about 6.5 to about 3.6 from the top to the bottom. In some embodiments, the upper portion of the tri-layer ESL 160 (e.g., dielectric layer 166, which can interface with the upper ILD layer) has a dielectric constant of about 5 to about 8, the middle portion of the tri-layer ESL 160 (e.g., oxygen-treated LKD layer 164 interfaced with dielectric layer 166 and NFD layer 162) has a dielectric constant of about 3.7 to about 4.5, and the lower portion of the tri-layer ESL 160 (e.g., NFD layer 162 interfaced with source / drain structure 150 and gate spacer 132) has a dielectric constant of about 3.6 to about 3.7. For example, the dielectric layer 166 (e.g., SiN layer) has a dielectric constant of approximately 6.5, the oxygen-treated LKD layer 164 (e.g., SiOC layer) has a dielectric constant of approximately 3.8, and the NFD layer 162 (e.g., SiOC layer) has a dielectric constant of approximately 3.7. In another example, the dielectric layer 166 (e.g., SiN layer) has a dielectric constant of approximately 6.5, the oxygen-treated LKD layer 164 (e.g., SiOCN layer) has a dielectric constant of approximately 4.3, and the NFD layer 162 (e.g., SiOC layer) has a dielectric constant of approximately 3.7. In yet another example, the dielectric layer 166 (e.g., SiN layer) has a dielectric constant of approximately 6.5, the oxygen-treated LKD layer 164 (e.g., SiOC layer) has a dielectric constant of approximately 3.7, and the NFD layer 162 (e.g., SiOC layer) has a dielectric constant of approximately 3.6. The parameters of the deposition process (such as the PECVD process and the ALD process) can be adjusted to provide the NFD layer 162, the oxygen-treated LKD layer 164, and the dielectric layer 166 having the desired dielectric constant, while providing the triple-layer ESL 160 having a dielectric constant that decreases from top to bottom, so that the triple-layer ESL 160 can provide sufficient etching selectivity while also exhibiting a lower effective dielectric constant (and thereby reducing effective capacitance).

[0047] refer to Figure 7 , an interlayer dielectric (ILD) layer 168 is formed over the tri-layer ESL 160. In the depicted embodiment, the ILD layer 168 is formed directly on the dielectric layer 166 of the tri-layer ESL 160, and the ILD layer 168 fills the remaining portion of the space (and / or distance s) between adjacent gate structures 128. The ILD layer 168 can be formed by CVD, flowable CVD (FCVD), a high aspect ratio deposition (HARP) process, a high density plasma CVD (HDPCVD), other suitable deposition processes, or combinations thereof.

[0048] The ILD layer 168 includes a dielectric material that is different from the dielectric material of the dielectric layer 166 to enable selective etching therebetween. In the depicted embodiment, the ILD layer 168 is a dielectric layer including silicon and oxygen. In some embodiments, the dielectric constant of the ILD layer 168 is less than the dielectric constant of the dielectric layer 166. For example, the ILD layer 168 may be a silicon oxide layer (e.g., a SiO2 layer), which may have a dielectric constant of approximately 3.9 (k≈3.9). In another example, the ILD layer 168 may be a porous silicon oxide layer, which may be configured to have a dielectric constant less than approximately 2.5 (k≈2.5). In yet another example, the ILD layer 168 may be a carbon-doped oxide layer (e.g., a SiOC layer), which may be configured to have a dielectric constant less than approximately 2.5 (k≈2.5). In some embodiments, the ILD layer 168 includes silicon oxide, carbon-doped oxide, silicon oxynitride, oxide formed from tetraethyl orthosilicate (TEOS), PSG, BSG, boron-doped PSG (BPSG), fluorine-doped silicate glass (FSG), xerogel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene (BCB)-based dielectric materials, polyimide, other suitable dielectric materials, or combinations thereof. In some embodiments, the ILD layer 168 has a multi-layer structure.

[0049] refer to Figure 8 A chemical mechanical polishing (CMP) process and / or other planarization process is performed on the ILD layer 168 and the tri-layer ESL 160. The CMP process is performed until the gate structure 128, such as its dummy gate stack 130, is reached and exposed. The CMP process may remove portions of the ILD layer 168 and tri-layer ESL 160 that extend above and / or are disposed above the top of the gate structure 128. The remaining portions of the ILD layer 168 and tri-layer ESL 160 form a device-level dielectric layer 170 above the source / drain structure 150. The device-level dielectric layer 170 may fill the spaces between adjacent gate structures 128 (e.g., between their gate spacers 132) and / or between adjacent source / drain structures 150 (e.g., along the Y direction and / or in the YZ plane). In some embodiments, the dummy gate stack 130 (e.g., its hard mask) and / or the gate spacers 132 serve as a CMP stop layer. In some embodiments, the CMP process is performed for a time sufficient to expose the dummy gate stack 130. The CMP process can planarize the top surface of the device-level dielectric layer 170 (which can be formed by each layer of the ILD layer 168 and the three-layer ESL 160), the top surface of the dummy gate stack 130, and the top surface of the gate spacer 132. After the CMP process, the planarized top surface can form a substantially flat surface of the device 100.

[0050] refer to Figure 9In some embodiments, a gate replacement process may be performed to replace the dummy gate stack 130 with the gate stack 180. In some embodiments, the dummy gate stack 130 is removed to form a gate opening (e.g., between the gate spacers 132) that exposes the multilayer stack 110 (such as its semiconductor layer 120 and sacrificial layer 115) in the channel region of the device 100. For example, the etching process selectively removes the dummy gate stack 130 while negligibly (or not) removing the device-level dielectric layer 170, the gate spacers 132, the internal spacers 145, the sacrificial layer 115, the semiconductor layer 120, or a combination thereof. The etching process is a dry etch, a wet etch, other suitable etches, or a combination thereof. In some embodiments, the etching process may use a patterned mask layer as an etch mask, and the patterned mask layer may cover the device-level dielectric layer 170 and / or the gate spacers 132 and have an opening therein that exposes the dummy gate stack 130.

[0051] During the gate replacement process, before forming the gate stack 180, a channel release process can be performed to form a suspended channel layer. For example, the sacrificial layer 115 exposed by the gate opening is selectively removed to form a gap between the semiconductor layers 120 and between the semiconductor layers 120 and the mesas 105', thereby suspending the semiconductor layers 120 in the channel region. In the depicted embodiment, each channel region has three suspended semiconductor layers 120 (hereinafter referred to as channel layers 120') stacked vertically in the z-direction to provide three channels through which current can flow between the corresponding source / drain structures 150 during operation of the transistors of the device 100. In some embodiments, the etching process selectively etches the sacrificial layer 115 while minimally (to no) etching the semiconductor layers 120, the mesas 105P', the gate spacers 132, the inner spacers 145, the device-level dielectric layer 170, or a combination thereof. In some embodiments, an etchant is selected for the etching process that etches silicon germanium (e.g., sacrificial layer 115) at a higher rate than silicon (e.g., semiconductor layer 120 and mesas 105') and dielectric materials (e.g., gate spacers 132, internal spacers 145, device-level dielectric layers 170, etc.) (i.e., the etchant has a high etch selectivity relative to silicon germanium). In some embodiments, an etchant is selected for the etching process that etches dielectric materials having a first composition (e.g., sacrificial layer 115) at a higher rate than silicon (e.g., semiconductor layer 120 and mesas 105') and dielectric materials having a composition different from the first composition (e.g., gate spacers 132, internal spacers 145, device-level dielectric layers 170, etc.) (i.e., the etchant has a high etch selectivity relative to dielectric materials having the first composition). The etching process is a dry etch, a wet etch, other suitable etches, or a combination thereof. In some embodiments, before performing the etching process, an oxidation process may convert the sacrificial layer 115 into a silicon germanium oxide layer, and the etching process may then remove the silicon germanium oxide layer. In some embodiments, an etching process is performed to modify the profile of the semiconductor layer 120 / channel layer 120 ′ to achieve a target channel size / shape.

[0052] Then, a gate stack 180 (also referred to as a high-k / metal gate) can be formed in the gate opening and / or gap. The gate stack 180 has a portion disposed between the respective gate spacers 132 and a portion disposed between the respective inner spacers 145. The gate stack 180 is also disposed between the channel layers 120' and between the channel layers 120' and the mesas 105P'. In the depicted embodiment, where the device 100 includes a GAA transistor, the gate stack 180 can, for example, surround and engage the respective channel layers 120' in the YZ plane (see, for example, FIG. Figure 16AIn some embodiments, the gate stack 180 may wrap around and / or partially surround the corresponding channel layer 120 ′ (ie, be disposed on at least two sides thereof).

[0053] Each gate stack 180 may include a gate dielectric 182. The gate dielectric 182 is disposed on the channel layer 120', the mesa 105P', the inner spacer 145, the gate spacer 132, or a combination thereof. The gate dielectric 182 may have the same or different compositions and / or configurations. The gate dielectric 182 includes at least one dielectric layer, such as an interfacial layer and / or a high-k dielectric layer. The interfacial layer includes a dielectric material, such as SiO2, SiGeO x , HfSiO, SiON, other dielectric materials or combinations thereof. The high-k dielectric layer includes a high-k dielectric material, which generally refers to a dielectric material having a dielectric constant greater than that of silicon dioxide, such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, HfAlO x , ZrO, ZrO2, ZrSiO2, AlO, AlSiO, Al2O3, TiO, TiO2, LaO, LaSiO, LaO3, La2O3, Ta2O3, Ta2O5, Y2O3, SrTiO3, BaZrO, BaTiO3 (BTO), (Ba, Sr)TiO3 (BST), HfO2-Al2O3, other high-k dielectric materials, or combinations thereof. In some embodiments, each gate dielectric 182 may include a hafnium-based oxide (e.g., HfO2) layer and / or a zirconium-based oxide (e.g., ZrO2) layer.

[0054] Each gate stack 180 may include a gate electrode 184. The gate electrode 184 is disposed over the gate dielectric 182. The gate electrodes 184 may have the same or different compositions and / or configurations, and include at least one conductive layer formed of a conductive material, which may include Al, Cu, Ti, Ta, W, Mo, Co, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive compositions, or combinations thereof. In some embodiments, the gate electrode 184 includes a work function layer. The work function layer is a conductive layer tuned to have a desired work function, such as an n-type work function or a p-type work function. The work function layer includes a work function metal and / or its alloys, such as Ti, Ta, Al, Ag, Mn, Zr, W, Ru, Mo, TiC, TiAl, TiAlC, TiAlSiC, TaC, TaCN, TaSiN, TiSiN, TiN, TaN, TaSN, WN, WCN, ZrSi2, MoSi2, TaSi2, NiSi2, TaAl, TaAlC, TaSiAlC, TiAlN, or combinations thereof. In some embodiments, the gate electrode 184 includes a bulk layer located above the gate dielectric 182 and / or the work function layer. The bulk layer may include Al, W, Cu, Ti, Ta, TiN, TaN, polysilicon, other suitable metals and / or their alloys, or combinations thereof. In some embodiments, the gate electrode 184 includes a barrier layer located above the work function layer and / or the gate dielectric 182. The barrier layer includes a material that can prevent diffusion and / or reaction of components between adjacent layers and / or promote adhesion between adjacent layers (such as between the work function layer and the bulk layer). In some embodiments, the barrier layer includes a metal and nitrogen, such as titanium nitride, tantalum nitride, tungsten nitride, titanium silicon nitride, tantalum silicon nitride, other suitable metal nitrides, or combinations thereof.

[0055] Forming the gate stack 180 may include: depositing a gate dielectric material (e.g., an interfacial layer, a high-k dielectric layer, etc.) that partially fills the gate opening; depositing a gate electrode material (e.g., a work function layer, a barrier layer, a bulk layer, etc.) that fills the remaining portion of the gate opening; and performing a planarization process to remove portions of the gate dielectric material and / or portions of the gate electrode material above the device-level dielectric layer 170. In some embodiments, such as depicted, fabrication of the device 100 may further include: etching back the gate stack 180; and forming a hard mask (e.g., a self-aligned cap (SAC) structure 185) over the etched-back gate stack 180. The SAC structure 185 includes a different material than the device-level dielectric layer 170 (e.g., its ILD layer 168) and / or subsequently formed dielectric layers to achieve etch selectivity. In some embodiments, the SAC structure 185 includes silicon and nitrogen and / or carbon, such as silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride, other silicon nitrides, other silicon carbides, or combinations thereof. In some embodiments, the SAC structure 185 includes metal and oxygen and / or nitrogen, such as aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, hafnium oxide, aluminum zirconium oxide, other metal oxides, other metal nitrides, or combinations thereof. While the depicted embodiment fabricates the gate stack 180 according to a gate-last process, the disclosed embodiments contemplate embodiments in which the metal gate stack of the device 100 can be fabricated according to a gate-first process or a hybrid gate-last / gate-first process.

[0056] refer to Figures 10 to 15 , a source / drain contact is formed in the device level dielectric layer 170 to one of the source / drain structures 150. Figure 10 A dielectric layer 186 may be formed over the device-level dielectric layer 170 and the gate structure 128. In some embodiments, the dielectric layer 186 includes a contact etch stop layer (CESL) 187 and an ILD layer 188. The ILD layer 188 may be configured and / or formed similarly to the ILD layer 168. For example, the ILD layer 188 may include a dielectric material including, for example, silicon oxide, carbon-doped silicon oxide, an oxide formed from TEOS, PSG, BSG, BPSG, FSG, xerogel, aerogel, amorphous fluorinated carbon, parylene, a BCB-based dielectric material, polyimide, other suitable dielectric materials, or combinations thereof. The dielectric material may be the same dielectric material as the dielectric material of the ILD layer 168 or a different dielectric material than the dielectric material of the ILD layer 168. In some embodiments, the ILD layer 188 is a low-k dielectric layer, such as a dielectric layer containing silicon and oxygen having a dielectric constant of less than approximately 3.9 and, in some embodiments, less than approximately 2.5.

[0057] CESL 187 includes a different material than ILD layer 188 to achieve etch selectivity therebetween, such as a dielectric material different from the dielectric material of ILD layer 188. In some embodiments, CESL 187 includes silicon and nitrogen. For example, CESL 187 is a silicon nitride layer and / or a silicon oxynitride layer. The disclosed embodiments contemplate ILD layer 188 and / or CESL 187 having a multilayer structure and / or including multiple dielectric materials. In some embodiments, forming dielectric layer 186 includes: depositing CESL 187 over device-level dielectric layer 170; depositing ILD layer 188 over CESL 187; and performing a CMP and / or other planarization process on ILD layer 188.

[0058] refer to Figure 11 , forming a source / drain contact opening 190 that exposes a corresponding one of the source / drain structures 150. For example, the source / drain contact opening 190 extends through the ILD layer 188, the CESL 187, the ILD layer 168, and the tri-layer ESL 160 to expose one of the source / drain structures 150 disposed between the gate structures 128. When forming the source / drain contact opening 190, portions of the tri-layer ESL 160 along the sidewalls of the gate spacers 132 may be removed. In the depicted embodiment, the dielectric layer 166 is completely removed along the sidewalls of the gate spacers 132, and the oxygen-treated LKD layer 164 is partially removed along the sidewalls of the gate spacers 132. In such an embodiment, the source / drain contact opening 190 has sidewalls formed by the ILD layer 188, the CESL 187, the oxygen-treated LKD layer 164, and the NFD layer 162. Furthermore, in such an embodiment, the thickness t4 of the portion of the tri-layer ESL 160 along the sidewalls of the gate spacer 132 is reduced to a thickness t6. In some embodiments, the thickness t6 is from about 0.75 nm to about 2.75 nm. For example, the thickness t6 may be from about 1.5 nm to about 1.75 nm. Furthermore, in such an embodiment, the thickness t2 of the oxygen-treated LKD layer 164 may be reduced to a thickness t7. In some embodiments, the thickness t7 is less than 1 nm.

[0059] In some embodiments, the thickness of the oxygen-treated LKD layer 164 along the sidewalls of the gate spacers 132 can be substantially uniform or vary along the gate height direction (e.g., along the z-direction), depending on the cross-sectional profile and / or shape of the source / drain contact openings 190. In the depicted embodiment, the source / drain contact openings 190 have a width that decreases from top to bottom (i.e., the source / drain contact openings 190 have a tapered width), and the thickness of the oxygen-treated LKD layer 164 increases from top to bottom (i.e., the oxygen-treated LKD layer 164 has a tapered thickness along the sidewalls of the gate spacers 132). For example, the thickness of the oxygen-treated LKD layer 164 increases from thickness t7 to thickness t2. In some embodiments, the oxygen-treated LKD layer 164 is partially removed along the sidewalls of the gate spacers 132 from top to bottom, and the thickness of the oxygen-treated LKD layer 164 increases from thickness t7 to a thickness greater than thickness t7 but less than thickness t2. The disclosed embodiments contemplate various cross-sectional profiles and / or shapes for the source / drain contact openings 190. For example, the source / drain contact openings 190 can have a tapered width that increases from top to bottom, and in such embodiments, the thickness of the oxygen-treated LKD layer 164 can decrease from top to bottom. In another example, the source / drain contact openings 190 can have a substantially uniform width from top to bottom (i.e., the source / drain contact openings 190 can have substantially vertical sidewalls), and in such embodiments, the thickness of the oxygen-treated LKD layer 164 can be substantially uniform from top to bottom. In such embodiments, the substantially uniform thickness of the oxygen-treated LKD layer 164 can be thickness t2 or less than thickness t2, such as when it is partially removed. The disclosed embodiments also contemplate forming more than one source / drain contact opening 190, such as a source / drain contact opening to each of the source / drain structures 150.

[0060] The device-level dielectric layer 170 and the dielectric layer 186 can be patterned by photolithography and etching processes. For example, forming the source / drain contact openings 190 may include: performing a photolithography process to form a patterned mask layer 191 above the ILD layer 188; and performing an etching process to transfer the pattern defined by one or more openings 1910 in the patterned mask layer 191 (which overlap with the corresponding source / drain structures 150) to the ILD layer 188, the CESL 187, the ILD layer 168, and the tri-layer ESL 160. The photolithography process may include: forming a resist layer (e.g., by spin coating) above the ILD layer 188; performing a pre-exposure bake process; performing an exposure process using a mask; performing a post-exposure bake process; and performing a development process. During the exposure process, the resist layer can be exposed to radiation energy (such as ultraviolet (UV) light, deep UV (DUV) light or extreme UV (EUV) light), wherein the mask blocks, transmits and / or reflects radiation to the resist layer, depending on the mask pattern and / or mask type (e.g., binary mask, phase shift mask or EUV mask) of the mask, so that an image is projected onto the resist layer corresponding to the mask pattern. Alternatively, the exposure process can be implemented or replaced by other methods, such as maskless lithography, electron beam writing, ion beam writing and / or nanoimprint technology. Because the resist layer is sensitive to radiation energy, the exposed (or non-exposed) portion of the resist layer undergoes chemical changes, and the exposed (or non-exposed) portion of the resist layer dissolves during the development process, depending on the properties of the resist layer and the properties of the developer used in the development process. After development, the patterned resist layer includes a resist pattern corresponding to the mask. In some embodiments, the patterned mask layer 191 is a patterned resist layer. In some embodiments, the patterned resist layer is used as an etch mask to remove portions of the hard mask layer, thereby forming a patterned mask layer 191. In some embodiments, the patterned mask layer 191 includes a patterned resist layer and a patterned hard mask layer, and the patterned resist layer is disposed over the patterned hard mask layer. In the depicted embodiment, the patterned mask layer 191 is formed directly on the dielectric layer 186 (e.g., the ILD layer 188 thereof). In some embodiments, the dielectric layer 186 is omitted, and the patterned mask layer 191 is formed directly on the device-level dielectric layer 170 and the gate structure 128.

[0061] refer to Figure 12 and Figure 13 , a contact spacer 192S partially filling the source / drain contact opening 190 is formed in the source / drain contact opening 190 . The contact spacer 192S is formed along the sidewall of the source / drain contact opening 190 and covers the sidewall of the source / drain contact opening 190 . Figure 12After removing the patterned mask layer 191 by any suitable process, a dielectric contact liner 192 can be deposited over the dielectric layer 186 to partially fill the source / drain contact openings 190. The dielectric contact liner 192 is disposed on the top surface of the ILD layer 188, the sidewalls of the source / drain contact openings 190, and the bottom of the source / drain contact openings 190. For example, the dielectric contact liner 192 covers the sidewalls of the source / drain contact openings 190 formed by the ILD layer 188, the CESL 187, the oxygen-treated LKD layer 164, and the NFD layer 162. The dielectric contact liner 192 also covers the bottom of the source / drain contact openings 190 formed by the exposed source / drain structure 150 (e.g., the semiconductor layer 158 thereof). The dielectric contact liner 192 is deposited by any suitable process. For example, the dielectric contact liner 192 is conformally deposited by ALD such that the dielectric contact liner 192 has a substantially uniform thickness t8 .

[0062] Dielectric contact liner 192 comprises a dielectric material different from the dielectric material of ILD layer 188, oxygen-treated LKD layer 164, and NFD layer 162 to enable selective etching therebetween. The dielectric material can be configured to hinder and / or prevent diffusion of metal components from the conductive portions of the source / drain contacts into dielectric layer 186, ILD layer 168, tri-layer ESL 160, or a combination thereof. In the depicted embodiment, dielectric contact liner 192 comprises silicon and nitrogen. For example, dielectric contact liner 192 is a silicon nitride layer. In some embodiments, dielectric contact liner 192 is a metal oxide layer and / or a metal nitride layer.

[0063] refer to Figure 13, portions of the dielectric contact liner 192 are removed by an etching process, such as a dry etch, a wet etch, another suitable etch, or a combination thereof. The remaining portions of the dielectric contact liner 192 form contact spacers 192S, which cover the sidewalls of the source / drain contact openings 190. Thus, after the etching process, the source / drain contact openings 190 have sidewalls formed by the contact spacers 192S and a bottom formed by the exposed source / drain structure 150 (e.g., its semiconductor layer 158). The contact spacers 192S extend longitudinally along the z-direction and have a thickness t9 (e.g., along the x-direction). In the depicted embodiment, the thickness t9 is approximately equal to the thickness t8. In some embodiments, the etching process may thin the dielectric contact liner 192 along the x-direction and / or the y-direction, such that the thickness t9 is less than the thickness t8. In some embodiments, the contact spacers 192S have a substantially uniform thickness along their length. For example, the thickness t9 is substantially the same from the top to the bottom of the source / drain contact opening 190 (i.e., along the length of the contact spacer 192S). In some embodiments, the contact spacers 192S have a tapered thickness along their length. For example, the thickness t9 can increase from the top to the bottom of the source / drain contact opening 190 (i.e., along the length of the contact spacer 192S). In another example, the thickness t9 can decrease from the top to the bottom of the source / drain contact opening 190 (i.e., along the length of the contact spacer 192S).

[0064] The etching process can selectively etch the dielectric contact liner while minimally (or not) etching the ILD layer 188, CESL 187, oxygen-treated LKD layer 164, NFD layer 162, semiconductor layer 158, or a combination thereof. In some embodiments, an etchant is selected for the etching process that etches the dielectric material having a first composition (e.g., silicon nitride) at a higher rate than the semiconductor material (e.g., silicon and / or germanium) and a dielectric material having a composition different from the first composition (e.g., silicon oxycarbide, silicon oxide, silicon oxycarbonitride, etc.) (i.e., the etchant has a high etch selectivity relative to the dielectric material having the first composition). In some embodiments, the etching process is an anisotropic etch, which generally refers to an etch process having different etch rates in different directions, thereby causing the etching process to remove material in a specific direction. For example, the etch process can have a vertical etch rate that is greater than the horizontal etch rate (in some embodiments, the horizontal etch rate is zero). Thus, the anisotropic etching process substantially removes material in the vertical direction (here, the z-direction) while minimally (or not) removing material in the horizontal direction (here, the x-direction and / or the y-direction). In such an embodiment, the anisotropic etch removes portions of the dielectric contact liner 192 that are located on horizontally oriented surfaces of the device 100 (i.e., from the top surface of the ILD layer 188 and the top surface of the source / drain structure 150), but does not remove or minimally removes portions of the dielectric contact liner 192 that are located on vertically oriented surfaces (i.e., in the depicted embodiment, portions of the ILD layer 188, CESL 187, oxygen-treated LKD layer 164, and NFD layer 162 that form sidewalls of the source / drain contact openings).

[0065] refer to Figure 14 and Figure 15 , can be achieved by interposing a gap between the dielectric layer 186 and the contact spacer 192S ( Figure 14 ) and performing a planarization process (e.g., a CMP process) to remove excess conductive contact material 194' (such as conductive contact material 194' disposed above the top surface of dielectric layer 186) to form source / drain contacts 194 ( Figure 15 ). The remaining portions of the conductive contact material 194' form the source / drain contacts 194. A planarization process may be performed until the dielectric layer 186 is reached and exposed. In some embodiments, the ILD layer 188 may be a CMP stop layer, and the CMP process may planarize the top surface of the device 100 (e.g., the top surface of the source / drain contacts 194, the top surface of the ILD layer 188, and the top surface of the contact spacers 192).

[0066] The conductive contact material 194' includes tungsten, ruthenium, cobalt, molybdenum, copper, aluminum, titanium, tantalum, iridium, palladium, platinum, nickel, tin, gold, silver, other suitable metals, alloys thereof, or combinations thereof. In some embodiments, forming the conductive contact material 194' includes depositing a metal bulk material, such as tungsten, cobalt, or ruthenium, over the device 100. In such an embodiment, the source / drain contact 194 may include a tungsten plug, a cobalt plug, or a ruthenium plug. The metal bulk material may have a multilayer structure, such as a bulk layer disposed over a seed layer. The metal bulk material may be formed by a blanket deposition process, such as blanket CVD. In some embodiments, the blanket deposition process is physical vapor deposition (PVD), ALD, electroplating, chemical plating, other suitable processes, or combinations thereof. In some embodiments, the metal bulk material is formed by a bottom-up deposition process, which generally refers to a deposition process that fills the source / drain contact openings 190 from the bottom to the top. In some embodiments, the bottom-up deposition process includes multiple deposition / etch cycles, each of which may include depositing a conductive material and sequentially etching back the conductive material.

[0067] In some embodiments, source / drain contact 194 is barrier-free. For example, conductive material 194′ includes a metal bulk material / layer but no barrier / liner material / layer. In such embodiments, the metal plug of source / drain contact 194 (e.g., formed from a metal bulk material / layer) can directly contact its surrounding dielectric material, such as contact spacer 192S (or ILD layer 188, CESL 187, and triple ESL 160, such as in embodiments where contact spacer 192S is omitted). In some embodiments, source / drain contact 194 includes at least one liner / barrier layer between its metal plug and the surrounding dielectric material. In such embodiments, forming conductive contact material 194′ further includes depositing a barrier / liner material over dielectric layer 186 prior to depositing the metal bulk material. The barrier / liner material partially fills and lines source / drain contact opening 190, and the metal bulk material is formed over the barrier / liner material and fills the remaining portion of source / drain contact opening 190. In such an embodiment, a barrier layer / liner is disposed between and separates the metal plug of the source / drain contact 194 (e.g., formed of a metal bulk material / layer) and its surrounding dielectric material, such as the contact spacer 192S (or the ILD layer 188, the CESL 187, and the tri-layer ESL 160, such as in an embodiment where the contact spacer 192S is omitted). The barrier / liner material may promote adhesion between the contact spacer 192S and the metal bulk material and / or prevent diffusion of metal components from the metal bulk material into adjacent dielectric materials, such as the contact spacer 192S, the ILD layer 188, the CESL 187, and the tri-layer ESL 160, or a combination thereof. In some embodiments, the barrier / liner material includes tantalum, tantalum nitride, tantalum aluminum nitride, tantalum silicon nitride, tantalum carbide, titanium, titanium nitride, titanium silicon nitride, titanium aluminum nitride, titanium carbide, tungsten, tungsten nitride, tungsten carbide, molybdenum nitride, cobalt, cobalt nitride, ruthenium, palladium, or combinations thereof.

[0068] In some embodiments, before or after forming the conductive material 194', a silicide structure 198 is formed over the exposed source / drain structure 150. For example, the silicide structure 198 can be formed by depositing a metal layer over the semiconductor layer 158 and heating the device 100, such as by an annealing process, so that the components of the semiconductor layer 158 (e.g., silicon and / or germanium) react with the metal components in the metal layer. The metal layer includes any metal component suitable for promoting silicide formation, such as nickel, platinum, palladium, vanadium, titanium, cobalt, tantalum, ytterbium, zirconium, other suitable metals, or combinations thereof. Thus, the silicide structure 198 includes the metal component and the components of the semiconductor layer 158 (e.g., silicon and / or germanium). In some embodiments, the metal layer is a titanium-containing layer, a cobalt-containing layer, or a nickel-containing layer, and the silicide structure 198 includes titanium, cobalt, or nickel and silicon and / or germanium. In such embodiments, the silicide structure 198 can be a titanium silicide layer, a nickel silicide layer, or a cobalt silicide layer. In some embodiments, during the silicidation process, portions of semiconductor layer 158 are converted into silicide structures 198. Any unreacted metal, such as the remaining portion of the metal layer, is selectively removed by a suitable process (such as an etching process). Silicide structures 198 can be considered to be portions of corresponding source / drain structures 150 or corresponding source / drain contacts 194.

[0069] Source / drain contacts 194 are coupled to the source / drain structure 150 and / or the silicide structure 198. The source / drain contacts 194 are separated and electrically isolated from the gate stack 180 by contact spacers 192S, the tri-layer ESL 160, and the gate spacers 132. Because the source / drain contacts 194 and the gate electrode 184 of the gate structure 128 are conductive materials separated by dielectric material (e.g., the gate spacers 132 and the tri-layer ESL 160 (and, in some embodiments, the contact spacers 192S)), a parasitic capacitor may form between them. Parasitic capacitance and / or capacitive coupling between the source / drain contacts 194 and the gate electrode 184 can degrade device performance, for example, by slowing down and / or delaying electrical signals. The disclosed tri-layer ESL 160 reduces parasitic capacitance by reducing the dielectric constant of the dielectric material between the source / drain contacts 194 and the gate electrode 184. For example, because capacitance is proportional to the dielectric constant of the dielectric material between two conductive plates (e.g., source / drain contacts 194 and gate electrode 184), capacitance decreases as the dielectric constant of the dielectric material decreases. In the depicted embodiment, because triple-layer ESL 160 is configured with a dual-layer low-k dielectric layer (e.g., NFD layer 162 and oxygen-treated LKD layer 164) and dielectric layer 166, triple-layer ESL 160 provides a desired etch selectivity between triple-layer ESL 160 (e.g., upper dielectric layer 166 (e.g., SiN layer)) and ILD layer 168 while exhibiting a lower effective capacitance than a nitride-only ESL, thereby providing a dielectric material with a lower effective capacitance between source / drain contacts 194 and gate electrode 184. In particular, reducing the nitrogen content of the ESL formed over the gate structure 128 and the source / drain structure 150 (e.g., by configuring the tri-layer ESL 160 with an NFD layer 162 (e.g., a SiOC layer) and, in some embodiments, a LKD layer 164 (e.g., a SiOC layer having a higher oxygen content) without nitrogen and oxygen treatment) can provide an ESL having a dielectric constant of less than 3.9. Reducing the effective capacitance can improve electrical signal transmission, thereby increasing device speed and / or improving overall device performance. Furthermore, because the tri-layer ESL 160 is configured to have a dielectric constant that decreases from top to bottom, even if portions of the tri-layer ESL 160 are removed during source / drain contact formation and / or during additional fabrication of the device 100, the dielectric constant of the remaining portion of the tri-layer ESL 160 located between the source / drain contacts 194 and the gate electrode 184 is lower than the dielectric constant of silicon oxide.

[0070] The disclosed embodiments contemplate various configurations of the three-layer ESL 160 and source / drain contacts 194 that may result from process variations, such as Figures 17 to 23In some embodiments, at least a portion of the oxygen-treated LKD layer 164 is completely removed along the sidewalls of the gate spacers 132, such as Figure 17 In such an embodiment, the NFD layer 162 of the triple ESL 160 is located between a first portion of the source / drain contact 190 and a first portion of the gate stack 180 (e.g., an upper portion thereof), while the NFD layer 162 of the triple ESL 160 and the oxygen-treated LKD layer 164 are both located between a second portion of the source / drain contact 190 and a second portion of the gate stack 180 (e.g., a lower portion thereof). In some embodiments, the dielectric layer 166 is partially removed along the sidewalls of the gate spacers 132, such as Figure 18 In such an embodiment, the NFD layer 162 and the oxygen-treated LKD layer 164 of the three-layer ESL 160 are located between a first portion of the source / drain contact 190 and a first portion of the gate stack 180 (e.g., an upper portion thereof), while the NFD layer 162, the oxygen-treated LKD layer 164, and the dielectric layer 166 of the three-layer ESL 160 are located between a second portion of the source / drain contact 190 and a second portion of the gate stack 180 (e.g., a lower portion thereof). In some embodiments, the contact spacer 192S is omitted from the source / drain contact structure of the device 100, such that the source / drain contact 194 directly contacts the three-layer ESL 160, such as Figures 19 to 21 In such an embodiment, the source / drain contacts 194 may directly contact the oxygen treated LKD layer 164 ( Figure 19 ), NFD layer 162 and oxygen-treated LKD layer 164 ( Figure 20 ) or oxygen treated LKD layer 164 and dielectric layer 166 ( Figure 21 In some embodiments, the source / drain contacts 194 or contact spacers 192S directly contact the NFD layer 162 but do not contact the LKD layer 164 and the dielectric layer 166, such as when these layers are completely removed when forming the source / drain contact openings 190. In some embodiments, reference is made to Figure 22 When planarizing the ILD layer 168 and / or the tri-layer ESL 160, a recess D may be generated, such as Figure 8 As described. Figure 22 In this embodiment, the planarization process may completely remove the upper portion of the dielectric layer 166 and partially remove the upper portion of the oxygen-treated LKD layer 164. In such an embodiment, the CESL 187 (eg, silicon nitride layer) may fill the recess D, such as Figure 23 , and CESL 187 may also be disposed between gate stack 180 (eg, an upper portion thereof) and source / drain contacts 194 (and, in some embodiments, contact spacers 192S), such as Figure 24 In such an embodiment, the CESL 187 may be disposed between the upper portion of the triple ESL 160 and the source / drain contacts 194 (and in some embodiments, the contact spacers 192S), such as Figure 24 Described in.

[0071] The present disclosure provides many different embodiments. An exemplary method includes forming a three-layer etch stop layer above the source / drain by: forming a nitrogen-free low-k dielectric layer on the source / drain; forming an oxygen-treated low-k dielectric layer on the nitrogen-free low-k dielectric layer; and forming a dielectric layer on the oxygen-treated low-k dielectric layer. The nitrogen-free dielectric layer has a first dielectric constant, the oxygen-treated low-k dielectric layer has a second dielectric constant greater than the first dielectric constant, and the dielectric layer has a third dielectric constant greater than the second dielectric constant and the first dielectric constant. In some embodiments, the nitrogen-free dielectric layer is formed to have a first thickness, the oxygen-treated low-k dielectric layer is formed to have a second thickness, and the dielectric layer is formed to have a third thickness. The third thickness is greater than each of the first thickness and the second thickness.

[0072] In some embodiments, the method further includes forming an interlayer dielectric layer above the three-layer etch stop layer. In some embodiments, the method further includes: removing portions of the three-layer etch stop layer and portions of the ILD layer to form source / drain contact openings exposing the source / drain; and forming source / drain contact structures in the source / drain contact openings. In some embodiments, forming the dielectric layer includes performing an atomic layer deposition process.

[0073] In some embodiments, the nitrogen-free low-k dielectric layer and the oxygen-treated low-k dielectric layer are each formed of an oxygen-containing dielectric material, wherein a first oxygen content of the oxygen-containing dielectric material of the nitrogen-free low-k dielectric layer is less than a second oxygen content of the oxygen-containing dielectric material of the oxygen-treated low-k dielectric layer. In some embodiments, the first oxygen content is less than about 50 atomic percent (at%), and the second oxygen content is greater than 50 at%.

[0074] In some embodiments, forming the nitrogen-free low-k dielectric layer includes depositing a first SiOC layer, and forming the oxygen-treated low-k dielectric layer includes depositing a second SiOC layer and oxygen-treating the second SiOC layer. In some embodiments, forming the dielectric layer includes forming a SiN layer.

[0075] In some embodiments, forming the nitrogen-free low-k dielectric layer includes performing a first plasma-enhanced chemical vapor deposition process, and forming the oxygen-treated low-k dielectric layer includes performing a second plasma-enhanced chemical vapor deposition process, and performing the oxygen treatment after performing the second plasma-enhanced chemical vapor deposition process. In some embodiments, no oxygen treatment is performed between performing the first plasma-enhanced chemical vapor deposition process and performing the second plasma-enhanced chemical vapor deposition process. In some embodiments, the first plasma-enhanced chemical vapor deposition process is performed at a deposition temperature of about 200° C. to about 600° C. and a deposition time of about 6 minutes to about 1 hour. In some embodiments, the second plasma-enhanced chemical vapor deposition process is performed at a deposition temperature of about 200° C. to about 600° C. and a deposition time of about 6 minutes to about 1 hour. In some embodiments, the second plasma-enhanced chemical vapor deposition process deposits a low-k dielectric layer over the nitrogen-free low-k dielectric layer, and the oxygen treatment exposes the low-k dielectric layer to O2 plasma.

[0076] Another exemplary method includes forming a contact etch stop layer (CESL) on the source / drain by depositing a first SiOC layer on the source / drain; depositing a second SiOC layer on the first SiOC layer; oxygen-treating the second SiOC layer; and depositing a SiN layer on the oxygen-treated second SiOC layer. The method also includes forming an interlayer dielectric (ILD) layer on the CESL; and forming source / drain contacts to the source / drain. The source / drain contacts are formed in the CESL and the ILD layer. In some embodiments, no oxygen treatment is performed between depositing the first SiOC layer and depositing the second SiOC layer. In some embodiments, the first SiOC layer and the second SiOC layer are deposited in the same deposition process chamber. In some embodiments, the first SiOC layer is deposited by a first plasma-enhanced chemical vapor deposition (PECVD) process, and the second SiOC layer is deposited by a second PECVD process. In some embodiments, the SiN layer is deposited by atomic layer deposition. In some embodiments, the deposition temperature for depositing the first SiOC layer is less than approximately 600° C. In some embodiments, the deposition temperature for depositing the second SiOC layer is less than approximately 600° C. In some embodiments, the deposition time for depositing the first SiOC layer is less than about 1 hour. In some embodiments, the deposition time for depositing the second SiOC layer is less than about 1 hour. In some embodiments, forming source / drain contacts to the source / drain includes completely removing a portion of the SiN layer and removing a portion of the second SiOC layer along a sidewall portion of the gate spacer.

[0077] An exemplary device structure includes: a gate stack; a gate spacer disposed along a sidewall of the gate stack; a source / drain disposed adjacent to the gate spacer; a source / drain contact structure disposed on the source / drain; and a contact etch stop layer disposed between the gate spacer and the source / drain contact structure. The contact etch stop layer has a nitrogen-free portion that interfaces with the source / drain and the gate spacer. In some embodiments, the nitrogen-free portion that interfaces with the source / drain and the gate spacer has a dielectric constant of approximately 3.6 to approximately 3.7. In some embodiments, the nitrogen-free portion is a first silicon oxycarbide portion having a first oxygen content, and the contact etch stop layer further has a second silicon oxycarbide portion disposed above the first silicon oxycarbide portion. The second silicon oxycarbide portion has a second oxygen content greater than the first oxygen content. In some embodiments, the first silicon oxycarbide portion has a first carbon content, and the second silicon oxycarbide portion has a second carbon content. The second carbon content is different from (e.g., in some embodiments, less than) the first carbon content.

[0078] Some embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: forming a three-layer etch stop layer above a source / drain by the following steps: forming a nitrogen-free low-k dielectric layer on the source / drain, wherein the nitrogen-free dielectric layer has a first dielectric constant; forming an oxygen-treated low-k dielectric layer on the nitrogen-free low-k dielectric layer, wherein the oxygen-treated low-k dielectric layer has a second dielectric constant greater than the first dielectric constant; and forming a dielectric layer on the oxygen-treated low-k dielectric layer, wherein the dielectric layer has a third dielectric constant greater than the second dielectric constant and the first dielectric constant; forming an interlayer dielectric layer above the three-layer etch stop layer; removing portions of the three-layer etch stop layer and portions of the interlayer dielectric layer to form a source / drain contact opening exposing the source / drain; and forming a source / drain contact structure in the source / drain contact opening.

[0079] In some embodiments, forming the nitrogen-free low-k dielectric layer includes depositing a first SiOC layer; forming the oxygen-treated low-k dielectric layer includes depositing a second SiOC layer and subjecting the second SiOC layer to an oxygen treatment; and forming the dielectric layer includes forming a SiN layer. In some embodiments, forming the nitrogen-free low-k dielectric layer includes performing a first plasma-enhanced chemical vapor deposition process; forming the oxygen-treated low-k dielectric layer includes performing a second plasma-enhanced chemical vapor deposition process, and subjecting the second plasma-enhanced chemical vapor deposition process to an oxygen treatment after the second plasma-enhanced chemical vapor deposition process; and forming the dielectric layer includes performing an atomic layer deposition process. In some embodiments, no oxygen treatment is performed between the first and second plasma-enhanced chemical vapor deposition processes. In some embodiments, each of the first and second plasma-enhanced chemical vapor deposition processes is performed at a deposition temperature of about 200°C to about 600°C and for a deposition time of about 6 minutes to about 1 hour. In some embodiments, the second plasma-enhanced chemical vapor deposition process deposits a low-k dielectric layer over the nitrogen-free low-k dielectric layer, and the oxygen treatment exposes the low-k dielectric layer to an O2 plasma. In some embodiments, the nitrogen-free low-k dielectric layer and the oxygen-treated low-k dielectric layer are each formed of an oxygen-containing dielectric material, wherein a first oxygen content of the oxygen-containing dielectric material of the nitrogen-free low-k dielectric layer is less than a second oxygen content of the oxygen-containing dielectric material of the oxygen-treated low-k dielectric layer. In some embodiments, the first oxygen content is less than about 50 atomic percent (at%), and the second oxygen content is greater than 50 at%. In some embodiments, the nitrogen-free dielectric layer is formed to have a first thickness, the oxygen-treated low-k dielectric layer is formed to have a second thickness, and the dielectric layer is formed to have a third thickness greater than each of the first thickness and the second thickness.

[0080] Other embodiments of the present application provide a method for manufacturing a semiconductor device, comprising: forming a contact etch stop layer above a source / drain by the following steps: depositing a first SiOC layer on the source / drain; depositing a second SiOC layer on the first SiOC layer; performing an oxygen treatment on the second SiOC layer; and depositing a SiN layer on the oxygen-treated second SiOC layer; forming an interlayer dielectric layer on the contact etch stop layer; and forming a source / drain contact to the source / drain, wherein the source / drain contact is formed in the contact etch stop layer and the interlayer dielectric layer.

[0081] In some embodiments, the first SiOC layer and the second SiOC layer are deposited in the same deposition process chamber. In some embodiments, the first SiOC layer is deposited by a first plasma enhanced chemical vapor deposition (PECVD), the second SiOC layer is deposited by a second plasma enhanced chemical vapor deposition, and the SiN layer is deposited by atomic layer deposition. In some embodiments, the deposition temperature of each of depositing the first SiOC layer and depositing the second SiOC layer is less than about 600°C. In some embodiments, the deposition time of each of depositing the first SiOC layer and depositing the second SiOC layer is less than about 1 hour. In some embodiments, forming the source / drain contacts to the source / drain includes completely removing a portion of the SiN layer and removing a portion of the second SiOC layer along the sidewall portion of the gate spacer. In some embodiments, no oxygen treatment is performed between depositing the first SiOC layer and depositing the second SiOC layer.

[0082] Some other embodiments of the present application provide a device structure, including: a gate stack; a gate spacer arranged along the sidewall of the gate stack; a source / drain arranged adjacent to the gate spacer; a source / drain contact structure arranged on the source / drain; and a contact etch stop layer arranged between the gate spacer and the source / drain contact structure, wherein the contact etch stop layer has a nitrogen-free portion that interfaces with the source / drain and the gate spacer.

[0083] In some embodiments, the nitrogen-free portion is a first silicon oxycarbide portion, wherein the first silicon oxycarbide portion has a first oxygen content; and the contact etch stop layer further includes a second silicon oxycarbide portion disposed above the first silicon oxycarbide portion, wherein the second silicon oxycarbide portion has a second oxygen content greater than the first oxygen content. In some embodiments, the first silicon oxycarbide portion has a first carbon content; and the second silicon oxycarbide portion has a second carbon content, wherein the second carbon content is less than the first carbon content. In some embodiments, the nitrogen-free portion intersecting the source / drain and the gate spacer has a dielectric constant of approximately 3.6 to approximately 3.7.

[0084] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art will appreciate that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: A triple etch stop layer is formed over the source / drain by the following steps: forming a nitrogen-free low-k dielectric layer on the source / drain, wherein the nitrogen-free dielectric layer has a first dielectric constant; forming an oxygen-treated low-k dielectric layer on the nitrogen-free low-k dielectric layer, wherein the oxygen-treated low-k dielectric layer has a second dielectric constant greater than the first dielectric constant; and forming a dielectric layer on the oxygen-treated low-k dielectric layer, wherein the dielectric layer has a third dielectric constant greater than the second dielectric constant and the first dielectric constant; forming an interlayer dielectric layer over the three etch stop layers; removing portions of the three-layer etch stop layer and portions of the interlayer dielectric layer to form source / drain contact openings exposing the source / drain; and A source / drain contact structure is formed in the source / drain contact opening.

2. The method according to claim 1, wherein: Forming the nitrogen-free low-k dielectric layer includes depositing a first SiOC layer; forming the oxygen-treated low-k dielectric layer includes depositing a second SiOC layer and performing an oxygen treatment on the second SiOC layer; and Forming the dielectric layer includes forming a SiN layer.

3. The method according to claim 1, wherein: Forming the nitrogen-free low-k dielectric layer includes performing a first plasma enhanced chemical vapor deposition process; forming the oxygen-treated low-k dielectric layer comprises performing a second plasma-enhanced chemical vapor deposition process, and performing an oxygen treatment after performing the second plasma-enhanced chemical vapor deposition process; as well as Forming the dielectric layer includes performing an atomic layer deposition process.

4. The method according to claim 3, wherein: No oxygen treatment is performed between performing the first plasma enhanced chemical vapor deposition process and the second plasma enhanced chemical vapor deposition process.

5. The method according to claim 3, wherein Each of the first plasma enhanced chemical vapor deposition process and the second plasma enhanced chemical vapor deposition process is performed at a deposition temperature of about 200° C. to about 600° C. and a deposition time of about 6 minutes to about 1 hour.

6. The method according to claim 3, wherein: The second plasma enhanced chemical vapor deposition process deposits a low-k dielectric layer over the nitrogen-free low-k dielectric layer, and the oxygen treatment exposes the low-k dielectric layer to O 2 plasma.

7. The method according to claim 1, wherein The nitrogen-free low-k dielectric layer and the oxygen-treated low-k dielectric layer are each formed of an oxygen-containing dielectric material, wherein a first oxygen content of the oxygen-containing dielectric material of the nitrogen-free low-k dielectric layer is less than a second oxygen content of the oxygen-containing dielectric material of the oxygen-treated low-k dielectric layer.

8. The method according to claim 7, wherein: The first oxygen content is less than about 50 atomic percent (at %), and the second oxygen content is greater than 50 atomic percent.

9. A method for manufacturing a semiconductor device, comprising: A contact etch stop layer is formed over the source / drain by the following steps: depositing a first SiOC layer on the source / drain; depositing a second SiOC layer on the first SiOC layer; performing oxygen treatment on the second SiOC layer; as well as depositing a SiN layer on the oxygen-treated second SiOC layer; forming an interlayer dielectric layer on the contact etch stop layer; as well as Source / drain contacts are formed to the source / drain, wherein the source / drain contacts are formed in the contact etch stop layer and the interlayer dielectric layer.

10. A device structure comprising: a gate stack; a gate spacer disposed along a sidewall of the gate stack; a source / drain disposed adjacent to the gate spacer; A source / drain contact structure is provided on the source / drain; as well as A contact etch stop layer is disposed between the gate spacer and the source / drain contact structure, wherein the contact etch stop layer has a nitrogen-free portion intersecting the source / drain and the gate spacer.

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