Power amplification circuit and power amplification device

Abstract

A power amplifier circuit includes: a first coupler that distributes a first signal into a second signal and a third signal having a phase different from that of the second signal; the carrier amplifier is used for amplifying the second signal and outputting a first amplified signal; the peak amplifier is used for amplifying the third signal and outputting a second amplified signal; the second coupler is used for synthesizing the first amplified signal and the second amplified signal to generate a third amplified signal; and a first bias circuit that switches a bias point of the peak amplifier to either a first bias point or a second bias point higher than the first bias point.

Description

Technical Field

[0001] The invention relates to a power amplifier circuit and a power amplifier device. Background Art

[0002] There is a Doherty amplifier including a carrier amplifier and a peak amplifier (see, for example, Patent Document 1).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: International Publication No. 2008 / 012898 Summary of the Invention

[0006] Problems to be solved by the invention

[0007] The power amplifier described in Patent Document 1 switches the bias supplied to the peak amplifier so that it shifts from a Doherty amplifier in low-power mode to a balanced amplifier in high-power mode. However, this power amplifier includes a λ / 4 transmission line, which increases the circuit size.

[0008] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a power amplifier circuit and a power amplifier device capable of reducing the circuit scale in a configuration capable of switching the bias point of a peak amplifier.

[0009] Solutions to Problems

[0010] A power amplifier circuit according to one aspect of the present invention includes: a first coupler for dividing a first signal into a second signal and a third signal having a phase different from that of the second signal; a carrier amplifier for amplifying the second signal and outputting a first amplified signal; a peaking amplifier for amplifying the third signal and outputting a second amplified signal; a second coupler for combining the first amplified signal and the second amplified signal to generate a third amplified signal; and a first bias circuit for switching the bias point of the peaking amplifier to either a first bias point or a second bias point higher than the first bias point.

[0011] A power amplifier device according to another aspect of the present invention includes: a semiconductor chip on which the power amplifier circuit is formed; and a substrate on which the semiconductor chip is mounted and on which a matching circuit provided in a preceding stage or a subsequent stage of the power amplifier circuit is formed.

[0012] A power amplifier device according to another aspect of the present invention includes: a first substrate of a first compound semiconductor, on which the power amplifier circuit is formed; and a second substrate of a single semiconductor or a second compound semiconductor, on which an amplifier is formed that amplifies an input signal and outputs the first signal, wherein the first compound semiconductor is different from the second compound semiconductor.

[0013] Effects of the Invention

[0014] According to the present invention, a power amplifier circuit and a power amplifier device can be provided, which can reduce the circuit scale in a configuration capable of switching the bias point of a peak amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a circuit diagram of the power amplifier circuit 101.

[0016] Figure 2 This is a plan view of the 90-degree coupler 41 as viewed from above.

[0017] Figure 3 yes Figure 2 A cross-sectional view taken along the cutting line III-III is shown.

[0018] Figure 4 This is a plan view of the 90-degree coupler 42 as viewed from above.

[0019] Figure 5 yes Figure 4 A cross-sectional view taken along the cutting line VV is shown.

[0020] Figure 6 is a circuit diagram of the power amplifier circuit 101D.

[0021] Figure 7 This is a plan view of the 90-degree coupler 141 as viewed from above.

[0022] Figure 8 yes Figure 7 A cross-sectional view taken along the cutting line VIII-VIII is shown.

[0023] Figure 9 101D are diagrams schematically showing cross sections of the semiconductor chip 11 on which the power amplifier circuit 101D is formed, taken along the xy plane.

[0024] Figure 10 : is a diagram showing an example of efficiency characteristics in the power amplifier circuit 101 .

[0025] Figure 11 1 is a diagram showing an example of load variation tolerance in the power amplifier circuit 101 in the balanced mode.

[0026] Figure 121 is a diagram showing an example of load variation tolerance in the power amplifier circuit 101 in the Doherty mode.

[0027] Figure 13 is a circuit diagram of the power amplifier circuit 102.

[0028] Figure 14 is a circuit diagram of the power amplifier circuit 103. DETAILED DESCRIPTION

[0029] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same elements, and repeated descriptions are omitted as much as possible.

[0030] [First embodiment]

[0031] The power amplifier circuit 101 and the power amplifier device 201 according to the first embodiment will be described. Figure 1 1 is a circuit diagram of the power amplifier circuit 101. Figure 1 As shown, the power amplifier 201 is provided in a communication device that complies with the WiFi (registered trademark) communication standard, for example.

[0032] The power amplifier circuit 101 is an amplifier circuit that amplifies a signal RF1 (first signal) supplied to an input terminal 31 and outputs an amplified signal RF6 (third amplified signal) from an output terminal 32 .

[0033] Signal RF1 is, for example, a radio frequency signal. Signal RF1 is modulated, for example, in accordance with the WiFi communication standard. The frequency of signal RF1 is, for example, greater than 5 GHz and less than 7 GHz. Signal RF1 may also have other frequencies.

[0034] Power amplifier device 201 includes matching circuits 21 and 22, and power amplifier circuit 101. Matching circuits 21 and 22 are provided before and after power amplifier circuit 101, respectively. Matching circuits 21 and 22 are formed on, for example, printed circuit board 12. Power amplifier circuit 101 is formed on semiconductor chip 11. Semiconductor chip 11 is connected to printed circuit board 12.

[0035] The power amplifier circuit 101 includes 90-degree couplers 41 (first coupler) and 42 (second coupler), a carrier amplifier 51 , a peak amplifier 52 , bias circuits 151 and 152 (first bias circuits), and a control circuit 162 .

[0036] In this embodiment, carrier amplifier 51 and peak amplifier 52 are configured using bipolar transistors, such as heterojunction bipolar transistors (HBTs). Alternatively, the amplifiers can be configured using other transistors, such as field-effect transistors (MOSFETs). In this case, the base, collector, and emitter can be replaced with the gate, drain, and source, respectively.

[0037] The matching circuit 21 is provided between the input terminal 31 and the power amplifier circuit 101 , and matches the impedance of a circuit (not shown) provided before the input terminal 31 and the power amplifier circuit 101 .

[0038] The matching circuit 22 is provided between the output terminal 32 and the power amplifier circuit 101 to match the impedance of the power amplifier circuit 101 with a load (not shown) such as a band selection switch, a duplexer, an antenna selection switch, and an antenna provided after the output terminal 32 .

[0039] The 90-degree coupler 41 includes electrodes 41 a (first electrode) and 41 b (second electrode). The 90-degree coupler 41 divides the signal RF1 supplied from the input terminal 31 via the matching circuit 21 into a signal RF2 (second signal) and a signal RF3 (third signal) having a phase different from that of the signal RF2.

[0040] Electrode 41a in 90-degree coupler 41 has a first end connected to input terminal 31 via matching circuit 21 and supplied with signal RF1, and a second end that outputs signal RF3. Electrode 41b is electromagnetically coupled to electrode 41a. Electrode 41b has a first end that outputs signal RF2 and a second end that serves as an isolation terminal supplied with a predetermined potential. In this embodiment, the second end of electrode 41b is connected to ground via resistor element 23. The phase of signal RF3 lags that of signal RF2 by approximately 90 degrees.

[0041] Figure 2 This is a plan view of the 90-degree coupler 41 as viewed from above. Figure 3 yes Figure 2 A cross-sectional view taken along the cutting line III-III is shown.

[0042] In each figure, the x-axis, y-axis, and z-axis are sometimes shown. The x-axis, y-axis, and z-axis form a right-handed three-dimensional orthogonal coordinate system. Hereinafter, the direction of the x-axis arrow is sometimes referred to as the x-axis + side, and the direction opposite to the arrow is sometimes referred to as the x-axis - side. The same applies to the other axes. In addition, the z-axis + side and the z-axis - side are sometimes referred to as the "upper side" and "lower side," respectively. In addition, the z-axis direction is sometimes referred to as the "stacking direction." In addition, the plane orthogonal to the x-axis, y-axis, or z-axis is sometimes referred to as the yz plane, zx plane, or xy plane.

[0043] like Figure 2 and Figure 3 As shown, electrodes 41a and 41b extend along the x-axis direction (the first direction and the second direction) and oppose each other. Specifically, electrode 41b is disposed above electrode 41a. Electrode 41a has an opposing surface 41aa on its upper side that opposes electrode 41b. Electrode 41b has an opposing surface 41ba on its lower side that opposes electrode 41a. A dielectric layer 41c is disposed between opposing surfaces 41aa and 41ba. The width of electrode 41b is smaller than that of electrode 41a.

[0044] The spacing between electrodes 41a and 41b is not fixed. In this embodiment, protrusions 41bb and 41bc are provided on the lower side of electrode 41b. Protrusions 41bb and 41bc protrude downward. The spacing between electrodes 41a and 41b decreases at protrusions 41bb and 41bc, thereby increasing the capacitance between electrodes 41a and 41b at protrusions 41bb and 41bc. By adjusting the position, shape, and size of protrusions 41bb and 41bc, the magnitude of the electromagnetic coupling between electrodes 41a and 41b can be adjusted. Especially in high-frequency bands above 5 GHz, the length of 90-degree coupler 41 tends to be shortened when considering the frequency band. Therefore, the impedance of 90-degree coupler 41 can be adjusted primarily using capacitance. That is, by using protrusions 41bb and 41bc to adjust the capacitance between electrodes 41a and 41b, optimal impedance can be more easily adjusted.

[0045] like Figure 1 As shown, the carrier amplifier 51 amplifies the signal RF2 supplied from the first end of the electrode 41 b in the 90-degree coupler 41 and outputs an amplified signal RF4 (first amplified signal).

[0046] The peak amplifier 52 amplifies the signal RF3 supplied from the second end of the electrode 41 a in the 90-degree coupler 41 , and outputs an amplified signal RF5 (a second amplified signal).

[0047] The 90-degree coupler 42 includes an electrode 42 a (third electrode) and an electrode 42 b (fourth electrode). The 90-degree coupler 42 combines the amplified signal RF4 and the amplified signal RF5 to generate an amplified signal RF6.

[0048] Electrode 42a in 90-degree coupler 42 has a first end that is open and serves as an isolation terminal, and a second end that is supplied with amplified signal RF5 from peak amplifier 52. Electrode 42b is electromagnetically coupled to electrode 42a. Electrode 42b has a first end that is supplied with amplified signal RF4 from carrier amplifier 51, and a second end that outputs amplified signal RF6 to output terminal 32 via matching circuit 22.

[0049] Figure 4 This is a plan view of the 90-degree coupler 42 as viewed from above. Figure 5 yes Figure 4 A cross-sectional view taken along the cutting line VV is shown.

[0050] like Figure 4 and Figure 5 As shown, electrodes 42a and 42b extend along the x-axis and oppose each other. Specifically, electrode 42b is disposed above electrode 42a. Electrode 42a has an opposing surface 42aa on its upper side that opposes electrode 42b. Electrode 42b has an opposing surface 42ba on its lower side that opposes electrode 42a. A dielectric layer 42c is disposed between opposing surfaces 42aa and 42ba. The width of electrode 42b is smaller than that of electrode 42a.

[0051] The spacing between electrodes 42a and 42b is not fixed. In this embodiment, protrusions 42bb and 42bc are provided on the lower side of electrode 42b. Protrusions 42bb and 42bc protrude downward. The spacing between electrodes 42a and 42b decreases at protrusions 42bb and 42bc, thereby increasing the capacitance between electrodes 42a and 42b at protrusions 42bb and 42bc. By adjusting the position, shape, and size of protrusions 42bb and 42bc, the magnitude of the electromagnetic coupling between electrodes 42a and 42b can be adjusted. Especially in high-frequency bands above 5 GHz, the length of 90-degree coupler 42 tends to be shortened when considering the frequency band. Therefore, the impedance of 90-degree coupler 42 can be adjusted primarily using capacitance. That is, by using protrusions 42bb and 42bc to adjust the capacitance between electrodes 42a and 42b, optimal impedance can be more easily adjusted.

[0052] like Figure 1 As shown, a control signal is supplied to bias circuit 151 via signal input terminal 171. Bias circuit 151 generates a bias based on the control signal and supplies it to carrier amplifier 51. In this embodiment, carrier amplifier 51 performs class A operation or class AB operation by the bias supplied from bias circuit 151.

[0053] The bias circuit 152 switches the bias point (operating point or operating type) of the peak amplifier 52 to either a first bias point or a second bias point higher than the first bias point. For example, the bias circuit 152 supplies either a first bias or a second bias higher than the first bias to the peak amplifier 52.

[0054] In this embodiment, the bias supplied to the peak amplifier 52 is switched between a first bias point and a second bias point based on MCS (Modulation and Coding Scheme) information indicating the modulation method and coding rate of the signal RF1 .

[0055] The MCS information indicates, for example, an MCS index determined by the WiFi communication standard. The MCS index indicates a combination of a modulation scheme and a coding rate, and for example, becomes a larger value as the maximum transmission rate increases.

[0056] The control circuit 162 receives MCS information from a communication device such as an RFIC, and controls the bias circuit 152 based on the received MCS information. Specifically, when the MCS index indicated by the MCS information is greater than or equal to a first threshold, the control circuit 162 controls the bias circuit 152 so that the bias point of the peak amplifier 52 is set to a second bias point. For example, when the MCS index indicated by the MCS information is greater than or equal to a first threshold, the control circuit 162 controls the bias circuit 152 to supply the second bias to the peak amplifier 52.

[0057] When the second bias is supplied to the peak amplifier 52, the power amplifier circuit 101 enters the balanced mode. At this time, the bias point of the peak amplifier 52 becomes the second bias point, and the peak amplifier 52 performs, for example, class AB operation. Thus, the power amplifier circuit 101 operates as a balanced amplifier.

[0058] On the other hand, when the MCS index indicated by the MCS information is smaller than the first threshold value, the control circuit 162 controls the bias circuit 152 to supply the first bias to the peak amplifier 52 .

[0059] When the first bias is supplied to the peak amplifier 52, the power amplifier circuit 101 enters the Doherty mode. At this time, the bias point of the peak amplifier 52 becomes the first bias point, and the peak amplifier 52 performs, for example, a class C operation. Thus, the power amplifier circuit 101 operates as a Doherty amplifier.

[0060] Furthermore, the control circuit 162 may use multiple MCS index thresholds. Specifically, the MCS index threshold is not limited to the first threshold and may also include an additional threshold greater than the first threshold. In this case, for example, when the MCS index indicated by the MCS information is less than the first threshold, the control circuit 162 controls the bias circuit 152 to supply a first bias to the peak amplifier 52. Furthermore, when the MCS index is greater than the first threshold and less than the additional threshold, the control circuit 162 controls the bias circuit 152 to supply a second bias to the peak amplifier 52. Furthermore, when the MCS index is greater than the additional threshold, the control circuit 162 controls the bias circuit 152 to supply a bias greater than the second bias to the peak amplifier 52. Furthermore, when the MCS index is greater than the additional threshold, the control circuit 162 controls the bias circuit 152 to supply a bias greater than the second bias to the peak amplifier 52. Furthermore, when there are three or more MCS index thresholds, the control circuit 162 performs the same control as when there are only two thresholds.

[0061] Figure 6 FIG. 1 is a circuit diagram of a power amplifier circuit 101D. Figure 6 As shown, the power amplifier circuit 101D is shown in detail. Figure 1 The power amplifier circuit 101D is a circuit diagram of the power amplifier circuit 101. Figure 1 Compared to the power amplifier circuit 101 shown in the figure, the circuit further includes inductors 61 , 62 , 71 , and 72 , and capacitors 63 , 64 , 73 , and 74 .

[0062] The matching circuit 21 includes inductors 21a and 21b, and a capacitor 21c. The matching circuit 22 includes inductors 22a and 22b, and a capacitor 22c.

[0063] The carrier amplifier 51 includes an input terminal 51a, an output terminal 51b, an amplifying transistor 51c, a capacitor 51d, and a resistor 51e. The peak amplifier 52 includes an input terminal 52a, an output terminal 52b, an amplifying transistor 52c, a capacitor 52d, and a resistor 52e.

[0064] Capacitor 21c in matching circuit 21 has a first end connected to input terminal 31 and a second end. Inductor 21a has a first end connected to the second end of capacitor 21c and a second end connected to the first end of electrode 41a in 90-degree coupler 41. Inductor 21b has a first end connected to the second end of inductor 21a and a second end connected to ground.

[0065] Input terminal 51a of carrier amplifier 51 is connected to the first end of electrode 41b of 90-degree coupler 41 and supplied with signal RF2. Output terminal 51b is connected to the first end of electrode 42b of 90-degree coupler 42 and supplied with amplified signal RF4.

[0066] The capacitor 51d has a first end connected to the input terminal 51a and a second end. The resistor 51e has a first end connected to the second end of the capacitor 51d and a second end connected to the bias circuit 151 and supplied with a bias.

[0067] The amplifier transistor 51 c has a collector connected to the output terminal 51 b , a base connected to the second end of the capacitor 51 d , and an emitter connected to the ground.

[0068] Inductor 71 has a first end connected to output terminal 51b of carrier amplifier 51 and a second end connected to ground via capacitor 73. Alternatively, a configuration may be employed in which the first end of inductor 71 is connected to output terminal 51b of carrier amplifier 51 via capacitor 73, and the second end of inductor 71 is connected to ground.

[0069] Inductor 61 has a first end connected to power supply voltage terminal 175 and a second end connected to output terminal 51b of carrier amplifier 51. Capacitor 63 has a first end connected to power supply voltage terminal 175 and a second end connected to ground.

[0070] The input terminal 52a of the peak amplifier 52 is connected to the second end of the electrode 41a of the 90-degree coupler 41 and is supplied with the signal RF3. The output terminal 52b is connected to the second end of the electrode 42a of the 90-degree coupler 42 and is supplied with the amplified signal RF5.

[0071] Capacitor 52d has a first end connected to input terminal 52a and a second end. Resistor 52e has a first end connected to the second end of capacitor 52d and a second end connected to bias circuit 152 and supplied with either a first bias or a second bias.

[0072] The amplifying transistor 52 c has a collector connected to the output terminal 52 b , a base connected to the second end of the capacitor 52 d , and an emitter connected to the ground.

[0073] Inductor 72 has a first end connected to output terminal 52b of peak amplifier 52 and a second end connected to ground via capacitor 74. Alternatively, a configuration may be employed in which the first end of inductor 72 is connected to output terminal 52b of peak amplifier 52 via capacitor 74, and the second end of inductor 72 is connected to ground.

[0074] Inductor 62 has a first end connected to power supply voltage terminal 176 and a second end connected to output terminal 52b of peak amplifier 52. Capacitor 64 has a first end connected to power supply voltage terminal 176 and a second end connected to ground.

[0075] Capacitor 22c in matching circuit 22 has a first end connected to the second end of electrode 42b, and a second end. Inductor 22a has a first end connected to the second end of capacitor 22c, and a second end connected to output terminal 32. Inductor 22b has a first end connected to the second end of capacitor 22c, and a second end connected to ground.

[0076] In addition, Figure 2 and Figure 3 In the illustrated 90-degree coupler 41, the electrode 41b is provided with the protrusions 41bb and 41bc, but the present invention is not limited thereto. The electrode 41a may also be provided with a protrusion.

[0077] Figure 7 This is a plan view of a 90-degree coupler 141 , which is a modified example of the 90-degree coupler 41 , as viewed from above. Figure 8 yes Figure 7 A cross-sectional view taken along the cutting line VIII-VIII is shown.

[0078] like Figure 7 and Figure 8 As shown, electrode 41a is provided above electrode 41b. Electrode 41a has an opposing surface 41aa on its lower side that faces electrode 41b. Electrode 41b has an opposing surface 41ba on its upper side that faces electrode 41a. The width of electrode 41a is smaller than that of electrode 41b.

[0079] Protrusions 41ab and 41ac are provided on the lower side of electrode 41a. Protrusions 41ab and 41ac protrude downward. The distance between electrodes 41a and 41b decreases at protrusions 41ab and 41ac, thereby increasing the capacitance between electrodes 41a and 41b at protrusions 41ab and 41ac.

[0080] [layout]

[0081] Figure 9 101D are diagrams schematically showing cross sections of the semiconductor chip 11 on which the power amplifier circuit 101D is formed, taken along the xy plane.

[0082] like Figure 9 As shown, the semiconductor chip 11 includes conductive layers 411 and 412. The conductive layers 411 and 412 are sequentially arranged from the upper side toward the lower side, for example.

[0083] A dielectric layer 41c or 42c (not shown) is provided between the conductive layer 411 and the conductive layer 412. Vias 81Va, 81Vb, 81Vc, 81Vd, 81Ve, 81Vf, and 81Vg extending in the stacking direction are formed in the dielectric layer 41c or 42c.

[0084] A ground layer (not shown) having a ground potential, for example, is provided on the upper side of the conductive layer 411. A dielectric layer (not shown) is provided between the conductive layer 411 and the ground layer.

[0085] The electrode 41 a in the 90-degree coupler 141 , the electrode 42 b in the 90-degree coupler 42 , the emitter electrode Ee, and electrodes 82Ea, 82Eb, 82Ec, 82Ed, 82Ee, and 82Ef are formed in the conductive layer 411 .

[0086] The conductive layer 412 forms the electrode 41b in the 90-degree coupler 141, the electrode 42a in the 90-degree coupler 42, nine base electrodes 51Eb, a collector electrode 51Ec, nine resistor elements 51e, nine base electrodes 52Eb, a collector electrode 52Ec, nine resistor elements 52e, and electrodes 82Em, ​​82En, 82Eo, 82Ep, and 82Eq.

[0087] The carrier amplifier 51 and the peak amplifier 52 are, for example, multi-finger transistors formed by electrically connecting a plurality of unit transistors (hereinafter sometimes referred to as fingers) in parallel.

[0088] In this embodiment, the carrier amplifier 51 includes nine sets of amplifying transistors 51c, capacitors 51d, and resistors 51e, and the peak amplifier 52 includes nine sets of amplifying transistors 52c, capacitors 52d, and resistors 52e.

[0089] The nine amplifier transistors 51c are arranged along the x-axis when the semiconductor chip 11 is viewed from above. The nine amplifier transistors 52c are provided on the x-axis side of the nine amplifier transistors 51c and are arranged along the axis along which the nine amplifier transistors 51c are arranged.

[0090] Nine base electrodes 51Eb are provided on the y-axis side of the nine amplifier transistors 51c in the conductive layer 412. The bases of the nine amplifier transistors 51c are electrically connected to the nine base electrodes 51Eb.

[0091] The first ends of the nine resistors 51e are electrically connected to the y-axis-side of the nine base electrodes 51Eb, and the second ends of the nine resistors 51e are electrically connected to the bias circuit 151 via the electrodes 82En.

[0092] Nine capacitors 51d are formed on the upper sides of the nine base electrodes 51Eb. The second ends, or lower electrodes, of the nine capacitors 51d are electrically connected to the upper surfaces of the nine base electrodes 51Eb. The first ends, or upper electrodes, of the nine capacitors 51d are electrically connected to the electrode 82Ec formed on the conductive layer 411.

[0093] In the conductive layer 412 , a collector electrode 51Ec is provided on the y-axis positive side of the nine amplifier transistors 51c . The collectors of the nine amplifier transistors 51c are electrically connected to the electrode 82Ee in the conductive layer 411 through the collector electrode 51Ec and the via 81Vd.

[0094] Nine base electrodes 52Eb are provided on the y-axis side of the nine amplifier transistors 52c, respectively. The bases of the nine amplifier transistors 52c are electrically connected to the nine base electrodes 52Eb, respectively.

[0095] The first ends of the nine resistors 52e are electrically connected to the y-axis side of the nine base electrodes 52Eb, and the second ends of the nine resistors 52e are electrically connected to the bias circuit 152 via the electrodes 82Em.

[0096] Nine capacitors 52d are formed on the upper sides of the nine base electrodes 52Eb. The second ends, or lower electrodes, of the nine capacitors 52d are electrically connected to the upper surfaces of the nine base electrodes 52Eb. The first ends, or upper electrodes, of the nine capacitors 52d are electrically connected to the electrode 82Eb formed on the conductive layer 411.

[0097] In the conductive layer 412, a collector electrode 52Ec is provided on the y-axis positive side of the nine amplifier transistors 52c. The collectors of the nine amplifier transistors 52c are electrically connected to the electrode 82Ed in the conductive layer 411 through the collector electrode 52Ec and the via 81Vc.

[0098] In the conductive layer 411 , the emitter electrode Ee is formed so as to extend along the axis along which the nine amplifier transistors 51 c and the nine amplifier transistors 52 c are arranged.

[0099] When the semiconductor chip 11 is viewed from above, the nine amplifier transistors 51 c and the nine amplifier transistors 52 c overlap with the emitter electrode Ee.

[0100] The emitters of the nine amplifier transistors 51 c and the emitters of the nine amplifier transistors 52 c are electrically connected to the emitter electrode Ee.

[0101] The upper surface of the emitter electrode Ee is electrically connected to the ground layer via bumps 51Bp and 52Bp. When the semiconductor chip 11 is viewed from above, the nine amplifier transistors 51c are located within the outline of the bumps 51Bp. Furthermore, when the semiconductor chip 11 is viewed from above, the nine amplifier transistors 52c are located within the outline of the bumps 52Bp.

[0102] A 90-degree coupler 141 is provided on the y-axis - side of the carrier amplifier 51 and the peaking amplifier 52. In the conductive layer 411, the first end of the electrode 41a in the 90-degree coupler 141 is located on the x-axis + side and is electrically connected to the matching circuit 21 via the electrode 82Ea. The second end of the electrode 41a is located on the x-axis - side and is electrically connected to the electrode 82Eb.

[0103] In conductive layer 412, the first end of electrode 41b in 90-degree coupler 141 is located on the x-axis (+) side and is electrically connected to electrode 82Ec via via 81Vb. The second end of electrode 41b is located on the x-axis (-) side and is electrically connected to ground via resistor 23, electrode 82Eo, and via 81Va.

[0104] A 90-degree coupler 42 is provided on the y-axis positive side of the carrier amplifier 51 and the peaking amplifier 52. In the conductive layer 411, the first end of the electrode 42b in the 90-degree coupler 42 is located on the x-axis positive side and is electrically connected to the electrode 82Ee. The second end of the electrode 42b is located on the x-axis negative side and is electrically connected to the matching circuit 22 via the electrode 82Ef.

[0105] In the conductive layer 412 , the first end of the electrode 42 a in the 90-degree coupler 42 is located on the x-axis + side and is open, while the second end of the electrode 42 a is located on the x-axis - side and is electrically connected to the electrode 82 Ed through the via 81Vg.

[0106] An inductor 71 and a capacitor 73 are formed on the x-axis + side of the 90-degree coupler 42. An inductor 72 and a capacitor 74 are formed on the x-axis - side of the 90-degree coupler 42.

[0107] (Effect)

[0108] Figure 10 : is a graph showing an example of efficiency characteristics in the power amplifier circuit 101. The vertical axis represents the power added efficiency of the power amplifier circuit 101 in "%." The horizontal axis represents the output power Pout in "dBm."

[0109] like Figure 10 As shown, curve Cd and curve Cb are curves in Doherty mode and balanced mode respectively. The power load efficiency of the power amplifier circuit 101 in Doherty mode is higher than that in balanced mode.

[0110] Specifically, when the MCS index is smaller than the first threshold, the power amplifier circuit 101 operates in Doherty mode, which can suppress the current consumption of the power amplifier circuit 101. In a low MCS rate mode (Doherty mode) where the MCS index is smaller than the first threshold, the modulated signal tends to be relatively simple, and the required linearity is not as high. Therefore, in this low MCS rate mode, distortion characteristics can be satisfied even at relatively high powers, and the power required by the power amplifier circuit tends to be higher than in a high MCS rate mode (balanced mode) where the MCS index is greater than the first threshold. Therefore, by operating the power amplifier circuit 101 in Doherty mode, the current consumption of the power amplifier circuit 101 can be suppressed, maintaining good characteristics.

[0111] Figure 11 This is a diagram showing an example of load variation tolerance in the balanced-mode power amplifier circuit 101. The vertical axis represents the gain of the power amplifier circuit 101 in dB, and the horizontal axis represents the output power Pout in dBm.

[0112] Figure 12 : is a diagram showing an example of load variation tolerance in the power amplifier circuit 101 in Doherty mode. Figure 12 The observation method and Figure 11 same.

[0113] exist Figure 11 and Figure 12 , the gain change when the load of the subsequent stage of the output terminal 32 is changed so that the VSVR (Voltage Standing Wave Ratio) becomes 1:2 and the phase is changed is shown.

[0114] The gain change due to load fluctuation in the balanced mode is suppressed compared to the gain change due to load fluctuation in the Doherty mode.

[0115] Specifically, when the MCS index is above the first threshold, power amplifier circuit 101 enters balanced mode, improving the load variation characteristics of power amplifier circuit 101. Furthermore, since peak amplifier 52 performs Class AB operation, the linearity of the amplification characteristics of power amplifier circuit 101 can be improved. In high MCS rate modes where the MCS index is above the first threshold, the modulated signal tends to be relatively complex, and the required linearity tends to be higher. Therefore, in this high MCS rate mode, distortion characteristics can only be met at relatively low power, and the power required by the power amplifier circuit tends to be lower than in low MCS rate modes where the MCS index is lower than the first threshold. Therefore, by operating power amplifier circuit 101 in balanced mode, the linearity of the amplification characteristics of power amplifier circuit 101 can be improved, maintaining good characteristics.

[0116] [Second embodiment]

[0117] The power amplifier circuit 102 according to the second embodiment will be described. In the second embodiment and beyond, descriptions of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, similar functions and effects resulting from similar configurations will not be described in detail in each embodiment.

[0118] Figure 13 1 is a circuit diagram of the power amplifier circuit 102. Figure 13 As shown in FIG. 1 , the power amplifier circuit 102 according to the second embodiment differs from the power amplifier circuit 101 according to the first embodiment in that it further includes a control circuit 161 .

[0119] Bias circuit 151 switches the bias point (operating point or operating type) of carrier amplifier 51 to either a third bias point or a fourth bias point higher than the third bias point. For example, bias circuit 151 supplies carrier amplifier 51 with either the third bias point or a fourth bias point higher than the third bias point.

[0120] In this embodiment, the bias supplied to the carrier amplifier 51 is switched between the third bias point and the fourth bias point based on the MCS information.

[0121] Control circuit 161 receives MCS information from a communication device, for example, and controls bias circuit 151 based on the received MCS information. Specifically, when the MCS index indicated by the MCS information is greater than or equal to a second threshold, control circuit 161 controls bias circuit 151 so that the bias point of carrier amplifier 51 is set to a fourth bias point. For example, when the MCS index indicated by the MCS information is greater than or equal to the second threshold, control circuit 161 controls bias circuit 151 to supply the fourth bias to carrier amplifier 51. The second threshold may be the same as or different from the first threshold described above.

[0122] When the fourth bias is supplied to the carrier amplifier 51 , the bias point of the carrier amplifier 51 becomes the fourth bias point, and the carrier amplifier 51 performs, for example, a class AB operation close to class A.

[0123] On the other hand, when the MCS index indicated by the MCS information is smaller than the second threshold, the control circuit 161 controls the bias circuit 151 to supply the third bias to the carrier amplifier 51 .

[0124] When the third bias is supplied to the carrier amplifier 51 , the bias point of the carrier amplifier 51 becomes the third bias point, and the carrier amplifier 51 performs, for example, a class AB operation close to class B.

[0125] Furthermore, there may be multiple threshold values ​​of the MCS index used in the control by the control circuit 161. In this case, the control circuit 161 performs the same control as that performed by the control circuit 162.

[0126] [Third embodiment]

[0127] Figure 14 1 is a circuit diagram of the power amplifier circuit 103 formed in the power amplifier device 203. Figure 14 As shown, the power amplifier device 203 according to the third embodiment is different from the power amplifier device 201 according to the first embodiment in that a power amplifier circuit is formed over a first substrate of a compound semiconductor and a second substrate of a single semiconductor.

[0128] In this embodiment, the first substrate is, for example, a GaAs semiconductor chip 11G containing a compound semiconductor of gallium and arsenic (hereinafter sometimes referred to as a first compound semiconductor), and the second substrate is, for example, a Si semiconductor chip 11S containing a single semiconductor of silicon.

[0129] The power amplifier circuit 103 is formed in the power amplifier device 203. The power amplifier circuit 103 is formed in the power amplifier device 201 and the power amplifier circuit 102 (see Figure 13 ), it further includes matching circuits 20A and 20B, a driver stage amplifier 50, and a bias circuit 150.

[0130] The matching circuits 20A and 20B, the driver stage amplifier 50 , the bias circuit 150 , and the control circuits 161 and 162 in the power amplifier circuit 103 are formed in the Si semiconductor chip 11S.

[0131] Matching circuits 21 and 22 , 90-degree couplers 41 and 42 , a carrier amplifier 51 , a peak amplifier 52 , and bias circuits 151 and 152 are formed on the GaAs semiconductor chip 11G.

[0132] The matching circuit 20A in the power amplifier circuit 103 is provided between the input terminal 31 and the driver-stage amplifier 50 , and matches the impedance of a circuit (not shown) provided before the input terminal 31 and the driver-stage amplifier 50 .

[0133] The driver-stage amplifier 50 amplifies the signal RF1 (input signal) supplied from the input terminal 31 via the matching circuit 20A and outputs an amplified signal RF12 (first signal). The driver-stage amplifier 50 includes, for example, a field-effect transistor. Alternatively, the driver-stage amplifier 50 may include a bipolar transistor. The bias circuit 150 generates a bias and supplies it to the driver-stage amplifier 50.

[0134] The matching circuit 20B is provided between the driver-stage amplifier 50 and the matching circuit 21 , and matches the impedances of the driver-stage amplifier 50 and the matching circuit 21 .

[0135] The 90-degree coupler 41 divides the amplified signal RF12 supplied from the driver stage amplifier 50 via the matching circuits 20B and 21 into a signal RF2 and a signal RF3 having a phase different from that of the signal RF2.

[0136] (Effect)

[0137] The field-effect transistor included in the driver-stage amplifier 50 is sensitive to changes in drain-side impedance. In the power amplifier device 203, a 90-degree coupler 41 is provided after the driver-stage amplifier 50. This allows the phase difference between the reflected wave from the carrier amplifier 51 and the reflected wave from the peak amplifier 52 to be approximately 180°.

[0138] This can reduce the power of the reflected wave, thereby simplifying the impedance matching between the driver stage amplifier 50 , the carrier amplifier 51 , and the peak amplifier 52 .

[0139] The bipolar transistors included in the carrier amplifier 51 and the peak amplifier 52 are sensitive to changes in voltage on the input side, and therefore, control of impedance on the input side is important.

[0140] Since the 90-degree coupler 41 is provided before the carrier amplifier 51 and the peak amplifier 52 , the impedance of the driver-stage amplifier 50 viewed from the carrier amplifier 51 and the impedance of the driver-stage amplifier 50 viewed from the peak amplifier 52 decrease when one increases.

[0141] Thus, when the voltage at the drain of the driver stage amplifier 50 changes dynamically, the carrier amplifier 51 and the peak amplifier 52 operate to cancel out the change.

[0142] That is, impedance matching between the Si semiconductor chip 11S and the GaAs semiconductor chip 11G can be simplified, and therefore, the power amplifier device 203 capable of amplifying signals in a wide frequency band can be provided.

[0143] Furthermore, in this embodiment, the Si semiconductor chip 11S is described as a single semiconductor containing silicon, but the present invention is not limited thereto. The Si semiconductor chip 11S may also be a single semiconductor containing an element other than silicon. Alternatively, a second substrate containing a second compound semiconductor may be provided in place of the Si semiconductor chip 11S. Here, the second compound semiconductor contains elements different from those contained in the first compound semiconductor, namely gallium and arsenic.

[0144] Furthermore, in the power amplifier circuit 101, a configuration has been described in which a second bias is supplied to the peak amplifier 52 when the MCS index for the signal RF1 is greater than or equal to a first threshold, and a first bias is supplied to the peak amplifier 52 when the MCS index is less than the first threshold. However, the present invention is not limited thereto. Alternatively, a configuration may be employed in which a second bias is supplied to the peak amplifier 52 (or the bias point of the peak amplifier 52 is changed to the second bias point) when the MCS index is greater than the first threshold, and a first bias is supplied to the peak amplifier 52 (or the bias point of the peak amplifier 52 is changed to the first bias point) when the MCS index is less than or equal to the first threshold.

[0145] Furthermore, in the power amplifier circuit 102, a configuration has been described in which a fourth bias is supplied to the carrier amplifier 51 when the MCS index for the signal RF1 is greater than or equal to the second threshold, and a third bias is supplied to the carrier amplifier 51 when the MCS index is less than the second threshold. However, the present invention is not limited thereto. Alternatively, a configuration may be employed in which a fourth bias is supplied to the carrier amplifier 51 (or the bias point of the carrier amplifier 51 is changed to the fourth bias point) when the MCS index is greater than the second threshold, and a third bias is supplied to the carrier amplifier 51 (or the bias point of the carrier amplifier 51 is changed to the third bias point) when the MCS index is less than or equal to the second threshold.

[0146] In the power amplifier circuit 101, the electrodes 41a and 41b of the 90-degree coupler 41 are described as overlapping when viewed from above. However, the present invention is not limited to this configuration. Alternatively, the electrodes 41a and 41b may be arranged side by side in the xy plane without overlapping when viewed from above.

[0147] Furthermore, in the power amplifier circuit 101, the electrodes 42a and 42b of the 90-degree coupler 42 are described as overlapping when viewed from above. However, the present invention is not limited to this. Alternatively, the electrodes 42a and 42b may be arranged side by side in the xy plane without overlapping when viewed from above.

[0148] Furthermore, in the description of power amplifier circuit 101, a configuration has been described in which power amplifier circuit 101 is formed on semiconductor chip 11 and matching circuits 21 and 22 are formed on printed circuit board 12. However, this is not limiting. Alternatively, a configuration may be employed in which at least one of matching circuits 21 and 22 is formed on semiconductor chip 11. Furthermore, when matching circuit 21 is formed on semiconductor chip 11, the electrodes become thinner, and the size of the inductor may be reduced. Therefore, signal loss through matching circuit 21 may increase, particularly in high-frequency bands above 5 GHz. Therefore, it is preferable to form matching circuit 21 on printed circuit board 12. Matching circuit 22 is similar to matching circuit 21.

[0149] The above describes an exemplary embodiment of the present invention. In power amplifier circuits 101 and 102, 90-degree coupler 41 divides signal RF1 into signal RF2 and signal RF3, which has a different phase from signal RF2. Carrier amplifier 51 amplifies signal RF2 and outputs amplified signal RF4. Peaking amplifier 52 amplifies signal RF3 and outputs amplified signal RF5. 90-degree coupler 42 combines amplified signals RF4 and RF5 to generate amplified signal RF6. Furthermore, bias circuit 152 switches the bias point of peaking amplifier 52 to either a first bias point or a second bias point higher than the first bias point.

[0150] Thus, by providing 90-degree couplers 41 and 42 instead of the large λ / 4 line, the circuit scale of power amplifier circuit 101 can be reduced. Furthermore, by switching the bias point of peak amplifier 52 to either a first bias point or a second bias point, power amplifier circuits 101 and 102 can be operated as, for example, Doherty amplifiers or balanced amplifiers. Consequently, a power amplifier circuit and a power amplifier device can be provided that can reduce the circuit scale while enabling switching of the peak amplifier's bias point.

[0151] Furthermore, the signal RF1 is modulated in the power amplifier circuits 101 and 102. The first bias point and the second bias point are switched based on MCS information indicating the modulation method and coding rate of the signal RF1.

[0152] With this configuration, when a complex modulation scheme or high coding rate is used, which requires high linearity in the amplification characteristics of power amplifier circuit 101, the bias point of peak amplifier 52 can be set to the second bias point, causing power amplifier circuit 101 to operate as a balanced amplifier. Furthermore, when a simple modulation scheme or low coding rate is used, which requires low linearity in the amplification characteristics of power amplifier circuit 101 and is primarily used up to high output, the bias point of peak amplifier 52 can be set to the first bias point, causing power amplifier circuit 101 to operate as a Doherty amplifier.

[0153] In power amplifier circuits 101 and 102, MCS information indicates an MCS index. When the MCS index is greater than a first threshold, the bias point of peak amplifier 52 is set to the second bias point. When the MCS index is less than the first threshold, the bias point of peak amplifier 52 is set to the first bias point.

[0154] In this way, the structure of switching the bias point of the peak amplifier 52 between the first bias point and the second bias point based on the MCS index and the first threshold, which becomes a larger value as the modulation method becomes more complex and becomes a larger value as the coding rate becomes higher, can enable the operation of the power amplifier circuit 101 to be appropriately and simply switched between the balanced amplifier and the Doherty amplifier.

[0155] Furthermore, in the power amplifier circuit 102 , the bias circuit 151 switches the bias point of the carrier amplifier 51 to either the third bias point or a fourth bias point higher than the third bias point.

[0156] In this way, by switching the bias point of the carrier amplifier 51 to either the third bias point or the fourth bias point, the carrier amplifier 51 can be operated in either class AB operation close to class B or class AB operation close to class A, for example.

[0157] Furthermore, the first signal is modulated in power amplifier circuits 101 and 102. When the MCS index for signal RF1 is greater than the second threshold, the bias point of carrier amplifier 51 becomes the fourth bias point. When the MCS index is less than the second threshold, the bias point of carrier amplifier 51 becomes the third bias point.

[0158] According to such a configuration, the bias point of the carrier amplifier 51 can be appropriately and easily switched according to the MCS index. This allows the power amplifier circuit 101 to appropriately operate as a balanced amplifier or a Doherty amplifier.

[0159] In the power amplifier circuits 101 and 102 , the frequency of the signal RF1 is 5 GHz or higher.

[0160] With such a configuration, the signal RF1 can be amplified satisfactorily in accordance with the modulation method and coding rate used in the WiFi communication standard in a frequency band of 5 GHz or higher.

[0161] In power amplifier circuits 101 and 102, 90-degree coupler 41 includes electrodes 41a and 41b. Electrode 41a has a first end to which signal RF1 is supplied and a second end to which signal RF3 is output. Electrode 41b is electromagnetically coupled to electrode 41a and has a first end to which signal RF2 is output and a second end to which a predetermined potential is supplied. Electrodes 41a and 41b face each other. Furthermore, the spacing between electrodes 41a and 41b is not constant.

[0162] According to such a configuration, the capacitance between the electrodes 41 a and 41 b can be adjusted, and therefore the distribution characteristics of the 90-degree coupler 41 can be appropriately adjusted.

[0163] In power amplifier circuits 101 and 102, 90-degree coupler 42 includes electrodes 42a and 42b. Electrode 42a has an open first end and a second end supplied with amplified signal RF5. Electrode 42b is electromagnetically coupled to electrode 42a and has a first end supplied with amplified signal RF4 and a second end outputting amplified signal RF6. Electrodes 42a and 42b face each other. Furthermore, the spacing between electrodes 42a and 42b is not constant.

[0164] According to such a configuration, the capacitance between the electrodes 42 a and 42 b can be adjusted, and therefore the combined characteristics of the 90-degree coupler 42 can be appropriately adjusted.

[0165] In power amplifier device 201, power amplifier circuit 101 or 102 is formed on semiconductor chip 11. Semiconductor chip 11 is mounted on printed circuit board 12, and matching circuits 21 and 22 are formed before and after power amplifier circuit 101 or 102, respectively.

[0166] In this manner, by forming the matching circuits 21 and 22 on the printed circuit board 12 , where a large inductor can be easily formed using thick electrodes, the loss of signals passing through the matching circuits 21 and 22 can be reduced compared to a configuration in which the matching circuits 21 and 22 are formed on the semiconductor chip 11 .

[0167] In power amplifier device 203, power amplifier circuit 101 or 102 is formed on GaAs semiconductor chip 11G. Driver amplifier 50, which amplifies signal RF1 and outputs amplified signal RF12, is formed on Si semiconductor chip 11S or a second substrate of a second compound semiconductor. GaAs semiconductor chip 11G is different from the second compound semiconductor.

[0168] The driver-stage amplifier 50 formed on the Si semiconductor chip 11S or the second compound semiconductor substrate is sensitive to the load-side impedance. However, by providing a 90-degree coupler 41 between the driver-stage amplifier 50 and the carrier amplifier 51 and peaking amplifier 52, impedance matching between the driver-stage amplifier 50, the carrier amplifier 51, and the peaking amplifier 52 is simplified. Furthermore, the carrier amplifier 51 and the peaking amplifier 52 are sensitive to changes in input voltage. However, by providing a 90-degree coupler 41 in the preceding stage, when the drain voltage of the driver-stage amplifier 50 dynamically changes, the carrier amplifier 51 and the peaking amplifier 52 can operate to cancel out these changes. In other words, impedance matching between the Si semiconductor chip 11S or the second compound semiconductor substrate and the GaAs semiconductor chip 11G is simplified, thereby providing a power amplifier device 203 capable of amplifying signals over a wide frequency band.

[0169] In addition, each embodiment described above is used to make the understanding of the present invention easy, and is not used to explain the present invention in a limiting manner. The present invention can be changed / improved without departing from its main purpose, and the present invention also includes its equivalents. That is, as long as the embodiment obtained by those skilled in the art appropriately designing and changing each embodiment has the characteristics of the present invention, it is also included in the scope of the present invention. For example, each element and its configuration, material, condition, shape, size, etc. possessed by each embodiment are not limited to the contents of the illustration and can be appropriately changed. In addition, each embodiment is an illustration, and of course, partial replacement or combination of the structures shown in different embodiments can be carried out, and as long as they have the characteristics of the present invention, they are also included in the scope of the present invention.

[0170] <1>

[0171] A power amplifier circuit comprising:

[0172] a first coupler that distributes the first signal into a second signal and a third signal having a phase different from that of the second signal;

[0173] a carrier amplifier, amplifying the second signal and outputting a first amplified signal;

[0174] a peak amplifier, amplifying the third signal and outputting a second amplified signal;

[0175] a second coupler, combining the first amplified signal and the second amplified signal to generate a third amplified signal; and

[0176] The first bias circuit switches the bias point of the peak amplifier to either a first bias point or a second bias point higher than the first bias point.

[0177] <2>

[0178] The power amplifier circuit according to <1>, wherein:

[0179] The first signal is modulated,

[0180] The power amplifier circuit switches between the first bias point and the second bias point based on MCS (Modulation and Coding Scheme) information indicating a modulation scheme and a coding rate of the first signal.

[0181] <3>

[0182] According to the power amplifier circuit described in <2>,

[0183] The MCS information indicates an MCS index,

[0184] When the MCS index is greater than or equal to a first threshold, the bias point of the peak amplifier becomes the second bias point. When the MCS index is less than the first threshold, the bias point of the peak amplifier becomes the first bias point.

[0185] <4>

[0186] The power amplifier circuit according to any one of <1> to <3>, wherein:

[0187] The power amplifier circuit further includes a second bias circuit that switches the bias point of the carrier amplifier to either a third bias point or a fourth bias point higher than the third bias point.

[0188] <5>

[0189] The power amplifier circuit according to <4>, wherein:

[0190] The first signal is modulated,

[0191] When the MCS index for the first signal is greater than a second threshold, the bias point of the carrier amplifier becomes the fourth bias point. When the MCS index is less than the second threshold, the bias point of the carrier amplifier becomes the third bias point.

[0192] <6>

[0193] The power amplifier circuit according to any one of <1> to <5>, wherein:

[0194] The frequency of the first signal is above 5 GHz.

[0195] <7>

[0196] The power amplifier circuit according to any one of <1> to <6>, wherein:

[0197] The first coupler comprises:

[0198] a first electrode having a first end to which the first signal is supplied and a second end to which the third signal is output; and

[0199] The second electrode is electromagnetically coupled to the first electrode and has a first end for outputting the second signal and a second end for supplying a predetermined potential.

[0200] The first electrode and the second electrode are opposite to each other,

[0201] The interval between the first electrode and the second electrode is not constant.

[0202] <8>

[0203] The power amplifier circuit according to any one of <1> to <7>, wherein:

[0204] The second coupler comprises:

[0205] a third electrode having an open first end and a second end supplied with the second amplified signal; and

[0206] a fourth electrode, electromagnetically coupled to the third electrode, having a first end supplied with the first amplified signal and a second end outputting the third amplified signal;

[0207] The third electrode and the fourth electrode are opposite to each other,

[0208] The interval between the third electrode and the fourth electrode is not constant.

[0209] <9>

[0210] A power amplifier device comprising:

[0211] A semiconductor chip having the power amplifier circuit described in any one of <1> to <8> formed thereon; and

[0212] The semiconductor chip is mounted on the substrate and a matching circuit is formed on the substrate to be provided at a preceding stage or a subsequent stage of the power amplifier circuit.

[0213] <10>

[0214] A power amplifier device comprising:

[0215] A first substrate of a first compound semiconductor having a power amplifier circuit according to any one of <1> to <8> formed thereon; and

[0216] The second substrate of the single semiconductor or the second compound semiconductor is provided with an amplifier for amplifying an input signal and outputting the first signal.

[0217] The first compound semiconductor is different from the second compound semiconductor.

[0218] Description of Reference Numerals

[0219] 11… semiconductor chips;

[0220] 11G…GaAs semiconductor chip;

[0221] 11S…Si semiconductor chip;

[0222] 12…Printed circuit board;

[0223] 20A, 20B, 21, 22…matching circuit;

[0224] 21a, 21b, 22a, 22b…inductors;

[0225] 21c, 22c…capacitors;

[0226] 23…resistance element;

[0227] 31…Input terminal;

[0228] 32…output terminal;

[0229] 41, 141…90 degree coupler;

[0230] 41a, 41b…electrodes;

[0231] 41aa, 41ba…opposing surfaces;

[0232] 41ab, 41ac, 41bb, 41bc...convex portion;

[0233] 42…90 degree coupler;

[0234] 42a, 42b ... electrodes;

[0235] 42aa, 42ba…opposing surfaces;

[0236] 42bb, 42bc...convex part;

[0237] 50… driver stage amplifier;

[0238] 51…Carrier amplifier;

[0239] 51a…input terminal;

[0240] 51b…output terminal;

[0241] 51c…amplifier transistor;

[0242] 51d…capacitor;

[0243] 51e…resistance element;

[0244] 52…Peak Amplifier;

[0245] 52a…input terminal;

[0246] 52b…output terminal;

[0247] 52c…amplifier transistor;

[0248] 52d…capacitor;

[0249] 52e…resistance element;

[0250] 101, 101D, 102, 103…power amplifier circuit;

[0251] 150, 151, 152…bias circuit;

[0252] 161, 162…control circuit;

[0253] 171…Signal input terminal;

[0254] 201, 203…power amplifier;

[0255] 411, 412…conductive layer.

Claims

1. A power amplifier circuit comprising: a first coupler that distributes the first signal into a second signal and a third signal having a phase different from that of the second signal; a carrier amplifier, amplifying the second signal and outputting a first amplified signal; a peak amplifier, amplifying the third signal and outputting a second amplified signal; a second coupler, combining the first amplified signal and the second amplified signal to generate a third amplified signal; as well as The first bias circuit switches the bias point of the peak amplifier to either a first bias point or a second bias point higher than the first bias point.

2. The power amplifier circuit according to claim 1, wherein: The first signal is modulated, The power amplifier circuit switches the first bias point and the second bias point based on MCS information indicating a modulation method and a coding rate of the first signal, where the MCS is a modulation and coding strategy.

3. The power amplifier circuit according to claim 2, wherein: The MCS information indicates an MCS index, When the MCS index is greater than or equal to a first threshold, the bias point of the peak amplifier becomes the second bias point. When the MCS index is less than the first threshold, the bias point of the peak amplifier becomes the first bias point.

4. The power amplifier circuit according to any one of claims 1 to 3, wherein: The power amplifier circuit further includes a second bias circuit that switches the bias point of the carrier amplifier to either a third bias point or a fourth bias point higher than the third bias point.

5. The power amplifier circuit according to claim 4, wherein: The first signal is modulated, When the MCS index for the first signal is greater than a second threshold, the bias point of the carrier amplifier becomes the fourth bias point. When the MCS index is less than the second threshold, the bias point of the carrier amplifier becomes the third bias point.

6. The power amplifier circuit according to any one of claims 1 to 5, wherein: The frequency of the first signal is above 5 GHz.

7. The power amplifier circuit according to any one of claims 1 to 6, wherein: The first coupler comprises: a first electrode having a first end to which the first signal is supplied and a second end to which the third signal is output; and The second electrode is electromagnetically coupled to the first electrode and has a first end for outputting the second signal and a second end for supplying a predetermined potential. The first electrode and the second electrode are opposite to each other, The interval between the first electrode and the second electrode is not constant.

8. The power amplifier circuit according to any one of claims 1 to 7, wherein: The second coupler comprises: a third electrode having an open first end and a second end supplied with the second amplified signal; and a fourth electrode, electromagnetically coupled to the third electrode, having a first end supplied with the first amplified signal and a second end outputting the third amplified signal; The third electrode and the fourth electrode are opposite to each other, The interval between the third electrode and the fourth electrode is not constant.

9. A power amplifier device comprising: A semiconductor chip having the power amplifier circuit according to any one of claims 1 to 8 formed thereon; and The semiconductor chip is mounted on the substrate and a matching circuit is formed on the substrate to be provided at a preceding stage or a subsequent stage of the power amplifier circuit.

10. A power amplifier device comprising: a first substrate of a first compound semiconductor, on which the power amplifier circuit according to any one of claims 1 to 8 is formed; and The second substrate of the single semiconductor or the second compound semiconductor is provided with an amplifier for amplifying an input signal and outputting the first signal. The first compound semiconductor is different from the second compound semiconductor.

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