Semiconductor memory device and manufacturing method thereof

Abstract

The invention provides a semiconductor manufacturing device and a manufacturing method thereof, which can easily form a bonding pad on a contact plug. According to one embodiment, a semiconductor memory device includes a first chip including a transistor, and a second chip including a memory cell array. The second chip includes a first surface bonded to the first chip, and a second surface located on a side opposite to the first surface. The contacts extend between the first face and the second face and are disposed separately from the memory cell array. The first wiring layer is provided above a first end of the second surface side of the contact, and is electrically connected to the contact. The first conductive layer is disposed between the first end of the contact and the first wiring layer.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device and a method for manufacturing the same. Background Art

[0002] Semiconductor storage devices such as NAND flash memories sometimes have a structure in which a circuit chip and a memory chip are bonded together. In this case, it is sometimes difficult to form pads on contact plugs that connect the circuit chip to the memory chip. Prior art literature Patent Literature

[0003] Patent Document 1: U.S. Patent Publication No. 2022 / 0059481 Patent Document 2: U.S. Patent Publication No. 2022 / 0068858 Patent Document 3: U.S. Patent Publication No. 2022 / 0077090 Patent Document 4: U.S. Patent Publication No. 2021 / 0082877 Patent Document 5: U.S. Patent Registration No. 11088113 Patent Document 6: U.S. Patent Registration No. 10026769 Patent Document 7: U.S. Patent Publication No. 2019 / 0279952 Summary of the Invention Problems to be solved by the invention

[0004] Provided are a semiconductor manufacturing apparatus and a manufacturing method thereof that can easily form a pad on a contact plug. Means for solving technical problems

[0005] The semiconductor memory device of this embodiment includes: a first chip including transistors; and a second chip including a memory cell array. The second chip includes: a first surface bonded to the first chip; and a second surface located opposite the first surface. A contact extends between the first surface and the second surface and is provided separately from the memory cell array. A first wiring layer is provided above a first end of the contact on the second surface side and is electrically connected to the contact. A first conductive layer is provided between the first end of the contact and the first wiring layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 This is a block diagram showing the configuration of a semiconductor memory device. Figure 2 This is a circuit diagram showing the configuration of a block. Figure 3 It is a plan view showing a configuration example of a chip according to the first embodiment. Figure 4 It is an XZ cross-sectional view showing the structure of a semiconductor memory device. Figure 5 is a cross-sectional view showing the structure of a memory cell. Figure 6 This is a cross-sectional view showing a configuration example of a chip according to the first embodiment. Figure 7 It is a plan view showing a configuration example of a pad. Figure 8 It is a plan view showing another configuration example of the pad. Figure 9 This is a cross-sectional view illustrating an example of a method for manufacturing the semiconductor memory device according to the first embodiment. Figure 10 It is a continuation Figure 9 A cross-sectional view showing a method for manufacturing a semiconductor memory device is shown. Figure 11 It is a continuation Figure 10 A cross-sectional view showing a method for manufacturing a semiconductor memory device is shown. Figure 12 It is a continuation Figure 11 A cross-sectional view showing a method for manufacturing a semiconductor memory device is shown. Figure 13 It is a continuation Figure 12 A cross-sectional view showing a method for manufacturing a semiconductor memory device is shown. Figure 14 It is a continuation Figure 13 A cross-sectional view showing a method for manufacturing a semiconductor memory device is shown. Figure 15 It is a continuation Figure 14 A cross-sectional view showing a method for manufacturing a semiconductor memory device is shown. Figure 16 It is a cross-sectional view showing a configuration example of a semiconductor memory device according to the second embodiment. Figure 17 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor memory device according to the second embodiment. Figure 18 It is a continuation Figure 17 A cross-sectional view showing an example of a method for manufacturing a semiconductor memory device is shown. Figure 19 It is a cross-sectional view showing a configuration example of a semiconductor memory device according to a third embodiment. Figure 20 It is a cross-sectional view showing a configuration example of a semiconductor memory device according to a fourth embodiment. Figure 21 It is a plan view showing a configuration example of a semiconductor memory device according to a fourth embodiment. Figure 22 This is a cross-sectional view illustrating an example of a manufacturing method according to the fourth embodiment. Figure 23It is a continuation Figure 22 A cross-sectional view showing a method for manufacturing a semiconductor memory device is shown. Figure 24 It is a continuation Figure 23 A cross-sectional view showing a method for manufacturing a semiconductor memory device is shown. Figure 25 It is a cross-sectional view showing a configuration example of a semiconductor memory device according to a fifth embodiment. Figure 26 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor memory device according to the fifth embodiment. Figure 27 It is a continuation Figure 26 A cross-sectional view showing a method for manufacturing a semiconductor memory device is shown. Figure 28 It is a cross-sectional view showing a configuration example of a semiconductor memory device according to a sixth embodiment. Figure 29 It is an XY plan view showing the structure of the semiconductor memory device according to the seventh embodiment. Figure 30 It is a cross-sectional view showing the structure of a semiconductor memory device according to a seventh embodiment. Figure 31 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor memory device according to the seventh embodiment. Figure 32 It is a continuation Figure 31 A cross-sectional view showing a method for manufacturing a semiconductor memory device is shown. Figure 33 It is a continuation Figure 32 A cross-sectional view showing a method for manufacturing a semiconductor memory device is shown. Figure 34 It is a continuation Figure 33 A cross-sectional view showing a method for manufacturing a semiconductor memory device is shown. Figure 35 It is a continuation Figure 34 A cross-sectional view showing a method for manufacturing a semiconductor memory device is shown. Figure 36 It is a continuation Figure 35 A cross-sectional view showing a method for manufacturing a semiconductor memory device is shown. Figure 37 It is a continuation Figure 36 A cross-sectional view showing a method for manufacturing a semiconductor memory device is shown. Figure 38 This is a table showing examples of combinations of materials for the conductive layer. DETAILED DESCRIPTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. This embodiment does not limit the present invention. In the following embodiments, the up-down direction of the semiconductor substrate may be different from the up-down direction according to the gravitational acceleration. The accompanying drawings are schematic or conceptual, and the proportions of the various parts may not be the same as the actual ones. In the specification and drawings, the same reference numerals are given to the same elements as those described above with respect to the drawings that have already appeared, and detailed descriptions are omitted as appropriate.

[0008] (First embodiment) The semiconductor memory device according to the first embodiment is formed by bonding a plurality of chips, but a design is implemented for appropriately connecting conductive films between the plurality of chips. Figure 1 As shown.

[0009] Figure 1 1 is a block diagram showing the configuration of a semiconductor memory device 1. The semiconductor memory device 1 includes a plurality of chips 10 and 20. Chip 20 includes a memory cell array 21 and is also referred to as a memory chip. Chip 10 includes circuits for controlling the memory cell array 21 and is also referred to as a circuit chip.

[0010] exist Figure 1 2 , the semiconductor storage device 1 is shown as an example in which the semiconductor storage device 1 includes one chip (memory chip) 20 . However, the semiconductor storage device 1 may include two or more memory chips.

[0011] The semiconductor storage device 1 may be a nonvolatile memory that stores data nonvolatilely, and can be applied to a memory system 1003 such as a memory card or an SSD (Solid State Drive). The memory system 1003 includes the semiconductor storage device 1 and a memory controller 1002 .

[0012] The semiconductor memory device 1 receives power supplies Vss and Vcc, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn from the memory controller 1002. It also transmits a ready / busy signal RBn and receives and transmits input / output signals I / O. The semiconductor memory device 1 is controlled by the memory controller 1002 via these signals.

[0013] Input / output signals I / O may include a command CMD, address information ADD, and a data signal DAT. Power supply Vss has a reference potential (e.g., ground potential). Power supply Vcc has a predetermined potential (e.g., power supply potential). Command latch enable signal CLE indicates that input / output signal I / O is command CMD. Address latch enable signal ALE indicates that output signal I / O is address information ADD. Write enable signal WEn may be used to enable a write operation. Read enable signal REn may be used to enable a read operation. Ready / busy signal RBn indicates that semiconductor memory device 1 is in a ready / busy state.

[0014] The chip 20 has power supply lines 22 and 23. Power supply Vss is transmitted to the chip 10 via the power supply line 22. Power supply Vcc is transmitted to the chip 10 via the power supply line 23.

[0015] The chip 20 further includes a memory cell array 21. In the memory cell array 21, a plurality of memory cell transistors (hereinafter referred to as memory cells) are three-dimensionally arrayed. Each memory cell array 21 includes a plurality of blocks BK.

[0016] Figure 2 1 is a circuit diagram showing the configuration of a block BK. Each block BK includes a plurality of memory cell transistors (hereinafter referred to as memory cells) MT connected in common to a word line WL.

[0017] Block BK, for example, includes four string units SU0-SU3. Each string unit SU includes multiple memory strings MS. The multiple memory strings MS correspond to multiple bit lines BL0-BL(m-1) (m is any integer greater than 2). The memory strings MS are connected to corresponding bit lines BL. Each memory string MS includes memory cells MT0-MT3 and select transistors ST1 and ST2.

[0018] In each memory string MS, the drain of the selection transistor ST1 is connected to the bit line BL. Memory cell transistors MT0 to MT3 are connected in series between the source of the selection transistor ST1 and the drain of the selection transistor ST2. The source of the selection transistor ST2 is connected to the source line SL.

[0019] The gates of the select transistors ST1 of each memory string MS included in the string unit SU are commonly connected to a select gate line SGD. The gates of the select transistors ST2 of each memory string MS included in the block BK are commonly connected to a select gate line SGS. The gates of the memory cell transistors MT of each memory string MS included in the block BK are commonly connected to a word line WL.

[0020] In a string unit SU, a collection of multiple memory cells MT connected to a word line WL is called a cell unit CU. For example, if a memory cell MT stores p bits of data (p is an integer greater than or equal to 1), the storage capacity of the cell unit CU is defined as p pages of data.

[0021] Each bit line BL is connected to the drain of the select transistor ST1 of the corresponding memory string MS in each string unit SU of the block BK and is shared among the memory strings MS in the block BK. The source line SL is connected in common to the source of the select transistor ST2 of each memory string MS included in the block BK and is shared among the string units SU in the block BK. The source line SL can also be shared among the blocks BK.

[0022] Figure 1 The chip 10 (circuit chip) shown includes a row decoder 1012 , a sense amplifier 1013 , a sequencer 1014 , a voltage generating circuit 1015 , and a power supply circuit 1016 .

[0023] The power supply circuit 1016 supplies power Vss and Vcc received via the power supply lines 22 and 23 to each unit. For example, the power supply circuit 1016 supplies power Vss and Vcc to the voltage generating circuit 1015.

[0024] The sequencer 1014 centrally controls various components. For example, the sequencer 1014 controls write operations based on a write command, one of the commands CMD. During this write operation, the sequencer 1014 writes data corresponding to a data signal DAT to the memory cell MT corresponding to the address information ADD in the memory cell array 21. Furthermore, the sequencer 1014 sends a write completion notification to the memory controller 1002. During this read operation, the sequencer 1014 controls read operations based on a read command, one of the commands CMD. During this read operation, the sequencer 1014 reads data from the memory cell MT specified by the address in the memory cell array 21 and returns a data signal DAT corresponding to the read data to the memory controller 1002.

[0025] The voltage generating circuit 1015 generates a voltage according to the control of the sequencer 1014 using power supplies Vss and Vcc, and supplies the voltage to the row decoder 1012 and the sense amplifier 1013 .

[0026] The row decoder 1012 decodes the address information ADD, selects a word line WL corresponding to a memory cell to be written / read in the memory cell array 21 based on the decoding result, and supplies a voltage to the selected word line WL.

[0027] The sense amplifier 1013 decodes the address information ADD and, based on the decoding result, selects a bit line BL corresponding to the memory cell to be written or read in the memory cell array 21. During a write process, the sense amplifier 1013 supplies a voltage to the selected bit line BL. During a read process, the sense amplifier 1013 supplies a voltage to the selected bit line BL and senses the potential of the selected bit line BL.

[0028] Figure 1 The power lines 22, 23 shown can be connected, for example, Figure 3 and Figure 4 Hereinafter, the direction perpendicular to the surface of the substrate 2 is referred to as the Z direction, and two directions perpendicular to each other in a plane perpendicular to the Z direction are referred to as the X direction and the Y direction.

[0029] Figure 3 It is an XY plan view showing the structure of the semiconductor memory device 1 . Figure 4 It is an XZ cross-sectional view showing the structure of the semiconductor memory device 1 . Figure 4 Example will Figure 3 The semiconductor memory device 1 has a substantially rectangular shape in an XY plan view, with the longitudinal direction being the X direction, for example. The semiconductor memory device 1 may include a chip 10 and a chip 20 stacked on the chip 10 .

[0030] like Figure 3 As shown, in the planar layout, a plurality of memory cell arrays 21 are provided in the center of the chip 20, a contact plug CC is provided on one side of the memory cell array 21, and a pad PD3 exposed from the opening TV is provided on the opposite side. The pad PD3 is the wiring MA1 exposed from the opening TV. The contact plug CP1 is arranged below the pad PD3 and overlaps with the pad PD3 in a top view observed from the Z direction. An edge seal ES is provided in a manner surrounding the memory cell array 21, the pad PD3, the contact plug CP1, and CC. In addition, the contact plug CC is used to transmit power, signals, etc. and is connected to a certain element of the chip 10. The edge seal ES is provided to suppress cracks and peeling from the outside.

[0031] like Figure 4As shown, a plurality of stacked bodies SST1 are respectively arranged in a plurality of memory cell arrays 21 in the chip 20. The plurality of stacked bodies SST1 can also be arranged two-dimensionally in the XY direction. Each stacked body SST1 has a roughly rectangular shape when viewed from above in the XY direction. Each stacked body SST1 functions as a part of the memory cell array 21. A plurality of wirings MA1 are arranged on the +Z side of the stacked body SST1. Most of each wiring MA1 is covered by the insulating film DL2, but is partially exposed in the opening TV near the -Y side end. Thus, each wiring MA1 can be bonded to the lead BW described later in the wire bonding installation through the opening TV.

[0032] Wiring MA1 is also provided in the chip 20 to electrically connect to the chip 10 through a contact plug ( Figure 4 CP1). When viewed from above in the Z direction, the wiring MA1 above the contact plug CP1 is provided in an island shape corresponding to the area above the contact plug CP1. An opening TV is also provided in the insulating film DL2 above the wiring MA1 above the contact plug CP1. The wiring MA1 above the contact plug CP1 is also partially exposed from the insulating film DL2 through the opening TV. The wiring MA1 above the contact plug CP1 can also be bonded to a wire (not shown) or the like during wire bonding via the opening TV.

[0033] The wiring MA1 above the contact plug CP1 is provided corresponding to the arrangement of the contact plug CP1 in the chip 20. For example, Figure 3 In FIG, two wirings MA1 are provided at two corners of the surface of the chip 20. However, the number and positions of the wirings MA1 above the contact plugs CP1 are not limited thereto.

[0034] An edge seal ES is provided as a common structure for chips 10 and 20. When viewed from the Z direction, the edge seal ES surrounds the stack SST1 from the outside in the XY directions. Thus, the edge seal ES protects the memory cell array 21 and the circuits that control it (such as the row decoder 1012, sense amplifier 1013, sequencer 1014, voltage generation circuit 1015, and power supply circuit 1016) from external static noise, cracks, and peeling.

[0035] In addition, for the sake of simplicity, illustration of the configuration of the edge seal ES is omitted as appropriate.

[0036] The chip 20 is arranged on the +Z side of the chip 10. That is, the chip 20 is bonded to the surface on the +Z side of the chip 10. The chip 20 has a surface F1 and a surface F2 located on the side opposite to the surface F1. The chip 20 is bonded to the chip 10 on the surface F1 side. Figure 3 The illustrated wiring MA1 and opening TV are provided on the surface F2 side of the chip 20 .

[0037] Chip 10 has an insulating film (e.g., a film containing silicon and oxygen) DL1 and an electrode PD1 on the +Z side. Chip 20 has an insulating film (e.g., a film containing silicon and oxygen) DL2 and an electrode PD2 on the -Z side. At the bonding surface BF1 between chips 10 and 20, the insulating film DL1 of chip 10 is bonded to the insulating film DL2 of chip 20, and the electrode PD1 of chip 10 is bonded to the electrode PD2 of chip 20.

[0038] Chip 10 includes a substrate 2, a transistor Tr, an electrode PD1, a wiring structure WS, and an insulating film DL1. Substrate 2 is located on the -Z side of chip 10 and extends in a plate-like shape in the XY directions. Substrate 2 can be a semiconductor substrate and can be formed from a material primarily composed of a semiconductor (e.g., silicon). Substrate 2 has a surface 2a on the +Z side. Transistor Tr functions as a circuit element for controlling the circuits of memory cell array 21 (row decoder 1012, sense amplifier 1013, sequencer 1014, voltage generating circuit 1015, power supply circuit 1016, etc.). Transistor Tr includes a conductive gate electrode located on surface 2a of substrate 2 via a gate insulating film, and a source / drain electrode located near surface 2a within substrate 2 as a semiconductor region. Electrode PD1 is located so that its surface is exposed at bonding surface BF1 of chips 10 and 20. Wiring structure WS extends primarily in the Z direction and connects the gate electrode, source / drain electrode, etc. of transistor Tr to electrode PD1.

[0039] Chip 20 includes a stacked structure SST1, a conductive layer 5, multiple pillars CL, multiple contact plugs CP2, multiple contact plugs CP1, multiple bit lines BL, multiple wirings MA1, electrodes PD2, and an insulating film DL2. In stacked structure SST1, multiple conductive layers 3 are stacked in the Z direction with insulating layers 4 interposed therebetween. The multiple conductive layers 3 function as select gate line SGD, word line WL3, word line WL2, word line WL1, word line WL0, and select gate line SGS, in this order from the -Z side to the +Z side.

[0040] Each conductive layer 3 extends in a plate shape in the XY direction. Each columnar body CL extends in the Z direction through the plurality of conductive layers 3. Each columnar body CL may also penetrate the stacked body SST1 in the Z direction. Each columnar body CL extends in a columnar shape in the Z direction. Each columnar body CL includes a semiconductor film CH that functions as a channel region (see Figure 5 The semiconductor film CH extends in a columnar shape (e.g., a pillar or a cylinder) having an axis along the Z direction. The multiple intersections where the multiple conductive layers 3 intersect the multiple columnar bodies CL, that is, the multiple intersections where the multiple conductive layers 3 intersect the multiple semiconductor films CH, function as multiple memory cells MT.

[0041] Figure 5(a) is an XZ cross-sectional view showing the structure of the memory cell MT. Figure 4 An enlarged cross-sectional view of part C. Figure 5 (b) is an XY cross-sectional view showing the structure of the memory cell MT. Figure 5 (a) is the cross section when cut along line DD. Figure 5 (a) Figure 5 As shown in (b), each columnar body CL includes an insulating film CR, a semiconductor film CH, an insulating film TNL, a charge storage film CT, an insulating film BLK1, and an insulating film BLK2. The insulating film CR extends in the Z direction to form a columnar shape with an axis along the Z direction. The insulating film CR is formed of an insulator containing silicon and oxygen. The semiconductor film CH extends in the Z direction to cover the insulating film CR from the outside in the XY directions to form a cylindrical shape with an axis along the Z direction. The semiconductor film CH can be formed of a semiconductor containing polycrystalline silicon. The insulating film TNL extends in the Z direction to cover the semiconductor film CH from the outside in the XY directions to form a cylindrical shape with an axis along the Z direction. The insulating film TNL can be formed of an insulator containing silicon and oxygen. The charge storage film CT extends in the Z direction to cover the insulating film TNL from the outside in the XY directions to form a cylindrical shape with an axis along the Z direction. The charge storage film CT can be formed of an insulator containing silicon and nitrogen. The insulating film BLK1 extends in the Z direction to cover the charge storage film CT from the outside in the XY directions, forming a cylindrical shape with an axis along the Z direction. The insulating film BLK1 can be formed of an insulator containing silicon and oxygen. The insulating film BLK2 extends in the Z direction to cover the insulating film BLK1 from the outside in the XY directions, forming a cylindrical shape with an axis along the Z direction. The insulating film BLK2 can be formed of an insulator containing aluminum and oxygen. Figure 5 (a) Figure 5 The portion enclosed by the dotted line in (b) functions as a memory cell MT.

[0042] The semiconductor film CH in the columnar body CL is as follows Figure 4 As shown, the front end reaches the conductive layer 5. The semiconductor film CH is connected to the conductive layer 5 at the +Z side and to the bit line BL via a plug at the -Z side. The conductive layer 5 can be formed of a conductive semiconductor (e.g., polysilicon). The conductive layer 5 functions as the cell source CSL in the source line SL. The semiconductor film CH functions as the channel region in the memory string MS.

[0043] Alternatively, the Y-direction widths of each conductive layer 3 can be equal. The X-direction widths of the multiple conductive layers 3 gradually increase from the -Z side to the +Z side. The X-direction ends of the multiple conductive layers 3 gradually become located outward from the -Z side to the +Z side. Thus, the plug connections in the memory cell array 21 form a staircase structure in which the select gate line SGD, the multiple word lines WL, and the select gate line SGS are sequentially extended from the -Z side to the +Z side.

[0044] Multiple contact plugs CP2 correspond to multiple conductive layers 3. Each contact plug CP2 is arranged between the electrode PD2 and the corresponding conductive layer 3 in the Z direction, with the -Z side end electrically connected to the electrode PD2, extending in the Z direction, and the +Z side end electrically connected to the corresponding conductive layer 3. Thus, the contact plug CP2 electrically connects the electrode PD2 and the corresponding conductive layer 3.

[0045] A plurality of contact plugs CP1 extend along the Z direction between plane F1 and plane F2 and are provided separately from the stack SST1 constituting the memory cell array. The contact plugs CP1 correspond to a plurality of electrodes PD2 and are connected between the electrodes PD2 and the conductive layer 5. That is, the -Z side end of each contact plug CP1 is electrically connected to the electrode PD2, and the +Z side end is electrically connected to the conductive layer 5. The electrode PD2 is connected to the PD1 of the chip 10 via the bonding surface BF1, and is further electrically connected to the substrate 2 or a transistor of the chip 10. The conductive layer 5 is connected to the wiring MA1 on the plane F2 side of the chip 20, and is electrically connected to the leads (not shown) bonded via the opening TV. Thus, an external device can supply power, input commands, or receive data to the circuits of the chip 10 (e.g., CMOS (Complementary Metal Oxide Semiconductor) circuit) via the leads and contact plugs CP1.

[0046] Multiple bit lines BL are arranged on the -Z side of stacked body SST1. The bit lines BL are aligned in the X direction. Each bit line BL extends in the Y direction. The bit lines BL correspond to a plurality of pillars CL. Each bit line BL is electrically connected to the -Z side end of the corresponding pillar CL. The bit lines BL are electrically connected to electrode PD2. Thus, the bit lines BL can be connected to transistors Tr in chip 10 via electrodes PD2, PD1, and wiring structure WS.

[0047] Multiple wiring lines MA1 are arranged on the +Z side of the stack SST1. The multiple wiring lines MA1 on the stack SST1 are aligned in the X direction. Each wiring line MA1 on the stack SST1 extends in the Y direction. When viewed from the Z direction, each wiring line MA1 extends in the Y direction, transversely across the stack SST1. Each wiring line MA1 functions as a power line 22 or 23, and its width and thickness can be determined based on the amount of power to be transmitted and the length of its extension.

[0048] Furthermore, the wiring MA1 is also provided above the end portion of the contact plug CP1 on the surface F2 side. In a plan view seen from the Z direction, the wiring MA1 on the contact plug CP1 overlaps with the contact plug CP1 and covers the end portion of the contact plug CP1 on the surface F2 side.

[0049] The wiring MA1 is made of a low-resistance metal material such as aluminum.

[0050] The conductive layer 5 is disposed on the surface F2 side of the chip 20 and on the +Z side of the stack SST1. The conductive layer 5 on the stack SST1 is common to the multiple pillars CL and MA1 of the stack SST1 and extends in the XY plane corresponding to the stack SST1. The conductive layer 5 is disposed between the stack SST1 and the wiring MA1, electrically connecting the stack SST1 and the wiring MA1. The conductive layer 5 functions as a cell source CSL, capable of supplying a source voltage to each pillar CL.

[0051] Furthermore, the conductive layer 5 is also provided on the end portion of the contact plug CP1 on the surface F2 side. In a plan view viewed from the Z direction, the conductive layer 5 on the contact plug CP1 overlaps with the contact plug CP1 and the wiring MA1 and is provided between the end portion of the contact plug CP1 on the surface F2 side and the wiring MA1.

[0052] Conductive layer 5 is made of a conductive material such as a single crystal semiconductor, polysilicon, titanium, titanium nitride, or tungsten into which an N-type impurity (such as phosphorus or arsenic) is introduced. For example, silicon can be used as the semiconductor material used for conductive layer 5 .

[0053] The electrode PD2 is arranged so that its surface is exposed on the bonding surface BF1 of the chips 10 and 20. Thus, the electrode PD2 is bonded to the electrode PD1 of the chip 10 on the bonding surface BF1.

[0054] Figure 6 : is a cross-sectional view showing a configuration example of the chip 20 according to the first embodiment. Figure 6 , the region R1 of the memory cell array 21, the region Rcc of the contact plug CC, the region R1 of the contact plug CP1, and the region Res of the edge seal ES are shown side by side.

[0055] Wiring MA1 and a conductive layer 5 are provided on the memory cell array 21, pads PD3, contact plugs CP1, CC, and edge seal ES. Wiring MA1 electrically isolates the memory cell array 21, pads PD3, contact plugs CP1, and edge seal ES. Conductive layer 5 also electrically isolates the memory cell array 21, pads PD3, contact plugs CP1, and edge seal ES. Edge seal ES can be electrically floating, but can also be connected to power line 22 to prevent static electricity.

[0056] The conductive layer 5 and wiring MA1 provided in region R2 of the memory cell array 21 are electrically connected to each other and function as the cell source CSL. The conductive layer 5 and wiring MA1 provided in region Rcc of the contact plug CC are electrically connected to each other and function as wiring connected to the contact plug CC. The conductive layer 5 and wiring MA1 provided in region R1 of the contact plug CP1 are electrically connected to each other and function as pad PD3 connected to the contact plug CP1. A wire BW is bonded to the pad PD3. The conductive layer 5 and wiring MA1 provided in region Res of the edge seal ES are electrically connected to each other and function as wiring connected to the edge seal ES. In the second embodiment, the conductive layer 5 has a stacked structure of conductive layers 5a and 5b.

[0057] Wiring MA1 is made of a metal material such as aluminum. Conductive layer 5 is made of a conductive material such as a single crystal semiconductor, polysilicon, titanium, titanium nitride, or tungsten. For example, conductive layer 5a is made of doped polysilicon, and conductive layer 5b is made of a stacked film of titanium, titanium nitride, and tungsten.

[0058] Figure 7 1 is a plan view showing a configuration example of the pad PD3. The wiring MA1 is exposed as the pad PD3 through the opening TV. The wire BW is bonded to the pad PD3.

[0059] In a plan view viewed from the Z direction, wiring MA1 is provided in the region of pad PD3, and contact plug CP1 is provided below wiring MA1. That is, contact plug CP1 is provided in the region of pad PD3 in an overlapping manner. This can reduce the layout area of ​​chip 20.

[0060] Furthermore, in a plan view viewed from the Z direction, the connection portion of the wire BW overlaps with the contact plug CP1. However, since the wiring MA1 is located above the contact plug CP1, the impact of the wire bonding is mitigated by the wiring MA1 and the conductive layer 5. Therefore, damage to the contact plug CP1 caused by the wire bonding can be suppressed.

[0061] Figure 8 1 is a top view showing another configuration example of the pad PD3. Figure 17In the top view from the Z direction, contact plug CP1 is positioned within pad PD3 but does not overlap with the connection portion of lead BW. Specifically, contact plug CP1 is not positioned directly below pad PD3 but rather is positioned at a corner of pad PD3, surrounding the connection portion of lead BW. Lead BW is bonded to the center of pad PD3, offset from directly above contact plug CP1. This prevents the impact of wire bonding from directly impacting contact plug CP1, further minimizing damage to contact plug CP1.

[0062] Thus, in this embodiment, by providing the conductive layer 5 between the wiring MA1 and the contact plug CP1, the end of the contact plug CP1 does not protrude from the surface of the wiring MA1, which serves as the bonding pad. Consequently, even though the wiring MA1 is provided above the contact plug CP1, the surface of the wiring MA1 remains substantially flat, making it easier to perform wire bonding. As a result, poor connections between the wire and the contact plug CP1 can be minimized. Furthermore, the excellent flatness of the boundary between the conductive layer 5 and the wiring MA1 ensures good coverage during film deposition of the wiring MA1, resulting in a highly reliable semiconductor memory device.

[0063] Next, a method for manufacturing the semiconductor memory device 1 according to the first embodiment will be described.

[0064] Figures 9 to 15 It is a cross-sectional view showing an example of a method for manufacturing the semiconductor memory device 1 according to the first embodiment.

[0065] According to the first embodiment, a conductive layer 5a (e.g., doped polysilicon) is deposited on a substrate 50. A stacked structure SST1 is formed on the surface F2 side of the conductive layer 5a. The insulating film DL2, slits SLT, columns CL, contact plugs CP1 and CC, and edge seal ES of the stacked structure SST1 are shown here, and other components are omitted.

[0066] In the first embodiment, during the process of forming the stack SST1, the stack SST1 is etched to form grooves or holes for forming the slits SLT, the columns CL, the contact plugs CP1, CC, and the edge seal ES. The conductive layer 5a is used as an etch stop to form the grooves or holes for forming the slits SLT, the columns CL, the contact plugs CP1, CC, and the edge seal ES. As a result, the end portions Eslt, Ecl, E1, Ecc, and Ees (hereinafter collectively referred to as end portions E1, etc.) of the slits SLT, the columns CL, the contact plugs CP1, CC, and the edge seal ES protrude into the conductive layer 5a.

[0067] The chip 20 formed in this manner is bonded to the chip 20 . Figure 9 The portion of the chip 20 bonded to the chip 10 on the surface F2 side is shown.

[0068] Then, if Figure 10 As shown, the substrate 50 is removed by CMP, and the conductive layer 5 a is etched back to expose the contact plugs CP1 and CC, the columnar bodies CL, and the end portion E1 of the edge seal ES.

[0069] Then, if Figure 11 As shown, the end Ecl of the columnar body CL is slightly etched back. At this time, in the columnar body CL, it is preferred to Figure 5 The insulating film CR is etched back to expose the side surfaces of the semiconductor film CH.

[0070] Then, if Figure 12 As shown, a conductive layer 5b is formed on the conductive layer 5a. For example, the conductive layer 5b can be a tungsten film using a stacked film containing titanium and titanium nitride as a barrier metal. In this case, the conductive layer 5b is a stacked film (Ti / TiN / W) of titanium (Ti), titanium nitride (TiN), and tungsten (W). The conductive layer 5b is electrically connected to the end E1 of the contact plug CP1, the end Ecc of the contact plug CC, the end Ecl of the columnar body CL, and the end Ees of the edge seal ES. In the columnar body CL, the conductive layer 5b can be reliably connected to the side surface and end Ecl of the semiconductor film CH exposed by etching back the insulating film CR.

[0071] Then, if Figure 13 As shown, the conductive layers 5a and 5b (hereinafter also referred to as the conductive layer 5) are processed using photolithography and etching techniques, thereby electrically isolating the conductive layers 5 in the respective regions R2, Rcc, R1, and Res.

[0072] Then, if Figure 14 As shown, an insulating film DL2 is formed on the conductive layer 5. The insulating film DL2 is embedded between the conductive layer 5 regions R2, Rcc, R1, and Res, electrically insulating them. For example, an insulating material containing silicon and oxygen is used for the insulating film DL2. Next, the insulating film DL2 on the conductive layer 5 is processed using photolithography and etching techniques. This exposes the upper portions of the contact plugs CC and CP1 and the edge seal ES in the conductive layer 5.

[0073] Then, if Figure 15 As shown, the material for wiring MA1 is formed on the insulating film DL2 and the conductive layer 5. For example, the wiring MA1 can be formed using a sputtering technique using a metal material such as aluminum. The material for wiring MA1 is formed on the upper portion of the conductive layer 5 of each of the contact plugs CC, CP1, and edge seal ES. Next, the material for wiring MA1 is processed using photolithography and etching techniques. This electrically isolates the wiring MA1 on each of the contact plugs CC, CP1, and edge seal ES.

[0074] Then, an insulating film DL2 is further formed on the wiring MA1, and the insulating film DL2 on the contact plug CP1 is removed using photolithography and etching techniques to form an opening TV. Figure 6 The pad PD3 is shown. By bonding the wire BW to the pad PD3, the Figure 6 The semiconductor memory device 1 is shown.

[0075] According to the first embodiment, the conductive layer 5 covers the contact plug CC, CP1, the slit SLT, and the end E1 of the edge seal ES. The conductive layer 5b on the upper portion of the conductive layer 5 contains a metal material such as tungsten, so even if the insulating film DL2 containing silicon and oxygen is processed, it is not etched much. Therefore, the surface of the conductive layer 5 on the side F2 can maintain a roughly flat state. As a result, the wiring MA1 on the conductive layer 5 also becomes roughly flat, and a bonding pad can be easily formed directly above the contact plug CP1. As a result, Figure 7 and Figure 8 As shown, the contact plug CP1 and the pad PD3 can be overlapped in a plan view seen from the Z direction. As a result, miniaturization of the semiconductor memory device 1 is facilitated.

[0076] Furthermore, in the first embodiment, although the conductive layer 5 is electrically isolated from each other in the regions R2, Rcc, R1, and Res, it is formed in the same process and in the same layer from the same material (e.g., tungsten). Similarly, the wiring MA1 is electrically isolated from each other in the regions R2, Rcc, R1, and Res, but it is formed in the same process and in the same layer from the same material (e.g., aluminum). Therefore, there is no need to form the conductive layer 5 and wiring MA1 separately in the regions R2, Rcc, R1, and Res, which helps shorten the manufacturing process.

[0077] (Second embodiment) Figure 16 This is a cross-sectional view illustrating an example configuration of a semiconductor memory device 1 according to a second embodiment. In the second embodiment, the conductive layer 5a is provided only in region R2 of the memory cell array 21 and is not provided in the other contact plugs CC and CP1, or in regions Rcc, R1, and Res of the edge seal ES. The remaining configuration of the second embodiment may be the same as that of the first embodiment.

[0078] Even if the conductive layer 5 a is not provided in the regions Rcc, R1, and Res, the second embodiment can obtain the same effects as those of the first embodiment as long as the conductive layer 5 b is formed substantially flat.

[0079] Figure 17 and Figure 18This is a cross-sectional view showing an example of a method for manufacturing the semiconductor memory device 1 according to the second embodiment. Figures 9 to 11 After the described process, Figure 17 As shown, the conductive layer 5a is processed using photolithography and etching techniques. Thus, the conductive layer 5a in the regions Rcc, R1, and Res is removed, leaving the conductive layer 5a only in the region R2 of the memory cell array 21.

[0080] Then, if Figure 18 As shown, a conductive layer 5b is formed on the conductive layer 5a, the contact plugs CC and CP1, and the edge seal ES.

[0081] Then, after referring to Figures 13 to 15 The described process is thus completed Figure 16 The semiconductor memory device 1 is shown.

[0082] According to the second embodiment, the conductive layer 5 in region R2 of the memory cell array 21 is formed as a stacked film of conductive layers 5a and 5b, while the conductive layer 5 in the other regions Rcc, R1, and Res is formed as conductive layer 5b. In this manner, the material of the conductive layer 5 can be changed between region R2 and the other regions Rcc, R1, and Res of the memory cell array 21.

[0083] (Third embodiment) Figure 19 : This is a cross-sectional view showing an example of the structure of the semiconductor memory device 1 according to the third embodiment. In the third embodiment, for example, a conductive layer 5a made of polysilicon is not provided, but a conductive layer 5b made of a metal material such as tungsten is provided in regions R2, Rcc, R1, and Res. Although the conductive layers 5b are electrically separated from each other in regions R2, Rcc, R1, and Res, they are formed in the same process and are formed from the same material in the same layer. The conductive layer 5b is, for example, a stacked film (Ti / TiN / W) of titanium (Ti), titanium nitride (TiN), and tungsten (W). The conductive layer 5b provided in region R1 is in contact with the contact plug CP1. The conductive layer 5b provided in region Rcc is in contact with the contact plug CC. The conductive layer 5b provided in region R2 is in contact with the columnar body CL. The conductive layer 5b provided in region Res is in contact with the edge seal ES. The other structures of the fourth embodiment may be the same as those of the third embodiment.

[0084] Even if the conductive layer 5 a is not provided, the third embodiment can obtain the same effects as those of the second embodiment as long as the conductive layer 5 b is formed substantially flat.

[0085] The manufacturing method of the third embodiment can be easily understood based on the manufacturing method of the second embodiment, so its illustration is omitted. For example, after the conductive layer 5a functions as an etching stopper in the formation process of the contact plugs CP1 and CC, Figure 17 In the process shown, all of the regions R2, Rcc, R1, and Res are removed. Figure 18 The described process is thus completed Figure 19 The semiconductor memory device 1 is shown.

[0086] (Fourth embodiment) Figure 20 It is a cross-sectional view showing a configuration example of a semiconductor memory device 1 according to a fourth embodiment. Figure 21 It is a plan view showing a configuration example of a semiconductor memory device 1 according to a fourth embodiment.

[0087] In the fourth embodiment, in the region R2 of the memory cell array 21, a conductive layer 5a made of, for example, polysilicon is provided, and a conductive layer 5b made of a metal material is not provided. On the other hand, in the region Rcc of the contact plug CC, the region R2 of the contact plug CP1 and the pad PD3, and the region Res of the edge seal ES, a conductive layer 5b made of, for example, a metal material such as tungsten is provided, and no conductive layer 5a is provided. The conductive layer 5a in the region R2 is electrically isolated from the conductive layer 5b in the regions Rcc, R1, and Res. The conductive layer 5b provided in the region R1 is in contact with the contact plug CP1. The conductive layer 5b provided in the region Rcc is in contact with the contact plug CC. The conductive layer 5a provided in the region R2 is in contact with the columnar body CL. The conductive layer 5b provided in the region Res is in contact with the edge seal ES. The other configurations of the fourth embodiment may be the same as those of the third embodiment.

[0088] Even if different conductive layers 5a and 5b are provided in the region R2 and the regions Rcc, R2, and Res of the memory cell array 21, the fourth embodiment can achieve the same effects as those of the third embodiment as long as the conductive layer 5b is formed substantially flat.

[0089] Figures 22 to 24 This is a cross-sectional view showing an example of a manufacturing method of the fourth embodiment. Figure 9 After the described steps, the substrate 50 is removed.

[0090] Then, if Figure 22 As shown in FIG. 1 , a mask material HM is formed on the conductive layer 5a. Then, using photolithography and etching techniques, the mask material HM in the region R2 is left, and the mask material HM in the other regions Rcc, R1, and Res is removed. Then, the mask material HM is used as a mask to process the conductive layer 5a. Figure 23As shown, the conductive layer 5a in the regions Rcc, R1, and Res is removed, leaving the conductive layer 5a in the region R2 of the memory cell array 21. At this time, the ends Ecc, E1, and Ees of the contact plugs CC and CP1 and the edge seal ES may protrude from the insulating film DL2.

[0091] Then, if Figure 24 As shown, the material for conductive layer 5b is deposited in regions R2, Rcc, R1, and Res. As a result, in regions Rcc, R1, and Res, the contact plugs CC and CP1 and the end portions Ecc, E1, and Ees of the edge seal ES are covered and buried by conductive layer 5b. This makes the surface of conductive layer 5b on the F2 side substantially flat.

[0092] Then, after referring to Figures 13 to 15 The described process is thus completed Figure 20 The semiconductor memory device 1 is shown.

[0093] (Fifth embodiment) Figure 25 This is a cross-sectional view illustrating an example configuration of a semiconductor memory device 1 according to a fifth embodiment. In the fifth embodiment, an insulating film DL2 is provided between contact plug CP1 and pad PD3 (wiring MA1) in region R1. The insulating film DL2 is provided above end E1 of contact plug CP1 and between conductive layer 5 and pad PD3. Contacts CNT are provided on both sides of the insulating film DL2, and pad PD3 is electrically connected to conductive layer 5 via the contacts CNT.

[0094] The insulating film DL2 is provided below the connection portion of the wire BW, thereby further mitigating the impact of the wire BW bonding. Consequently, damage to the contact plug CP1 caused by the wire bonding can be further suppressed. The remaining configuration of the fifth embodiment can be the same as that of the first embodiment. Therefore, the fifth embodiment can achieve the same effects as the first embodiment.

[0095] The fifth embodiment can also be combined with the second to fourth embodiments. Thus, the fifth embodiment can also obtain the effects of any of the second to fourth embodiments.

[0096] Figure 26 and Figure 27 This is a cross-sectional view showing an example of a method for manufacturing the semiconductor memory device 1 according to the fifth embodiment. Figures 9 to 13 After the process described, refer to Figure 14 In the above-described step of forming the insulating film DL2, the insulating film DL2 is left on the contact plug CP1 in the region R1. Figure 26Contact holes CNTH for contacts CNT are formed on both sides of the contact plug CP1 in the region R1.

[0097] Then, if Figure 27 As shown, the material for wiring MA1 is formed on the insulating film DL2 and the conductive layer 5. The material for wiring MA1 is formed on the conductive layer 5 in each of regions R2, Rcc, R1, and Res. Next, the material for wiring MA1 is processed using photolithography and etching techniques. This electrically isolates the wiring MA1 on the memory cell array 21, contact plugs CC and CP1, and edge seal ES. Furthermore, in region R1, the material for wiring MA1 is embedded in contact holes CNTH, and contacts CNT are formed on both sides of the insulating film DL2. Contacts CNT are connected to the conductive layer 5.

[0098] Then, an insulating film DL2 is further formed on the wiring MA1, and the insulating film DL2 on the contact plug CP1 is removed using photolithography and etching techniques to form an opening TV and a pad PD3. By bonding the lead BW to the pad PD3, the wiring MA1 is completed. Figure 25 The semiconductor memory device 1 is shown.

[0099] (Sixth embodiment) Figure 28 This is a cross-sectional view illustrating an example configuration of a semiconductor memory device 1 according to a sixth embodiment. In the sixth embodiment, conductive layer 5 is a stacked film of conductive layers 5a, 5b, and 5c. Conductive layer 5c is provided between conductive layers 5a and 5b and comprises, for example, polycrystalline silicon. The remaining configuration of the sixth embodiment can be the same as that of the first embodiment. Therefore, the sixth embodiment can achieve the same effects as the first embodiment.

[0100] According to the manufacturing method of the sixth embodiment, after the conductive layer 5 c is formed in the first embodiment, the conductive layer 5 b is formed and the conductive layer 5 c is processed in the same manner as the conductive layer 5 b.

[0101] (Seventh embodiment) Figure 29This is an XY top view showing an example of the configuration of a semiconductor memory device 1 according to a seventh embodiment. The semiconductor memory device 1 may include a chip 10 and a chip 20 stacked on the chip 10. Multiple stacks SST1 are each arranged in a plurality of memory cell arrays 21 in the chip 20. The multiple stacks SST1 may also be arranged two-dimensionally in the XY directions. Each stack SST1 has a generally rectangular shape when viewed from an XY top view, for example, with the X direction as the longitudinal direction. Each stack SST1 functions as a portion of the memory cell array 21. Multiple wirings MA1 are arranged on the +Z side of the stack SST1. The multiple wirings MA1 are aligned with each other in the X direction. Each wiring MA1 extends in the Y direction. When viewed from the Z direction, each wiring MA1 extends in the Y direction so as to cross-section the stack SST1. Each wiring MA1 functions as a power line 22 or 23 and has a width and thickness corresponding to the amount of power to be transmitted and the length of its extension. Most of each wiring MA1 is covered by the insulating film DL2, but the -Y side end is partially exposed in the opening TV. Thus, each wiring MA1 can be bonded to the wire BW described later in the wire bonding installation through the opening TV. Figure 29 The cross section when cut along line AA is as follows. Figure 4 shown.

[0102] Figure 30 : is a cross-sectional view showing a configuration example of a semiconductor memory device 1 according to a seventh embodiment. Figure 30 For convenience, region R1 of contact plug CP1 and region R2 of memory cell array 21 are shown side by side. Furthermore, to distinguish the configurations of regions R1 and R2, conductive layer 5, wiring MA1, and opening TV in region R1 of contact plug CP1 are shown as conductive layer 5_1, wiring MA1_1, and opening TV_1, respectively, and conductive layer 5, wiring MA1, and opening TV in region R2 of memory cell array 21 are shown as conductive layer 5_2, wiring MA1_2, and opening TV_2, respectively.

[0103] In region R1 of contact plug CP1, contact plug CP1 extends between planes F1 and F2 in the Z direction and is disposed between electrode PD2 and conductive layer 5_1. End E1 of contact plug CP1 on the plane F2 side is located within conductive layer 5_1 and does not reach wiring MA1_1. Wiring MA1_1 is disposed on conductive layer 5_1 and above contact plug CP1 (directly above in the +Z direction). Wiring MA1_1 is electrically connected to contact plug CP1 via conductive layer 5_1. Because end E1 of contact plug CP1 does not reach wiring MA1_1, wiring MA1_1 can be formed on the substantially flat surface of conductive layer 5_1. Consequently, the surface of wiring MA1_1 is also substantially flat, allowing wiring MA1_1 to function as a pad that facilitates wire bonding. Insulating film DL2 covers wiring MA1_1 and MA1_2, exposing portions of each wiring MA1_1 and MA1_2 as bonding pads. The opening TV_1 exposes a portion of the wiring MA1_1 from the insulating film DL2 , and can allow the portion of the wiring MA1_1 to function as a bonding pad.

[0104] In region R2 of the memory cell array 21, the memory cell array 21 is disposed between planes F1 and F2. End E2 of the memory cell array 21 on the plane F2 side is located within the conductive layer 5_2 and does not reach the wiring MA1_2. The wiring MA1_2 is disposed on the conductive layer 5_2 and above the memory cell array 21 (directly above in the +Z direction). The wiring MA1_2 is electrically connected to the memory cell array 21 via the conductive layer 5_2. The opening TV_2 exposes a portion of the wiring MA1_2 from the insulating film DL2, allowing the portion of the wiring MA1_2 to function as a bonding pad.

[0105] The conductive layer 5_1 and the conductive layer 5_2 are provided on the same layer and contain the same material. Therefore, the heights of the conductive layer 5_1 and the conductive layer 5_2 in the Z direction are also substantially the same, and processing is also easy. For example, the conductive layers 5_1 and 5_2 can be made of single crystal silicon into which N-type impurities have been introduced. In this case, the conductive layers 5_1 and 5_2 can be semiconductor regions of a silicon substrate into which N-type impurities (e.g., phosphorus or arsenic) have been introduced and electrically separated from each other by the insulating isolation portion STI. The conductive layers 5_1 and 5_2 are electrically separated by the insulating isolation portion STI and can each function as a conductive layer. In addition, the conductive layers 5_1 and 5_2 can function as etching stoppers in the formation process of the contact plug CP1 or the columnar body CL.

[0106] Furthermore, wiring MA1_1 and wiring MA1_2 are provided on the same layer and comprise the same material. Therefore, the Z-direction heights of wiring MA1_1 and wiring MA1_2 are also substantially the same, making processing easier. For example, wiring MA1_1 and MA1_2 are comprised of a low-resistance metal material such as aluminum. Wiring MA1_1 and MA1_2 are electrically separated by insulating film DL2, allowing each to function as a bonding pad. Since wiring MA1_1 and wiring MA1_2 have substantially the same height, the Z-direction heights of the bonding pads of wiring MA1_1 and wiring MA1_2 are also substantially the same. This also facilitates wire bonding.

[0107] Thus, in the seventh embodiment, by providing the conductive layer 5_1 between the wiring MA1_1 and the contact plug CP1, the end E1 of the contact plug CP1 does not protrude from the surface of the wiring MA1_1, which serves as the bonding pad. Consequently, even though the wiring MA1_1 is provided above the contact plug CP1, the surface of the wiring MA1_1 is substantially flat, making it easier to perform wire bonding. As a result, poor connection between the wire and the contact plug CP1 can be suppressed.

[0108] Furthermore, in the seventh embodiment, the wiring MA1_1 can be arranged so as to overlap above the contact plug CP1 , and thus the size of the chip 10 can be reduced.

[0109] Next, a method for manufacturing the semiconductor memory device 1 according to the seventh embodiment will be described.

[0110] Figures 31 to 37 It is a cross-sectional view showing an example of a method for manufacturing the semiconductor memory device 1 according to the seventh embodiment. Figures 31 to 33 The following shows the manufacturing process of the chip 20 having the memory cell array 21.

[0111] First, if Figure 31 As shown, using ion implantation techniques, N-type impurities (e.g., phosphorus or arsenic) are introduced into the surface region of substrate 50 on the surface F1 side. Substrate 50 is, for example, a single crystal silicon substrate. By introducing N-type impurities, a single crystal silicon layer containing N-type impurities is formed on the surface of substrate 50. This single crystal silicon layer has a relatively high concentration of N-type impurities. This single crystal silicon layer later becomes conductive layers 5_1 and 5_2.

[0112] Next, the single crystal silicon layer (hereinafter also referred to as N + The single crystal silicon layer is processed to form a trench for forming an isolation portion STI. By burying an insulating material in the trench, the N + Insulation isolation STI is formed in the single crystal silicon layer, and N +The insulating isolation portion STI separates the N-type silicon layer from the predetermined region R1 where the contact plug CP1 is formed and the predetermined region R2 where the memory cell array 21 is formed. + The single crystal silicon layer is separated. The insulating isolation portion STI is made of an insulating material such as a film containing silicon and oxygen. + The single crystal silicon layer is formed in each of a planned region R1 where the contact plug CP1 is to be formed and a planned region R2 which is separated from the region R1 and where the memory cell array 21 is to be formed.

[0113] Then, if Figure 32 As shown, a sacrificial layer SAC including a film containing silicon and oxygen, a film containing silicon and nitrogen, and a film containing silicon and oxygen is formed on the substrate 50. The sacrificial layer SAC is replaced with a material for a cell source (e.g., polysilicon) connected to the semiconductor film CH of the columnar body CL in a subsequent process. Furthermore, a material for a cell source (e.g., polysilicon) is formed on the sacrificial layer SAC. Thus, Figure 32 The structure shown.

[0114] Next, a stacked body SST1 is formed for the memory cell array 21. Note that illustration of the steps for forming the memory cell array 21 is omitted as appropriate.

[0115] The insulating layers 4 are alternately stacked on the sacrificial layers SAC on the surface F1 side of the substrate 50 (see Figure 4 ) and a sacrificial film (not shown) to form a stacked body SST1. At this stage, the conductive layer 3 has not yet been formed (refer to Figure 4 ), the laminate SST1 becomes a laminate of the insulating layer 4 and the sacrificial film. The sacrificial film is, for example, a film containing silicon and nitrogen that can be selectively removed relative to the insulating layer 4. Next, a memory hole is formed through the laminate SST1, and a reference is formed in the memory hole. Figure 5 The columnar body CL is illustrated.

[0116] Next, the stacked body SST1 is processed into a stair-like shape using photolithography and etching techniques, and then contact plugs CP2 are formed to reach the surface of each step of the stair-like shape.

[0117] Next, a slit SLT is formed that penetrates the stacked body SST1 in the Z direction, and the sacrificial layer SAC is removed through the slit SLT. Next, the insulating film BLK2, the insulating film BLK1, the charge storage film CT, and the insulating film TNL located around the semiconductor film CH of the columnar body CL are removed. The material of the conductive film 40 (for example, doped polysilicon) is buried in the space area after the sacrificial layer SAC is removed, and the sacrificial layer SAC is replaced with the material of the conductive film 40. Thus, a conductive film 40 is formed. Figure 33 The conductive film 40 shown (DSC process) is in direct contact with the semiconductor film CH of the columnar body CL at the lower end portion of the columnar body CL.

[0118] Next, the sacrificial film of the stack SST1 is replaced with the conductive layer 3 via the slit SLT. As a result, the stack SST1 becomes a stack composed of alternating conductive layers 3 and insulating layers 4. Furthermore, the conductive layer 3 is provided around each columnar body CL and functions as the gate electrode of the memory cell. Furthermore, the conductive layer 3 is connected to the corresponding contact plug CP2 and can receive a gate voltage from each contact plug CP2.

[0119] The slit SLT may be entirely buried in an insulating film. Alternatively, the slit SLT may be formed by forming an insulating film thinly on its inner wall and then burying a conductor inside the insulating film, thereby forming a wiring electrically connected to the conductive layer 5_2 in a state insulated from the stacked body SST1. In this way, the stacked body SST1 of the memory cell array 21 is formed. In addition, the end E2 of the columnar body CL and the slit SLT reaches the conductive layer 5_2. However, since the conductive layer 5_2 contains N + The single crystal silicon layer therefore does not penetrate the conductive layer 5_2 but stays within the conductive layer 5_2.

[0120] Next, a contact hole is formed in the insulating film DL2 on the region R1, reaching the conductive layer 5_1, and a conductive material (e.g., a metal material such as copper or tungsten) is embedded in the hole. Thus, a contact plug CP1 is formed that extends from the surface of the insulating film DL2 in the Z direction and reaches the conductive layer 5_1. The end E1 of the contact plug CP1 reaches the conductive layer 5_1. However, since the conductive layer 5_2 contains N + The single crystal silicon layer therefore does not penetrate the conductive layer 5_1 but stays within the conductive layer 5_1 .

[0121] Next, an electrode PD2 is formed on the contact plug CP1. Electrode PD2 is made of a metal material such as copper or tungsten. Figure 33 The structure of the chip 20 is shown.

[0122] Then, if Figure 34 As shown in FIG. 1 , the surface F1 of the chip 20 is attached to the chip 10. Thus, the electrode PD2 is bonded to the pad of the chip 10. Figures 34 to 37 In FIG, the internal structure of the chip 10 is omitted. The structure of the chip 10 is as shown in FIG. Figure 4 As described above, the contact plug CP1 can electrically connect the conductive layer 5_1 and the elements of the chip 10 .

[0123] Then, if Figure 35As shown, the substrate 50 is polished using a CMP (Chemical Mechanical Polishing) method or the like until the insulating isolation portion STI is exposed on the surface F2 side of the chip 20. Thus, the substrate 50 except for the conductive layers 5_1 and 5_2 is removed. At this time, the insulating isolation portion STI functions as a stop for the CMP process. The conductive layers 5_1 and 5_2 remain, exposed on the surface F2 side while being electrically separated by the insulating isolation portion STI. At this time, the end E1 of the contact plug CP1 does not penetrate the conductive layer 5_1 but remains within the conductive layer 5_1, so that the surface of the conductive layer 5_1 on the surface F2 side is approximately flat. Furthermore, the ends of the pillars CL and the slits SLT do not penetrate the conductive layer 5_2 but remain within the conductive layer 5_2, so that the surface of the conductive layer 5_2 on the surface F2 side is also approximately flat.

[0124] Then, if Figure 36 As shown, the material of the wiring MA1_1 and MA1_2 (for example, a metal material such as aluminum) is formed on the conductive layers 5_1 and 5_2. Then, the wiring MA1_1 and MA1_2 are processed using photolithography and etching techniques. As a result, the wiring MA1_1 and MA1_2 are formed in a state of being separated from each other on the conductive layers 5_1 and 5_2 in the regions R1 and R2, respectively. Since the surfaces of the conductive layers 5_1 and 5_2 are roughly flat, the surfaces of the wiring MA1_1 and MA1_2 are also roughly flat. In addition, as shown in FIG. Figure 3 As shown, the conductive layer 5_1 is provided in an island shape in the region R1 where the contact plug CP1 is located, and the conductive layer 5_2 is provided in a stripe shape in the region R2 where the stacked body SST1 is located.

[0125] Then, if Figure 37 As shown in FIG. 1 , an insulating film DL2 is formed on the wirings MA1_1 and MA1_2 and the conductive layers 5_1 and 5_2. The insulating film DL2 may be a film containing silicon and oxygen, for example.

[0126] Next, using photolithography and etching techniques, a portion of the insulating film DL2 on the wirings MA1_1 and MA1_2 is removed. This results in openings TV_1 and TV_2 being formed on the surfaces of the wirings MA1_1 and MA1_2, respectively. Specifically, a conductive layer 5_1, wiring MA1_1, and opening TV_1 are provided directly above contact plug CP1 (in the +Z direction). The wiring MA1_1 exposed in opening TV_1 functions as a bonding pad. A conductive layer 5_2, wiring MA1_2, and opening TV_2 are provided above laminate SST1 (in the +Z direction). The wiring MA1_2 exposed in opening TV_2 functions as a bonding pad.

[0127] Then, after a wire bonding step and the like, the semiconductor memory device 1 of this embodiment is completed.

[0128] Thus, according to the seventh embodiment, before forming the contact plug CP1 or attaching the chip 10, the conductive layer 5_1 (eg, N + Single crystal silicon layer). Conductive layer 5_1 covers end E1 of contact plug CP1, and the surface of conductive layer 5_1 on the side of plane F2 becomes substantially flat. As a result, wiring MA1_1 on conductive layer 5_1 also becomes substantially flat, making it easy to form a bonding pad above contact plug CP1.

[0129] Conductive layer 5_2 (eg N + The single crystal silicon layer also accommodates the pillars CL and the ends E2 of the slits SLT, similarly to the conductive layer 5_1, making the surface of the conductive layer 5_2 substantially flat. This also makes the wiring MA1_2 on the conductive layer 5_2 substantially flat, making it easy to form bonding pads on the laminate SST1.

[0130] If the conductive layers 5_1 and 5_2 are not pre-separated by the insulating isolation portion STI, the conductive film 40 is provided at the end E1 of the contact plug CP1. After the chip 20 is attached to the chip 10, the conductive film 40 formed of polysilicon or the like is processed as the cell source CSL. In this case, during the processing of the cell source CSL and the formation of the opening TV for the bonding pad, the end E1 of the contact plug CP1 is exposed in a convex shape, making it impossible to form the wiring MA on the contact plug CP1 with good coverage. In this case, the bonding pad of the contact plug CP1 needs to be formed separately from the wiring MA.

[0131] In contrast, according to the seventh embodiment, the conductive layer 5_1 covers the end E1 of the contact plug CP1. Since the conductive layer 5_1 is already separated from the conductive layer 5_2 by the insulating isolation portion STI, the conductive layer 5_1 itself does not need to be processed after the chip 20 is bonded to the chip 10. Furthermore, since the conductive layer 5_1 comprises, for example, a single crystal silicon layer, it is less likely to be etched even if the opening TV_1 is formed in the insulating film DL2 containing silicon and oxygen. Therefore, the surface of the conductive layer 5_1 on the side of the plane F2 can be maintained in a substantially flat state. Consequently, the wiring MA1_1 on the conductive layer 5_1 also becomes substantially flat, making it easy to form a bonding pad directly above the contact plug CP1. This contributes to the miniaturization of the semiconductor memory device 1.

[0132] In the seventh embodiment, although the conductive layers 5_1 and 5_2 are electrically separated from each other, they are formed in the same process and made of the same material (eg, N +Similarly, although electrically separated, wirings MA1_1 and MA1_2 are formed in the same process and in the same layer from the same material (e.g., a metal material such as aluminum). Therefore, in regions R1 and R2, there is no need to separately form conductive layers 5_1 and 5_2, wirings MA1_1 and MA1_2, and openings TV_1 and TV_2, thereby shortening the manufacturing process.

[0133] Furthermore, in the seventh embodiment, before forming the pillars CL and the slits SLT, the conductive layer 5_2, which functions as the cell source CSL, is formed in a state connected to the substrate 50. Therefore, the charge generated during the steps of forming the memory holes in the pillars CL or the slits SLT can be discharged from the conductive layer 5_2 to the substrate 50. This eliminates the need for a conductor connecting the conductive film 40 and the substrate 50, which has been conventionally provided to counteract arc discharge.

[0134] (Material of Conductive Layer 5) The material of the conductive layer 5 can be various combinations of the region R2 and the regions Rcc, R1, and Res. Figure 38 This is a table showing an example of the combination of the material of the conductive layer 5 in the region R2 and the material of the conductive layer 5 in the regions Rcc, R1, and Res.

[0135] Figure 38 The Ti / TiN / W film represents a stacked film of titanium (Ti), titanium nitride (TiN), and tungsten (W). Titanium (Ti) and titanium nitride (TiN) serve as a base (barrier metal) for tungsten (W). For example, Figure 19 The conductive layer 5b includes a Ti / TiN / W film. The conductive layer 5b may be a single layer film of any one of titanium (Ti), titanium nitride (TiN), and tungsten (W).

[0136] The Ti(poly) / TiN / W film represents a stacked film of a polysilicon film used as a stopper when forming the contact plug CP1, etc., and titanium (Ti), titanium nitride (TiN), and tungsten (W) stacked thereon. For example, Figure 6 The conductive layer 5 is a stacked film including a conductive layer 5 a containing polysilicon and a conductive layer 5 b containing a Ti / TiN / W film.

[0137] The poly / Ti / TiN / W film represents a stacked film of a polysilicon film serving as a stopper, a polysilicon film stacked thereon, and a Ti / TiN / W film. For example, Figure 28 The conductive layer 5 is a stacked film including a conductive layer 5a containing polycrystalline silicon, a conductive layer 5c containing polycrystalline silicon stacked thereon, and a conductive layer 5b containing a Ti / TiN / W film.

[0138] The poly film means that the conductive layer 5 that functions as the cell source CSL of the memory cell array 21 includes polysilicon. Figure 29 In region R2, the conductive layer 5a comprises polysilicon. In regions Rcc, R1, and Res, the conductive layer 5b comprises a Ti / TiN / W film. The poly film may be the conductive film 40 that is replaced in the above-mentioned DSC process.

[0139] By combining these films in the region R2 and the regions Rcc, R1, and Res, the conductive layer 5 can be formed.

[0140] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways and can be omitted, replaced, or modified in various ways without departing from the scope of the invention. These embodiments and their variations are included in the scope and spirit of the invention and are included in the scope equivalent to the invention described in the claims.

Claims

1. A semiconductor memory device comprising: A first chip comprising transistors; and A second chip includes a memory cell array, The second chip comprises: a first surface, which is bonded to the first chip; a second surface located on the opposite side of the first surface; a contact extending between the first surface and the second surface and disposed separately from the memory cell array; a first wiring layer provided above a first end of the second surface side of the contact and electrically connected to the contact; and A first conductive layer is provided between the first end of the contact and the first wiring layer.

2. The semiconductor memory device according to claim 1, wherein The second chip further includes a second wiring layer, which is provided between the memory cell array and the second surface and is electrically connected to the memory cell array. The second wiring layer is provided in the same layer as the first wiring layer and includes the same material as the first wiring layer.

3. The semiconductor memory device according to claim 2, wherein The second chip further includes a second conductive layer, which is provided between the memory cell array and the second wiring layer and is electrically connected to the memory cell array. The second conductive layer is disposed on the same layer as the first conductive layer and comprises the same material as the first conductive layer.

4. The semiconductor memory device according to claim 2 or 3, wherein: The second chip further includes a first insulating layer covering the first wiring layer and the second wiring layer, exposing a portion of the first wiring layer as a first pad and exposing a portion of the second wiring layer as a second pad.

5. The semiconductor memory device according to claim 2 or 3, wherein The second chip further includes a first insulating layer that covers the second wiring layer and exposes a portion of the second wiring layer as a second pad.

6. The semiconductor memory device according to any one of claims 2 to 5, wherein The contact overlaps with a connection portion of a lead connected to the first pad when viewed from a direction perpendicular to the first surface.

7. The semiconductor memory device according to any one of claims 2 to 5, wherein The contact is located around a connection portion of a lead connected to the first pad when viewed from a direction perpendicular to the first surface.

8. The semiconductor memory device according to any one of claims 1 to 7, wherein The first conductive layer includes one of polysilicon containing impurities, titanium, titanium nitride, and tungsten.

9. The semiconductor memory device according to any one of claims 1 to 8, wherein The second conductive layer includes any one of polysilicon containing impurities, titanium, titanium nitride, and tungsten.

10. The semiconductor memory device according to any one of claims 1 to 9, wherein The material of the first conductive layer is different from the material of the second conductive layer.

11. The semiconductor memory device according to any one of claims 1 to 10, wherein A second insulating film is further provided above the contact and between the first conductive layer and the first wiring layer.

12. The semiconductor memory device according to any one of claims 1, 3 to 9, wherein The first conductive layer includes single crystal silicon containing impurities.

13. The device according to claim 12, wherein The first end is located in the first conductive layer.

14. A method for manufacturing a semiconductor memory device, the semiconductor memory device comprising a first chip and a second chip, the first chip comprising transistors, the second chip comprising a memory cell array, the method comprising: forming the second chip including contacts and the memory cell array using a substrate; Laminating the first chip to the first surface of the second chip on the side opposite to the substrate; removing the substrate from a second surface of the second chip opposite to the first surface; forming a first conductive layer and a second conductive layer electrically insulated from each other respectively on the contacts and the memory cell array on the second surface side of the second chip; as well as forming an electrically insulated first wiring layer and a second wiring layer on the first conductive layer and the second conductive layer, respectively; The forming of the second chip includes: forming the contact on a first region of the substrate; as well as The memory cell array is formed on the second region of the substrate separated from the first region.

15. The manufacturing method according to claim 14, wherein: Before forming the contacts and the memory cell array, the method further includes: forming a material film on the first region and the second region of the substrate, In forming the contact and the memory cell array, the contact and the memory cell array are formed using the material film as an etching stopper. In the forming of the first conductive layer and the second conductive layer, the first conductive layer and the second conductive layer are formed on the material film.

16. The method according to claim 14, wherein The first conductive layer is formed of a single layer or a stacked film of polycrystalline silicon containing impurities, titanium, titanium nitride, or tungsten.

17. The manufacturing method according to claim 14, wherein: The second conductive layer is formed using a single layer or a stacked film of polycrystalline silicon containing impurities, titanium, titanium nitride, or tungsten.

18. A method for manufacturing a semiconductor memory device, the semiconductor memory device comprising a first chip and a second chip, the first chip comprising transistors, the second chip comprising a memory cell array, the method comprising: forming the second chip using a substrate including a first semiconductor region and a second semiconductor region; Laminating the first chip to the first surface side of the second chip on the side opposite to the substrate; On a second surface side of the second chip opposite to the first surface, removing the substrate except for the first semiconductor region and the second semiconductor region; as well as forming a first wiring layer and a second wiring layer over each of the first semiconductor region and the second semiconductor region, respectively; The forming of the second chip includes: The first semiconductor region where the contact is to be formed and the second semiconductor region separated from the first semiconductor region and where the memory cell array is to be formed are formed by introducing impurities into the substrate and forming an insulating separation portion on the substrate; as well as The memory cell array connected to the second semiconductor region is formed on the second semiconductor region, and the contact reaching the first semiconductor region is formed on the first semiconductor region.

19. The manufacturing method according to claim 18, wherein: forming an insulating film on the first wiring layer and the second wiring layer, By opening a portion of the insulating film, a portion of the first wiring layer is exposed as a first pad, and a portion of the second wiring layer is exposed as a second pad.

20. The manufacturing method according to claim 18, wherein The first semiconductor region and the second semiconductor region use single crystal silicon containing impurities.

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