Semiconductor device

Abstract

Provided is a semiconductor device including different types of memory devices in the same chip. And the data transmission speed between the two storage devices is improved. The semiconductor device includes a first layer, a second layer, and a third layer. The first layer includes a first memory device in which a plurality of nonvolatile first memory elements are stacked in a thickness direction of the first layer. The second layer includes a second memory device having a plurality of second memory elements including a transistor having an oxide semiconductor. The third layer includes a first driving circuit that controls operation of the first memory device and a second driving circuit that controls operation of the second memory device. The first layer, the second layer, and the third layer have portions overlapping each other.

Description

Technical Field

[0001] One embodiment of the present invention relates to a memory device. One embodiment of the present invention relates to a semiconductor device including a memory device.

[0002] Note that one embodiment of the present invention is not limited to the aforementioned technical fields. Examples of the technical fields of one embodiment of the present invention disclosed in this specification and other related disclosures include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, and methods for driving or manufacturing the same. A semiconductor device refers to any device that can operate using semiconductor properties. Background Art

[0003] Non-volatile storage devices are incorporated into various mobile devices, such as smartphones, tablets, wristwatches, and wearable devices used for AR (Augmented Reality) and VR (Virtual Reality). Hard disk drives have been the primary non-volatile storage devices used until now, but flash memory is increasingly being used in these mobile devices due to its impact resistance, miniaturization, lightweight design, and the lack of physical work required.

[0004] Meanwhile, transistors containing an oxide semiconductor in their channel formation region (also known as oxide semiconductor transistors, OS (Oxide Semiconductor) transistors) are known. OS transistors have the characteristic of having an extremely low drain current (also known as off-state current) when the transistor is in the off state. Patent Document 1 discloses a NAND memory device using an OS transistor.

[0005] [Prior technical literature]

[0006] [Patent Document]

[0007] [Patent Document 1] International Patent Application Publication No. 2022 / 0068967 Summary of the Invention

[0008] Technical problem to be solved by the invention

[0009] Data stored in a nonvolatile memory device used for storage is often temporarily read out to a higher-level memory device such as DRAM and then sent to a processor. Therefore, the faster the data transfer speed between the nonvolatile memory device and DRAM, the better.

[0010] One object of one embodiment of the present invention is to provide a semiconductor device including different types of memory devices on the same chip. Another object of one embodiment of the present invention is to increase the data transmission speed between two memory devices. Another object of one embodiment of the present invention is to provide a semiconductor device including two types of memory devices and peripheral circuits on the same chip.

[0011] One object of one embodiment of the present invention is to provide a highly reliable memory device or semiconductor device. Another object of one embodiment of the present invention is to provide a memory device or semiconductor device having a novel structure. Another object of one embodiment of the present invention is to at least alleviate at least one of the problems of the prior art.

[0012] Note that the description of these objectives does not preclude the existence of other objectives. One embodiment of the present invention does not necessarily achieve all of the above objectives. Note that objectives other than the above can be extracted from the description of the specification, drawings, claims, etc.

[0013] Means of solving technical problems

[0014] One embodiment of the present invention is a semiconductor device including a first layer, a second layer, and a third layer. The first layer includes a first memory device having a plurality of nonvolatile first memory elements stacked in the thickness direction of the first layer. The second layer includes a second memory device having a plurality of second memory elements. The second memory elements include transistors including oxide semiconductors. The third layer includes a first driver circuit for controlling the operation of the first memory device and a second driver circuit for controlling the operation of the second memory device. The first layer and the second layer, the second layer and the third layer, and the first layer and the third layer each have overlapping portions.

[0015] In the above semiconductor device, the first layer is preferably located on the third layer. In this case, the second layer is preferably located on the third layer.

[0016] Furthermore, in the above semiconductor device, the third layer is preferably located between the first layer and the second layer.

[0017] In the semiconductor device, the first memory element preferably includes a first conductive layer, a first semiconductor layer, and a functional layer located therebetween. In this case, the functional layer preferably includes a thin film exhibiting ferroelectricity.

[0018] In the semiconductor device described above, the first memory element preferably includes a first conductive layer, a first semiconductor layer, and a functional layer disposed therebetween. In this case, the functional layer preferably includes at least one of hafnium and zirconium. Furthermore, the functional layer preferably further includes scandium, yttrium, and one or more lanthanide elements.

[0019] In the semiconductor device, the transistor preferably includes a gate insulating layer. In this case, the gate insulating layer preferably includes a thin film exhibiting ferroelectricity.

[0020] In the semiconductor device described above, the second layer preferably includes an insulating layer. Furthermore, the transistor preferably includes a source electrode, a drain electrode, and a second semiconductor layer. In this case, the source electrode and the drain electrode preferably each contact the second semiconductor layer. Furthermore, one of the source electrode and the drain electrode is preferably located above the insulating layer, and the other is preferably located below the insulating layer.

[0021] Effects of the Invention

[0022] According to one embodiment of the present invention, a semiconductor device can be provided that includes different types of memory devices on the same chip. Furthermore, the data transmission speed between the two memory devices can be increased. Furthermore, a semiconductor device can be provided that includes two types of memory devices and peripheral circuits on the same chip.

[0023] Furthermore, according to one embodiment of the present invention, a highly reliable memory device or semiconductor device can be provided. Furthermore, a memory device or semiconductor device having a novel structure can be provided. According to one embodiment of the present invention, at least one of the problems of the prior art can be alleviated.

[0024] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of the above effects. Note that effects other than the above can be extracted from the description of the specification, drawings, claims, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1A and Figure 1B This is an example of the structure of a semiconductor device.

[0026] Figures 2A to 2C This is an example of the structure of a semiconductor device.

[0027] Figures 3A to 3E This is an example of the structure of a storage device.

[0028] Figure 4 This is an example of the structure of a semiconductor device.

[0029] Figure 5 This is an example of the structure of a semiconductor device.

[0030] Figure 6 This is an example of the structure of a storage device.

[0031] 7A to 7C This is an example of the structure of a storage device.

[0032] Figure 8This is an example of the structure of a semiconductor device.

[0033] Figure 9A and Figure 9B This is an example of the structure of a storage device.

[0034] Figure 10 It is a diagram illustrating hysteresis characteristics.

[0035] Figure 11A and Figure 11B This is an example of the structure of a storage device.

[0036] Figure 12 This is an example of the structure of a semiconductor device.

[0037] Figure 13 This is an example of the structure of a semiconductor device.

[0038] Figure 14 This is an example of the structure of a semiconductor device.

[0039] Figure 15 This is an example of the structure of a semiconductor device.

[0040] Figure 16 This is an example of the structure of a semiconductor device.

[0041] Figure 17 This is an example of the structure of a semiconductor device.

[0042] Figure 18 This is an example of the structure of a semiconductor device.

[0043] Figure 19 This is an example of the structure of a semiconductor device.

[0044] Figure 20 This is a block diagram illustrating an example of the structure of a semiconductor device.

[0045] Figures 21A to 21H A diagram illustrating an example of a circuit configuration of a memory cell.

[0046] Figure 22A and Figure 22B It is a perspective view illustrating an example of the structure of a semiconductor device.

[0047] Figure 23 is a block diagram illustrating a CPU.

[0048] Figure 24A and Figure 24B It is a perspective view of a semiconductor device.

[0049] Figure 25A and Figure 25B It is a perspective view of a semiconductor device.

[0050] Figure 26A and Figure 26B is a diagram showing various storage devices in a hierarchical manner;

[0051] Figures 27A to 27J is a diagram illustrating an example of an electronic device.

[0052] Figures 28A to 28E is a diagram illustrating an example of an electronic device.

[0053] Figures 29A to 29C is a diagram illustrating an example of an electronic device.

[0054] Figure 30 is a schematic diagram of an example of space equipment. Modes for Carrying Out the Invention

[0055] The following describes the embodiments with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different ways, and those skilled in the art will readily appreciate that the methods and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited solely to the following embodiments.

[0056] Note that in the structures of the invention described below, the same reference numerals are used in common across different drawings to represent the same parts or parts having the same function, and their repeated descriptions are omitted. In addition, when parts having the same function are represented, the same hatching is sometimes used without the addition of a special reference numeral.

[0057] Note that in the drawings described in this specification, the size of each component, layer thickness, or region may be exaggerated to facilitate understanding. Therefore, the present invention is not limited to the dimensions shown in the drawings.

[0058] The ordinal numbers such as “first” and “second” used in this specification are added to avoid confusion between components and are not intended to limit the number.

[0059] (Implementation Method 1)

[0060] In this embodiment, a semiconductor device and a memory device which are one embodiment of the present invention are described.

[0061] One embodiment of the present invention is a semiconductor device including two memory devices (storage elements). The semiconductor device has a stacked structure comprising a first layer including memory cells (also called storage elements) of the first memory device, a second layer including memory cells of the second memory device, and a third layer including a first driver circuit for controlling the operation of the first memory device and a second driver circuit for controlling the operation of the second memory device. This structure shortens the wiring length between the first and second memory devices, thereby increasing the amount of data that can be transferred per unit time during data exchange between the first and second memory devices.

[0062] The first storage device preferably includes a nonvolatile memory element for storage. Furthermore, it preferably has a larger data capacity than the second storage device. For example, it is preferable to use a large-capacity storage device having a so-called three-dimensional structure, in which the memory elements are not only arranged in the in-plane direction of the first layer but also stacked in the thickness direction. More specifically, it is preferable to use a 3D-NAND type storage device that includes memory strings extending in the direction normal to the formed surface.

[0063] As the first memory device, a nonvolatile memory device using ferroelectrics is preferable, as this can realize a memory device with higher reliability and lower power consumption than a so-called charge trap type memory element.

[0064] The second storage device is preferably a storage device with a faster access speed than the first storage device. The second storage device may also be a volatile storage device in which the data is lost when power is turned off. More specifically, DRAM (Dynamic Random Access Memory) may be used.

[0065] In addition, as the second storage device, it is more preferable to use a storage device in which a transistor (OS transistor) using an oxide semiconductor for the channel formation region is used in the storage cell. Due to the extremely small leakage current in the off state of the OS transistor, the storage device using the OS transistor can retain data for a long period of time compared to DRAM, thereby reducing power consumption. Furthermore, the oxide semiconductor can be formed into a thin film, so the OS transistor can be manufactured on any formed surface. For example, there is the following advantage: a circuit composed of an OS transistor can be directly stacked on a semiconductor circuit composed of single crystal silicon.

[0066] Hereinafter, more specific examples will be described with reference to the drawings.

[0067] Figure 1A A semiconductor device 10 according to one embodiment of the present invention is shown. The semiconductor device 10 has a structure in which a layer 11, a layer 12, and a layer 13 are stacked in this order. The layer 12 is sandwiched between the layer 11 and the layer 13.

[0068] Figure 1BThis diagram shows each layer of semiconductor device 10 separately. Layer 13 includes a memory device 31 having multiple memory elements (memory cells) and a connection portion 32. Layer 12 includes a memory device 21 having multiple memory elements and a terminal portion 22. Layer 11 includes a driver circuit 43 that controls the operation of memory device 31 and a driver circuit 42 that controls the operation of memory device 21.

[0069] Tier 12 can use a storage device having a larger data capacity and including a nonvolatile storage element than Tier 13. On the other hand, Tier 13 can use a storage device having a faster access speed than Tier 12.

[0070] Driver circuit 43 is connected to driver circuit 42 via wiring 45, enabling data communication between them. For example, data can be transferred from storage device 31 to storage device 21 via driver circuit 43, wiring 45, and driver circuit 42. Conversely, data can also be transferred from storage device 21 to storage device 31.

[0071] Semiconductor device 10 is provided with a plurality of plugs 23 that connect a circuit provided in layer 11 (here, driver circuit 42) to terminal portion 22 of layer 12. Furthermore, semiconductor device 10 is provided with a plurality of plugs 33 that connect a circuit provided in layer 11 (here, driver circuit 43) to connection portion 32 of layer 13. A portion of plug 33 penetrates layer 12.

[0072] By adopting this structure, the footprint can be significantly reduced compared to arranging two storage devices and two driver circuits side by side. Furthermore, the wiring length between the storage devices and driver circuits can be shortened compared to arranging them side by side, thereby reducing the wiring load. Consequently, the data writing and reading speeds can be increased for each storage device.

[0073] In addition, Figure 1B The region overlapping with the terminal portion 22 in the layer 13 can also be used as part of the storage device 31. In other words, the storage device 31 can have a structure including a portion overlapping with the terminal portion 22 in the layer 12. By effectively utilizing space, the data capacity of the storage device 31 can be increased, which is preferable.

[0074] Figure 2A This is an example of a case where the positions of layer 12 and layer 13 are swapped, and layer 13 is located between layer 11 and layer 12. In this case, a portion of plug 23 penetrates layer 13.

[0075] In addition, if Figure 2B As shown, layer 11 can also be arranged between layer 12 and layer 13. Figure 2B In the figure, layer 11 is located on layer 12, and layer 13 is located on layer 11.

[0076] also, Figure 2C It's a swap Figure 2B An example of the positions of layers 12 and 13 is that layer 11 is located on layer 13, and layer 12 is located on layer 11.

[0077] exist Figure 2B and Figure 2C In the illustrated structure, it is also possible to employ a configuration in which plugs 23 and 33 do not penetrate other layers. This allows for a reduction in the physical length of plugs 23 and 33, thereby increasing operating speed. Furthermore, the area of ​​layer 12 overlapping plug 33 and the area of ​​layer 13 overlapping plug 23 can be used as storage device 21 and storage device 31, respectively, thereby increasing the data capacity of both storage devices.

[0078] Next, an example of a structure that can be used for the storage device 21 provided in the layer 12 will be described. Figure 3A It is a perspective schematic diagram of the storage device 21.

[0079] The memory device 21 is provided on an insulating layer 50 and includes a plurality of memory strings 60. The memory strings 60 include a plurality of cell transistors stacked in a direction perpendicular to the top surface of the insulating layer 50. The memory device 21 also includes a plurality of conductive layers 51, 52, 53, 54, and 55 serving as various wirings, and a plurality of plugs 56.

[0080] exist Figure 3A In FIG, arrows are used to indicate the mutually orthogonal X, Y, and Z directions. The memory strings 60 are arranged at equal intervals in the X and Y directions. Figure 3A , a block including 5×5 memory strings 60 is shown as an example. The storage device 21 includes a plurality of such blocks. Note that, in practice, the number of memory strings 60 included in one block is preferably greater.

[0081] A memory string 60 is arranged so that conductive layers 53 and 54 are connected. For example, conductive layer 53 functions as a source line, and conductive layer 54 functions as a bit line. Furthermore, multiple conductive layers 51 are stacked between conductive layers 53 and 54. Conductive layers 51 function as control gate lines. Furthermore, conductive layer 52, functioning as a select line, is disposed between the topmost conductive layer 51 and conductive layer 54. Furthermore, each of the multiple conductive layers 51 is connected to one of the multiple conductive layers 55 via a plug 56.

[0082] Conductive layers 54 and 52 extend in directions intersecting each other, forming a 5 x 5 matrix. Conductive layers 51 and 53 are connected to all memory strings 60 (here, 5 x 5) in their respective blocks.

[0083] Note that while FIG3(A) illustrates an example structure having five conductive layers 51, the number of layers is not limited thereto. The greater the number of stacked layers, the greater the number of cell transistors constituting a memory string 60, thereby increasing the data capacity of the memory device 21. The greater the number of cell transistors constituting a memory string 60, the better. For example, the number of cell transistors can be 64 or more, 128 or more, 160 or more, 192 or more, 224 or more, or 256 or more.

[0084] Figure 3B 1 selectively shows a memory string 60 and its surrounding structures. A memory cell 65 serving as a cell transistor is provided at a portion of the memory string 60 that intersects the conductive layer 51. The lowermost conductive layer 51 among the plurality of conductive layers 51 can also be used as a selection line.

[0085] Figure 3C yes Figure 3B Circuit diagram of the structure shown. Conductive layer 53 corresponds to wiring CL, conductive layer 54 corresponds to wiring BL, the bottom conductive layer 51 corresponds to wiring SSL, the conductive layers 51 other than these correspond to wiring WL (wiring WL1 to wiring WLm (m is an integer greater than or equal to 2)), and conductive layer 52 corresponds to wiring BSL.

[0086] like Figure 3C As shown, a transistor STr, a plurality of transistors CTr, and a transistor BTr are provided between the wiring BL and the wiring CL. The transistor STr and the transistor BTr are both used as selection transistors, and the transistor CTr is used as a cell transistor. The transistor CTr is used as a memory element.

[0087] Furthermore, the transistor CTr may use, for example, a charge trap flash memory or a floating gate flash memory. Furthermore, a memory element using ferroelectrics may be used, which has a structure in which a ferroelectric capacitor is connected to the gate, a structure in which a ferroelectric is used for the gate insulating layer, or a structure in which a ferroelectric capacitor is connected to one of the source and the drain.

[0088] Figure 3D and Figure 3E Shown in use Figure 3B and Figure 3C An example is shown in which a pair of memory strings in the U-shaped memory string form a single memory string 60. In this case, conductive layer 53 serves as a pipe gate line, and conductive layer 57 serves as a source line. Transistor PTr, located at the bottom of the U-shaped memory string, serves as a select transistor (also called a pipe transistor) connecting the pair of memory strings. The gate of transistor PTr is connected to wiring PL.

[0089] Next, an example of a configuration that can be used for the storage device 21 , the storage device 31 , the drive circuit 42 , and the drive circuit 43 will be described.

[0090] Figure 4 1 is a block diagram showing an example of the structure of the circuit OSC and the memory cell unit MCL. The circuit OSC is a circuit included in the drive circuit 42 and the drive circuit 43, and the memory cell unit MCL is a circuit including the memory cell included in the memory device 21. Figure 4 , the memory cell unit OMCL is shown. The memory cell unit OMCL is a circuit including the memory cells included in the memory device 31.

[0091] The memory cell unit MCL includes a memory cell array MCA. The memory cell array MCA includes multiple memory strings SRG. The memory strings SRG are electrically connected to a wiring BL. The memory strings SRG include multiple transistors CTr, a selection transistor BTr, and a transistor STr electrically connected in series. Note that one semiconductor CTr serves as a cell transistor and is included in each memory cell MC included in the string SRG.

[0092] The cell transistor is a transistor that operates with a normally-on characteristic and includes a control gate and a charge storage layer. The charge storage layer is provided in a region that overlaps with the channel formation region via a tunnel insulating film. The control gate is provided in a region that overlaps with the charge storage layer via a barrier film. In the cell transistor, a tunnel current is generated by applying a write potential to the control gate and supplying a predetermined potential to the first terminal or the second terminal of the cell transistor, thereby injecting electrons from the channel formation region of the cell transistor into the charge storage layer. As a result, in the cell transistor in which electrons are injected into the charge storage layer, the threshold voltage increases. Alternatively, a floating gate may be used instead of the charge storage layer.

[0093] Alternatively, a structure in which a ferroelectric capacitor is connected to the gate or a structure in which a ferroelectric is used as the gate insulating layer may be used as the unit transistor. By adopting such a structure, reliability can be further improved and power consumption can be reduced.

[0094] The channel formation regions of the transistors BTr, CTr, and STr preferably include, for example, silicon, germanium, gallium arsenide, silicon carbide (SiC), metal oxide, or a plurality of materials selected from these materials.

[0095] In particular, in the channel formation region, it is preferred to use an oxide of one or more metals selected from the group consisting of indium, element M (e.g., element M is one or more elements selected from aluminum, gallium, yttrium, and tin), and zinc. This metal oxide can function as a wide-bandgap semiconductor, allowing the transistors BTr, CTr, and STr containing this metal oxide in the channel formation region to have very low off-state current. In other words, since the leakage current of the transistors BTr, CTr, and STr in the off state can be reduced, the power consumption of the memory device can sometimes be reduced.

[0096] Note that although Figure 4 Although an example is shown in which the transistor BTr and the transistor STr are formed in the memory cell portion MCL, the transistor BTr and the transistor STr may be formed in the circuit OSC.

[0097] Furthermore, the memory cell array MCA includes a plurality of memory cells MC within the string SRG. The plurality of memory cells MC are arranged in rows and columns (also referred to as a matrix). Note that the memory cell array MCA includes m memory cells in one column and n memory cells in one row, i.e., a total of m×n memory cells MC (m and n are integers greater than or equal to 2). The memory cell MC located in the i-th row and j-th column (i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to 1 and less than or equal to n) is denoted as MC[i, j].

[0098] Wirings WL are multiple word lines, each electrically connected to a memory cell MC in a row. Wirings BL are multiple bit lines, each electrically connected to a memory cell MC in a column. Wirings CL are power supply lines.

[0099] Next, the connection structure of the string SRG will be described: The transistor BTr, a plurality of transistors CTr, and the transistor STr are connected in series, the transistor BTr is electrically connected to the wiring BL, and the transistor STr is electrically connected to the wiring BL.

[0100] The wiring BSL and the wiring SSL are used as wiring for selecting a string when performing operations such as writing, reading, and erasing. The wiring BSL is electrically connected to the gate of the transistor BTr, and the wiring SSL is electrically connected to the gate of the transistor STr.

[0101] Note that although a structure is adopted in which one string SRG is electrically connected to one wiring BL, one embodiment of the present invention is not limited to this. Figure 5 As shown, the memory cell unit MCL may also adopt a structure in which a plurality of strings SRG are electrically connected to one wiring BL. Note that Figure 5 The block diagram shows a memory cell portion MCL and a portion of the circuit OSC.

[0102] Circuit OSC includes a control circuit CTR, a circuit PRPH, a circuit ORPH, and an output circuit OUTP. Control circuit CTR receives control signals CS (clock signal, chip enable signal, write enable signal, address signal, etc.) and data signal WDATA from outside semiconductor device 10, for example.

[0103] Circuit PRPH corresponds to the drive circuit 42, and circuit ORPH corresponds to the drive circuit 43. Although an example is shown here in which circuits PRPH and ORPH share the control circuit CTR and the output circuit OUTP, each circuit may have one or both of the control circuit CTR and the output circuit OUTP.

[0104] The control circuit CTR has the function of accessing the circuit PRPH to write data to the memory cell unit MCL and read data from the memory cell unit MCL. The control circuit CTR also has the function of accessing the circuit ORPH to write data to the memory cell unit OMCL and read data from the memory cell unit OMCL.

[0105] For example, when a write command based on control signal CS and data signal WDATA are input from outside semiconductor device 10, control circuit CTR first writes data signal WDATA into memory cell section OMCL. It then reads the data written from memory cell section OMCL and writes the read data into memory cell section MCL. In other words, memory cell section OMCL can be said to function as a cache memory for memory cell section MCL. Note that, for example, if the amount of data signal WDATA is small, control circuit CTR can write data directly into memory cell section MCL without passing through memory cell section OMCL.

[0106] When a read command based on control signal CS is input from outside semiconductor device 10, control circuit CTR reads data from memory cell unit MCL (if the data exists in memory cell unit OMCL, it can also be read from memory cell unit OMCL) and outputs it to output circuit OUTP. Output circuit OUTP outputs data signal RDATA to the outside of semiconductor device 10. Note that write and read commands include address signals.

[0107] Furthermore, the control circuit CTR may also have a function for detecting and correcting errors (also known as ECC) when reading data from the memory cell unit MCL. The memory cell unit OMCL may also function as a cache memory for the control circuit CTR to perform error detection and correction. Note that the signals processed by the control circuit CTR and its functions are not limited to these. Other signals may be input (or output) as needed, and the control circuit CTR may also have other functions.

[0108] That is, the control circuit CTR can write a data signal WDATA input from outside the semiconductor device 10 into the memory cell section OMCL, read the written data from the memory cell section OMCL, and rewrite the read data into the memory cell section MCL. Since the data signal WDATA input from outside the semiconductor device 10 travels through the plug in the semiconductor device 10, the data travel distance is short.

[0109] Semiconductor device 10 includes a memory cell section OMCL. The short data transfer distance between memory cell section OMCL and memory cell section MCL reduces signal transmission delay, enables high-speed operation, and suppresses power consumption increases due to parasitic capacitance. Memory cell section OMCL can be used as a cache memory in semiconductor device 10. Specifically, it can be used as a storage device for temporarily storing data transmitted from semiconductor device 10 to or received from a processor, for example.

[0110] Circuit PRPH includes, for example, circuit WLD, circuit BLD, and circuit CVC. Circuit WLD functions as a word line driver circuit and is electrically connected to wiring WL. Circuit BLD functions as a bit line driver circuit and is electrically connected to wiring BL. Circuit CVC functions as a power supply for generating and outputting a constant potential and is electrically connected to wiring CL. Note that circuit PRPH may not include circuit CVC; for example, circuit CVC may be provided externally to semiconductor device 10. In this case, semiconductor device 10 has a structure in which a constant potential is supplied externally to memory cell portion MCL.

[0111] Circuit ORPH includes, for example, circuit OWLD and circuit OBLD. Circuit OWLD functions as a word line driver circuit and is electrically connected to wirings wwl and rwl. Circuit OBLD functions as a bit line driver circuit and is electrically connected to wirings wbl and rbl.

[0112] Next, a configuration example of the memory cell unit OMCL will be described. Figure 6 is a block diagram showing a structural example of the memory cell unit OMCL.

[0113] Note that the memory cell section OMCL includes s in one column and t in one row, that is, a total of s×t memory cells OMC (s and t are integers greater than 2). The memory cells OMC are arranged in a matrix. Figure 4 , a memory cell OMC located in row p and column r (p is an integer greater than or equal to 1 and less than or equal to s, and r is an integer greater than or equal to 1 and less than or equal to t) is represented as OMC[p, r]. Similarly to the memory cell unit MCL, the memory cell unit OMCL may also have a structure in which memory cells are arranged three-dimensionally.

[0114] The wiring wwl and the wiring rwl are electrically connected to a plurality of memory cells OMC arranged in the row direction, and the wiring wbl and the wiring rbl are electrically connected to a plurality of memory cells OMC arranged in the column direction.

[0115] Figure 7A 2 is a circuit diagram showing a configuration example of a memory cell OMC. The memory cell OMC includes a transistor M11, a transistor M12, and a capacitor C11.

[0116] In transistor M11, one of its source and drain is electrically connected to the gate of transistor M12 and one terminal of capacitor C11, while the other is electrically connected to wiring wb1. The gate is electrically connected to wiring wwl. In transistor M12, one of its source and drain is electrically connected to wiring rb1, while the other is electrically connected to wiring rwl. The other terminal of capacitor C11 is electrically connected to wiring CAL. A predetermined potential is applied to wiring CAL. The connection portion with transistor M12 is referred to as node N11.

[0117] Note that in this specification, etc., words such as "terminals" are used to describe the input and output of signals, potentials, etc. between constituent elements. In reality, circuits sometimes do not have physical connection parts such as "terminals" but are only electrically connected using wiring or electrodes.

[0118] In memory cell OMC, wiring wbl serves as a write bit line, wiring rbl serves as a read bit line, wiring wwl serves as a write word line, and wiring rwl serves as a read word line. Transistor M11 serves as a switch for connecting node N11 to wiring wbl or disconnecting it.

[0119] Data is written by applying a high-level potential to wiring wwl, turning on transistor M11 and electrically connecting node N11 to wiring wbl. Specifically, when transistor M11 is in the on state, a potential corresponding to the data to be written is applied to wiring wbl, writing that potential to node N11. Then, a low-level potential is applied to wiring wwl, turning off transistor M11 and maintaining the potential of node N11.

[0120] Data is read by applying a predetermined potential to wiring rbl, which is then electrically floating. A low-level potential is then applied to wiring rwl. Hereinafter, applying a predetermined potential to a wiring and then floating it is referred to as precharging.

[0121] For example, by precharging the wiring rbl with the potential Vdd, a potential difference is applied between the source and drain of the transistor M12. Since the current flowing between the source and drain of the transistor M12 is determined by the potential held at the node N11, the potential held at the node N11 can be read by reading the potential change of the wiring rbl when the wiring rbl is in a floating state.

[0122] By applying a high-level potential to the wiring wwl, a row in which memory cells OMC to be written are arranged is selected, and by applying a low-level potential to the wiring rwl, a row in which memory cells OMC to be read are arranged is selected. Conversely, by applying a low-level potential to the wiring wwl, a row in which memory cells OMC to which data are not written are arranged can be deselected, and by applying a potential equal to the potential precharged to the wiring rbl to the wiring rwl, a row in which memory cells OMC to which data are not read are arranged can be deselected.

[0123] Transistor M11 and transistor M12 can use OS transistors. The off-state current of OS transistors is very small, so by using OS transistors as transistor M11, the potential written to node N11 can be maintained for a long time. In other words, the data written to memory cell OMC can be maintained for a long time. Alternatively, by using OS transistors as transistor M11, memory cell OMC can also reduce the capacitance of capacitor C11. Alternatively, by using OS transistors as transistor M11, as shown in FIG. Figure 7B As shown, the memory cell OMC may not include the capacitor C11. When the memory cell OMC does not include the capacitor C11, the potential written to the node N11 is held by the gate capacitance of the transistor M12 or the like.

[0124] Transistor M11 and transistor M12 may also have back gates (also referred to as second gates or bottom gates). For example, by applying a predetermined potential to the back gate of transistor M11, the threshold voltage of transistor M11 can be increased or decreased. Alternatively, by electrically connecting the back gate of transistor M11 to the gate of transistor M12 (also referred to as first gate, top gate, or front gate), the on-state current of transistor M11 can be increased.

[0125] Specifically, by shifting the threshold voltage to a negative value, the on-state current of the transistor can be increased, and the memory cell OMC can operate at high speed. On the other hand, by shifting the threshold voltage of transistor M11 to a positive value, the off-state current of the transistor can be reduced, and the memory cell OMC can retain data for a long time. Alternatively, different potentials can be applied to the back gates of transistors M11 and M12. For example, the potential applied to the back gate of transistor M11 can be lowered, while the potential applied to the back gate of transistor M12 can be increased.

[0126] In addition, transistors other than OS transistors may be used as transistors M11 and transistor M12. Transistor M11 preferably uses a transistor with a low off-state current. For example, a transistor containing a semiconductor with a large bandgap in the channel formation region may be used. A semiconductor with a large bandgap sometimes refers to a semiconductor with a bandgap of 2.2 eV or greater. Examples of materials other than oxide semiconductors include silicon carbide, gallium nitride, and diamond. On the other hand, transistor M12 preferably uses a transistor with a high on-state current. Semiconductor materials such as silicon and germanium may also be used.

[0127] This memory cell OMC is a gain-cell type memory cell consisting of two transistors and one capacitor, or two transistors and zero capacitor. Even with a small charge storage capacity, the gain-cell type memory cell can amplify the stored charge using the nearest transistors, operating as a memory. The gain-cell type memory cell can read data without destroying the stored data (non-destructive readout).

[0128] Alternatively, the memory cell OMC may be formed of a transistor and a capacitor. Figure 7C The memory cell OMC shown includes a transistor M13 and a capacitor C12.

[0129] In transistor M13, one of its source and drain is electrically connected to one terminal of capacitor C12, the other is electrically connected to wiring abl, and its gate is electrically connected to wiring awl. The other terminal of capacitor C12 is electrically connected to wiring CAL. The connection portion connected to one of the source and drain of transistor M13 is referred to as node N12.

[0130] The transistor M13 can use the same OS transistor as the transistor M11 and the transistor M12. Figure 7C In the memory cell OMC shown, the wiring abl is used as a bit line, and the wiring awl is used as a word line.

[0131] The storage unit OMC adopts Figure 7C The structure shown in FIG. 1 can improve the arrangement density of the memory cell OMC, but destructive reading is performed when reading data. In addition, even if the memory cell OMC included in the memory cell unit OMCL is Figure 7A 、 Figure 7B and Figure 7C The memory cell section OMCL can also perform random access to any of the memory cells OMC shown.

[0132] Next, the circuit BLD and the circuit OBLD included in the circuit OSC will be described in more detail. Figure 8 2 is a block diagram showing a configuration example of a part of the circuit OSC. Figure 8 from Figure 4 The output circuit OUTP, the circuit CVC, and the like are omitted from the illustrated circuit OSC, and a configuration example of the circuit BLD, a configuration example of the circuit OBLD, and the flow of signals in the circuit OSC are more specifically illustrated.

[0133] The circuit BLD may have a structure including, for example, a column decoder CD, a write circuit WC, a sense amplifier SA, and an output circuit OPC.

[0134] Column decoder CD has the function of selecting wiring BL electrically connected to memory cell MC to be written or read based on address signal AD received from control circuit CTR. Address signal AD is an internal signal of circuit OSC corresponding to the address signal in control signal CS. Address signal AD is also transmitted to circuit WLD. Circuit WLD has the function of driving wiring BSL, wiring WL, and wiring SSL, and has the function of selecting wiring WL electrically connected to memory cell MC to be written or read based on address signal AD.

[0135] Write circuit WC has the function of supplying a potential corresponding to data signal WD supplied from control circuit CTR to wiring BL selected by column decoder CD. Data signal WD is an internal signal of circuit OSC and corresponds to data signal ORD or data signal WDATA.

[0136] Sense amplifier SA amplifies the data signal read from wiring BL. Note that the amplified data signal is output as data signal RD to control circuit CTR via output circuit OPC. Control circuit CTR outputs a signal corresponding to data signal RD to circuit OUTP.

[0137] The circuit OBLD may have a structure including, for example, a column decoder OCD, a write circuit OWC, a precharge circuit OPR, a sense amplifier OSA, and an output circuit OOPC.

[0138] The column decoder OCD has the function of selecting the wiring wbl and wiring rbl electrically connected to the memory cell OMC to be written or read based on the address signal OAD received from the control circuit CTR. Here, the address signal OAD is an internal signal of the circuit OSC. The address signal OAD is also transmitted to the circuit OWLD. The circuit OWLD has the function of driving the wiring wwl and wiring rwl and, based on the address signal OAD, selects the wiring wwl and wiring rwl electrically connected to the memory cell OMC to be written or read.

[0139] The write circuit OWC has a function of supplying a potential corresponding to the data signal OWD supplied from the control circuit CTR to the wiring wbl selected by the column decoder OCD. Here, the data signal OWD is an internal signal of the circuit OSC and corresponds to the data signal WDATA.

[0140] Furthermore, the precharge circuit OPR precharges the wiring rbl, and the sense amplifier OSA amplifies the data signal read from the wiring rbl. Note that the amplified data signal is output as the data signal ORD via the output circuit OOPC to the control circuit CTR. The control circuit CTR outputs a signal corresponding to the data signal ORD to the write circuit WC or the output circuit OUTP.

[0141] Note that the components of circuit BLD and circuit OBLD are not limited to these components. Other components may be added as needed, or unnecessary components may be reduced. Furthermore, the functions of circuit BLD and circuit OBLD are not limited to these components. Other functions may be provided, or unnecessary functions may be reduced.

[0142] The above is a description of a semiconductor device 10 according to one embodiment of the present invention. According to one embodiment of the present invention, by including different types of memory devices on the same chip, a highly versatile semiconductor device can be provided. Furthermore, the data transmission speed between the two memory devices can be improved. Furthermore, by including two types of memory devices and peripheral circuits on the same chip, a semiconductor device with a small footprint can be realized.

[0143] At least a part of the structural examples described in this embodiment mode and the drawings corresponding to the structural examples can be combined with other structural examples, drawings, etc. as appropriate.

[0144] (Implementation Method 2)

[0145] In this embodiment, a configuration example of a memory string according to one embodiment of the present invention and a semiconductor device using the memory string will be described.

[0146] [Memory string]

[0147] The memory string 100 according to one embodiment of the present invention can be used in a 3D-NAND memory device. Note that in the drawings shown below, arrows may be used to indicate the orthogonal X, Y, and Z directions.

[0148] Figure 9A This is a cross-sectional view of the memory string 100 as viewed from the Y direction. Note that Figure 9A The central axis 120 of the memory string 100 extending in the Z direction is described in FIG. Figure 9B This is an equivalent circuit of the memory string 100. The memory string 100 has a structure in which a plurality of transistors Tr are connected in series. Each transistor is connected to a wiring CG.

[0149] The transistors Tr that make up the memory string 100 are ferroelectric transistors (FeFETs). Ferroelectric transistors use ferroelectrics as the gate insulator. Ferroelectric transistors can change their threshold voltage by applying a voltage above a certain level to the gate. Using these transistors Tr, a NAND-type ferroelectric memory can be realized.

[0150] The memory string 100 includes a conductive layer 101 disposed above a substrate (not shown), m layers (m is an integer greater than or equal to 2) of insulating layers 102, and n layers (n is an integer greater than or equal to 2) of conductive layers 103. The insulating layers 102 and the conductive layers 103 are alternately stacked above the substrate. Figure 9A In the present embodiment, the first insulating layer 102 is referred to as insulating layer 102_1, and the m-th insulating layer 102 is referred to as insulating layer 102_m. Similarly, the first conductive layer 103 is referred to as conductive layer 103_1, and the n-th conductive layer 103 is referred to as conductive layer 103_n. In this embodiment, any insulating layer 102 is simply referred to as "insulating layer 102." Similarly, any conductive layer 103 is simply referred to as "conductive layer 103."

[0151] Memory string 100 includes conductive layer 104, insulating layer 105, structure 110, and insulating layer 121. Structure 110 extends along the Z direction. Structure 110 penetrates insulating layers 102_1 to 102_m and conductive layers 103_1 to 103_n and is disposed between conductive layer 101 and conductive layer 104.

[0152] Structural body 110 has a columnar structure including a semiconductor layer 112 and a functional layer 118. Specifically, functional layer 118 is provided so that semiconductor layer 112 extends along a central axis 120 and surrounds the semiconductor layer 112. Semiconductor layer 112 has a cylindrical shape along central axis 120, and functional layer 118 is provided concentrically outside semiconductor layer 112.

[0153] Note that the cross-sectional shape of the structure 110 is not limited to a circle, and may be a triangle, a rectangle, or a polygon larger than a pentagon. Furthermore, the cross-sectional profile of the structure 110 perpendicular to the Z direction may consist solely of curves or a combination of straight lines and curves.

[0154] Insulating layer 121 is provided to cover the side surfaces of insulating layers 102_1 to 102_m and conductive layers 103_1 to 103_n. Conductive layer 104 is provided on insulating layer 102_m. Conductive layer 101 and conductive layer 104 are electrically connected to semiconductor layer 112. Insulating layer 105 is provided on insulating layer 102_m, insulating layer 121, and conductive layer 104.

[0155] An intersection of the structure 110 and the conductive layer 103 serves as a transistor Tr. The transistor Tr serves as a memory cell (also referred to as a memory element).

[0156] The conductive layer 103 is used as a gate of the transistor Tr. The memory string 100 includes n intersections of the structure 110 and the conductive layer 103. Therefore, the memory string 100 includes n transistors Tr, that is, n memory cells.

[0157] exist Figure 9A 、 Figure 9B In the embodiment, the first transistor Tr is represented as transistor Tr_1, and the n-th transistor Tr is represented as transistor Tr_n. In this embodiment and other embodiments, any transistor Tr is simply represented as "transistor Tr." Similarly, the wiring CG connected to the n-th transistor Tr_n is represented as wiring CG_n.

[0158] In many cases, polycrystalline silicon is used for the main body of a 3D-NAND memory string. In memory string 100 according to one embodiment of the present invention, semiconductor layer 112 corresponds to the main body. Semiconductor layer 112 can use single crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, amorphous semiconductors, etc., alone or in combination. As semiconductor materials, for example, silicon, germanium, etc. can be used. In addition, compound semiconductors such as silicon germanium, silicon carbide (SiC), gallium arsenide, oxide semiconductors, and nitride semiconductors can also be used.

[0159] Alternatively, the semiconductor layer 112 may be a semiconductor whose crystallinity is enhanced by using a catalyst element. The catalyst element may be an element selected from metal elements such as nickel (Ni), iron (Fe), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), copper (Cu), gold (Au), and germanium (Ge).

[0160] For example, the crystallinity can be improved by forming amorphous silicon as the semiconductor layer 112 and adding nickel as a catalyst element and performing a heat treatment. The catalyst element bonds to silicon to form a silicide. In addition, the catalyst element is easily bonded to a portion with many defects, such as an amorphous state. As a result, the catalyst element contained in the silicide reacts with the amorphous silicon to form a new silicide. In this way, crystallization progresses while the silicide moves. In addition, by allowing the catalyst element to reach a semiconductor containing impurity elements such as Group 15 elements and Group 13 elements, the redispersion of the catalyst element can be suppressed.

[0161] Furthermore, when nickel is added as a catalyst element to the semiconductor layer 112, a concentration gradient of the nickel element may occur within the semiconductor layer 112. For example, the nickel concentration in a region of the transistor that functions as a channel may be lower than the nickel concentration in other regions (e.g., the source and drain regions). In other words, the nickel concentration in the source and drain regions may be higher than the nickel concentration in the region that functions as a channel.

[0162] The semiconductor layer 112 is used as a semiconductor layer forming a channel of the transistor Tr. The semiconductor layer used for the transistor may be a stacked semiconductor. When the semiconductor layer has a stacked structure, semiconductor materials having different crystalline states or different semiconductor materials may be used.

[0163] In particular, the transistor Tr is preferably a transistor using an oxide semiconductor such as one of metal oxides in the semiconductor layer 112 in which the channel is formed. Oxide semiconductors have a band gap of 2 eV or greater, resulting in extremely low off-state current. This reduces the power consumption of the memory string 100. Consequently, the power consumption of the semiconductor device including the memory string 100 can be reduced.

[0164] In addition, a memory cell including an OS transistor may be referred to as an “OS memory.” In addition, a memory string 100 including the memory cell may also be referred to as an “OS memory.”

[0165] Furthermore, compared to transistors using polysilicon for the semiconductor layer in which the channel is formed, OS transistors can further reduce on-state resistance. In other words, the conductivity of the main body can be improved. By using OS transistors as transistors Tr, the operating speed of the memory string 100 can be increased. Furthermore, while transistors using polysilicon experience threshold voltage variations due to grain boundaries, OS transistors are less affected by grain boundaries and have smaller threshold voltage variations. Therefore, by using OS transistors as transistors Tr, the memory string 100 can suppress malfunctions caused by threshold voltage variations.

[0166] In addition, the OS transistor operates stably in a high-temperature environment and has little characteristic variation. For example, even in a high-temperature environment, the off-state current hardly increases. Specifically, even at an ambient temperature above room temperature and below 200°C, the off-state current hardly increases. In addition, even in a high-temperature environment, the on-state current is not easily reduced. Therefore, the memory string 100 including the OS memory operates stably even in a high-temperature environment and has high reliability. In addition, the insulation withstand voltage between the source and the drain of the OS transistor is very high. By using the OS transistor as a transistor constituting the memory string 100, a memory string 100 that operates stably and has high reliability even in a high-temperature environment can be realized. As a result, the reliability of the semiconductor device including the memory string 100 can be improved.

[0167] A NAND-type storage device that includes OS memory is also referred to as an "OS NAND-type" or "OS NAND-type storage device." Furthermore, a 3D-NAND-type storage device that includes OS memory is also referred to as a "3D OS NAND-type" or "3D OS NAND-type storage device." Therefore, the memory string 100 according to one embodiment of the present invention can be considered a 3D OS NAND-type storage device.

[0168] A dielectric material can be used as the functional layer 118 .

[0169] When an electric field is applied to a dielectric, positively charged and negatively charged regions are generated within the dielectric. This phenomenon is called polarization. Dielectrics whose polarization disappears in the absence of an electric field are called paraelectrics, while those whose polarization remains in the absence of an electric field are called ferroelectrics. Furthermore, the property of remaining polarization in the absence of an electric field is called ferroelectricity.

[0170] The functional layer 118 uses a material that exhibits ferroelectricity. Examples of materials that exhibit ferroelectricity include oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. In addition, it is preferred to use materials in which elements of Group 3 (Group IIIa) are added to these oxides. For example, it is preferred to include scandium, yttrium, and one or more elements belonging to the lanthanide series. In particular, yttrium, lanthanum, or scandium is relatively easy to handle and has a high affinity with semiconductor manufacturing processes, so it is preferred. By adding such elements, not only can ferroelectricity be stably exhibited, but also the degradation of characteristics during repeated rewriting can be suppressed to improve reliability. In addition, silicon, aluminum, gadolinium, scandium, etc. are added.

[0171] Oxides containing one or both of hafnium and zirconium easily exhibit ferroelectricity even in extremely thin films produced by thin film deposition methods such as sputtering and ALD, and therefore have high affinity with semiconductor manufacturing processes, thereby reducing manufacturing costs.

[0172] Alternatively, the functional layer 118 may include piezoelectric ceramics having a perovskite structure, such as barium titanate, lead titanate, strontium titanate, barium strontium titanate (BST), lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), or bismuth ferrite (BFO).

[0173] Alternatively, an organic ferroelectric such as polyvinylidene fluoride (PVDF) or a copolymer of vinylidene fluoride (VDF) and trifluoroethylene (TrFE) may be used as the functional layer 118 .

[0174] Furthermore, as a material exhibiting ferroelectricity, for example, a mixture or compound formed of a plurality of materials selected from the above materials can be used. Furthermore, the functional layer 118 can have a stacked-layer structure formed of a plurality of materials selected from the above materials.

[0175] In particular, hafnium oxide or a material containing hafnium oxide and zirconium oxide (HZO) is preferred as a material exhibiting ferroelectricity because it exhibits ferroelectricity even when processed into a thin film of several nanometers. By using hafnium oxide or hafnium zirconium oxide, the thickness of the functional layer 118 can be reduced to 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less.

[0176] In addition, when hafnium zirconium oxide (HfZrO) is used as a material exhibiting ferroelectricity X (x is a real number greater than 0), it is preferred to use atomic layer deposition (ALD), and particularly thermal ALD. Furthermore, it is preferred to use plasma-enhanced ALD (including thermal ALD) (PEALD: Plasma Enhanced ALD).

[0177] In addition, when using the thermal ALD method, it is preferred to use a material that does not contain hydrocarbons (Hydro Carbon, also referred to as HC) as a precursor. Either or both of the hydrogen and carbon contained in the film sometimes hinder crystallization. Therefore, it is preferred to reduce the concentration of either or both of the hydrogen and carbon in the film by using a precursor that does not contain hydrocarbons. For example, chlorine-based materials can be cited as precursors that do not contain hydrocarbons. Note that when using hafnium zirconium oxide, a chlorine-based precursor such as HfCl4 or ZrCl4 can be used as a precursor.

[0178] When hafnium zirconium oxide is used for the functional layer 118 , hafnium oxide and zirconium oxide are preferably alternately deposited to have a composition ratio of 1:1 by a thermal ALD method or an ALD method using plasma.

[0179] In addition, as the oxidant used in the thermal ALD method or the ALD method using plasma, H2O or O3 can be used. However, the oxidant is not limited thereto and may include any one or more selected from O2, O3, N2O, NO2, H2O, and H2O2.

[0180] The impurity concentration in the film used for the functional layer 118 is preferably low. In particular, the lower the concentration of hydrogen (H) and carbon (C), the better. Specifically, the hydrogen concentration in the film is preferably 5×10 20 atoms / cm 3 Below, more preferably 1×10 20 atoms / cm 3 In addition, the carbon concentration in the film is preferably 5×10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 the following.

[0181] The crystalline structure of the film used for the functional layer 118 is not particularly limited as long as it is a polar and centrosymmetric crystalline structure. For example, a crystalline system other than the cubic system may be used. Furthermore, the film used for the functional layer 118 may have a single crystal structure, a polycrystalline structure, or a composite structure including an amorphous structure and a crystalline structure.

[0182] The layer exhibiting ferroelectricity used in the functional layer 118 is also referred to as a “ferroelectric layer.” The ferroelectric layer has hysteresis characteristics. Figure 10 is a graph showing an example of hysteresis characteristics. Figure 10 In FIG, the horizontal axis represents the voltage (electric field) applied to the ferroelectric layer, and the vertical axis represents the polarization of the ferroelectric layer. Note that the electric field strength can be calculated by dividing the voltage by the thickness of the ferroelectric layer.

[0183] The hysteresis characteristics of the ferroelectric layer can be represented by a curve 71 and a curve 72. The voltage at the intersection of the curve 71 and the curve 72 is referred to as the saturation polarization voltage VSP and the saturation polarization voltage -VSP.

[0184] When a voltage below -VSP is applied to the ferroelectric layer and then the voltage applied to the ferroelectric layer is gradually increased, the polarization of the ferroelectric layer increases according to curve 71. On the other hand, when a voltage above VSP is applied to the ferroelectric layer and then the voltage applied to the ferroelectric layer is gradually decreased, the polarization of the ferroelectric layer decreases according to curve 72. Note that VSP is sometimes referred to as a "positive saturation polarization voltage" or a "first saturation polarization voltage," and -VSP is sometimes referred to as a "negative saturation polarization voltage" or a "second saturation polarization voltage." The absolute value of the first saturation polarization voltage and the absolute value of the second saturation polarization voltage may be the same or different.

[0185] Here, the voltage at which the polarization of the ferroelectric layer is zero when the polarization changes according to the curve 71 is referred to as the coercive voltage Vc. In addition, the voltage at which the polarization of the ferroelectric layer is zero when the polarization changes according to the curve 72 is referred to as the coercive voltage -Vc. The value of Vc and the value of -Vc are values ​​between -VSP and VSP. Note that Vc is sometimes referred to as a "positive coercive voltage" or a "first coercive voltage" and -Vc is sometimes referred to as a "negative coercive voltage" or a "second coercive voltage." The absolute value of the first coercive voltage and the absolute value of the second coercive voltage may be the same or different.

[0186] Furthermore, when a voltage exceeding the coercive voltage is applied to the ferroelectric layer, the polarization of the ferroelectric layer is easily reversed. In the case where the polarization reversal of the ferroelectric layer serving as the gate insulating layer is not desired in the FeFET, the voltage applied between the gate and the source (also referred to as "gate voltage" or "Vg") can be set to be greater than -Vc and less than Vc. In order to control the on and off states of the FeFET without reversing the polarization of the ferroelectric layer serving as the gate insulating layer, the absolute value of the coercive voltage is preferably large.

[0187] The maximum polarization value when no voltage is applied to the ferroelectric layer (at 0V) is called "remanent polarization Pr," and the minimum value is called "remanent polarization -Pr." Furthermore, the absolute value of the difference between remanent polarization Pr and remanent polarization -Pr is called "remanent polarization 2Pr." The larger the remanent polarization 2Pr, the greater the fluctuation range of the threshold voltage due to polarization reversal. Therefore, a larger remanent polarization 2Pr is preferred.

[0188] A charge accumulation layer may be used instead of a ferroelectric layer as the functional layer 118. For example, a stacked structure of a blocking layer, a charge accumulation layer, and a tunneling layer may be used as the functional layer 118 to realize a transistor used as a memory cell for storing data by retaining charge in the charge accumulation layer.

[0189] This type of memory cell is sometimes referred to by various names depending on the stacked structure from the control gate to the semiconductor. For example, if the control gate, barrier layer, charge accumulation layer, tunneling layer, and semiconductor layer are composed of metal, oxide, nitride, oxide, or semiconductor, the memory cell is called a MONOS (Metal Oxide Nitride Oxide Semiconductor) type memory cell.

[0190] In addition, the memory cell can be a SONOS (Silicon Oxide Nitride Oxide Semiconductor) type memory cell using n-type silicon or p-type silicon for the control gate, a TANOS (Tantalum nitride Aluminum oxide Nitride Oxide Semiconductor) type memory cell using tantalum nitride for the control gate and aluminum oxide for the barrier layer, or a THNOS (Tantalum nitride Hafnium oxide Nitride Oxide Semiconductor) type memory cell using tantalum nitride for the control gate and hafnium oxide for the barrier layer.

[0191] For example, the functional layer 118 may have a stacked-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film from the semiconductor layer 112 side. In this case, the silicon nitride film serves as a charge storage layer.

[0192] Figure 11A 、 Figure 11B Memory string 100A includes a back gate. Memory string 100A differs from memory string 100 described above primarily in that it includes a conductive layer 106 and an insulating layer 111. A structure 110A includes conductive layer 106, insulating layer 111, semiconductor layer 112, and functional layer 118.

[0193] The memory string 100A includes a conductive layer 106 located at a central axis, and an insulating layer 111 , a semiconductor layer 112 , and a functional layer 118 are sequentially arranged in a concentric circle shape so as to surround the conductive layer 106 .

[0194] The conductive layer 106 serves as a back gate of the transistor Tr. The insulating layer 111 serves as a back gate insulator of the transistor Tr.

[0195] exist Figure 11B In the example, the back gates of the transistors Tr (transistors Tr_1 to Tr_n) are electrically connected to the wiring SL via the wiring BGL. Note that the conductive layer 106 can also function as the wiring BGL. That is, the back gate of each transistor Tr is supplied with the potential of the wiring SL. Therefore, compared to a case where no back gate is provided, the threshold voltage of each transistor Tr is more stable, enabling more reliable writing and erasing operations.

[0196] [Semiconductor devices]

[0197] Next, a more specific structural example of the semiconductor device including the two types of memory devices shown in Embodiment 1 will be described.

[0198] Figure 12An example of the cross-sectional structure of layer 11 and layer 12 is shown. Figure 14 An example of the cross-sectional structure of the layer 12 and the layer 13 is shown.

[0199] use Figure 12 and Figure 14 The following case is described: a circuit using a single crystal silicon substrate is applied as layer 11, a storage device including a three-dimensional NAND memory is applied as layer 12, and a storage device including an OS transistor is applied as layer 13.

[0200] exist Figure 12 In FIG. 1 , the layer 11 is provided with transistors 300 , and the layer 12 is provided with a plurality of memory strings.

[0201] Each memory string provided in layer 12 includes a transistor 141, a plurality of transistors 142, and a transistor 143. Note that in describing the structure of layer 12, detailed descriptions of portions that can refer to memory string 100 shown in FIG. 9 will be omitted, and only differences will be described.

[0202] <Layer 11>

[0203] The transistor 300 in layer 11 is provided on a substrate 311 and includes a conductive layer 316 , an insulating layer 315 , a semiconductor region 313 formed of a portion of the substrate 311 , a low resistance region 314 a functioning as a source region or a drain region, and a low resistance region 314 b . Figure 12 A cross section of the transistor 300 along the channel length direction is shown.

[0204] The transistor 300 is preferably a so-called Fin-type transistor, in which the conductive layer 316 covers the top surface and side surfaces of the semiconductor region 313 in the channel width direction via the insulating layer 315 in a cross-section along the channel width. This increases the effective channel width, thereby improving the on-state characteristics of the transistor 300. Furthermore, since the influence of the electric field of the gate electrode can be increased, the off-state characteristics of the transistor 300 can be improved.

[0205] Furthermore, the transistor 300 may be a p-channel transistor or an n-channel transistor.

[0206] The channel formation region of the semiconductor region 313, the region adjacent thereto, the low resistance region 314a and the low resistance region 314b serving as the source region or the drain region, and the like preferably comprise a semiconductor such as a silicon-based semiconductor, more preferably single crystal silicon. Alternatively, they may be formed using materials such as Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaN (gallium nitride), and GaAlAs (gallium aluminum arsenide). Silicon in which effective mass is controlled by applying stress to the crystal lattice to change the interplanar spacing may be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) using GaAs, GaAlAs, or the like.

[0207] The low-resistance regions 314 a and 314 b contain, in addition to the semiconductor material used for the semiconductor region 313 , an element imparting n-type conductivity such as arsenic and phosphorus, or an element imparting p-type conductivity such as boron.

[0208] The conductive layer 316 serving as a gate electrode can be made of a conductive material such as a semiconductor material such as silicon, a metal material, an alloy material, or a metal oxide material containing an element imparting n-type conductivity such as arsenic or phosphorus or an element imparting p-type conductivity such as boron.

[0209] Furthermore, since the material of the conductor determines the work function, the threshold voltage (Vth) of the transistor can be adjusted by changing the conductor material. Specifically, materials such as titanium nitride or tantalum nitride are preferably used as the conductor. To achieve both conductivity and embeddability, a stack of metal materials such as tungsten or aluminum is preferably used as the conductor, with tungsten being particularly preferred for its heat resistance.

[0210] Notice, Figure 12 The structure of the transistor 300 shown is only an example and is not limited to the above structure. An appropriate transistor may be used depending on the circuit structure, driving method, etc.

[0211] An insulating layer 320 , an insulating layer 322 , an insulating layer 324 , and an insulating layer 326 are stacked in this order to cover the transistor 300 .

[0212] As the insulating layer 320 , the insulating layer 322 , the insulating layer 324 , and the insulating layer 326 , for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride can be used.

[0213] The insulating layer 322 can also be used as a planarization film for planarizing steps caused by the transistor 300 provided thereunder. For example, the top surface of the insulating layer 322 can be planarized by a planarization process such as chemical mechanical polishing (CMP) to improve planarity.

[0214] As the insulating layer 324 , a film having a barrier property that can prevent hydrogen, impurities, and the like from diffusing from the substrate 311 , the transistor 300 , and the like into a region where the transistor 141 and the like are provided is preferably used.

[0215] As an example of a film having hydrogen barrier properties, silicon nitride formed by CVD can be used. Here, hydrogen sometimes diffuses into a semiconductor element having an oxide semiconductor, such as transistor 141, causing the characteristics of the semiconductor element to deteriorate. Therefore, it is preferable to provide a film that inhibits the diffusion of hydrogen between transistor 141 and transistor 300. Specifically, the film that inhibits the diffusion of hydrogen refers to a film that has a small amount of hydrogen released.

[0216] The amount of hydrogen released can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, when the film surface temperature in TDS analysis is within the range of 50°C to 500°C, and the amount of hydrogen released per unit area of ​​the insulating layer 324 is converted into hydrogen atoms, the amount of hydrogen released from the insulating layer 324 is preferably 10×10 15 atoms / cm 2 Below, more preferably 5×10 15 atoms / cm 2 The following is enough.

[0217] Note that the dielectric constant of the insulating layer 326 is preferably lower than that of the insulating layer 324. For example, the relative dielectric constant of the insulating layer 326 is preferably less than 4, more preferably less than 3. For example, the relative dielectric constant of the insulating layer 326 is preferably 0.7 times or less, more preferably 0.6 times or less, the relative dielectric constant of the insulating layer 324. By using a material with a low relative dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0218] Furthermore, conductive layers 328 and 330 are embedded in insulating layers 320, 322, 324, and 326. Furthermore, conductive layers 328 and 330 function as plugs or wiring. Note that the same symbol may be used to represent multiple conductors that function as plugs or wiring. Furthermore, in this specification and other documents, wiring and a plug connected to the wiring may be considered a single component. In other words, a portion of a conductor may function as wiring, and a portion of the conductor may function as a plug.

[0219] As materials for each plug and wiring (conductive layer 328 and conductive layer 330, etc.), a single layer or stacked layers of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials can be used. Preferably, a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity is used, with tungsten being preferred. Alternatively, it is preferably formed using a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, wiring resistance can be reduced.

[0220] Although Figure 12 Although omitted in the figure, a wiring layer may be provided over the insulating layer 326 and the conductive layer 330. For example, it is preferable to provide an insulator having hydrogen barrier properties similar to the insulating layer 324 over the insulating layer 326 and the conductive layer 330, and to form a conductor having hydrogen barrier properties over the insulator. By forming a conductor having hydrogen barrier properties in the openings included in the insulator having hydrogen barrier properties, the transistor 300 can be separated from the transistor 141 and the like using the barrier layer, thereby suppressing the diffusion of hydrogen from the transistor 300 into the transistor 141 and the like.

[0221] As a conductor having hydrogen barrier properties, for example, tantalum nitride is preferably used. In addition, by stacking tantalum nitride and tungsten with high conductivity, hydrogen diffusion from the transistor 300 can be suppressed while maintaining the conductivity as a wiring. In this case, the tantalum nitride layer having hydrogen barrier properties is preferably in contact with an insulator having hydrogen barrier properties. Note that in Figure 12 In the embodiment, an insulating layer 350 having a hydrogen barrier property is provided on the insulating layer 326 and the conductive layer 330 .

[0222] <Layer 12>

[0223] Layer 12 includes conductive layer 125 , multiple conductive layers 103 , conductive layer 126 , conductive layer 127 , insulating layer 121 , insulating layer 122 , functional layer 118 , semiconductor layer 112 , conductive layer 101 , conductive layer 104 , and the like.

[0224] The insulating layer 121 serves as a gate insulating layer of the transistor 142, and the insulating layer 122 serves as a gate insulating layer of the transistor 143. The conductive layer 125 serves as a wiring. The conductive layer 126 serves as a gate of the transistor 142, and the conductive layer 127 serves as a gate of the transistor 143.

[0225] An insulating layer 384 is provided on the insulating layer 105. A conductive layer 386 is provided between the insulating layer 105 and the insulating layer 384 so as to reach the conductive layer 104. The conductive layer 386 serves as a plug.

[0226] For example, the conductive layer 125 may be made of a material containing one or more metal elements selected from the group consisting of aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and ruthenium. Furthermore, highly conductive semiconductors, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used. Furthermore, conductive materials containing metal elements such as titanium and tantalum and nitrogen may also be used. For example, conductive materials containing nitrogen, such as titanium nitride and tantalum nitride, may also be used. Furthermore, for example, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide doped with silicon may also be used. Furthermore, for example, indium gallium zinc oxide containing nitrogen may also be used. Using such materials may sometimes allow the capture of hydrogen or water that has infiltrated from surrounding insulators.

[0227] There is no particular limitation on the method for forming the conductive layer 125. For example, sputtering, CVD (including thermal CVD, MOCVD, PECVD, etc.), MBE (Molecular Beam Epitaxy), ALD (Atomic Layer Deposition), PLD (Pulsed Laser Deposition), etc. can be used.

[0228] A material with a low dielectric constant is preferably used for the insulating layer 102. This can reduce capacitance between the conductive layer 126 and the conductive layer 103, between the conductive layers 103 and 103, or between the conductive layer 103 and the conductive layer 127, thereby increasing the driving speed of the semiconductor device.

[0229] For example, a material containing silicon oxide or silicon oxynitride can be used as the insulating layer 102. Alternatively, a single layer or a stack of layers of an insulator containing a material selected from the group consisting of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used. The insulating layer 102 can be deposited using a deposition method such as sputtering, CVD (including thermal CVD, MOCVD, and PECVD), MBE, ALD, or PLD.

[0230] The conductive layer 103 , the conductive layer 126 , and the conductive layer 127 can use the same material as that of the conductive layer 125 .

[0231] As the conductive layer 101 and the conductive layer 104, for example, silicon diffused with impurities is preferably used. As the impurity, an n-type impurity (donor) can be used. As the n-type impurity, for example, phosphorus, arsenic, etc. can be used. In addition, as the impurity, a p-type impurity (acceptor) can be used. As the p-type impurity, for example, boron, aluminum, gallium, etc. can be used. In addition, as silicon, for example, single crystal silicon, hydrogenated amorphous silicon, microcrystalline silicon, or polycrystalline silicon can be used. In addition, as the conductive layer 101 and the conductive layer 104, in addition to silicon, a metal oxide with a high carrier density can sometimes be used. In addition, compound semiconductors such as Ge, ZnSe, CdS, GaAs, InP, GaN, SiGe, etc. can sometimes be used.

[0232] The material used for the conductive layer 101 and the conductive layer 104 is preferably the same as that of the semiconductor layer 112. In this case, the carrier density of the conductive layer 101 and the conductive layer 104 is preferably higher than that of the semiconductor layer 112.

[0233] Silicon is preferably used as the semiconductor layer 112. Alternatively, single crystal silicon, hydrogenated amorphous silicon, microcrystalline silicon, or polycrystalline silicon may be used. Furthermore, metal oxides other than silicon may also be used as the semiconductor layer 112. Compound semiconductors such as Ge, ZnSe, CdS, GaAs, InP, GaN, and SiGe may also be used.

[0234] As metal oxides that can be used for the semiconductor layer 112, for example, In oxide, Ga oxide, and Zn oxide can be cited. The metal oxide preferably contains at least In or Zn. In addition, the metal oxide preferably contains two or three selected from In, element M, and Zn. Note that element M is a metal element or semi-metal element with a high bond energy with oxygen, for example, a metal element or semi-metal element with a higher bond energy with oxygen than indium. As element M, specifically Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb can be cited. The element M contained in the metal oxide is preferably any one or more of the above elements, and is particularly preferably one or more selected from Al, Ga, Y, and Sn, among which Ga is more preferred.

[0235] When an In-M-Zn oxide is used as the metal oxide, the atomic ratio of In in the In-M-Zn oxide is preferably greater than or equal to the atomic ratio of M. For example, the atomic ratio of the metal elements in such an In-M-Zn oxide includes In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5, or compositions close thereto. Note that the close composition range includes a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current and field-effect mobility of the transistor can be improved.

[0236] The atomic ratio of In in the In-M-Zn oxide may be smaller than the atomic ratio of the element M. For example, the atomic ratio of the metal elements in such an In-M-Zn oxide includes In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, or compositions thereabouts. Increasing the atomic ratio of M in the metal oxide can suppress the formation of oxygen vacancies.

[0237] The semiconductor layer 112 can be made of, for example, In oxide, In-Zn oxide, In-Ga oxide, In-Sn oxide, In-Ti oxide, In-Ga-Al oxide, In-Ga-Sn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, In-Al-Zn oxide, In-Ti-Zn oxide, In-Ga-Sn-Zn oxide, In-Ga-Al-Zn oxide, or the like. Furthermore, Ga-Zn oxide can also be used. Using a material that does not contain Zn, such as indium oxide, is preferred because it improves compatibility with the LSI manufacturing process. On the other hand, using a material that contains Zn is preferred because it facilitates improved crystallinity.

[0238] In particular, by using In-Zn oxides in which the atomic ratio of metal elements is In:Zn=4:1, In:Zn=2:1 or thereabouts, or In-Sn-Zn oxides in which the atomic ratio of metal elements is In:Sn:Zn=4:0.1:1, In:Sn:Zn=2:0.1:1 or thereabouts, the field effect mobility of the transistor can be appropriately improved, so it is preferred.

[0239] Metal oxides can also replace indium or contain one or more metal elements with a large period number in addition to indium. There is a trend that the greater the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including a metal element with a large period number, the field effect mobility of the transistor can sometimes be improved. As metal elements with a large period number, metal elements belonging to the 5th period and metal elements belonging to the 6th period can be cited. As such metal elements, specifically Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm and Eu can be cited. Note that La, Ce, Pr, Nd, Pm, Sm and Eu are called light rare earth elements.

[0240] Furthermore, the metal oxide may contain one or more non-metallic elements. When the metal oxide contains non-metallic elements, the field-effect mobility of the transistor may sometimes be improved. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0241] Metal oxides can be formed using sputtering or atomic layer deposition (ALD) as appropriate. ALD deposition is particularly preferred due to its excellent coverage. Note that when forming metal oxides using sputtering, the composition of the deposited metal oxide may differ from that of the target. In particular, the zinc content of the deposited metal oxide may be reduced to approximately 50% of the zinc content in the target.

[0242] In this specification, etc., the content rate of a certain metal oxide in a metal element refers to the ratio of the number of atoms of the element to the total number of atoms of the metal element contained in the metal oxide. For example, a metal oxide contains metal element X, metal element Y, and metal element Z, and the number of atoms of metal element X, metal element Y, and metal element Z contained in the metal oxide is A, respectively. X 、A Y 、A Z When the content of metal element X is expressed as A X / (A X +A Y +A Z ). In addition, when the ratio of the number of atoms of metal element X, metal element Y, and metal element Z in the metal oxide (atomic ratio) is expressed as B X :B Y :B Z When the content of metal element X is expressed as B X / (B X +B Y +B Z ).

[0243] For example, when a metal oxide containing In is used, a transistor with a large on-state current can be realized by increasing the In content.

[0244] By using a metal oxide that does not contain Ga or has a low Ga content in the semiconductor layer 112, a transistor with high reliability when a positive bias is applied can be realized. In other words, a transistor with small fluctuations in threshold voltage during a PBTS (Positive Bias Temperature Stress) test can be realized. Furthermore, when using a metal oxide containing Ga, the Ga content is preferably lower than the In content. This allows for the realization of a transistor with high mobility and reliability.

[0245] On the other hand, increasing the Ga content can achieve transistors with high reliability against light. Specifically, it can achieve transistors with minimal fluctuation in threshold voltage during NBTIS (Negative Bias Temperature Illumination Stress) testing. Specifically, metal oxides with a Ga atomic ratio greater than that of In have a larger band gap, which can reduce the fluctuation in threshold voltage during NBTIS testing of transistors.

[0246] Furthermore, increasing the Zn content improves the crystallinity of the metal oxide, which can suppress the diffusion of impurities in the metal oxide. This suppresses variations in the electrical characteristics of the transistor, thereby improving reliability.

[0247] The semiconductor layer 112 may also have a stacked structure including two or more metal oxide layers. The compositions of the two or more metal oxide layers included in the semiconductor layer 112 may also be the same or substantially the same as each other. By adopting a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used to form them, thereby reducing manufacturing costs. Note that a stacked structure of two or more oxide semiconductor layers with different stacked compositions may also be adopted. In addition, by utilizing the ALD method, a metal oxide layer whose composition continuously changes in the thickness direction may be formed. Thus, compared with the case of using a film of a predetermined composition, not only can the range of design options be expanded, but the generation of interface states, etc., generated between two layers with different compositions can also be prevented, thereby improving electrical characteristics and reliability.

[0248] A crystalline metal oxide layer is preferably used for the semiconductor layer 112. For example, a metal oxide layer having a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, or a nanocrystalline (nc) structure can be used. Using a crystalline metal oxide layer for the semiconductor layer 112 can reduce the defect state density in the semiconductor layer 112, thereby achieving a highly reliable semiconductor device.

[0249] The higher the crystallinity of the metal oxide layer used for the semiconductor layer 112, the lower the defect state density in the semiconductor layer 112. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0250] For the functional layer 118 , reference can be made to the above description. Figure 12 An example using a dielectric exhibiting ferroelectricity is shown.

[0251] in addition, Figure 13 This is an example of a stacked-layer structure including an insulating layer 131, an insulating layer 132, and an insulating layer 133 instead of the functional layer 118. For example, the insulating layer 132 functions as a charge accumulation layer. For example, a silicon oxide film can be used for the insulating layer 131, a silicon nitride film can be used for the insulating layer 132, and a silicon oxide film can be used for the insulating layer 133. Figure 13 The transistor 141 shown is used as a charge trap type cell transistor. Note that the present invention is not limited to this, and a floating gate type cell transistor may also be used.

[0252] <Layer 13>

[0253] like Figure 14 As shown, layer 13 is provided on layer 12. Layer 13 includes transistor 200 and capacitor 250.

[0254] Transistor 200 is a transistor containing a metal oxide in the channel formation region (OS transistor). Transistor 200 includes a pair of gates that sandwich the semiconductor forming the channel. Transistor 200 has a characteristic of extremely low off-state current. For example, by using transistor M11 in the memory cell OMC shown in the above embodiment, data written to the memory cell OMC can be retained for a long time. It can also be applied to transistor M12. In addition, capacitor 250 can be used as capacitor C11 or capacitor C12 in the above embodiment.

[0255] In layer 13, insulating films such as insulating layer 210, insulating layer 212, insulating layer 214, insulating layer 216, insulating layer 220, insulating layer 222, insulating layer 240, insulating layer 244, insulating layer 241, insulating layer 242, insulating layer 246, and insulating layer 248 are stacked on insulating layer 384. Insulating layer 212, insulating layer 216, insulating layer 240, insulating layer 241, insulating layer 246, and insulating layer 248 serve as interlayer insulating films, and the same material as insulating layer 102 can be used. Furthermore, insulating films having barrier properties that can prevent the diffusion of hydrogen, impurities, and the like are preferably used as insulating layers 210, 214, 220, 222, 244, and 242.

[0256] A conductive layer 218 is provided in a manner embedded in the insulating layer 210, the insulating layer 212, the insulating layer 214, and the insulating layer 216. The conductive layer 218 is used as a plug. Figure 14 In the embodiment, the conductive layer 218 is provided in contact with the conductive layer 386 .

[0257] The transistor 200 includes a conductive layer 205 configured to be embedded in an insulating layer 214 and an insulating layer 216, an insulating layer 220 and an insulating layer 222 on the insulating layer 216 and the conductive layer 205, an insulating layer 224 on the insulating layer 222, a semiconductor layer 201 on the insulating layer 224, a pair of conductive layers 204 arranged on the semiconductor layer 201, an insulating layer 240 located on the conductive layer 204 and having a groove reaching the semiconductor layer 201, and an insulating layer 203 and a conductive layer 202 arranged to be embedded in the insulating layer 240.

[0258] One of the pair of conductive layers 204 functions as a source electrode, and the other functions as a drain electrode. Conductive layer 202 functions as a first gate electrode, and insulating layer 203 functions as a first gate insulating layer. Conductive layer 205 functions as a second gate electrode, and insulating layers 220, 222, and 224 function as a second gate insulating layer.

[0259] As the insulating layer 224 and the insulating layer 203 in contact with the semiconductor layer 201, an oxide is preferably used. For example, oxides such as silicon oxide, silicon oxynitride, aluminum oxide, and hafnium oxide are preferably used. In addition, nitrides such as silicon nitride, silicon oxynitride, and aluminum nitride may also be used. In addition, a single layer or a stack of insulators containing so-called high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, and zirconium oxide are preferably used. With the miniaturization and high integration of transistors, problems such as leakage current sometimes occur due to the thin filming of the gate insulating film. Therefore, by using a high-k material as an insulator used as a gate insulating film, the gate potential of the transistor during operation can be reduced while maintaining the physical thickness.

[0260] A stacked film formed by stacking a plurality of insulating films is preferably used as the insulating layer 203. For example, a stacked film formed by stacking two, three, or four or more insulating material films is preferably used.

[0261] Note that the thin film containing the ferroelectric material described in Embodiment 1 is preferably used as the insulating layer 203. This allows the transistor 200 to be used as a nonvolatile memory element. In this case, a structure without using the capacitor 250 is also possible.

[0262] The insulating layer 234 is provided so as to cover the conductive layer 204 and has the function of suppressing oxidation of the conductive layer 204. In this case, the insulating layer 234 is provided so as to cover the side surfaces of the semiconductor layer 201 and the side surfaces of the insulating layer 224 and to be in contact with the insulating layer 222. As the insulating layer 234, an insulating film having barrier properties that can prevent the diffusion of hydrogen, impurities, etc. is preferably used.

[0263] Capacitor 250 is provided on insulating layer 246. Capacitor 250 includes a conductive layer 251, a conductive layer 252, and an insulating layer 253 located therebetween. Capacitor 250 is a so-called MIM (Metal-Insulator-Metal) capacitor.

[0264] A single layer or a stack of layers of an insulator containing the above-mentioned high-k material is preferably used as the insulating layer 253. Alternatively, the ferroelectric material described in Embodiment 1 can be used as the insulating layer 253. In this way, the capacitor 250 can be used as a ferroelectric capacitor, and a nonvolatile memory cell can be realized by combining it with the transistor 200.

[0265] Furthermore, a conductive layer 254 serving as wiring may be included over the insulating layer 246. The conductive layer 254 can be formed by processing the same conductive film as the conductive layer 251.

[0266] Conductive layer 254 is connected to conductive layer 204 via conductive layer 236 and conductive layer 238. Conductive layer 236 and conductive layer 238 function as plugs. Conductive layer 236 and conductive layer 238 can use the same material as conductive layer 328 and conductive layer 330.

[0267] Figure 15 Examples of different structures of layer 13 are shown. Figure 15 In FIG, a transistor 400a and a transistor 400b are provided in layer 13. Both the transistor 400a and the transistor 400b are vertical transistors.

[0268] Both the transistor 400a and the transistor 400b include a semiconductor layer 401, a conductive layer 402 serving as a gate electrode, an insulating layer 403 serving as a gate insulating layer, a conductive layer 404 serving as one of a source electrode and a drain electrode, and a conductive layer 406 serving as the other of the source electrode and the drain electrode.

[0269] The structure of transistor 400b will be described. Conductive layer 407 is provided over insulating layer 216, conductive layer 406 is provided over conductive layer 407, and insulating layer 410 is provided to cover conductive layer 406. Conductive layer 405 is provided over insulating layer 410, and conductive layer 404 is provided over conductive layer 405. Openings reaching conductive layer 406 are provided in conductive layers 404, 405, and insulating layer 410. Semiconductor layer 401 is in contact with conductive layers 404 and 406, and also in contact with the side surface located within the opening of insulating layer 410. Insulating layer 403 is provided to cover semiconductor layer 401, and conductive layer 402 is provided to fill the opening.

[0270] In one or both of the transistor 400a and the transistor 400b, the thin film containing the material exhibiting ferroelectricity described in Embodiment 1 can be used as the insulating layer 403 serving as a gate insulating layer. In particular, such a thin film is preferably used for the insulating layer 403 of the transistor 400b. Thus, the transistor 400b can be used as a nonvolatile memory element.

[0271] Since the channel length of the transistor 400b can be precisely controlled according to the thickness of the insulating layer 410, the unevenness of the channel length can be made extremely small compared to a planar transistor. Furthermore, by thinning the insulating layer 410, a transistor with an extremely small channel length can also be manufactured. For example, a transistor with a channel length of less than 2 μm, less than 1 μm, less than 500 nm, less than 300 nm, less than 200 nm, less than 100 nm, less than 50 nm, less than 30 nm or less than 20 nm and greater than 5 nm, greater than 7 nm or greater than 10 nm can be manufactured. Therefore, a transistor with a channel length of less than 10 nm can be realized without using the very expensive exposure equipment used in the most advanced LSI technology.

[0272] Various semiconductor materials can be used for the semiconductor layer 401, with oxide semiconductors containing metal oxides being particularly preferred. By using an oxide semiconductor formed under appropriate conditions, a transistor having both high on-state current and extremely low off-state current can be realized at low cost. Unless otherwise specified, preferred structural examples when an oxide semiconductor is used for the semiconductor layer 401 are described below.

[0273] The top surfaces of the conductive layers 404 and 406 are in contact with the semiconductor layer 401. Therefore, when an oxide semiconductor is used for the semiconductor layer 401, there is a concern that the surfaces of the conductive layers 404 and 406 may be oxidized due to the deposition process of the semiconductor film to be the semiconductor layer 401 or the influence of heat applied thereafter, thereby forming an insulating oxide film between the conductive layers 404 and 406 and the semiconductor layer 401, resulting in an increase in contact resistance. Therefore, it is preferable to use an oxide conductor containing a conductive oxide for at least the uppermost portions of the conductive layers 404 and 406. This prevents an increase in contact resistance due to oxidation of the surfaces of the conductive layers 404 and 406. The conductive layers 404 and 406 may also be referred to as oxide layers, metal oxide layers, or oxide conductor layers.

[0274] The conductive layer 405 can function as either a source wiring or a drain wiring. Alternatively, a portion of the conductive layer 407 can function as the other of the source wiring and the drain wiring. By providing the conductive layer 405 and the conductive layer 407 in contact with the conductive layer 404 and the conductive layer 406, respectively, the resistance of the wiring can be reduced. The conductive layer 405 and the conductive layer 407 are preferably made of a material having a higher conductivity than an oxide conductor, such as a metal, an alloy, or a nitride thereof.

[0275] The semiconductor layer 401 is provided in such a manner as to be in contact with the inner wall of the opening of the insulating layer 410. An oxide insulating film is preferably used as the insulating layer 410. In particular, an oxide insulating film that releases oxygen by heating is preferably used. In addition, as the insulating layer 410, a stacked structure of three or more layers is preferably adopted, that is, a structure in which an oxide insulating film is sandwiched by an insulating film having oxygen barrier properties (for example, a nitride insulating film). Thus, the oxygen contained in the oxide insulating film can be confined in a region surrounded by a pair of nitride insulating films and the semiconductor layer 401, and the oxygen in the oxide insulating film can be prevented from being detached and reduced during the process, so that oxygen can be supplied to the semiconductor layer 401 more efficiently.

[0276] The transistor 400 a includes an insulating layer 414 and a conductive layer 402 instead of the insulating layer 410 and the conductive layer 406 of the transistor 400 b , respectively. Other than this, the structure of the transistor 400 a is substantially the same as that of the transistor 400 b .

[0277] The gate electrode of transistor 400b also serves as one of the source electrode and drain electrode of transistor 400a. Figure 7B In the structure shown, the transistor M11 and the transistor 400b correspond to the transistor M12.

[0278] The insulating layer 410, the insulating layer 414, and the insulating layer 418 serve as interlayer insulating films. As the insulating layer 412, the insulating layer 416, and the like, an insulating film having a barrier property against hydrogen, impurities, and the like is preferably used.

[0279] The source electrode and drain electrode of the transistor having the above structure are located at different heights, so the current flowing through the semiconductor flows in the height direction. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction), so the transistor of one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, etc. In the above transistor, the source electrode, the semiconductor and the drain electrode can be arranged in an overlapping manner, so compared with the so-called planar transistor (also called a lateral transistor, LFET (LateralFET), etc.) in which the semiconductor is arranged on a plane, the occupied area can be greatly reduced.

[0280] Figure 16 Shows part of the structure and Figure 15 Different examples. Figure 16 Layer 13 is shown including transistor 400 having the same structure as transistor 400a and including capacitor 420 in place of transistor 400b.

[0281] The capacitor 420 includes a conductive layer 421, a conductive layer 422, and an insulating layer 423 interposed therebetween. The insulating layer 423 serves as a dielectric layer of the capacitor 420. In addition, the conductive layer 407 is provided in contact with the conductive layer 421 and serves as wiring.

[0282] Insulating layer 410 has an opening that reaches conductive layer 407. Conductive layer 421 is provided in contact with the top surface of insulating layer 410, the side surfaces within the opening, and the top surface of conductive layer 407 at the bottom of the opening. Insulating layer 423 is provided to cover conductive layer 421. Conductive layer 422 is provided to cover insulating layer 423.

[0283] A single layer or a stack of layers of an insulator containing the above-mentioned high-k material is preferably used as the insulating layer 423. Alternatively, the ferroelectric material described in Embodiment 1 can be used as the insulating layer 423. Thus, the capacitor 420 can be used as a ferroelectric capacitor, and a nonvolatile memory cell can be realized by combining it with the transistor 400.

[0284] For example, transistor 400 is equivalent to Figure 7C In the structure shown, the transistor M13 and the capacitor 420 correspond to the capacitor C12.

[0285] By adopting a structure in which vertical transistors and vertical capacitors are stacked, the area occupied by the memory cell can be minimized, thereby realizing a memory device that can be easily highly integrated and has a large capacity.

[0286] Note that, although the structure in which layer 13 is provided on layer 12 is shown above, a structure in which layer 12 is provided on layer 13 is also possible. For example, Figure 17 An example is shown in which the layer 13 including the transistor 200 is arranged below the layer 12. Figure 18 An example is shown in which the layer 13 including the transistor 400 a and the transistor 400 b is arranged below the layer 12 . Figure 17 and Figure 18 The example in which the layer 13 includes the conductive layer 260 and the conductive layer 460, which are respectively used as plugs, is shown. The layer 11 (not shown) located on the lower side of the layer 13 can be connected to the layer 12 on the layer 13 through the conductive layer 260 or the conductive layer 460. Figure 19 An example is shown in which the layer 13 including the transistor 400 and the capacitor 420 is arranged below the layer 12 .

[0287] At least a part of the structural examples described in this embodiment mode and the drawings corresponding to these examples can be combined with other structural examples, drawings, etc. as appropriate.

[0288] (Implementation 3)

[0289] This embodiment describes a semiconductor device 900 according to one embodiment of the present invention, which is different from the above embodiments. Semiconductor device 900 can be used as a memory device. A semiconductor device to which the memory cell unit MCL or memory cell unit OMCL described in Embodiment 1 can be applied is described below.

[0290] Figure 20 is a block diagram showing a structural example of a semiconductor device 900 . Figure 20 The semiconductor device 900 shown includes a driver circuit 910 and a memory array 920. The memory array 920 includes one or more memory cells 950. Figure 20 The example in which the memory array 920 includes a plurality of memory cells 950 arranged in a matrix is ​​shown.

[0291] As the memory cell 950 , the memory cell section MCL or the memory cell section OMCL described as an example in the above embodiment can be used.

[0292] The driving circuit 910 includes a PSW 931 (power switch), a PSW 932 , and a peripheral circuit 915 . The peripheral circuit 915 includes a peripheral circuit 911 , a control circuit 912 , and a voltage generating circuit 928 .

[0293] In semiconductor device 900, the aforementioned circuits, signals, and voltages may be selected or omitted as needed. Alternatively, other circuits or signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals, while signal RDA is an external output signal. Signal CLK is a clock signal.

[0294] In addition, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 can also be generated by control circuit 912.

[0295] The control circuit 912 is a logic circuit that controls the overall operation of the semiconductor device 900. For example, the control circuit 912 performs logical operations on the signals CE, GW, and BW to determine the operating mode (e.g., write operation, read operation) of the semiconductor device 900. Alternatively, the control circuit 912 generates control signals for the peripheral circuits 911 to implement the aforementioned operating modes.

[0296] Voltage generating circuit 928 has a function of generating a negative voltage. Signal WAKE has a function of controlling the input of signal CLK to voltage generating circuit 928. For example, when signal WAKE is applied with an H level signal, signal CLK is input to voltage generating circuit 928, and voltage generating circuit 928 generates a negative voltage.

[0297] The peripheral circuit 911 is used to write and read data from the memory cell 950. The peripheral circuit 911 includes a row decoder 941 (Row Decoder), a column decoder 942 (Column Decoder), a row driver 923 (Row Driver), a column driver 924 (Column Driver), an input circuit 925 (Input Cir.), an output circuit 926 (Output Cir.), and a sense amplifier 927 (Sense Amplifier).

[0298] The row decoder 941 and column decoder 942 decode the signal ADDR. The row decoder 941 specifies the row to be accessed, while the column decoder 942 specifies the column to be accessed. The row driver 923 selects the row designated by the row decoder 941. The column driver 924 writes data to the memory cell 950, reads data from the memory cell 950, and stores the read data.

[0299] Input circuit 925 holds signal WDA. Data held in input circuit 925 is output to column driver 924. The output data from input circuit 925 is data (Din) written to memory cell 950. Data (Dout) read from memory cell 950 by column driver 924 is output to output circuit 926. Output circuit 926 holds Dout. Furthermore, output circuit 926 outputs Dout to the outside of semiconductor device 900. The data signal output from output circuit 926 is signal RDA.

[0300] PSW931 has the function of controlling the supply of V to the peripheral circuit 915 DD PSW932 has the function of controlling the supply of V to the row driver 923. HM Here, the high power supply voltage of the semiconductor device 900 is V DD , the low power supply voltage is GND (ground potential). In addition, V HM It is a high power supply voltage used to make the word line high, which is higher than V DD The on / off of PSW931 is controlled by signal PON1, and the on / off of PSW932 is controlled by signal PON2. Figure 20 In the peripheral circuit 915, V DD The number of power domains is 1, but it can also be multiple. In this case, a power switch can be set for each power domain.

[0301] Reference Figures 21A to 21H Other examples of memory cell structures that can be used for the memory cell 950 are described below.

[0302] When two components are described as being connected, this includes electrical connection via circuit elements (transistors, switches, diodes, resistors, etc.). Electrical connection refers to a state where current can flow between two components. Furthermore, when two components are connected via a switch or transistor, current can flow when the switch or transistor is turned on, and therefore falls within the scope of electrical connection.

[0303] [DOSRAM]

[0304] Figure 21A An example circuit structure of a DRAM type memory cell is shown. In this specification, etc., a DRAM using an OS transistor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 951 includes a transistor M1 and a capacitor CA.

[0305] The transistor M1 may include a front gate (sometimes simply referred to as a gate) and a back gate. In this case, the back gate may be connected to a wiring to which a constant potential or a signal is supplied, and the front gate and the back gate may be connected.

[0306] A first terminal of the transistor M1 is connected to a first terminal of the capacitor CA, a second terminal of the transistor M1 is connected to a wiring BIL, a gate of the transistor M1 is connected to a wiring WOL, and a second terminal of the capacitor CA is connected to a wiring CAL.

[0307] Wiring BIL serves as a bit line, and wiring WOL serves as a word line. Wiring CAL is used to apply a specified potential to the second terminal of capacitor CA. When writing or reading data, a low-level potential (sometimes referred to as a reference potential) is preferably applied to wiring CAL.

[0308] Data writing and reading are performed by applying a high-level potential to the wiring WOL to turn on the transistor M1 and thereby establish a conduction state (allowing current to flow) between the wiring BIL and the first terminal of the capacitor CA.

[0309] Furthermore, the memory cell that can be used as the memory cell 950 is not limited to the memory cell 951, and the circuit structure can be changed. For example, Figure 21B The structure of the memory cell 952 is shown. The memory cell 952 is an example of a case where the capacitor CA and the wiring CAL are not included. The first terminal of the transistor M1 is in an electrically floating state.

[0310] In the memory cell 952, the potential written by the transistor M1 is retained in the capacitance (also referred to as parasitic capacitance) between the first terminal and the gate shown by the dotted line. By adopting this structure, the structure of the memory cell can be greatly simplified.

[0311] As transistor M1, an OS transistor is preferably used. OS transistors have the characteristic of extremely low off-state current. By using an OS transistor as transistor M1, the leakage current of transistor M1 can be made very low. In other words, transistor M1 can be used to retain written data for a long time, thereby reducing the refresh frequency of the memory cell. In addition, the refresh operation of the memory cell can be omitted. In addition, because the leakage current is very low, multi-valued data or analog data can be retained in memory cells 951 and 952.

[0312] [NOSRAM]

[0313] Figure 21C This figure shows an example circuit structure of a gain-cell type memory cell comprising two transistors and one capacitor. Memory cell 953 includes transistor M2, transistor M3, and capacitor CB. In this specification and other documents, a memory device comprising a gain-cell type memory cell using an OS transistor for transistor M2 is sometimes referred to as a NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0314] A first terminal of transistor M2 is connected to a first terminal of capacitor CB, a second terminal of transistor M2 is connected to wiring WBL, and a gate of transistor M2 is connected to wiring WOL. A second terminal of capacitor CB is connected to wiring CAL. A first terminal of transistor M3 is connected to wiring RBL, a second terminal of transistor M3 is connected to wiring SL, and a gate of transistor M3 is connected to a first terminal of capacitor CB.

[0315] Wiring WBL serves as a write bit line, wiring RBL serves as a read bit line, and wiring WOL serves as a word line. Wiring CAL serves as a wiring for applying a predetermined potential to the second terminal of capacitor CB. When writing data, retaining data, and reading data, a low-level potential (sometimes referred to as a reference potential) is preferably applied to wiring CAL.

[0316] Data is written by applying a high potential to wiring WOL, turning on transistor M2 and bringing wiring WBL and the first terminal of capacitor CB into a conductive state. Specifically, while transistor M2 is on, a potential corresponding to the information to be recorded is applied to wiring WBL, writing that potential to the first terminal of capacitor CB and the gate of transistor M3. Subsequently, a low potential is applied to wiring WOL, turning off transistor M2. This maintains the potential of the first terminal of capacitor CB and the gate of transistor M3.

[0317] Data is read by applying a predetermined potential to wiring SL. Since the current flowing between the source and drain of transistor M3 and the potential of the first terminal of transistor M3 are determined by the potentials of its gate and second terminal, the potential held by the first terminal of capacitor CB (or the gate of transistor M3) can be read by reading the potential of wiring RBL connected to the first terminal of transistor M3. In other words, the information written to the memory cell can be read from the potential held by the first terminal of capacitor CB (or the gate of transistor M3).

[0318] For example, a structure may be adopted in which the wiring WBL and the wiring RBL are combined into one wiring BIL. Figure 21D An example circuit structure of a memory cell in this case is shown below. In memory cell 954, the wiring WBL and wiring RBL of memory cell 953 are combined into a single wiring BIL, and the second terminal of transistor M2 and the first terminal of transistor M3 are connected to wiring BIL. In other words, memory cell 954 operates by combining the write bit line and the read bit line into a single wiring BIL.

[0319] Figure 21E The memory cell 955 shown is an example of a case where the capacitor CB and the wiring CAL in the memory cell 953 are omitted. Figure 21F The memory cell 956 shown is an example in which the capacitor CB and the wiring CAL are omitted from the memory cell 954. By adopting such a structure, the integration density of the memory cells can be increased.

[0320] Note that it is preferable to use an OS transistor as at least the transistor M2. In particular, it is preferable to use an OS transistor as the transistor M2 and the transistor M3.

[0321] Because the OS transistor has an extremely low off-state current, transistor M2 can be used to hold written data for a long time, thereby reducing the refresh frequency of the memory cell. Furthermore, the memory cell refresh operation can be omitted. Furthermore, since the leakage current is very low, multi-valued data or analog data can be held in memory cells 953, 954, 955, and 956.

[0322] The memory cells 953 , 954 , 955 , and 956 , each of which uses an OS transistor as the transistor M2 , are one embodiment of NOSRAM.

[0323] A Si transistor can also be used as the transistor M3. A Si transistor can improve field-effect mobility and can be a p-channel transistor, thereby increasing the degree of freedom in circuit design.

[0324] Furthermore, when an OS transistor is used as the transistor M3, the memory cell can be formed of only n-type transistors.

[0325] also, Figure 21G A gain unit type memory cell 957 including three transistors and one capacitor is shown. The memory cell 957 includes transistors M4 to M6 and a capacitor CC.

[0326] A first terminal of transistor M4 is connected to the first terminal of capacitor CC, a second terminal of transistor M4 is connected to wiring BIL, and a gate of transistor M4 is connected to wiring WOL. A second terminal of capacitor CC is connected to the first terminal of transistor M5 and wiring GNDL. A second terminal of transistor M5 is connected to the first terminal of transistor M6, and a gate of transistor M5 is connected to the first terminal of capacitor CC. A second terminal of transistor M6 is connected to wiring BIL, and a gate of transistor M6 is connected to wiring RWL.

[0327] The wiring BIL serves as a bit line, the wiring WOL serves as a write word line, and the wiring RWL serves as a read word line. The wiring GNDL is a wiring for supplying a low-level potential.

[0328] Data is written by applying a high potential to wiring WOL, turning on transistor M4 and bringing wiring BIL and the first terminal of capacitor CC into a conductive state. Specifically, while transistor M4 is on, a potential corresponding to the information to be recorded is applied to wiring BIL, writing that potential to the first terminal of capacitor CC and the gate of transistor M5. Subsequently, a low potential is applied to wiring WOL, turning off transistor M4. This maintains the potential of the first terminal of capacitor CC and the gate of transistor M5.

[0329] Data is read by precharging wiring BIL to a predetermined potential, then electrically floating it and applying a high-level potential to wiring RWL. By setting wiring RWL to a high-level potential, transistor M6 is turned on, and wiring BIL and the second terminal of transistor M5 are conductive. At this point, the potential of wiring BIL is applied to the second terminal of transistor M5. However, the potential of the second terminal of transistor M5 and the potential of wiring BIL change according to the potential held by the first terminal of capacitor CC (or the gate of transistor M5). Here, the potential held by the first terminal of capacitor CC (or the gate of transistor M5) can be read by reading the potential of wiring BIL. In other words, the information written to the memory cell can be read from the potential held by the first terminal of capacitor CC (or the gate of transistor M5).

[0330] Note that an OS transistor is preferably used as at least the transistor M4.

[0331] Si transistors may be used as the transistors M5 and M6. As described above, the field effect mobility of Si transistors may be higher than that of OS transistors depending on the crystal state of silicon used for the semiconductor layer.

[0332] Furthermore, when OS transistors are used as the transistors M5 and M6, the memory cell can be formed only of n-type transistors.

[0333] [OS-SRAM]

[0334] Figure 21H An example of an SRAM (Static Random Access Memory) using an OS transistor is shown. In this specification, etc., an SRAM using an OS transistor is referred to as an OS-SRAM (Oxide Semiconductor-SRAM). Figure 21H The memory cell 958 shown is an SRAM type memory cell capable of backup.

[0335] The memory cell 958 includes transistors M7 to M10, transistors MS1 to MS4, capacitors CD1 and CD2. Transistors MS1 and MS2 are p-channel transistors, and transistors MS3 and MS4 are n-channel transistors.

[0336] A first terminal of transistor M7 is connected to wiring BIL, and a second terminal of transistor M7 is connected to the first terminal of transistor MS1, the first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and the first terminal of transistor M10. The gate of transistor M7 is connected to wiring WOL. A first terminal of transistor M8 is connected to wiring BILB, and a second terminal of transistor M8 is connected to the first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and the first terminal of transistor M9. The gate of transistor M8 is connected to wiring WOL.

[0337] The second terminal of the transistor MS1 is connected to the wiring VDL. The second terminal of the transistor MS2 is connected to the wiring VDL. The second terminal of the transistor MS3 is connected to the wiring GNDL. The second terminal of the transistor MS4 is connected to the wiring GNDL.

[0338] The second terminal of transistor M9 is connected to the first terminal of capacitor CD1, and the gate of transistor M9 is connected to wiring BRL. The second terminal of transistor M10 is connected to the first terminal of capacitor CD2, and the gate of transistor M10 is connected to wiring BRL.

[0339] A second terminal of the capacitor CD1 is connected to the wiring GNDL, and a second terminal of the capacitor CD2 is connected to the wiring GNDL.

[0340] The wiring BIL and the wiring BILB serve as bit lines, the wiring WOL serves as a word line, and the wiring BRL is a wiring for controlling the on and off states of the transistors M9 and M10 .

[0341] The wiring VDL is a wiring for supplying a high-level potential, and the wiring GNDL is a wiring for supplying a low-level potential.

[0342] Data is written by applying a high potential to the wiring WOL and a high potential to the wiring BRL. Specifically, when the transistor M10 is turned on, a potential corresponding to the information to be recorded is applied to the wiring BIL, and this potential is written to the second terminal side of the transistor M10.

[0343] Memory cell 958 forms an inverter loop using transistors MS1 and MS2. Therefore, the inverse of the data signal corresponding to this potential is input to the second terminal of transistor M8. Since transistor M8 is on, the potential applied to wiring BIL, that is, the inverse of the signal input to wiring BIL, is output to wiring BILB. Furthermore, since transistors M9 and M10 are on, the potentials of the second terminals of transistor M7 and transistor M8 are maintained by the first terminals of capacitors CD2 and CD1, respectively. Subsequently, by applying a low-level potential to wiring WOL and a low-level potential to wiring BRL, transistors M7 and M10 are turned off, thereby maintaining the potentials of the first terminals of capacitors CD1 and CD2.

[0344] Data is read out using the following method: First, wiring BIL and wiring BILB are precharged to predetermined potentials. A high-level potential is then applied to wiring WOL and wiring BRL. This causes the potential at the first terminal of capacitor CD1 to be refreshed by the inverter loop of memory cell 958 and output to wiring BILB. Furthermore, the potential at the first terminal of capacitor CD2 is refreshed by the inverter loop of memory cell 958 and output to wiring BIL. Since wiring BIL and wiring BILB change from their precharged potentials to the potentials of the first terminals of capacitor CD2 and CD1, respectively, the potential held in the memory cell can be read from the potentials of wiring BIL or wiring BILB.

[0345] Transistors M7 to M10 are preferably OS transistors. This allows transistors M7 to M10 to hold written data for a long time, thereby reducing the refresh frequency of the memory cell. Alternatively, the memory cell refresh operation may be omitted.

[0346] Furthermore, Si transistors are preferably used as the transistors MS1 to MS4 .

[0347] The driving circuit 910 and the memory array 920 included in the semiconductor device 900 may also be arranged on the same plane. Figure 22A As shown, the driving circuit 910 and the memory array 920 may also overlap. By overlapping the driving circuit 910 and the memory array 920, the signal transmission distance can be shortened. Figure 22B As shown, a plurality of memory arrays 920 may be stacked on the driver circuit 910 .

[0348] Next, an example of an arithmetic processing device that may include a semiconductor device such as the above-mentioned memory device will be described.

[0349] Figure 23 It is a block diagram of the computing device 960. Figure 23 The illustrated computing device 960 can be used, for example, as a CPU (Central Processing Unit). Furthermore, the computing device 960 can also be used as a processor such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), or an NPU (Neural Processing Unit), which includes more (tens to hundreds) processor cores capable of parallel processing than a CPU.

[0350] Figure 23 The illustrated computing device 960 includes an ALU 991 (Arithmetic Logic Unit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, registers 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. Substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. A rewritable ROM and a ROM interface may also be included. Cache 999 and cache interface 989 may also be provided on separate chips.

[0351] The cache memory 999 is connected to the main memory provided on a separate chip via the cache interface 989. The cache interface 989 has the function of supplying a portion of the data stored in the main memory to the cache memory 999. The cache interface 989 also has the function of outputting a portion of the data held in the cache memory 999 to the ALU 991, register 996, or the like via the bus interface 998.

[0352] As described later, the memory array 920 may be provided in a stacked manner on the computing device 960. The memory array 920 may be used as a cache memory. In this case, the cache memory interface 989 may have a function of supplying data stored in the memory array 920 to the cache memory 999. In this case, it is preferable that a driver circuit 910 be included as part of the cache memory interface 989.

[0353] Note that the cache memory 999 may not be provided and only the memory array 920 may be used as a cache memory.

[0354] Figure 23 The computing device 960 shown is only an example of a simplified structure, so the actual computing device 960 has various structures depending on its use. For example, it is preferable to use a device that includes Figure 23 The structure of the computing device 960 shown is a so-called multi-core structure in which a plurality of cores are provided for one core and the cores are operated simultaneously. The more cores there are, the higher the computing performance can be. The more cores there are, the more preferred it is, for example, preferably 2, more preferably 4, further preferably 8, further preferably 12, and further preferably 16 or more. In addition, when very high computing performance is required, such as when used in a server, it is preferred to adopt a multi-core structure including 16 or more cores, preferably 32 or more, and more preferably 64 or more cores. In addition, the number of bits that can be processed in the internal computing circuit, data bus, etc. of the computing device 960 can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0355] The instructions input to the operation device 960 through the bus interface 998 are input to the instruction decoder 993 and decoded, and then input to the ALU controller 992, the interrupt controller 994, the register controller 997, and the timing controller 995.

[0356] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on decoded instructions. Specifically, the ALU controller 992 generates signals to control the operation of the ALU 991. Furthermore, when executing programs in the arithmetic unit 960, the interrupt controller 994 identifies interrupt requests from external input / output devices, peripheral circuits, and the like based on their priority, mask status, and other factors, and processes them accordingly. The register controller 997 generates the address of the register 996 and reads and writes to the register 996 based on the state of the arithmetic unit 960.

[0357] Furthermore, the timing controller 995 generates signals for controlling the operation timing of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997. For example, the timing controller 995 includes an internal clock generator that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0358] exist Figure 23 In the illustrated arithmetic device 960, register controller 997 selects a hold operation for register 996 based on instructions from ALU 991. In other words, register controller 997 selects whether data is held in the memory cells included in register 996 by flip-flops or capacitors. If data is held by flip-flops, a power supply potential is supplied to the memory cells in register 996. If data is held by capacitors, data is rewritten to the capacitors, and the supply of power supply voltage to the memory cells in register 996 may be stopped.

[0359] The memory array 920 and the computing device 960 may be arranged in an overlapping manner. Figure 24A and Figure 24B This is a perspective view of a semiconductor device 970A. The semiconductor device 970A includes a layer 930 on which a memory array is provided on a computing device 960. The layer 930 includes a memory array 920L1, a memory array 920L2, and a memory array 920L3. The computing device 960 and the memory arrays have overlapping areas. To facilitate understanding of the structure of the semiconductor device 970A, Figure 24B 9 and layer 930 are shown separately.

[0360] By overlapping the memory array layer 930 and the computing device 960, the distance between them can be shortened. This increases the communication speed between them. Furthermore, the shorter distance reduces power consumption.

[0361] Methods for stacking layer 930, including the memory array, and computing device 960 include: directly stacking layer 930, including the memory array, on computing device 960 (also known as monolithic stacking); or forming computing device 960 and layer 930 on separate substrates, laminating the two substrates, and connecting them using vias or conductive film bonding techniques (e.g., Cu-Cu bonding). The former method eliminates the need to consider misalignment during lamination, thus reducing both chip size and manufacturing costs.

[0362] Here, the memory arrays 920L1, 920L2, and 920L3 in layer 930, which do not include cache memory 999 in computing device 960, can all be used as cache memory. In this case, for example, memory array 920L1, memory array 920L2, and memory array 920L3 can be used as an L1 cache (also known as a first-level cache), an L2 cache (also known as a second-level cache), and an L3 cache (also known as a third-level cache), respectively. Of the three memory arrays, memory array 920L3 has the largest capacity and the lowest access frequency. Furthermore, memory array 920L1 has the smallest capacity and the highest access frequency.

[0363] Note that when the cache 999 provided in the computing device 960 is used as an L1 cache, each memory array provided in the layer 930 can be used as a lower-level cache or main memory. The main memory is a memory having a larger capacity and a lower access frequency than the cache.

[0364] In addition, if Figure 24B As shown, a driver circuit 910L1, a driver circuit 910L2, and a driver circuit 910L3 are provided. Driver circuit 910L1 is connected to memory array 920L1 via connection electrode 940L1. Similarly, driver circuit 910L2 is connected to memory array 920L2 via connection electrode 940L2, and driver circuit 910L3 is connected to memory array 920L3 via connection electrode 940L3.

[0365] Note that although the case where three memory arrays are used as cache memory is shown here, the number may be one, two, or four or more.

[0366] When the memory array 920L1 is used as a cache, the driver circuit 910L1 may also be used as part of the cache interface 989, and the driver circuit 910L1 may also be connected to the cache interface 989. Similarly, the driver circuits 910L2 and 910L3 may also be used as part of the cache interface 989 or may be connected to a part of the cache interface 989.

[0367] Whether the memory array 920 is used as a cache or a main memory depends on the control circuit 912 included in each driver circuit 910. The control circuit 912 can use some of the plurality of memory cells 950 included in the semiconductor device 900 as RAM based on a signal supplied from the arithmetic device 960.

[0368] In semiconductor device 900, some of the plurality of memory cells 950 can be used as cache memory and others as main memory. In other words, semiconductor device 900 can function both as cache memory and as main memory. Semiconductor device 900 according to one embodiment of the present invention can be used as a general-purpose memory, for example.

[0369] Alternatively, the layer 930 including one memory array 920 may be provided so as to overlap with the computing device 960 . Figure 25A It is a perspective view of the semiconductor device 970B.

[0370] In the semiconductor device 970B, one memory array 920 can be divided into a plurality of areas and used by assigning different functions to the areas. Figure 25A An example is shown in which the area L1, the area L2, and the area L3 are used as an L1 cache, an L2 cache, and an L3 cache, respectively.

[0371] Furthermore, in semiconductor device 970B, the capacity of each of regions L1 through L3 can be changed depending on the situation. For example, the capacity of the L1 cache can be increased by increasing the area of ​​region L1. This structure improves the efficiency of computational processing and increases processing speed.

[0372] Furthermore, a plurality of memory arrays may be stacked. Figure 25B It is a perspective view of a semiconductor device 970C.

[0373] Semiconductor device 970C is stacked with a layer 930L1 including memory array 920L1, a layer 930L2 above it including memory array 920L2, and a layer 930L3 above it including memory array 920L3. Memory array 920L1, which is physically closest to computing device 960, can be used as an upper-level cache, while memory array 920L3, which is farthest from computing device 960, can be used as a lower-level cache or main memory. This structure increases the capacity of each memory array, thereby further improving processing capabilities.

[0374] At least a part of the structural examples described in this embodiment mode and the drawings corresponding to the structural examples can be combined with other structural examples, drawings, etc. as appropriate.

[0375] Implementation 4

[0376] In this embodiment, an application example of a storage device according to one embodiment of the present invention will be described.

[0377] Generally speaking, various memory devices are used in semiconductor devices such as computers according to their applications. Figure 26A Various memory devices used in semiconductor devices are shown in a hierarchical manner. Memory devices in the upper layers are required to have faster operating speeds, while memory devices in the lower layers are required to have larger storage capacities and higher recording densities. Figure 26A In the example, from the top layer, it includes memories installed as registers in arithmetic processing units such as a CPU, L1 cache, L2 cache, L3 cache, main memory, storage, etc. Note that although the example includes up to L3 cache, lower-level caches may also be included.

[0378] Because registers, included with CPUs and other processing units, are used to temporarily store calculation results, they are frequently accessed by the processing units. Consequently, faster operating speeds are required over storage capacity. Registers also hold configuration information for the processing units.

[0379] Cache memory copies and stores a portion of the information stored in main memory. By copying frequently used data to the cache, data access speed can be increased. While cache memory requires less storage capacity than main memory, it requires a higher operating speed. Furthermore, data that has been overwritten in the cache memory is copied and made available to main memory.

[0380] The main memory has a function of holding programs, data, and the like read from storage.

[0381] Storage is used to store data that requires long-term preservation and various programs used by processing devices. Therefore, compared to faster operating speeds, storage requires larger storage capacity and higher recording density. For example, high-capacity non-volatile storage devices such as 3D NAND can be used.

[0382] Since the storage device according to one embodiment of the present invention includes a storage device with a large storage capacity and a storage device with a high operating speed, it can be applied to Figure 26A In both the layer where the storage is located and the layer where the main memory is located.

[0383] A memory device (OS memory) using an oxide semiconductor according to one embodiment of the present invention has a high operating speed and can retain data for a long period of time. Figure 26A As shown, the storage device according to one embodiment of the present invention can be used in both a hierarchy including a cache and a hierarchy including a main memory.

[0384] also, Figure 26B An example is shown in which an SRAM is used for a part of the cache and an OS memory according to one embodiment of the present invention is used for the other part.

[0385] The cache at the lowest level can be called an LLC (Last Level Cache). The LLC does not need to operate faster than the cache above it, but is required to have a larger storage capacity. The OS memory of one embodiment of the present invention has a fast operating speed and can retain data for a long time, making it suitable for use in the LLC. Note that the OS memory of one embodiment of the present invention can also be used in the FLC (Final Level Cache).

[0386] For example, Figure 26B As shown in FIG. 1 , SRAM can be used for upper level cache (L1 cache, L2 cache, etc.) and the OS memory of one embodiment of the present invention can be used for LLC. Figure 26B As shown, DRAM can be used in addition to the OS memory as the main memory.

[0387] At least a part of the structural examples described in this embodiment mode and the drawings corresponding to these examples can be combined with other structural examples, drawings, etc. as appropriate.

[0388] (Implementation 5)

[0389] In this embodiment, an application example of a storage device according to one embodiment of the present invention will be described.

[0390] The storage device of one embodiment of the present invention can be applied to storage devices in various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras, video playback devices, navigation systems, and game consoles). Furthermore, it can be used in image sensors, the Internet of Things (IoT), and medical applications. Here, computers include tablet computers, laptops, desktop computers, and mainframe computers such as server systems.

[0391] An example of an electronic device including a storage device according to one embodiment of the present invention will be described. Figures 27A to 27J and Figures 28A to 28E The case where the electronic component 700 having a storage device is included in each electronic device is shown.

[0392] [Mobile phone]

[0393] Figure 27A The illustrated information terminal 5500 is a mobile phone (smartphone) which is one type of information terminal. The information terminal 5500 includes a housing 5510 and a display portion 5511 . The display portion 5511 includes a touch panel as an input interface, and the housing 5510 is provided with buttons.

[0394] By applying the storage device of one embodiment of the present invention to the information terminal 5500 , it is possible to store documents temporarily generated when a program is executed (for example, a cache when a web browser is used).

[0395] [Wearable Terminal]

[0396] also, Figure 27B An example of a wearable terminal is shown as an information terminal 5900. The information terminal 5900 includes a housing 5901, a display portion 5902, an operation switch 5903, an operation switch 5904, a strap 5905, and the like.

[0397] Similar to the above-mentioned information terminal 5500 , by applying the storage device of one embodiment of the present invention to a wearable terminal, it is possible to store documents temporarily generated when executing application software.

[0398] [Information Terminal]

[0399] Figure 27C 1 and 2. The tabletop information terminal 5300 is shown. The tabletop information terminal 5300 includes an information terminal body 5301, a display portion 5302, and a keyboard 5303.

[0400] Similar to the above-described information terminal 5500 , by applying the storage device according to one embodiment of the present invention to the desktop information terminal 5300 , documents temporarily generated when executing application software can be stored.

[0401] Note that although Figures 27A to 27C While smartphones, wearable terminals, and desktop information terminals are shown as electronic devices, other information terminals include, for example, PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0402] [Electrical appliances]

[0403] Figure 27D An example of an electric appliance is shown as an electric refrigerator-freezer 5800. Electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, etc. For example, electric refrigerator-freezer 5800 supports the IoT (Internet of Things).

[0404] A storage device according to one embodiment of the present invention can be applied to an electric refrigerator-freezer 5800. For example, by utilizing the Internet, the electric refrigerator-freezer 5800 can transmit and receive information about food stored therein or the expiration date of such food to a data terminal or the like. The electric refrigerator-freezer 5800 can store, in the storage device according to one embodiment of the present invention, a document temporarily generated when transmitting this information.

[0405] exist Figure 27D In the description, an electric refrigerator-freezer is described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water dispensers, air conditioners including heating and cooling units, washing machines, clothes dryers, and audio-visual equipment.

[0406] [Game console]

[0407] also, Figure 27E A portable game machine 5200 as an example of a game machine is shown. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0408] also, Figure 27F The following is a stationary game machine 7500 as an example of a game machine. In particular, the stationary game machine 7500 can be said to be a home-use stationary game machine. The stationary game machine 7500 includes a main body 7520 and a controller 7522. The main body 7520 can be connected to the controller 7522 in a wireless manner or a wired manner. Figure 27F Although not shown in the figure, the controller 7522 may include a display unit for displaying game images, a touch panel and a joystick as input interfaces other than buttons, a rotary grip, a sliding grip, etc. In addition, the controller 7522 is not limited to Figure 27F The shape of controller 7522 can also be changed depending on the type of game. For example, in shooting games such as FPS (First Person Shooter), a trigger button can be used, and a controller shaped like a gun can be used. In music games, for example, controllers shaped like musical instruments can be used. Furthermore, stationary game consoles can also be equipped with one or more of a camera, depth sensor, microphone, etc., so that the player can operate the controller using gestures or voice instead of the controller.

[0409] Furthermore, the video images of the aforementioned game machines can be outputted by display devices such as televisions, personal computer monitors, game monitors, and head-mounted displays.

[0410] By using a storage device according to one embodiment of the present invention in the portable game console 5200 or the stationary game console 7500, power consumption can be reduced. Furthermore, the reduced power consumption reduces heat generated by the circuit, thereby reducing the negative effects of heat on the circuit itself, peripheral circuits, and modules.

[0411] Furthermore, by using the storage device of one embodiment of the present invention in the portable game machine 5200 or the stationary game machine 7500 , calculation files temporarily generated when a game is executed can be stored.

[0412] exist Figure 27E and Figure 27F In the description, portable game consoles and home-use stationary game consoles are shown as examples of game consoles, but other game consoles include arcade game consoles installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0413] [Mobile Object]

[0414] A storage device according to one embodiment of the present invention can be used in a vehicle as a mobile object and in the vicinity of a driver's seat of the vehicle.

[0415] Figure 27G A car 5700 is shown as an example of a moving object.

[0416] A dashboard that displays various information, such as a speedometer, tachometer, distance traveled, fuel level, gear status, and air-conditioning settings, is provided near the driver's seat of the automobile 5700. A display device that displays the above information may also be provided near the driver's seat.

[0417] In particular, by displaying images captured by a camera device (not shown) installed on the vehicle 5700 on the display device, it is possible to compensate for vision obstructed by pillars, blind spots around the driver's seat, and the like, thereby improving safety. In other words, by displaying images captured by a camera device installed outside the vehicle 5700, it is possible to supplement the field of view and avoid blind spots, thereby improving safety.

[0418] A storage device according to one embodiment of the present invention can temporarily store data. For example, this storage device can be used to temporarily store necessary data for autonomous driving systems, navigation systems, hazard prediction systems, and other systems in automobile 5700. Furthermore, a storage device according to one embodiment of the present invention can also store recordings from a drive recorder installed in automobile 5700.

[0419] Although the above examples illustrate automobiles as an example of a mobile object, mobile objects are not limited to automobiles. For example, trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (UAVs), airplanes, and rockets) may also be used as mobile objects.

[0420] [camera]

[0421] A storage device according to one embodiment of the present invention can be applied to a camera.

[0422] Figure 27H A digital camera 6240 is shown as an example of an imaging device. The digital camera 6240 includes a housing 6241, a display unit 6242, operation switches 6243, a shutter button 6244, and a detachable lens 6246. While the digital camera 6240 is configured so that the lens 6246 can be removed from the housing 6241, the lens 6246 and the housing 6241 may also be integrally formed. Furthermore, the digital camera 6240 may also include a separately mounted flash device and a viewfinder.

[0423] By using a storage device according to one embodiment of the present invention in a digital camera 6240, power consumption can be reduced. Furthermore, lower power consumption reduces heat generated by the circuit, thereby reducing negative effects of heat generation on the circuit itself, peripheral circuits, and modules.

[0424] [Video Camera]

[0425] A storage device according to one embodiment of the present invention can be applied to a video camera.

[0426] Figure 27I A video camera 6300, an example of an imaging device, is shown. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, operating switches 6304, a lens 6305, a connector 6306, and the like. The operating switches 6304 and the lens 6305 are provided on the first housing 6301, and the display unit 6303 is provided on the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connector 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connector 6306. The image on the display unit 6303 can also be switched according to the angle between the first housing 6301 and the second housing 6302 in the connector 6306.

[0427] When recording images captured by the video camera 6300, encoding is required according to a data recording method. By using a storage device according to one embodiment of the present invention, the video camera 6300 can store files temporarily generated during encoding.

[0428] [ICD]

[0429] A storage device according to one embodiment of the present invention can be applied to an implantable cardioverter-defibrillator (ICD).

[0430] Figure 27J 1 is a schematic cross-sectional view showing an example of an ICD. An ICD main body 5400 includes at least a battery 5401, electronic components 700, a regulator, a control circuit, an antenna 5404, a wire 5402 extending to the right atrium, and a wire 5403 extending to the right ventricle.

[0431] The ICD body 5400 is surgically placed in the body, and two metal wires pass through the subclavian vein 5405 and the superior vena cava 5406 of the human body, with the tip of one metal wire placed in the right ventricle and the tip of the other metal wire placed in the right atrium.

[0432] The ICD main body 5400 has the function of a pacemaker and performs pacing when the heart rhythm is outside a predetermined range. In addition, when the heart rhythm does not improve even with pacing (rapid ventricular rhythm or ventricular fibrillation, etc.), defibrillation treatment is performed.

[0433] To properly perform pacing and defibrillation, the ICD main unit 5400 must constantly monitor the heart rhythm. Therefore, the ICD main unit 5400 includes a sensor for detecting the heart rhythm. Furthermore, the ICD main unit 5400 can store data on the heart rhythm measured by the sensor, the number of pacing treatments performed, and the duration of treatment in the electronic component 700.

[0434] Furthermore, since power is received by antenna 5404 and charged to battery 5401, safety can be improved by including multiple batteries in ICD main body 5400. Specifically, even if some batteries in ICD main body 5400 fail, the remaining batteries can function as an auxiliary power source.

[0435] In addition, in addition to the antenna 5404 that can receive electricity, it can also include an antenna that can send physiological signals. For example, it can also constitute a system for monitoring cardiac activity that can confirm physiological signals such as pulse, respiratory rate, heart rhythm and body temperature by an external monitoring device.

[0436] [Expansion unit for PC]

[0437] A storage device according to one embodiment of the present invention can be applied to computers such as PCs (Personal Computers) and expansion devices for information terminals.

[0438] Figure 28AAn example of such an expansion device is shown as an expansion device 6100 that is portable and has a chip that can store data installed on the outside of a PC. The expansion device 6100 can be connected to the PC via a USB (Universal Serial Bus) and can use the chip to store data. Figure 28A A portable expansion device 6100 is shown, but the expansion device according to one embodiment of the present invention is not limited thereto. For example, a larger expansion device equipped with a cooling fan may also be used.

[0439] The expansion device 6100 includes a housing 6101, a cover 6102, a USB connector 6103, and a substrate 6104. The substrate 6104 is housed in the housing 6101. For example, the substrate 6104 is provided with circuitry for driving a storage device, etc., according to one embodiment of the present invention. For example, the substrate 6104 is mounted with the electronic component 700 and a controller chip 6106. The USB connector 6103 serves as an interface for connecting to external devices.

[0440] [SD card]

[0441] The storage device according to one embodiment of the present invention can be applied to an SD card that can be mounted on electronic devices such as information terminals and digital cameras.

[0442] Figure 28B This is a schematic diagram of the appearance of an SD card. Figure 28C Schematic diagram of the internal structure of an SD card. SD card 5110 includes a housing 5111, a connector 5112, and a substrate 5113. Connector 5112 functions as an interface for connecting to an external device. Substrate 5113 is housed in housing 5111. Substrate 5113 is provided with a storage device and a circuit that drives the storage device. For example, electronic component 700 and controller chip 5115 are mounted on substrate 5113. Furthermore, the circuit structures of electronic component 700 and controller chip 5115 are not limited to those described above, and the circuit structures may be appropriately modified depending on the circumstances. For example, the write circuit, row driver, read circuit, etc., included in the electronic component, may be mounted on controller chip 5115 instead of on electronic component 700.

[0443] By also providing the electronic component 700 on the back side of the substrate 5113, the capacity of the SD card 5110 can be increased. Furthermore, a wireless chip having a wireless communication function can be provided on the substrate 5113. This enables wireless communication between an external device and the SD card 5110, and data can be read from and written to the electronic component 700.

[0444] [SSD]

[0445] A storage device according to one embodiment of the present invention can be applied to an SSD (Solid State Drive) that can be mounted on electronic devices such as information terminals.

[0446] Figure 28D This is a schematic diagram of the appearance of SSD. Figure 28E This is a schematic diagram of the internal structure of an SSD. SSD 5150 includes a housing 5151, a connector 5152, and a substrate 5153. Connector 5152 functions as an interface for connecting to external devices. Substrate 5153 is housed in housing 5151. Substrate 5153 is provided with a storage device and circuitry that drives the storage device. For example, electronic components 700, memory chip 5155, and controller chip 5156 are mounted on substrate 5153. By also providing electronic components 700 on the back side of substrate 5153, the capacity of SSD 5150 can be increased. Memory chip 5155 includes working memory. For example, a DRAM chip can be used for memory chip 5155. Controller chip 5156 includes a processor, an ECC (Error-Correcting Code) circuit, and other components. Note that the circuit structures of electronic components 700, memory chip 5155, and controller chip 5155 are not limited to those described above and can be modified as appropriate. For example, a memory used as a working memory may also be provided in the controller chip 5156 .

[0447] [computer]

[0448] Figure 29A The computer 5600 shown is an example of a large-scale computer. In the computer 5600 , a plurality of rack-mounted computers 5620 are housed in a rack 5610 .

[0449] Computer 5620 may have, for example, Figure 29B The structure of the stereogram shown. Figure 29B In the embodiment, computer 5620 includes motherboard 5630, which includes multiple slots 5631 and multiple connection terminals. A personal computer card 5621 is inserted into slot 5631. Personal computer card 5621 includes connection terminals 5623, 5624, and 5625, which are connected to motherboard 5630.

[0450] Figure 29C The illustrated personal computer card 5621 is an example of a processing board including a CPU, a GPU, a storage device, etc. The personal computer card 5621 includes a board 5622. In addition, the board 5622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Figure 29C Semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 are shown. For description of these semiconductor devices, refer to the description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 described below.

[0451] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630 and is used as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of the standard of the connection terminal 5629 include PCIe.

[0452] The connection terminals 5623, 5624, and 5625 can be used, for example, as interfaces for supplying power to the PC card 5621 or inputting signals. Furthermore, for example, they can be used as interfaces for outputting signals calculated by the PC card 5621. Examples of the standards for the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when outputting video signals from the connection terminals 5623, 5624, and 5625, examples of the standards include HDMI (registered trademark).

[0453] The semiconductor device 5626 includes terminals (not shown) for inputting and outputting signals. By inserting the terminals into sockets (not shown) included in the board 5622 , the semiconductor device 5626 and the board 5622 can be electrically connected.

[0454] The semiconductor device 5627 includes a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, reflow soldering the terminals to wiring included in the board 5622. Examples of the semiconductor device 5627 include an FPGA (Field Programmable Gate Array), a GPU, and a CPU.

[0455] The semiconductor device 5628 includes a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by soldering the terminals to wiring provided on the board 5622 using reflow soldering. A memory device can be used as the semiconductor device 5628, for example. The electronic component 700 can be used as the semiconductor device 5628, for example.

[0456] The computer 5600 can be used as a parallel computer. By using the computer 5600 as a parallel computer, for example, large-scale calculations required for learning and inference of artificial intelligence can be performed.

[0457] By using a storage device according to one embodiment of the present invention in the various electronic devices described above, miniaturization and low power consumption of the electronic devices can be achieved. Furthermore, the storage device according to one embodiment of the present invention consumes less power, thereby reducing circuit heat generation. This reduces the negative impact of this heat generation on the circuit itself, peripheral circuits, and modules. Furthermore, by using a storage device according to one embodiment of the present invention, electronic devices that can operate stably even in high-temperature environments can be realized. This improves the reliability of the electronic devices.

[0458] At least a part of the structural examples described in this embodiment mode and the drawings corresponding to the structural examples can be combined with other structural examples, drawings, etc. as appropriate.

[0459] (Implementation 6)

[0460] In this embodiment, the Figure 30 A specific example of a case where a semiconductor device according to one embodiment of the present invention is applied to space equipment will be described.

[0461] A semiconductor device according to one embodiment of the present invention includes an OS transistor. OS transistors exhibit minimal fluctuations in their electrical characteristics due to exposure to radiation. In other words, they have high resistance to radiation and can be suitably used in environments where radiation is likely to enter. For example, OS transistors can be suitably used in space.

[0462] exist Figure 30 , an artificial satellite 6800 is shown as an example of a space device. The artificial satellite 6800 includes a main body 6801, a solar cell panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Figure 30 An example of a planet 6804 in outer space is shown. Note that outer space refers to an altitude of 100 km or higher, for example, but the outer space described in this specification may also include one or more of the thermosphere, mesosphere, and stratosphere.

[0463] Furthermore, outer space is an environment with a radiation dose over 100 times greater than that on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation), such as X-rays and gamma rays, and particle radiation, such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and muon rays.

[0464] When sunlight hits the solar panels 6802, they generate the electricity required for the operation of the satellite 6800. However, if sunlight does not reach the solar panels, or if the amount of sunlight hitting the solar panels is low, the amount of electricity generated decreases. Consequently, there is a possibility that the required electricity for the operation of the satellite 6800 may not be generated. To enable the satellite 6800 to operate even when the generated electricity is low, a secondary battery 6805 is preferably provided in the satellite 6800. Solar panels are sometimes referred to as solar cell modules.

[0465] Satellite 6800 can generate a signal. This signal is transmitted via antenna 6803 and can be received by a receiver on the ground or another satellite. By receiving the signal transmitted by satellite 6800, the position of the receiver receiving the signal can be measured. Thus, satellite 6800 can form a satellite positioning system.

[0466] Furthermore, control device 6807 has the function of controlling artificial satellite 6800. Control device 6807 is configured using, for example, one or more of a CPU, a GPU, and a storage device. Furthermore, a semiconductor device including an OS transistor, which is one embodiment of the present invention, is preferably used as control device 6807. Compared to Si transistors, OS transistors exhibit less variation in electrical characteristics due to exposure to radiation. In other words, OS transistors are highly reliable and can be suitably used even in environments where radiation is likely to be incident.

[0467] Furthermore, artificial satellite 6800 may include sensors. For example, by including a visible light sensor, artificial satellite 6800 may be capable of detecting sunlight reflected from objects on the ground. Alternatively, by including a thermal infrared sensor, artificial satellite 6800 may be capable of detecting thermal infrared radiation emitted from the Earth's surface. Thus, artificial satellite 6800 may be used, for example, as an Earth observation satellite.

[0468] Note that although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, a semiconductor device according to one embodiment of the present invention can be suitably applied to space equipment such as a spacecraft, a space capsule, and a space probe.

[0469] At least a part of the structural examples described in this embodiment mode and the drawings corresponding to the structural examples can be combined with other structural examples, drawings, etc. as appropriate.

[0470] [Explanation of symbols]

[0471] 10: Semiconductor device, 11: Layer, 12: Layer, 13: Layer, 21: Memory device, 22: Terminal portion, 23: Plug, 31: Memory device, 32: Connecting portion, 33: Plug, 42: Drive circuit, 43: Drive circuit, 45: Wiring, 50: Insulating layer, 51: Conductive layer, 52: Conductive layer, 53: Conductive layer, 54: Conductive layer, 55: Conductive layer, 56: Plug, 57: Conductive layer, 60: Memory string, 65: Memory cell, 71: Curve, 72: Curve, 100A: Memory string, 100: Memory string, 101: Conductive layer, 102_1: Insulating layer, 102_m: Insulating layer, 102: Insulating layer, 103_ 1: Conductive layer, 103_n: Conductive layer, 103: Conductive layer, 104: Conductive layer, 105: Insulating layer, 106: Conductive layer, 110: Structure, 111: Insulating layer, 112: Semiconductor layer, 118: Functional layer, 120: Central axis, 121: Insulating layer, 122: Insulating layer, 125: Conductive layer, 126: Conductive layer, 127: Conductive layer, 131: Insulating layer, 132: Insulating layer, 133: Insulating layer, 141: Transistor, 142: Transistor, 143: Transistor, 200: Transistor, 201: Semiconductor layer, 202: Conductive layer, 203: Insulating layer, 204: Conductive layer, 205: Conductive layer, 210: Insulating layer, 212: Insulating layer, 214: Insulating layer, 216: Insulating layer, 218: Conductive layer, 220: Insulating layer, 222: Insulating layer, 224: Insulating layer, 234: Insulating layer, 236: Conductive layer, 238: Conductive layer, 240: Insulating layer, 241: Insulating layer, 242: Insulating layer, 244: Insulating layer, 246: Insulating layer, 248: Insulating layer, 250: Capacitor, 251: Conductive layer, 252: Conductive layer, 253: Insulating layer, 254: Conductive layer, 300: Transistor, 311: Substrate, 313: Semiconductor region, 314a: Low resistance region, 314b: Low resistance region, 315: Insulating layer, 316 : Conductive layer, 320: Insulating layer, 322: Insulating layer, 324: Insulating layer, 326: Insulating layer, 328: Conductive layer, 330: Conductive layer, 350: Insulating layer, 384: Insulating layer, 386: Conductive layer, 400a: Transistor, 400b: Transistor, 400: Transistor, 401: Semiconductor layer, 402: Conductive layer, 403: Insulating layer, 404: Conductive layer, 405: Conductive layer, 406: Conductive layer, 407: Conductive layer, 410: Insulating layer, 412: Insulating layer, 414: Insulating layer, 416: Insulating layer, 418: Insulating layer, 420: Capacitor, 421: Conductive layer, 422: Conductive layer, 423: Insulating layer

Claims

1. A semiconductor device comprising: First floor; Second floor; as well as The third floor, wherein the first layer includes a first storage device comprising a plurality of nonvolatile first storage elements stacked in a thickness direction of the first layer, The second layer includes a second storage device having a plurality of second storage elements, The second memory element includes a transistor including an oxide semiconductor, The third layer includes a first driving circuit for controlling the operation of the first storage device and a second driving circuit for controlling the operation of the second storage device. Furthermore, the first layer and the second layer, the second layer and the third layer, and the first layer and the third layer respectively have overlapping portions.

2. The semiconductor device according to claim 1, wherein the first layer is located on the third layer, And the second layer is located on the third layer.

3. The semiconductor device according to claim 1, The third layer is located between the first layer and the second layer.

4. The semiconductor device according to claim 1, The first storage element includes a first conductive layer, a first semiconductor layer and a functional layer located therebetween. And the functional layer includes a thin film exhibiting ferroelectricity.

5. The semiconductor device according to claim 1, The first storage element includes a first conductive layer, a first semiconductor layer and a functional layer located therebetween. And the functional layer contains at least one of hafnium and zirconium.

6. The semiconductor device according to claim 5, The functional layer further comprises scandium, yttrium and one or more lanthanide elements.

7. The semiconductor device according to claim 1, wherein the transistor comprises a gate insulating layer, Furthermore, the gate insulating layer includes a thin film exhibiting ferroelectricity.

8. The semiconductor device according to claim 1, wherein the second layer comprises an insulating layer, The transistor includes a source electrode, a drain electrode and a second semiconductor layer, The source electrode and the drain electrode are respectively in contact with the second semiconductor layer, One of the source electrode and the drain electrode is located above the insulating layer, And the other of the source electrode and the drain electrode is located below the insulating layer.

Images