Capacitor device and electronic apparatus

Abstract

The invention provides a capacitor device and electronic equipment, and relates to the technical field of passive devices. The capacitor device comprises a substrate, a capacitor and a first electrode layer, the substrate is provided with a first side and a second side which are opposite in the thickness direction of the substrate, the capacitor comprises a first pole plate, a dielectric layer and a second pole plate which are arranged on the second side in a stacked mode, the first electrode layer is arranged on the first side and electrically connected with the first pole plate, and the second electrode layer is electrically connected with the dielectric layer. The first electrode layer is used for being connected with an external circuit in a welded mode. And the connection between the capacitor device and the printed circuit board is firmer. And the connection between the capacitor device and the printed circuit board is firmer.

Description

Capacitor devices and electronic devices Technical Field

[0001] The present disclosure relates to the technical field of passive devices, and in particular to a capacitor device and an electronic device. Background Art

[0002] Capacitors, as a type of passive device, can be used in circuits for circuit matching, filtering, coupling, charge storage, and more. Integrated Passive Device (IPD) technology utilizes semiconductor processes to manufacture passive devices. Capacitors fabricated using IPD technology exhibit high dimensional accuracy, integration, and miniaturization.

[0003] However, the connection between the capacitor device manufactured using the integrated passive device technology in the related art and the printed circuit board (PCB) is not firm.

[0004] Summary of the Invention

[0005] Embodiments of the present disclosure provide a capacitor device and an electronic device, wherein the capacitor device is more firmly connected to a printed circuit board.

[0006] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0007] In one aspect, a capacitive device is provided, comprising:

[0008] The substrate has a first side and a second side opposite to each other along its thickness direction;

[0009] A capacitor comprising a first plate, a dielectric layer, and a second plate stacked on the second side;

[0010] The first electrode layer is arranged on the first side and is electrically connected to the first electrode plate. The first electrode layer is used for welding connection with an external circuit.

[0011] In some embodiments, the capacitive device further includes a conductive column extending through the substrate along a thickness direction of the substrate, one end of the conductive column being electrically connected to the first electrode layer, and the other end of the conductive column being electrically connected to the first electrode plate.

[0012] In some embodiments, the capacitive device includes a plurality of conductive pillars, and the plurality of conductive pillars are arranged at intervals.

[0013] In some embodiments, the conductive pillars are disposed adjacent to an edge of the substrate.

[0014] In some embodiments, the plurality of conductive pillars are arranged in a ring shape.

[0015] In some embodiments, the plurality of conductive pillars are arranged in a planar array.

[0016] In some embodiments, a support column is provided in the conductive column, and one end of the support column facing the first electrode plate supports the first electrode plate; or, the conductive column is a solid columnar structure made of a conductive material.

[0017] In some embodiments, the support pillars include an organic material.

[0018] In some embodiments, the second plate is further away from the substrate than the first plate.

[0019] In some embodiments, the capacitor device further includes a second electrode layer and an insulating layer, the second electrode layer is located on a side of the second electrode plate away from the substrate, the insulating layer is located between the second electrode layer and the second electrode plate, the second electrode layer is electrically connected to the second electrode plate, and the second electrode layer is used for welding connection to an external circuit.

[0020] In some embodiments, the insulating layer is provided with a second via hole, and the second electrode layer is electrically connected to the second electrode plate through the second via hole.

[0021] In some embodiments, an edge of the insulating layer extends toward the substrate and covers edges of the first electrode plate, the dielectric layer, and the second electrode plate.

[0022] In some embodiments, the insulating layer includes an organic material.

[0023] In some embodiments, the second electrode plate is used for welding connection to an external circuit.

[0024] In some embodiments, the first electrode plate includes a plurality of first sub-plates, the second electrode plate includes a plurality of second sub-plates, the first sub-plates and the second sub-plates are alternately arranged, two adjacent first sub-plates are electrically connected, and two adjacent second sub-plates are electrically connected.

[0025] In some embodiments, the orthographic projection of the first electrode plate and / or the second electrode plate on the substrate is a polygon, a circle, an ellipse, or an irregular shape.

[0026] In another aspect, a capacitive device is provided, comprising:

[0027] The substrate has a first side and a second side opposite to each other along its thickness direction;

[0028] A capacitor comprising a first plate, a dielectric layer, and a second plate stacked on the second side;

[0029] A first electrode layer is provided on the first side and electrically connected to the first electrode plate. An anti-oxidation layer made of a conductive material is provided on a side of the first electrode layer away from the substrate.

[0030] On the other hand, an electronic device is provided, comprising the capacitive device.

[0031] In some embodiments, the electronic device further includes a printed circuit board, a chip, and a bonding wire, the capacitor device and the chip are arranged on the same side of the printed circuit board, a solder pad is provided on the surface of the printed circuit board, the first electrode layer of the capacitor device is soldered to the solder pad, one end of the bonding wire is connected to the chip, and the other end of the bonding wire is connected to the capacitor device.

[0032] In some embodiments, the second electrode plate of the capacitor device is farther away from the substrate than the first electrode plate, and the capacitor device further includes a second electrode layer and an insulating layer, the second electrode layer is located on the side of the second electrode plate away from the substrate, the insulating layer is located between the second electrode layer and the second electrode plate, the second electrode layer is electrically connected to the second electrode plate, and the other end of the bonding wire is connected to the second electrode layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0034] FIG1 is a perspective schematic diagram of a capacitor device provided by an embodiment of the present disclosure;

[0035] FIG2 is a cross-sectional view of a capacitor device provided by an embodiment of the present disclosure;

[0036] FIG3 is a schematic diagram of several possible shapes of the first electrode plate in an embodiment of the present disclosure;

[0037] FIG4 is a schematic diagram of a connection between a capacitor device and a printed circuit board in the related art;

[0038] FIG5 is a schematic diagram of a connection between a capacitor device and a printed circuit board provided by an embodiment of the present disclosure;

[0039] FIG6 is a cross-sectional view of another capacitor device provided in an embodiment of the present disclosure;

[0040] FIG7 is a cross-sectional view of another capacitor device provided in an embodiment of the present disclosure;

[0041] 8 and 9 are schematic diagrams showing the locations of the conductive pillars on the substrate according to an embodiment of the present disclosure;

[0042] FIG10 is a cross-sectional view of another capacitor device provided in an embodiment of the present disclosure;

[0043] 11 to 14 are schematic diagrams showing the locations of a plurality of conductive pillars on a substrate according to an embodiment of the present disclosure;

[0044] FIG15 is a cross-sectional view of another capacitor device provided in an embodiment of the present disclosure;

[0045] FIG16 is a cross-sectional view of another capacitor device provided in an embodiment of the present disclosure;

[0046] FIG17 is a cross-sectional view of another capacitor device provided in an embodiment of the present disclosure;

[0047] FIG18 is a schematic diagram of a partial structure of an electronic device in the related art;

[0048] FIG19 is a schematic diagram of a partial structure of an electronic device provided by an embodiment of the present disclosure;

[0049] FIG20 is a schematic diagram of a partial structure of another electronic device provided by an embodiment of the present disclosure;

[0050] FIG21 is a partial structural diagram of another electronic device provided by an embodiment of the present disclosure;

[0051] 22( a ) to 22 ( k ) are flow charts of a process for preparing the capacitor device shown in FIG. 17 ;

[0052] 23( a ) to 23 ( j ) are flow charts of another process for preparing the capacitor device shown in FIG. 17 .

[0053] Figure numerals: 10-capacitor device; 20-printed circuit board; 30-chip; 40-bonding wire; 50-solder; 1-substrate; 2-capacitor; 3-first electrode layer; 4-second electrode layer; 5-conductive column; 6-insulating layer; 7-support column; 11-blind hole; 12-first via hole; 21-first electrode plate; 22-second electrode plate; 23-dielectric layer; 31-anti-oxidation layer; 51-seed layer; 61-second via hole; 111-first hollow area; 121-second hollow area; 211-first sub-plate; 212-first connecting portion; 221-second sub-plate; 222-second connecting portion. Specific embodiments

[0054] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0055] In the embodiments of the present disclosure, words such as "first", "second", "third", and "fourth" are used to distinguish between identical or similar items with substantially the same functions and effects. This is only for the purpose of clearly describing the technical solutions of the embodiments of the present disclosure, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0056] In the embodiments of the present disclosure, “a plurality of” means two or more, and “at least one” means one or more, unless otherwise clearly and specifically defined.

[0057] In the embodiments of the present disclosure, the orientations or positional relationships indicated by terms such as “upper” and “lower” are based on the orientations or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present disclosure and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present disclosure.

[0058] Passive components are electronic components that don't contain electrons and can't amplify or regulate current or signals. They only perform passive functions within basic circuit structures, such as transmitting and distributing electrical energy. Common passive components include capacitors, inductors, and resistors.

[0059] Among the existing capacitor devices, the most widely used is the multilayer ceramic capacitor device (Multilayer Ceramic Capacitor, referred to as MLCC). Multilayer ceramic capacitor devices are made by alternately superimposing the inner electrode material and the ceramic embryo in multiple layers in parallel and co-firing them into a whole. The ceramic embryo acts as a capacitor dielectric layer, and the terminal electrodes on both sides of the device form a capacitor device. Since the electrodes are at both ends of the capacitor device, they are mainly connected to the printed circuit board by welding, and the space occupied by the capacitor device after welding is relatively large. In addition, due to the limitations of ceramic technology, the dimensional accuracy of the dielectric layer is poor, especially the thickness accuracy of the dielectric layer is poor, resulting in poor uniformity of the capacitance values ​​of different capacitor devices. Multilayer ceramic capacitor devices are mainly manufactured by low temperature co-fired ceramic (Low Temperature Co-fired Ceramic, referred to as LTCC) technology, which can only prepare capacitor devices of specific package sizes and can only prepare capacitor devices of specific capacitance values, making it difficult to meet the needs of capacitor devices of different sizes and capacitance values.

[0060] With the development of technologies such as 5G and optical communications, the demand for capacitors of varying sizes and capacitance values ​​is increasing. To address this issue, a capacitor device fabricated using integrated passive device technology has been proposed. The resulting capacitor device exhibits high dimensional accuracy, integration, and miniaturization.

[0061] The capacitive device and electronic device provided by the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings Figures 1 to 25.

[0062] FIG1 is a schematic three-dimensional diagram of a capacitor device provided by an embodiment of the present disclosure, and FIG2 is a cross-sectional diagram of a capacitor device provided by an embodiment of the present disclosure. For example, FIG2 is a cross-sectional diagram along line AA in FIG1 .

[0063] As shown in FIG. 1 and FIG. 2 , an embodiment of the present disclosure provides a capacitive device 10 including a substrate 1 and a capacitor 2 disposed on the substrate 1 .

[0064] Substrate 1 serves as the framework of capacitor device 10, supporting and connecting the other film structures of capacitor device 10. Along the thickness direction of substrate 1 (Y direction shown in Figure 2), substrate 1 has a first side S1 and a second side S2 opposite to each other, and capacitor 2 is disposed on the second side S2 of substrate 1.

[0065] In practical applications, to improve the deformation resistance of capacitor device 10, substrate 1 can be a rigid substrate 1, such as a glass substrate, a silicon substrate, or a ceramic substrate. When substrate 1 is a glass substrate, capacitor device 10 can be manufactured using a glass-based semiconductor process; when substrate 1 is a silicon substrate, capacitor device 10 can be manufactured using a silicon-based semiconductor process. Compared to existing multilayer ceramic capacitor device 10 manufacturing processes, the use of glass-based semiconductor processes or silicon-based semiconductor processes to manufacture capacitor device 10 can improve the dimensional accuracy of capacitor device 10.

[0066] Of course, the substrate 1 may also be a flexible substrate, such as a polyethylene terephthalate (PET) substrate, a polyethylene naphthalate diformic acid glycol ester (PEN) substrate, or a polyimide (PI) substrate.

[0067] Exemplarily, the thickness of the substrate 1 is 0.1 mm to 2 mm, for example, the thickness of the substrate 1 is any value among 0.1 mm, 0.2 mm, 0.5 mm, 0.8 mm, 1 mm, 1.2 mm, 1.5 mm, 1.8 mm, 2 mm, or a value in a range consisting of any two values.

[0068] It should be noted that, for the sake of convenience, this disclosure only uses the example of a capacitor device 10 having a rectangular parallelepiped structure. In actual applications, the shape of the capacitor device 10 is not limited to this, and the capacitor device 10 can also have a cube structure, a cylindrical structure, an elliptical cylinder structure, a polygonal prism structure, or other irregular shapes.

[0069] Continuing with Figure 2 , capacitor 2 includes a stacked first plate 21, a dielectric layer 23, and a second plate 22. The first plate 21 and the second plate 22 are positioned facing each other, with the dielectric layer 23 positioned between the first plate 21 and the second plate 22 to separate them.

[0070] The material of the first electrode plate 21 and the second electrode plate 22 is a conductor. For example, the first electrode plate 21 and the second electrode plate 22 are made of a metal material, such as silver, copper, aluminum, molybdenum, etc. The materials of the first electrode plate 21 and the second electrode plate 22 can be the same or different.

[0071] The dielectric layer 23 is made of an insulator. For example, the dielectric layer 23 is made of an inorganic material, such as silicon oxide, silicon nitride, ceramic, etc.

[0072] Exemplarily, the thickness of the first electrode plate 21 is 0.1 μm to 10 μm, for example, the thickness of the first electrode plate 21 is any value among 0.1 μm, 0.5 μm, 0.8 μm, 1 μm, 2 μm, 5 μm, 8 μm, and 10 μm, or a value in a range consisting of any two values; the thickness of the second electrode plate 22 is 0.4 μm to 10 μm, for example, the thickness of the second electrode plate 22 is any value among 0.4 μm, 0.5 μm, 0.8 μm, 1 μm, 2 μm, 5 μm, 8 μm, and 10 μm, or a value in a range consisting of any two values; the thickness of the dielectric layer 23 is 0.05 μm to 5 μm, for example, the thickness of the dielectric layer 23 is any value among 0.05 μm, 0.1 μm, 0.5 μm, 0.8 μm, 1 μm, 2 μm, and 5 μm, or a value in a range consisting of any two values.

[0073] For example, the capacitor 2 is directly connected to the second side S2 of the substrate 1, for example, the first electrode 21 is directly connected to the substrate 1. This can reduce the number of film layers of the capacitor device 10, thereby reducing the complexity of the manufacturing process and the volume of the capacitor device 10.

[0074] Of course, other film layers may be provided between the capacitor 2 and the substrate 1. For example, a buffer layer may be provided between the capacitor 2 and the substrate 1 to connect the substrate 1 and the capacitor 2 and to improve the connection stress when the capacitor 2 and the substrate 1 are directly connected.

[0075] Figure 3 is a schematic diagram of several possible shapes for the first electrode plate in the embodiment of the present disclosure. The shape shown in Figure 3 is the orthographic projection of the first electrode plate 21 on the substrate 1. As shown in Figures (a) to (f) in Figure 3, the shape of the first electrode plate 21 can be square, rectangular, circular, elliptical, hexagonal, irregular, etc. In addition to the shapes shown in Figure 3, the first electrode plate 21 can also have other shapes, which are not listed here.

[0076] Exemplarily, the shape of the first electrode plate 21 is adapted to the shape of the substrate 1. For example, when the substrate 1 is rectangular, the shape of the first electrode plate 21 is also rectangular; when the substrate 1 is circular, the shape of the first electrode plate 21 is also circular.

[0077] The shape of the second electrode plate 22 can be the same as or different from that of the first electrode plate 21 , as long as there is a facing area between the first electrode plate 21 and the second electrode plate 22 .

[0078] Compared with existing multilayer ceramic capacitor devices, the capacitor device 10 in the embodiment of the present disclosure can be prepared by semiconductor technology, so first electrodes 21 and second electrodes 22 of various shapes can be prepared by graphic technology, meeting the use requirements of capacitor devices 10 of different sizes and different capacitance values.

[0079] Of the first electrode plate 21 and the second electrode plate 22 , the first electrode plate 21 may be closer to the substrate 1 , or the second electrode plate 22 may be closer to the substrate 1 . The drawings in this specification only take the example of the first electrode plate 21 being closer to the substrate 1 for illustration.

[0080] Continuing with FIG. 2 , in actual applications, the capacitor device 10 may further include an insulating layer 6 , which covers the edges of the capacitor 2 to prevent moisture and the like from entering the interior of the capacitor 2 through the edges, thereby preventing corrosion of the capacitor 2. The insulating layer 6 may be made of a photosensitive organic material, such as polyimide or photoresist, or an inorganic insulating material, such as silicon oxide or silicon nitride.

[0081] Exemplarily, the edge of the first electrode plate 21 is retracted a certain distance relative to the edge of the substrate 1 , so that after the insulating layer 6 covers the edge of the first electrode plate 21 , the outer edge of the insulating layer 6 is flush with the outer edge of the substrate 1 .

[0082] Fig. 4 is a schematic diagram of the connection between a capacitor device and a printed circuit board in the related art. As shown in Figure 4, the capacitor device in the related art includes a substrate and a lower plate, a dielectric, and an upper plate stacked on the substrate. A connecting post is provided in the substrate, and the upper end of the connecting post is electrically connected to the lower plate. When the capacitor device in the related art is connected to a carrier (such as a printed circuit board), the lower end of the connecting post is welded to the printed circuit board by a solder ball. However, due to the small cross-sectional area of ​​the connecting post, the connection area between the lower end of the connecting post and the printed circuit board is small, resulting in a loose connection between the capacitor device and the printed circuit board 20.

[0083] In view of this, the capacitive device 10 provided in the embodiment of the present disclosure further includes a first electrode layer 3. The first electrode layer 3 is provided on the first side S1 of the substrate 1 and is electrically connected to the first electrode plate 21 for welding connection with an external circuit.

[0084] 2 , the first electrode layer 3 is directly connected to the first side S1 of the substrate 1. This can reduce the number of film layers of the capacitor device 10, thereby reducing the complexity of the manufacturing process and the volume of the capacitor device 10.

[0085] Of course, other film layers may also be provided between the first electrode layer 3 and the substrate 1. For example, a buffer layer may be provided between the first electrode layer 3 and the substrate 1. The buffer layer is used to connect the substrate 1 and the first electrode layer 3 to improve the connection stress when the first electrode layer 3 and the substrate 1 are directly connected.

[0086] Figure 5 is a schematic diagram illustrating the connection between a capacitor device and a printed circuit board according to an embodiment of the present disclosure. As shown in Figure 5, the capacitor device 10 according to an embodiment of the present disclosure is connected to the carrier via the first electrode layer 3. Specifically, when the capacitor device 10 is connected to the carrier, the first electrode layer 3 faces the carrier, and a solder layer is provided between the first electrode layer 3 and the carrier. The solder layer solders the first electrode layer 3 to the carrier, thereby securing the capacitor device 10 to the carrier.

[0087] Illustratively, the carrier is a printed circuit board 20, and a metal pad is provided on the side of the printed circuit board 20 facing the capacitor device 10. The solder layer is a solder layer, and the solder layer connects the metal pad and the first electrode layer 3. For example, the capacitor device 10 is soldered to the surface of the printed circuit board 20 in the form of a patch.

[0088] The capacitor device in the related art is connected to the printed circuit board by welding via a connecting column. The degree of connection strength between the capacitor device and the printed circuit board depends on the connection area between the connecting column and the printed circuit board, that is, the cross-sectional area of ​​the connecting column (the cross-sectional area in the horizontal direction shown in Figure 4). The capacitor device 10 provided in the embodiment of the present disclosure is connected to the printed circuit board 20 by welding via the first electrode layer 3. The degree of connection strength between the capacitor device 10 and the printed circuit board 20 depends on the connection area between the first electrode layer 3 and the printed circuit board 20, that is, the cross-sectional area of ​​the first electrode layer 3 (the cross-sectional area in the horizontal direction shown in Figure 5).

[0089] When the size of the capacitor device 10 is constant, the area of ​​the first electrode layer 3 is larger than the cross-sectional area of ​​the connecting column, that is, the connection area between the capacitor device 10 provided in the embodiment of the present disclosure and the printed circuit board 20 is larger than the connection area between the capacitor device and the printed circuit board in the related art, thereby making the connection between the capacitor device 10 provided in the embodiment of the present disclosure and the printed circuit board 20 more secure.

[0090] The area of ​​the first electrode layer 3 can be flexibly set according to actual needs, as long as the area of ​​the first electrode layer 3 is larger than the cross-sectional area of ​​the connecting pillar in the related art. The larger the area of ​​the first electrode layer 3, the larger the area for welding the capacitor device 10 to the carrier, and the more secure the connection between the capacitor device 10 and the carrier.

[0091] For example, the first electrode layer 3 completely covers the surface of the first side S1 of the substrate 1, so that the area of ​​the first electrode layer 3 is larger, thereby increasing the connection area between the capacitive device 10 and the carrier. Of course, as shown in FIG2 , the edge of the first electrode layer 3 can also be retracted a certain distance relative to the edge of the substrate 1.

[0092] It should be noted that, in the printed circuit board 20 used to connect the capacitive device 10 provided in the embodiment of the present disclosure, the area of ​​the pad can also be set larger corresponding to the first electrode layer 3, thereby increasing the soldering area between the capacitive device 10 and the printed circuit board 20. For example, the area of ​​the pad can be greater than, equal to, or less than that of the first electrode layer 3, as long as the connection area between the first electrode layer 3 and the pad is greater than the connection area between the connecting column and the pad.

[0093] Exemplarily, the area of ​​the pad is larger than that of the first electrode layer 3 , thereby reducing the mounting accuracy of the capacitor 10 and preventing the reduction of the welding area between the first electrode layer 3 and the pad due to the mounting position error of the capacitor 10 .

[0094] Figures 4 and 5 illustrate the connection between the capacitor device 10 and the printed circuit board 20. However, in practice, the application of the capacitor device 10 is not limited to this. The capacitor device 10 can also be connected to other devices. For example, the capacitor device 10 can be electrically connected to other passive devices such as resistors and inductors, or directly connected to the chip 30, etc., which are not listed here.

[0095] The orthographic projection shape of the first electrode layer 3 on the substrate 1 can be a polygon such as a rectangle or square, or a circle, an ellipse, or other irregular shapes. The embodiment of the present disclosure does not limit the orthographic projection shape of the first electrode layer 3 on the substrate 1.

[0096] The first electrode layer 3 can be made of metal materials such as copper, silver, aluminum, and molybdenum.

[0097] For example, the thickness of the first electrode layer 3 may be 1 μm to 10 μm. For example, the thickness of the first electrode layer 3 may be any value among 1 μm, 2 μm, 3 μm, 5 μm, 6 μm, 8 μm, 10 μm, or a value in a range consisting of any two values.

[0098] When the first electrode layer 3 is made of a metal material with relatively active chemical properties, the surface of the first electrode layer 3 away from the substrate 1 is easily oxidized by oxygen in the air, forming an oxide layer, which reduces the conductivity of the first electrode layer 3 and reduces the connection performance between the first electrode layer 3 and the welding layer.

[0099] Figure 6 is a cross-sectional view of another capacitor device provided in an embodiment of the present disclosure. For example, Figure 6 is a cross-sectional view of AA in Figure 1. In view of this, as shown in Figure 6, an anti-oxidation layer 31 made of a conductive material can be provided on the side of the first electrode layer 3 away from the substrate 1. The anti-oxidation layer 31 can be made of a chemically inactive metal material (such as nickel, gold, tin, etc.) that is not easily oxidized when exposed to air. The anti-oxidation layer 31 is arranged on the surface of the first electrode layer 3 away from the substrate 1, which can isolate the oxygen in the air, thereby preventing the first electrode layer 3 from being oxidized.

[0100] Exemplarily, the materials of the anti-oxidation layer 31 include nickel and gold. For example, the anti-oxidation layer 31 is prepared by an immersion gold process, which is an electrochemical gold plating technology. The immersion gold process can deposit a nickel-gold plating with stable color, good brightness, smooth coating, and good solderability on the surface of the first electrode layer 3. The immersion gold process can basically be divided into four stages: pre-treatment (degreasing, micro-etching, activation, and post-immersion), nickel immersion, gold immersion, and post-treatment (waste gold washing, DI water washing, and drying). The thickness of the anti-oxidation layer 31 formed by the immersion gold process can be between 0.025μm and 0.1um. The anti-oxidation layer 31 of nickel-gold material can effectively prevent oxidation and corrosion, thereby improving the reliability and durability of the circuit. In addition, the anti-oxidation layer 31 formed by the immersion gold process can also improve the welding performance, making the welding more firm and reliable.

[0101] Exemplarily, the material of the anti-oxidation layer 31 includes tin. For example, the anti-oxidation layer 31 is formed by a tin spraying process, also known as hot air leveling. First, molten tin is applied to the surface of the first electrode layer 3. Then, heated compressed air is used to blow the molten solder flat. The molten solder is evenly adhered to the surface of the first electrode layer 3 away from the substrate 1, forming the anti-oxidation layer 31.

[0102] Of course, the material and preparation process of the anti-oxidation layer 31 are not limited thereto, as long as it can isolate oxygen in the air, prevent the first electrode layer 3 from being oxidized, conduct electricity easily, and have good connection performance with the welding layer.

[0103] In the capacitor devices 10 shown in Figures 2, 4 and 5, the capacitors 2 are all planar capacitors, that is, the capacitors 2 include a first electrode 21, a second electrode 22 and a dielectric layer 23 located between the first electrode 21 and the second electrode 22. The capacitor device 10 of this structure has a smaller size along the thickness direction (Y direction) of the substrate 1 and can be used in application scenarios that require the capacitor device 10 to have a thinner thickness.

[0104] FIG7 is a cross-sectional view of another capacitive device provided by an embodiment of the present disclosure, for example, FIG7 is a cross-sectional view taken along line AA in FIG1. ​​As shown in FIG7, in some embodiments, the first electrode plate 21 includes a plurality of first sub-plates 211, and the second electrode plate 22 includes a plurality of second sub-plates 221. The first sub-plates 211 and the second sub-plates 221 are alternately arranged, and two adjacent first sub-plates 211 are electrically connected, and two adjacent second sub-plates 221 are electrically connected.

[0105] The first sub-plates 211 and the second sub-plates 221 are arranged alternately along the thickness direction (Y direction) of the substrate 1, and a dielectric layer 23 is provided between adjacent first sub-plates 211 and second sub-plates 221, so that the capacitor 2 has an interdigitated capacitor structure, which increases the capacitance value of the capacitor 2 while keeping the size of the capacitor device 10 in the X direction unchanged.

[0106] For example, with continued reference to FIG7 , the first electrode plate 21 includes a first connecting portion 212 and a plurality of first sub-plates 211. The plurality of first sub-plates 211 are arranged at intervals along the Y direction, and the plurality of first sub-plates 211 are all connected to the first connecting portion 212, so that the first electrode plate 21 as a whole has a comb shape. The second electrode plate 22 includes a second connecting portion 222 and a plurality of second sub-plates 221. The plurality of second sub-plates 221 are arranged at intervals along the Y direction, and the plurality of second sub-plates 221 are all connected to the second connecting portion 222, so that the second electrode plate 22 as a whole has a comb shape.

[0107] When the first plate 21 includes multiple first sub-plates 211 and the second plate 22 includes multiple second sub-plates 221, one of the first sub-plates 211 may be closer to the substrate 1, or one of the second sub-plates 221 may be closer to the substrate 1. For example, when the first sub-plate 211 is closer to the substrate 1, the first sub-plate 211 may be directly connected to the substrate 1, and a buffer layer or other film structure may be provided between the first sub-plate 211 and the substrate 1. The same applies when the second sub-plate 221 is closer to the substrate 1.

[0108] When the first electrode plate 21 includes a first connecting portion 212 and multiple first sub-plates 211, the first connecting portion 212 can be located near the edge of the capacitive device 10, with a portion of the insulating layer 6 covering the side of the first connecting portion 212 away from the first sub-plate 211. When the second electrode plate 22 includes a second connecting portion 222 and multiple second sub-plates 221, the second connecting portion 222 can be located near the edge of the capacitive device 10, with a portion of the insulating layer 6 covering the side of the second connecting portion 222 away from the second sub-plate 221. The first and second connecting portions 212, 222 are positioned near the edge. This can, on the one hand, reduce the difficulty of the manufacturing process of the capacitive device 10, and on the other hand, can isolate water and oxygen in the air, preventing the capacitor 2 from corrosion.

[0109] Continuing to refer to Figures 2, 6 and 7, in some embodiments, the capacitor device 10 may further include a conductive column 5, which penetrates the substrate 1 along the thickness direction (Y direction) of the substrate 1, and one end of the conductive column 5 is electrically connected to the first electrode layer 3, and the other end of the conductive column 5 is electrically connected to the first electrode plate 21.

[0110] Exemplarily, the substrate 1 is provided with a through hole that penetrates the substrate 1 along the thickness direction, and the conductive pillar 5 is disposed in the through hole. For example, when the substrate 1 is a glass substrate 1, the through hole can be formed in the substrate 1 using TGV (Through Glass Via) technology. For another example, when the substrate 1 is a silicon substrate 1, the through hole can be formed in the substrate 1 using TSV (Through Silicon Via) technology.

[0111] The conductive pillar 5 is a columnar structure made of a conductive material. The cross section of the conductive pillar 5 along the X direction may be circular, rectangular, trapezoidal or other irregular shapes. The embodiment of the present disclosure does not limit the cross-sectional shape of the conductive pillar 5.

[0112] For example, the cross-section of the conductive pillar 5 is circular. The ratio of the diameter of the conductive pillar 5 to the thickness of the substrate 1 can be 1:1 to 1:10. For example, the ratio of the diameter of the conductive pillar 5 to the thickness of the substrate 1 can be any value among 1:1, 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9, 1:10, or a value in a range consisting of any two values.

[0113] The material of the conductive pillar 5 may include one or more of gold, silver, copper, aluminum, and molybdenum, as long as the first electrode layer 3 and the first electrode plate 21 can be electrically connected.

[0114] Figures 8 and 9 are schematic diagrams illustrating the placement of conductive pillars on a substrate in an embodiment of the present disclosure. Figures 8 and 9 are top views along the Y direction. For ease of illustration, Figures 8 and 9 only illustrate the substrate 1 and conductive pillars 5, with other structures removed. As shown in Figures 8 and 9, the number of conductive pillars 5 can be one.

[0115] Continuing with reference to FIG8 , when there is only one conductive pillar 5, the conductive pillar 5 can be disposed at the geometric center of the substrate 1. Continuing with reference to FIG9 , when there is only one conductive pillar 5, the conductive pillar 5 can be disposed at a position deviated from the geometric center of the substrate 1, for example, the conductive pillar 5 can be disposed near an edge of the substrate 1. In practical applications, the location of the conductive pillar 5 can be flexibly selected based on the performance requirements of the capacitive device 10.

[0116] Conductive pillars 5 act like metal traces and generate parasitic inductance within capacitor device 10, affecting the performance of capacitor device 10. For example, the parasitic inductance generated by conductive pillars 5 affects the self-resonant frequency of capacitor device 10, which in turn affects the operating frequency range of capacitor device 10. The lower the self-resonant frequency, the smaller the operating frequency range of capacitor device 10.

[0117] The formula for the self-resonant frequency of the capacitive device 10 is as follows:

[0118] (Formula 1)

[0119] Wherein, SRF represents the self-resonant frequency of the capacitive device 10 , L represents the inductance value of the parasitic inductance in the capacitive device 10 , and C represents the capacitance value of the capacitive device 10 .

[0120] As can be seen from Formula 1, the self-resonant frequency of the capacitor device 10 is inversely proportional to the product of L and C. When the capacitance value C of the capacitor device 10 is constant, in order to increase the self-resonant frequency of the capacitor device 10, the inductance value L of the parasitic inductance needs to be reduced.

[0121] Figure 10 is a cross-sectional view of another capacitive device provided by an embodiment of the present disclosure. For example, Figure 10 is a cross-sectional view taken along line AA in Figure 1. As shown in Figure 10, in some embodiments, capacitive device 10 includes multiple conductive pillars 5. Providing multiple conductive pillars 5 can reduce the parasitic inductance of capacitive device 10, thereby increasing the self-resonant frequency of capacitive device 10 while maintaining a constant capacitance.

[0122] The structures and sizes of the plurality of conductive pillars 5 may be the same or different. For the sake of convenience, the case where the plurality of conductive pillars 5 have the same structure and size is taken as an example.

[0123] The number of conductive pillars 5 can be two, three, four, five, six, eight, nine, etc., and the embodiment of the present disclosure does not limit the number of conductive pillars 5. The more conductive pillars 5 there are, the smaller the inductance value L of the parasitic inductance is, and the greater the self-resonant frequency of the capacitor device 10 is. However, the more conductive pillars 5 there are, the more through holes need to be set on the substrate 1 accordingly. The more through holes there are on the substrate 1, the weaker the strength of the substrate 1. In actual application, the number of conductive pillars 5 can be flexibly determined according to the inductance value of the parasitic inductance and the strength of the substrate 1.

[0124] Figures 11 to 14 are schematic diagrams illustrating the placement of multiple conductive pillars on a substrate in accordance with an embodiment of the present disclosure. As shown in Figures 11 to 14, the multiple conductive pillars 5 can be arranged in an intermittent manner. When the multiple conductive pillars 5 are arranged in an intermittent manner, they can be arranged in pairs (as shown in Figures 11 to 13), or some conductive pillars 5 can be connected together and some can be arranged in intermittent manner (as shown in Figure 14).

[0125] Continuing with FIG11 , when the plurality of conductive pillars 5 are spaced apart in pairs, the shortest distance between two adjacent conductive pillars 5 is d1, which can be determined based on the diameter of the conductive pillar 5. For example, d1 is greater than or equal to the diameter of the conductive pillar 5, or for another example, d1 is greater than or equal to twice the diameter of the conductive pillar 5.

[0126] Exemplarily, d1 may be 0.05 mm to 1 mm. For example, d1 is any value among 0.05 mm, 0.1 mm, 0.2 mm, 0.4 mm, 0.5 mm, 0.6 mm, 0.8 mm, 1 mm, or a value in a range consisting of any two values.

[0127] The distance between two adjacent conductive pillars 5 can be the same, as shown in Figures 11 and 13. The distance between two adjacent conductive pillars 5 can also be different, as shown in Figure 12.

[0128] When the capacitor device 10 is subjected to external forces, cracks are likely to form along the through-holes in the substrate 1. When multiple conductive pillars 5 are arranged in an area near the geometric center of the substrate 1, multiple through-holes are arranged in an area near the geometric center of the substrate 1. When the capacitor device 10 is subjected to external forces, cracks are likely to form in the area near the geometric center of the substrate 1, causing the entire capacitor device 10 to fail.

[0129] 11, 12, and 14, in some embodiments, the conductive pillars 5 may be disposed near the edge of the substrate 1. When the capacitor device 10 is subjected to external force, cracks are less likely to occur in the region near the geometric center of the substrate 1, thereby improving the structural strength of the capacitor device 10.

[0130] In practical applications, in order to further improve the structural strength of the capacitor device 10, the number of conductive pillars 5 can be reduced, the distance between two adjacent conductive pillars 5 can be increased, and the cross-sectional shape of the conductive pillars 5 can be circular to reduce stress concentration at the edges of the conductive pillars 5.

[0131] Continuing to refer to FIG. 11 , FIG. 12 and FIG. 14 , in some embodiments, the plurality of conductive pillars 5 are arranged in a ring shape.

[0132] Exemplarily, when the substrate 1 is rectangular, the plurality of conductive pillars 5 are arranged in a rectangular ring shape, as shown in FIG11 .

[0133] Exemplarily, when the substrate 1 is circular, the plurality of conductive pillars 5 are arranged in a circular ring shape.

[0134] Of course, the shape of the multiple conductive pillars 5 arranged in a ring shape may be different from the shape of the substrate 1. For example, when the substrate 1 is rectangular, the multiple conductive pillars 5 are arranged in a circular ring shape.

[0135] Continuing with Figure 12 , when multiple conductive pillars 5 are arranged in a ring, conductive pillars 5 may not be provided in areas near the corners of substrate 1. Corner regions of substrate 1 have weak structural strength and are easily damaged by stress. Eliminating conductive pillars 5 in these corners can improve the strength of substrate 1. In Figure 12 , as opposed to Figure 11 , conductive pillars 5 are not provided in any of the four corner regions.

[0136] Continuing with FIG14 , the plurality of conductive pillars 5 can be divided into a plurality of conductive pillar groups 5 . Each conductive pillar group 5 includes a plurality of conductive pillars 5 , and the plurality of conductive pillars 5 within the same conductive pillar group 5 are connected to form an integrated structure. Adjacent conductive pillar groups 5 are spaced apart. This reduces the area of ​​the substrate 1 where through-holes are provided, thereby reducing the impact on the strength of the substrate 1 .

[0137] Continuing with FIG. 13 , in some embodiments, the plurality of conductive pillars 5 may be arranged in a planar array. A planar array arrangement refers to a dense arrangement of the plurality of conductive pillars 5. For example, the first direction and the second direction are both located in the plane of the substrate 1, and the first and second directions are perpendicular to each other. The plurality of conductive pillars 5 are arranged in an array along both the first and second directions.

[0138] FIG13 shows a plurality of conductive pillars 5 arranged in a rectangular array. The plurality of conductive pillars 5 can also be arranged in a circular array, a triangular array, a trapezoidal array, a hexagonal array, etc. The present disclosure does not limit the shape of the planar array arrangement. The shape of the planar array arrangement refers to the shape of the pattern enclosed by the outer edges of the planar array arrangement.

[0139] Figure 15 is a cross-sectional view of another capacitive device provided by an embodiment of the present disclosure. As shown in Figure 15 , in some embodiments, a support column 7 is provided within the conductive column 5. The end of the support column 7 facing the first electrode plate 21 supports the first electrode plate 21. The provision of the support column 7 within the conductive column 5 reduces the material consumption of the conductive column 5 while ensuring electrical connection between the first electrode layer 3 and the first electrode plate 21.

[0140] For example, the conductive pillar 5 is a cylindrical structure, the axis of the cylindrical structure extends along the thickness direction of the substrate 1, and the support pillar 7 is arranged inside the cylindrical structure. The end of the cylindrical structure of the conductive pillar 5 facing the first electrode layer 3 can be an open structure or a closed structure.

[0141] For example, a through hole is provided on the substrate 1 , the conductive pillar 5 is a metal layer attached to the inner wall of the through hole, and the support pillar 7 is a filling material filled in the metal layer.

[0142] The material of the support pillar 7 is different from that of the conductive pillar 5. The support pillar 7 can be made of a conductive material or an insulating material. When the support pillar 7 is made of a conductive material, the resistance between the first electrode layer 3 and the first electrode plate 21 can be reduced. When the support pillar 7 is made of an insulating material, the amount of conductive material used can be reduced.

[0143] Exemplarily, the support pillar 7 includes an organic material, thereby facilitating the filling of the organic material into the conductive pillar 5 during the preparation process. For example, the support pillar 7 includes PI, and the PI is filled into the conductive pillar 5 during the preparation process, so that the end of the PI facing the first electrode plate 21 supports the first electrode plate 21, preventing the first electrode plate 21 from collapsing toward the inside of the conductive pillar 5.

[0144] Of course, the conductive pillar 5 may also be a solid columnar structure made of a conductive material, as shown in FIG. 2 , FIG. 6 and FIG. 7 .

[0145] It is understood that the above description is based on the case where the first electrode layer 3 and the first electrode plate 21 are electrically connected via the conductive pillars 5. In actual applications, the electrical connection between the first electrode layer 3 and the first electrode plate 21 can also be achieved through other methods. For example, the first electrode layer 3 and the first electrode plate 21 can be electrically connected via leads.

[0146] To facilitate electrical connection between the conductive pillars 5 and the first electrode plate 21, the first electrode plate 21 can be closer to the substrate 1 than the second electrode plate 22. In this case, the second electrode plate 22 is further away from the substrate 1 than the first electrode plate 21. After the capacitive device 10 is mounted on the carrier, the first electrode plate 21 is electrically connected to the pad on the carrier via the first electrode layer 3, thereby electrically connecting the capacitive device 10 to the circuit within the carrier. The second electrode plate 22 can be used to electrically connect to an external circuit.

[0147] Among them, the second electrode plate 22 can be used for direct electrical connection to an external circuit, as shown in Figure 5. At this time, the surface of the second electrode plate 22 on one side away from the substrate 1 can be provided with an anti-oxidation layer 31 made of a conductive material. The anti-oxidation layer 31 can be made of a chemically inactive metal material (such as nickel, gold, tin, etc.) and is not easily oxidized when exposed to the air. The anti-oxidation layer 31 is provided on the surface of the second electrode plate 22 away from the substrate 1, which can isolate the oxygen in the air, thereby preventing the second electrode plate 22 from being oxidized, and the anti-oxidation layer 31 can make the welding of the second electrode plate 22 and the external circuit more secure.

[0148] Exemplarily, the anti-oxidation layer 31 of the second electrode plate 22 may be the same as the anti-oxidation layer 31 of the first electrode layer 3 .

[0149] Of course, the second electrode plate 22 can also be electrically connected to the external circuit through other structures. Figure 16 is a cross-sectional view of another capacitor device 10 provided in an embodiment of the present disclosure. As shown in Figure 16, in some embodiments, the capacitor device 10 further includes a second electrode layer 4, which is located on the side of the second electrode plate 22 away from the substrate 1, and a portion of the insulating layer 6 is located between the second electrode layer 4 and the second electrode plate 22. The second electrode layer 4 is electrically connected to the second electrode plate 22, and the second electrode layer 4 is used for welding connection to the external circuit.

[0150] Part of the insulating layer 6 is located between the second electrode layer 4 and the second electrode plate 22 , which increases the covering area of ​​the insulating layer 6 on the capacitor 2 , improves the sealing of the capacitor 2 , and prevents external water and oxygen from entering the capacitor 2 and corroding the capacitor 2 .

[0151] When the second electrode plate 22 is directly welded to an external circuit, the heat from welding and the force applied by the external circuit to the second electrode plate 22 can easily cause the second electrode plate 22 to deform, thereby changing the value of the capacitor 2. The second electrode layer 4 is provided for welding to the external circuit, so that the second electrode plate 22 is not easily deformed during welding, which is unlikely to change the value of the capacitor 2.

[0152] In addition, part of the insulating layer 6 is located between the second electrode layer 4 and the second electrode plate 22. When the second electrode layer 4 is deformed, the insulating layer 6 between the second electrode layer 4 and the second electrode plate 22 acts as a buffer, making the second electrode plate 22 less likely to deform.

[0153] Exemplarily, the thickness of the second electrode layer 4 is 1 μm to 10 μm. For example, the thickness of the second electrode layer 4 is any value among 1 μm, 2 μm, 4 μm, 5 μm, 6 μm, 8 μm, 10 μm, or a value in a range consisting of any two values.

[0154] Exemplarily, the material of the second electrode layer 4 includes one or more metal materials such as gold, copper, silver, aluminum, and molybdenum.

[0155] A conductive anti-oxidation layer 31 may be provided on the side of the second electrode layer 4 facing away from the substrate 1. This layer may be made of a chemically inactive metal material (e.g., nickel, gold, tin, etc.) that is not easily oxidized when exposed to air. Disposed on the surface of the second electrode layer 4 facing away from the substrate 1, the anti-oxidation layer 31 isolates the surface of the second electrode layer 4 from oxygen in the air, thereby preventing oxidation of the second electrode layer 4. Furthermore, the anti-oxidation layer 31 strengthens the connection between the second electrode layer 4 and the external circuit.

[0156] Exemplarily, the thickness of the insulating layer 6 between the second electrode layer 4 and the second electrode plate 22 is greater than the thickness of the second electrode plate 22. The thicker the insulating layer 6 is, the better the buffering effect is.

[0157] Insulating layer 6 can include an organic material, such as PI. Organic materials have a good buffering effect, making second electrode plate 22 less susceptible to deformation. Furthermore, during the preparation of capacitor device 10, organic materials have good fluidity, making it easier to coat capacitor 2, reducing the difficulty of preparing insulating layer 6. For example, when the organic material is PI, a spin coating process can be used to form insulating layer 6 on the surface of capacitor 2.

[0158] 16 , in some embodiments, the insulating layer 6 is provided with a second via 61, and the second electrode layer 4 is electrically connected to the second electrode plate 22 through the second via 61. For example, the insulating layer 6 includes a photosensitive material, and the second via 61 is formed in the insulating layer 6 by photolithography, and then the second electrode layer 4 is deposited on the insulating layer 6.

[0159] Figure 17 is a cross-sectional view of another capacitor device according to an embodiment of the present disclosure, for example, Figure 17 is a cross-sectional view taken along line AA in Figure 1. As shown in Figure 17, when the capacitor device 10 includes the second electrode layer 4, the number of the conductive pillar 5 may also be one.

[0160] The present disclosure also provides an electronic device including the capacitive device 10. The electronic device may be a handheld device (e.g., a mobile phone, a GPS navigator, etc.) or a communication device (e.g., a wireless local area network device, a radio frequency module, etc.). The present disclosure does not limit the type of electronic device.

[0161] FIG18 is a schematic diagram of a partial structure of an electronic device in the related art. As shown in FIG18 , the electronic device in the related art includes a printed circuit board, a capacitor device, a chip, and bonding wires. Two pads and on-board traces are provided on the surface of the printed circuit board, and one of the pads is electrically connected to the on-board trace. One plate of the capacitor device is soldered to one of the pads, and the other plate of the capacitor device is soldered to the other pad. One end of the bonding wire is electrically connected to the chip, and the other end of the bonding wire is electrically connected to the on-board trace. That is, the chip is electrically connected to the capacitor device through the bonding wires, the on-board traces, and the pads in sequence.

[0162] When an electronic device is working, the signal transmission between the chip and the capacitor device needs to pass through the bonding wires, on-board traces and pads. That is, the signal transmission path between the chip and the capacitor device is long, resulting in greater attenuation during the signal transmission process.

[0163] FIG19 is a schematic diagram of a partial structure of an electronic device provided by an embodiment of the present disclosure. As shown in FIG19 , in some embodiments, the electronic device further includes a printed circuit board 20, a chip 30, and bonding wires 40. The capacitive device 10 and the chip 30 are disposed on the same side of the printed circuit board 20. A pad is provided on the surface of the printed circuit board 20. The capacitive device 10 is soldered to the pad via the first electrode layer 3. One end of the bonding wire 40 is connected to the chip 30, and the other end of the bonding wire 40 is connected to the capacitive device 10.

[0164] Since the other end of the bonding wire 40 is directly connected to the capacitor device 10 without the need to be connected to the on-board traces on the printed circuit board 20, the signal transmission path between the chip 30 and the capacitor device 10 now only includes the bonding wire 40, shortening the signal transmission path between the chip 30 and the capacitor device 10 and reducing the signal attenuation between the chip 30 and the capacitor device 10.

[0165] Figure 20 is a partial structural diagram of another electronic device provided by an embodiment of the present disclosure. As shown in Figure 20 , in some embodiments, the other end of a bonding wire 40 is directly connected to the second electrode plate 22 of the capacitive device 10. The second electrode plate 22 is disposed on a side of the capacitive device 10 away from the printed circuit board 20, facilitating the electrical connection between the bonding wire 40 and the second electrode plate 22.

[0166] Exemplarily, the second electrode plate 22 is connected to the bonding wire 40 by welding.

[0167] When the bonding wire 40 is directly electrically connected to the second electrode plate 22, an anti-oxidation layer 31 made of a conductive material may be provided on the surface of the second electrode plate 22 away from the substrate 1. The anti-oxidation layer 31 may be made of a chemically inactive metal material (such as nickel, gold, tin, etc.) that is not easily oxidized when exposed to air. The anti-oxidation layer 31 is provided on the surface of the second electrode plate 22 away from the substrate 1 to isolate oxygen in the air, thereby preventing the second electrode plate 22 from being oxidized. The anti-oxidation layer 31 also makes the welding between the second electrode plate 22 and the external circuit more secure.

[0168] Figure 21 is a partial structural diagram of another electronic device provided by an embodiment of the present disclosure. As shown in Figure 21, in some embodiments, the second electrode 22 of the capacitive device 10 is further away from the substrate 1 than the first electrode 21. The capacitive device 10 further includes a second electrode layer 4 and an insulating layer 6. The second electrode layer 4 is located on the side of the second electrode 22 away from the substrate 1, and the insulating layer 6 is located between the second electrode layer 4 and the second electrode 22. The second electrode layer 4 is electrically connected to the second electrode 22, and the other end of the bonding wire 40 is connected to the second electrode layer 4.

[0169] When the bonding wire 40 is electrically connected to the second electrode layer 4, a conductive anti-oxidation layer 31 may be provided on the side of the second electrode layer 4 facing away from the substrate 1. The anti-oxidation layer 31 may be made of a chemically inactive metal material (e.g., nickel, gold, tin, etc.) that is not easily oxidized when exposed to air. The anti-oxidation layer 31, disposed on the surface of the second electrode layer 4 facing away from the substrate 1, isolates the second electrode layer 4 from oxygen in the air, thereby preventing oxidation. Furthermore, the anti-oxidation layer 31 strengthens the connection between the second electrode layer 4 and the external circuit.

[0170] Part of the insulating layer 6 is located between the second electrode layer 4 and the second electrode plate 22 , which increases the covering area of ​​the insulating layer 6 on the capacitor 2 , improves the sealing of the capacitor 2 , and prevents external water and oxygen from entering the capacitor 2 and corroding the capacitor 2 .

[0171] When the second electrode plate 22 is directly welded to an external circuit, the heat from welding and the force applied by the external circuit to the second electrode plate 22 can easily cause the second electrode plate 22 to deform, thereby changing the value of the capacitor 2. The second electrode layer 4 is provided for welding to the external circuit, so that the second electrode plate 22 is not easily deformed during welding, which is unlikely to change the value of the capacitor 2.

[0172] In addition, part of the insulating layer 6 is located between the second electrode layer 4 and the second electrode plate 22. When the second electrode layer 4 is deformed, the insulating layer 6 between the second electrode layer 4 and the second electrode plate 22 acts as a buffer, making the second electrode plate 22 less likely to deform.

[0173] The present disclosure also provides a method for preparing a capacitor device, which is used to prepare the capacitor device described above. Figures 22(a) to 22(k) are flow charts of one method for preparing the capacitor device shown in Figure 17, and Figures 23(a) to 23(j) are flow charts of another method for preparing the capacitor device shown in Figure 17. The following describes the method for preparing the capacitor device provided by the present disclosure in detail, using the preparation of the capacitor device shown in Figure 17 as an example.

[0174] As shown in FIG. 22( a ) to FIG. 22 ( k ), a method for preparing a capacitor device includes the following steps:

[0175] a1) Providing a substrate 1.

[0176] FIG22(a) is a cross-sectional view of the substrate 1. FIG22(a) is a cross-sectional view of

[0177] The substrate 1 can be a rigid substrate 1, such as a glass substrate 1, a silicon substrate 1, a ceramic substrate 1, etc. Of course, the substrate 1 can also be a flexible substrate 1, such as a polyethylene terephthalate substrate 1, a polyethylene naphthalate substrate 1, or a polyimide substrate 1, etc.

[0178] Exemplarily, the thickness of the substrate 1 is 0.1 mm to 2 mm, for example, the thickness of the substrate 1 is any value among 0.1 mm, 0.2 mm, 0.5 mm, 0.8 mm, 1 mm, 1.2 mm, 1.5 mm, 1.8 mm, 2 mm, or a value in a range consisting of any two values.

[0179] b1) A blind hole 11 is opened in the substrate 1 .

[0180] FIG22( b ) shows a cross-sectional view of the substrate 1 after the blind hole 11 is opened.

[0181] The shape of the blind hole 11 can be circular, rectangular, trapezoidal or other irregular shapes, and the embodiment of the present disclosure does not limit the shape of the blind hole 11.

[0182] The depth of the blind hole 11 can be 0.05 mm to 1 mm. For example, the depth of the blind hole 11 is any value among 0.05 mm, 0.1 mm, 0.2 mm, 0.4 mm, 0.5 mm, 0.6 mm, 0.8 mm, 1 mm, or a value in a range consisting of any two values.

[0183] Exemplarily, when the shape of the blind hole 11 is circular, the ratio of the diameter of the blind hole 11 to the thickness of the substrate 1 can be 1:1 to 1:10. For example, the ratio of the diameter of the blind hole 11 to the thickness of the substrate 1 can be any value among 1:1, 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9, 1:10, or a value in a range consisting of any two values.

[0184] c1) forming a seed layer 51 on the inner wall of the blind hole 11 .

[0185] FIG22( c ) shows a cross-sectional view after a seed layer 51 is formed on the inner wall of the blind hole 11 , wherein a first hollow area 111 is provided inside the seed layer 51 .

[0186] Illustratively, the seed layer 51 is formed on the inner wall of the blind hole 11 by sputtering or the like.

[0187] The material of the seed layer 51 can be one or more metal materials such as gold, silver, copper, aluminum, and molybdenum.

[0188] d1) Performing metallization filling in the first hollow area 111 to form a conductive pillar 5 .

[0189] FIG22( d ) shows a cross-sectional view of the first hollow region 111 after metallization filling is completed.

[0190] Illustratively, after a seed layer 51 is formed on the inner wall of the blind hole 11, copper metal is injected into the first hollow area 111 by electroplating, and then excess metal on the surface of the substrate 1 is removed by etching and chemical mechanical polishing (CMP) to form a conductive column 5.

[0191] e1) forming a first electrode plate 21 on the surface of the substrate 1 .

[0192] FIG22( e ) is a cross-sectional view showing the surface of the substrate 1 after the first electrode 21 is formed.

[0193] Exemplarily, the first electrode 21 is formed on the surface of the substrate 1 by processes such as sputtering or electroplating conductive traces, spin coating photoresist, and exposing and etching patterns.

[0194] The material of the first electrode plate 21 can be one or more metal materials such as gold, silver, copper, aluminum, and molybdenum.

[0195] Exemplarily, the thickness of the first electrode plate 21 is 0.1 μm to 10 μm, for example, the thickness of the first electrode plate 21 is any value among 0.1 μm, 0.5 μm, 0.8 μm, 1 μm, 2 μm, 5 μm, 8 μm, 10 μm, or a value in a range consisting of any two values.

[0196] f1) forming a dielectric layer 23 on the surface of the first electrode plate 21 .

[0197] FIG22( f ) is a cross-sectional view showing the first electrode plate 21 after a dielectric layer 23 is formed on the surface of the first electrode plate 21 .

[0198] Exemplarily, the dielectric layer 23 is prepared by chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0199] The dielectric layer 23 is made of an insulator. For example, the dielectric layer 23 is made of an inorganic material, such as silicon oxide, silicon nitride, ceramic, etc.

[0200] Exemplarily, the thickness of the dielectric layer 23 is 0.05 μm to 5 μm, for example, the thickness of the dielectric layer 23 is any value among 0.05 μm, 0.1 μm, 0.5 μm, 0.8 μm, 1 μm, 2 μm, 5 μm, or a value in a range consisting of any two values.

[0201] g1) forming a second electrode plate 22 on the surface of the dielectric layer 23 .

[0202] FIG22( g ) is a cross-sectional view showing the surface of the dielectric layer 23 after the second electrode 22 is formed.

[0203] Exemplarily, the second electrode 22 is formed on the surface of the substrate 1 by processes such as sputtering or electroplating conductive traces, spin coating photoresist, and exposing and etching patterns.

[0204] The material of the second electrode plate 22 can be one or more metal materials such as gold, silver, copper, aluminum, and molybdenum.

[0205] Illustratively, the thickness of the second electrode plate 22 is 0.4 μm to 10 μm, for example, the thickness of the second electrode plate 22 is any value among 0.4 μm, 0.5 μm, 0.8 μm, 1 μm, 2 μm, 5 μm, 8 μm, 10 μm, or a value in a range consisting of any two values.

[0206] The stacked first electrode plate 21 , dielectric layer 23 and second electrode plate 22 form a capacitor 2 .

[0207] h1) forming an insulating layer 6 on the surface of the capacitor 2.

[0208] FIG22( h) is a cross-sectional view showing the capacitor 2 after an insulating layer 6 is formed on its surface.

[0209] A second via hole 61 is provided in a region of the insulating layer 6 opposite to the second electrode plate 22 .

[0210] Insulating layer 6 covers the edges of capacitor 2 to prevent moisture from entering the interior of capacitor 2 through the edges, thereby preventing corrosion of capacitor 2. Insulating layer 6 can be made of a photosensitive organic material, such as polyimide or photoresist, or an inorganic insulating material, such as silicon oxide or silicon nitride.

[0211] For example, when the material of the insulating layer 6 is photoresist, the insulating layer 6 can be formed by a spin coating process, and then the second via hole 61 can be obtained by a photolithography process.

[0212] Exemplarily, the thickness of the insulating layer 6 is greater than or equal to the thickness of the second electrode plate 22 .

[0213] i1) forming a second electrode layer 4 on the surface of the insulating layer 6 .

[0214] FIG22( i ) is a cross-sectional view after the second electrode layer 4 is formed on the surface of the insulating layer 6 .

[0215] A partial area of ​​the second electrode layer 4 is electrically connected to the second electrode plate 22 through the second via hole 61 .

[0216] Exemplarily, the thickness of the second electrode layer 4 is 1 μm to 10 μm. For example, the thickness of the second electrode layer 4 is any value among 1 μm, 2 μm, 4 μm, 5 μm, 6 μm, 8 μm, 10 μm, or a value in a range consisting of any two values.

[0217] Exemplarily, the material of the second electrode layer 4 includes one or more metal materials such as gold, copper, silver, aluminum, and molybdenum.

[0218] A conductive anti-oxidation layer 31 may be provided on the side of the second electrode layer 4 facing away from the substrate 1. This layer may be made of a chemically inactive metal material (e.g., nickel, gold, tin, etc.) that is not easily oxidized when exposed to air. Disposed on the surface of the second electrode layer 4 facing away from the substrate 1, the anti-oxidation layer 31 isolates the surface of the second electrode layer 4 from oxygen in the air, thereby preventing oxidation of the second electrode layer 4. Furthermore, the anti-oxidation layer 31 strengthens the connection between the second electrode layer 4 and the external circuit.

[0219] j1) Exposing one end of the conductive pillar 5 away from the first electrode plate 21 .

[0220] FIG22(j) shows a cross-sectional view of the substrate 1 after thinning.

[0221] Exemplarily, the side of the substrate 1 away from the first electrode plate 21 is processed by thinning, grinding, CMP, etc., so that the end of the conductive pillar 5 away from the first electrode plate 21 is exposed.

[0222] k1) forming a first electrode layer 3 on a side of the substrate 1 away from the first electrode plate 21 .

[0223] FIG22( k ) is a cross-sectional view showing the first electrode layer 3 formed on the side of the substrate 1 away from the first electrode plate 21 .

[0224] Exemplarily, the first electrode layer 3 is formed on the surface of the substrate 1 by processes such as sputtering or electroplating conductive traces, spin coating photoresist, and exposing and etching patterns.

[0225] The first electrode layer 3 can be made of metal materials such as copper, silver, aluminum, and molybdenum.

[0226] For example, the thickness of the first electrode layer 3 may be 1 μm to 10 μm. For example, the thickness of the first electrode layer 3 may be any value among 1 μm, 2 μm, 3 μm, 5 μm, 6 μm, 8 μm, 10 μm, or a value in a range consisting of any two values.

[0227] When the first electrode layer 3 is made of a metal material with relatively active chemical properties, the surface of the first electrode layer 3 away from the substrate 1 is easily oxidized by oxygen in the air, forming an oxide layer, which reduces the conductivity of the first electrode layer 3 and reduces the connection performance between the first electrode layer 3 and the welding layer.

[0228] As shown in FIG. 23( a ) to FIG. 23 ( j ), another method for preparing a capacitive device 10 includes the following steps:

[0229] a2) Providing a substrate 1.

[0230] FIG23(a) is a cross-sectional view of the substrate 1. ...

[0231] The substrate 1 can be a rigid substrate 1, such as a glass substrate 1, a silicon substrate 1, a ceramic substrate 1, etc. Of course, the substrate 1 can also be a flexible substrate 1, such as a polyethylene terephthalate substrate 1, a polyethylene naphthalate substrate 1, or a polyimide substrate 1, etc.

[0232] Exemplarily, the thickness of the substrate 1 is 0.1 mm to 2 mm, for example, the thickness of the substrate 1 is any value among 0.1 mm, 0.2 mm, 0.5 mm, 0.8 mm, 1 mm, 1.2 mm, 1.5 mm, 1.8 mm, 2 mm, or a value in a range consisting of any two values.

[0233] b2) Opening a first via hole 12 in the substrate 1 .

[0234] FIG23( b ) is a cross-sectional view of the substrate 1 after the first via hole 12 is formed.

[0235] The shape of the first via hole 12 may be circular, rectangular, trapezoidal or other irregular shapes, and the embodiment of the present disclosure does not limit the shape of the first via hole 12 .

[0236] Exemplarily, when the shape of the first via 12 is circular, the ratio of the diameter of the first via 12 to the thickness of the substrate 1 can be 1:1 to 1:10. For example, the ratio of the diameter of the first via 12 to the thickness of the substrate 1 can be any value among 1:1, 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9, 1:10, or a value in a range consisting of any two values.

[0237] c2) forming a seed layer 51 on the inner wall of the first via hole 12 .

[0238] FIG23( c ) shows a cross-sectional view after a seed layer 51 is formed on the inner wall of the first via hole 12 , wherein a second hollow area 121 is provided in the seed layer 51 .

[0239] Exemplarily, the seed layer 51 is formed on the inner wall of the first via hole 12 by sputtering or the like.

[0240] The material of the seed layer 51 can be one or more metal materials such as gold, silver, copper, aluminum, and molybdenum.

[0241] d2) Performing metallization filling in the second hollow area 121 to form a conductive pillar 5 .

[0242] FIG23( d ) shows a cross-sectional view of the first via hole 12 after metallization filling is completed.

[0243] Illustratively, after a seed layer 51 is formed on the inner wall of the first via hole 12 , copper metal is injected into the second hollow area 121 by electroplating, and then excess metal on the surface of the substrate 1 is removed by etching and chemical mechanical polishing (CMP) to form a conductive column 5 .

[0244] e2) forming a first electrode plate 21 on one side of the substrate 1 .

[0245] FIG23( e ) is a cross-sectional view showing the surface of the substrate 1 after the first electrode 21 is formed.

[0246] Exemplarily, the first electrode 21 is formed on the surface of the substrate 1 by processes such as sputtering or electroplating conductive traces, spin coating photoresist, and exposing and etching patterns.

[0247] The material of the first electrode plate 21 can be one or more metal materials such as gold, silver, copper, aluminum, and molybdenum.

[0248] Exemplarily, the thickness of the first electrode plate 21 is 0.1 μm to 10 μm, for example, the thickness of the first electrode plate 21 is any value among 0.1 μm, 0.5 μm, 0.8 μm, 1 μm, 2 μm, 5 μm, 8 μm, 10 μm, or a value in a range consisting of any two values.

[0249] f2) forming a first electrode layer 3 on the other side of the substrate 1 .

[0250] FIG23( f ) is a cross-sectional view showing the surface of the substrate 1 after the first electrode layer 3 is formed.

[0251] Exemplarily, the first electrode layer 3 is formed on the surface of the substrate 1 by processes such as sputtering or electroplating conductive traces, spin coating photoresist, and exposing and etching patterns.

[0252] The material of the first electrode layer 3 can be one or more metal materials such as gold, silver, copper, aluminum, and molybdenum.

[0253] For example, the thickness of the first electrode layer 3 may be 1 μm to 10 μm. For example, the thickness of the first electrode layer 3 may be any value among 1 μm, 2 μm, 3 μm, 5 μm, 6 μm, 8 μm, 10 μm, or a value in a range consisting of any two values.

[0254] When the first electrode layer 3 is made of a metal material with relatively active chemical properties, the surface of the first electrode layer 3 away from the substrate 1 is easily oxidized by oxygen in the air, forming an oxide layer, which reduces the conductivity of the first electrode layer 3 and reduces the connection performance between the first electrode layer 3 and the welding layer.

[0255] g2) forming a dielectric layer 23 on the surface of the first electrode plate 21 .

[0256] FIG23( g ) is a cross-sectional view showing the first electrode plate 21 after a dielectric layer 23 is formed on the surface of the first electrode plate 21 .

[0257] Exemplarily, the dielectric layer 23 is prepared by chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0258] The dielectric layer 23 is made of an insulator. For example, the dielectric layer 23 is made of an inorganic material, such as silicon oxide, silicon nitride, ceramic, etc.

[0259] Exemplarily, the thickness of the dielectric layer 23 is 0.05 μm to 5 μm, for example, the thickness of the dielectric layer 23 is any value among 0.05 μm, 0.1 μm, 0.5 μm, 0.8 μm, 1 μm, 2 μm, 5 μm, or a value in a range consisting of any two values.

[0260] h2) forming a second electrode plate 22 on the surface of the dielectric layer 23 .

[0261] FIG23( h ) is a cross-sectional view showing the surface of the dielectric layer 23 after the second electrode 22 is formed.

[0262] Exemplarily, the second electrode 22 is formed on the surface of the substrate 1 by processes such as sputtering or electroplating conductive traces, spin coating photoresist, and exposing and etching patterns.

[0263] The material of the second electrode plate 22 can be one or more metal materials such as gold, silver, copper, aluminum, and molybdenum.

[0264] Illustratively, the thickness of the second electrode plate 22 is 0.4 μm to 10 μm, for example, the thickness of the second electrode plate 22 is any value among 0.4 μm, 0.5 μm, 0.8 μm, 1 μm, 2 μm, 5 μm, 8 μm, 10 μm, or a value in a range consisting of any two values.

[0265] The stacked first electrode plate 21 , dielectric layer 23 and second electrode plate 22 form a capacitor 2 .

[0266] i2) forming an insulating layer 6 on the surface of the capacitor 2.

[0267] FIG23( i ) shows a cross-sectional view of the capacitor 2 after the insulating layer 6 is formed on the surface of the capacitor 2 .

[0268] A second via hole 61 is provided in a region of the insulating layer 6 opposite to the second electrode plate 22 .

[0269] Insulating layer 6 covers the edges of capacitor 2 to prevent moisture from entering the interior of capacitor 2 through the edges, thereby preventing corrosion of capacitor 2. Insulating layer 6 can be made of a photosensitive organic material, such as polyimide or photoresist, or an inorganic insulating material, such as silicon oxide or silicon nitride.

[0270] For example, when the material of the insulating layer 6 is photoresist, the insulating layer 6 can be formed by a spin coating process, and then the second via hole 61 can be obtained by a photolithography process.

[0271] Exemplarily, the thickness of the insulating layer 6 is greater than or equal to the thickness of the second electrode plate 22 .

[0272] j2) forming a second electrode layer 4 on the surface of the insulating layer 6.

[0273] FIG23( j ) is a cross-sectional view after the second electrode layer 4 is formed on the surface of the insulating layer 6 .

[0274] A partial area of ​​the second electrode layer 4 is electrically connected to the second electrode plate 22 through the second via hole 61 .

[0275] Exemplarily, the thickness of the second electrode layer 4 is 1 μm to 10 μm. For example, the thickness of the second electrode layer 4 is any value among 1 μm, 2 μm, 4 μm, 5 μm, 6 μm, 8 μm, 10 μm, or a value in a range consisting of any two values.

[0276] Exemplarily, the material of the second electrode layer 4 includes one or more metal materials such as gold, copper, silver, aluminum, and molybdenum.

[0277] A conductive anti-oxidation layer 31 may be provided on the side of the second electrode layer 4 facing away from the substrate 1. This layer may be made of a chemically inactive metal material (e.g., nickel, gold, tin, etc.) that is not easily oxidized when exposed to air. Disposed on the surface of the second electrode layer 4 facing away from the substrate 1, the anti-oxidation layer 31 isolates the surface of the second electrode layer 4 from oxygen in the air, thereby preventing oxidation of the second electrode layer 4. Furthermore, the anti-oxidation layer 31 strengthens the connection between the second electrode layer 4 and the external circuit.

[0278] The capacitor device 10 prepared by the method for preparing the capacitor device 10 provided in the embodiment of the present disclosure can be connected to the outside by welding through the first electrode layer 3 , thereby improving the connection firmness of the capacitor device 10 .

[0279] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A capacitor device, characterized in that, Comprising: A substrate having a first side and a second side opposite to each other along its thickness direction; A capacitor including a first electrode plate, a dielectric layer, and a second electrode plate stacked on the second side; A first electrode layer disposed on the first side and electrically connected to the first electrode plate, the first electrode layer being used for welding connection with an external circuit.

2. The capacitor device according to claim 1, wherein, The capacitor device further includes a conductive post, the conductive post penetrating through the substrate along the thickness direction of the substrate, one end of the conductive post being electrically connected to the first electrode layer, and the other end of the conductive post being electrically connected to the first electrode plate.

3. The capacitor device according to claim 2, wherein, The capacitor device includes a plurality of the conductive posts, and the plurality of conductive posts are arranged at intervals.

4. The capacitor device according to claim 3, wherein, The conductive post is disposed adjacent to the edge of the substrate.

5. The capacitor device according to claim 4, wherein, The plurality of conductive posts are arranged in a ring shape.

6. The capacitor device according to claim 3, wherein, The plurality of conductive posts are arranged in a planar array.

7. The capacitor device according to claim 2, wherein, A support post is provided in the conductive post, and one end of the support post facing the first electrode plate supports the first electrode plate; alternatively, the conductive post is a solid columnar structure made of a conductor material.

8. The capacitor device according to claim 7, wherein, The support post includes an organic material.

9. The capacitor device according to any one of claims 1 to 8, wherein The second electrode plate is farther away from the substrate than the first electrode plate.

10. The capacitor device according to claim 9, wherein, The capacitor device further includes a second electrode layer and an insulating layer, the second electrode layer is located on a side of the second electrode plate away from the substrate, the insulating layer is located between the second electrode layer and the second electrode plate, the second electrode layer is electrically connected to the second electrode plate, and the second electrode layer is used for welding connection with an external circuit.

11. The capacitor device according to claim 10, wherein, The insulating layer is provided with a second via hole, and the second electrode layer is electrically connected to the second electrode plate through the second via hole.

12. The capacitor device according to claim 10, wherein, An edge of the insulating layer extends towards the substrate and covers edges of the first electrode plate, the dielectric layer, and the second electrode plate.

13. The capacitor device according to claim 12, wherein, The insulating layer includes an organic material.

14. The capacitor device according to claim 9, wherein, The second electrode plate is used for welding connection with an external circuit.

15. The capacitor device according to any one of claims 1 to 8, wherein, The first electrode plate includes a plurality of first sub-electrode plates, the second electrode plate includes a plurality of second sub-electrode plates, the first sub-electrode plates and the second sub-electrode plates are arranged in an interleaved manner, and adjacent two first sub-electrode plates are electrically connected, and adjacent two second sub-electrode plates are electrically connected.

16. The capacitor device according to claim 1, wherein, A positive projection of the first electrode plate and / or the second electrode plate on the substrate is a polygon, a circle, an ellipse, or an irregular shape.

17. A capacitor device, characterized in that, Comprising: A substrate having a first side and a second side opposite to each other along its thickness direction; A capacitor including a first electrode plate, a dielectric layer, and a second electrode plate stacked on the second side; A first electrode layer disposed on the first side and electrically connected to the first electrode plate, and an anti-oxidation layer made of a conductor material is provided on a side of the first electrode layer away from the substrate.

18. An electronic device, characterized in that, Including the capacitor device according to any one of claims 1 to 17.

19. The electronic device according to claim 18, wherein, The electronic device further includes a printed circuit board, a chip, and a bonding wire. The capacitor device and the chip are disposed on the same side of the printed circuit board. A pad is provided on a surface of the printed circuit board. The first electrode layer of the capacitor device is welded to the pad. One end of the bonding wire is connected to the chip, and the other end of the bonding wire is connected to the capacitor device.

20. The electronic device according to claim 19, wherein, The second electrode plate of the capacitor device is farther away from the substrate than the first electrode plate. The capacitor device further includes a second electrode layer and an insulating layer. The second electrode layer is located on the side of the second electrode plate away from the substrate, the insulating layer is located between the second electrode layer and the second electrode plate, the second electrode layer is electrically connected to the second electrode plate, and the other end of the bonding wire is connected to the second electrode layer.

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