Wafer testing method and device and storage medium
By obtaining PCM parameters and using mapping relationships to adjust the trim circuit gear, the problem of insufficient or excessive chip programming caused by process fluctuations is solved, and the yield and reliability of the wafer are improved.
Patent Information
- Application Number
- CN202510811683.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-17
- Publication Date
- 2025-09-30
AI Technical Summary
In the prior art, insufficient or excessive chip programming caused by process fluctuations results in a low chip yield.
By obtaining PCM parameters and using the preset mapping relationship to adjust the trim circuit gear, intelligent adjustment of the CP test process can be achieved to avoid over- or under-programming.
It effectively improves the yield and reliability of wafers, with the increase ranging from 15% to 60%.
Smart Images
Figure CN120722147A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor device testing technology, and in particular to a wafer testing method, device, and storage medium. Background Art
[0002] In the semiconductor integrated circuit manufacturing industry, chip performance uniformity is a key parameter for improving product yield and reliability. A wafer acceptance test (WAT) structure with a phase change memory (PCM) is typically installed within the wafer dicing lanes to monitor process fluctuations.
[0003] Non-volatile memory (NVM) chip testing involves complex erase, write, and read operations. Each operating mode requires specific voltage settings to ensure correct data storage and retrieval. For example, a write operation requires applying a high control gate voltage (VCG) to the cell gate (CG) of the selected cell and a high bit line voltage (VBL) to the bit line (BL).
[0004] To ensure consistent functional characteristics across all chips, high-voltage parameters such as the cell gate voltage (VCG) and the bit line voltage (VBL) must be strictly controlled within specific specifications. This range is typically achieved through trimming circuits (trim circuits). Trim circuits are a mechanism for fine-tuning circuit parameters, helping to bring high voltages like VCG and VBL within specifications, thereby ensuring successful write operations.
[0005] However, in the actual production process, due to the existence of process fluctuations, even after trim circuit modulation, some batches of chips may still face the problem of under- or over-programming. Process fluctuations include fluctuations in the line width and film thickness of key dimensions, such as the lithography and etching processes that define the floating gate, and film thickness fluctuations in the self-alignment process. These factors may affect the electrical characteristics of the chip, making it impossible for the preset trim circuit gear to achieve the optimal programming conditions in all cases, resulting in a lower yield of the chips in this batch. Summary of the Invention
[0006] The present application provides a method for solving the yield loss problem of chips in the related art caused by insufficient or excessive programming due to process fluctuations.
[0007] On the one hand, an embodiment of the present application provides a wafer testing method, comprising: Obtaining PCM parameters, where the PCM parameters are parameters obtained by performing a WAT test on a target wafer; According to the PCM parameters, the trim circuit gear is adjusted and determined by querying a preset mapping relationship, wherein the preset mapping relationship is a mapping relationship between the PCM parameters and their corresponding trim circuit gears; A CP test is performed on the target wafer according to the trim circuit gear.
[0008] In some embodiments, the preset mapping relationship is a mapping relationship between different PCM parameter value ranges and their corresponding trim circuit gears; The adjusting and determining of the trim circuit gear by querying a preset mapping relationship according to the PCM parameters includes: Classifying the PCM parameters into the value intervals to which they belong; The preset mapping relationship is queried according to the corresponding numerical range to adjust and determine the trim circuit gear.
[0009] In some embodiments, the PCM parameter includes VTP or programming current, wherein the VTP is a threshold voltage after a programming operation is performed on a flash memory on a wafer, and the programming current is a leakage current after programming the flash memory.
[0010] In some embodiments, performing a CP test on the target wafer according to the trim circuit gear includes: The standard programming voltage in the CP test is adjusted according to the adjusted trim circuit gear to obtain an adjusted programming voltage; A CP test is performed on the target wafer according to the adjusted programming voltage.
[0011] In some embodiments, the programming voltage includes a control gate voltage and / or a bit line voltage.
[0012] In some embodiments, before obtaining the PCM parameters, the method further includes: Obtaining PCM parameters of a sample wafer, where the PCM parameters of the sample wafer are parameters obtained by performing a WAT test on a WAT test structure on the sample wafer, wherein the sample wafer is a wafer used for testing and / or a wafer prepared before preparing the target wafer; Dividing the numerical intervals according to the PCM parameters of the sample wafer; The preset mapping relationship is set according to the numerical range.
[0013] In some embodiments, the WAT test structure is disposed in a dicing area of the sample wafer.
[0014] On the other hand, an embodiment of the present application provides a computer device, which includes a processor and a memory, wherein the memory stores at least one instruction or program, and the instruction or program is loaded and executed by the processor to implement any of the wafer testing methods described above.
[0015] On the other hand, an embodiment of the present application provides a computer-readable storage medium, wherein the storage medium stores at least one instruction, and the instruction is loaded and executed by a processor to implement any of the wafer testing methods described above.
[0016] The technical solution of this application has at least the following advantages: By collecting PCM parameters and adjusting and determining the trim circuit position based on the preset mapping relationship queried according to the PCM parameters, intelligent adjustment is achieved during the CP test process, avoiding over- or under-programming and effectively improving the wafer yield and reliability. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0018] Figure 1 This is a flow chart of a wafer testing method provided by an exemplary embodiment of the present application; Figure 2 This is a flowchart of the work required before obtaining PCM parameters provided by an exemplary embodiment of the present application; Figure 3 This is a VTP data distribution interval diagram provided by an exemplary embodiment of the present application; Figure 4 This is a wafer test image after testing using a standard test method provided by an exemplary embodiment of the present application; Figure 5 This is a wafer test image provided by an exemplary embodiment of the present application after testing using the method provided by the present application; Figure 6 It is a block diagram of a computer device provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION
[0019] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.
[0020] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0021] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.
[0022] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0023] refer to Figure 1 , which shows a flow chart of a wafer testing method provided by an exemplary embodiment of the present application, such as Figure 1 The method shown includes: Step S101 , obtaining PCM parameters, where the PCM parameters are parameters obtained by performing a WAT test on a target wafer.
[0024] Optionally, the PCM parameters include a programmed threshold voltage (VTP) or a programming current, where VTP is a threshold voltage after a programming operation is performed on the flash memory on the wafer, and the programming current is a leakage current after the flash memory is programmed.
[0025] In an optional embodiment, the PCM parameter is the VTP of the target wafer.
[0026] For example, the target wafer can be placed on the wafer carrier of the test equipment, and the probe can be brought into contact with the pads on the chip in the target wafer for programming (at least one of reading, writing and erasing operations on the chip) to measure the PCM parameters.
[0027] Step S102 : According to the PCM parameters, the trim circuit gear is adjusted and determined by querying a preset mapping relationship. The preset mapping relationship is a mapping relationship between the PCM parameters and their corresponding trim circuit gears.
[0028] Exemplarily, according to the PCM parameters, the trim circuit gear is adjusted and determined by querying the preset mapping relationship, including but not limited to: classifying the PCM parameters into their corresponding numerical ranges; and adjusting and determining the trim circuit gear according to the corresponding numerical ranges by querying the preset mapping relationship.
[0029] The preset mapping relationship is a mapping relationship between different PCM parameter value ranges and their corresponding trim circuit gears.
[0030] For example, after performing a CP test on a target wafer, VTP = 0.8 volts (V). As shown in Table 1, the numerical range of the PCM parameter (VTP) is interval 1 = (-∞, 0.7V], interval 2 = (0.7V, 0.9V), and interval 3 = [0.9V, +∞). Therefore, it can be determined that the numerical range to which the obtained PCM parameter (VTP = 0.8V) belongs is interval 2, and the trim circuit gear adjustment change corresponding to interval 2 is 0. Therefore, it can be determined that the trim circuit gear for the wafer probe (Chip Probing, CP) test is the standard gear. Table 1 Step S103 , performing a CP test on the target wafer according to the trim circuit gear.
[0031] Among them, the CP test is performed on the target wafer according to the trim circuit gear, including: The standard programming voltage in the CP test is adjusted according to the adjusted trim circuit gear to obtain the adjusted programming voltage; the CP test is performed on the target wafer according to the adjusted programming voltage. The CP test is used to detect whether the wafer is qualified and can also improve the yield.
[0032] Illustratively, the programming voltage includes a control gate voltage and / or a bit line voltage.
[0033] In an optional embodiment, before performing a CP test on the target wafer, the standard programming conditions for the CP test are first set, that is, the VCG of the target wafer needs to be set to 9V after programming, and when the PCM parameter of the target wafer is 0.6V, the gear originally trimmed to 9V is correspondingly adjusted to be reduced by one gear during the CP test stage to appropriately lower the programming voltage to adapt to the process conditions of the wafer. That is, assuming that the original trim gear value of 10 gears is reduced to 9 gears, the CP test is performed on the target wafer with a trim gear value of 9 gears corresponding to the actual programming voltage of 8.8v.
[0034] refer to Figure 2 , which shows a flowchart of a method for establishing a mapping relationship provided by an exemplary embodiment of the present application, such as Figure 2 As shown, the method includes: Step S201, obtaining PCM parameters of a sample wafer.
[0035] The PCM parameters of the sample wafer are parameters obtained by performing a WAT test on a wafer acceptance test (WAT) structure on the sample wafer, and the sample wafer is a wafer used for testing and / or a wafer prepared before preparing a target wafer.
[0036] In step S201, the WAT test is to set up a test structure in the dicing area of the wafer, and then the test structure is subjected to the WAT test. The electrical parameters of the sample wafer can be measured to obtain relevant data, such as threshold voltage (VT), drain current (Id), on-resistance, etc. These data are used to monitor process fluctuations.
[0037] Exemplarily, the WAT test structure is disposed in a dicing area of a sample wafer.
[0038] For example, the WAT test structure uses a flash memory unit monitoring structure, which is preset in the cutting path of the sample wafer to monitor and obtain the PCM parameters of the sample wafer during the WAT test process.
[0039] Step S202 , dividing the value intervals according to the PCM parameters of the sample wafer.
[0040] Figure 3 The distribution of PCM parameters (VTP) of the sample wafer is shown as Figure 3 As shown in the figure, the horizontal axis is the VTP value (unit is V), and the vertical axis is the normal percentile. According to the distribution of VTP, VTP can be divided into three value intervals, namely interval 1 = (-∞, 0.7V], interval 2 = (0.7V, 0.9V), and interval 3 = [0.9V, +∞).
[0041] Step S203: setting a preset mapping relationship according to the numerical range.
[0042] As shown in Table 2, the VTP value has been divided into three intervals in step S202. The VTP distribution in interval 2 is relatively continuous. The CP test is performed on the sample wafer using the PCM parameters in this interval. The standard programming conditions for the CP test are set, that is, the VCG of the sample wafer must reach the target value after programming (the target value can be set according to the actual application. For example, in this embodiment, 9V is the target value). After the trim circuit is modulated, the programming voltage of the sample wafer reaches 9V, and the yield of the sample wafer is qualified. In this case, the trim circuit gear of the sample wafer in this interval does not need to be adjusted subsequently, and the adjustment change is 0 (the standard gear remains unchanged).
[0043] Furthermore, a CP test was performed on the sample wafer with PCM parameters in interval 1, and the standard programming conditions for the CP test were set, that is, the VCG of the sample wafer needed to reach 9V after programming. After modulation by the trim circuit, the programming voltage of the sample wafer reached 9V. The trim circuit gear at this time was recorded as the standard gear for this interval. However, insufficient yield occurred at this time. After the experiment, it was found that the initial voltage was too low and the programming degree was insufficient. It was necessary to add 1 gear to the standard trim circuit gear of the sample wafer in this interval to improve the yield. Therefore, it was concluded that the adjustment change of the trim circuit gear of the wafer in this interval was: standard gear + 1 gear.
[0044] Furthermore, a CP test was performed on the sample wafer with PCM parameters in interval 3, and the standard programming conditions for the CP test were set, that is, the VCG of the sample wafer needed to reach 9V after programming. After modulation by the trim circuit, the programming voltage of the sample wafer reached 9V. The trim circuit gear at this time was recorded as the standard gear for this interval. However, the defective rate was too high at this time. After the experiment, it was found that the initial voltage was too high and the programming voltage was too high. It was necessary to reduce the standard trim circuit gear of the sample wafer in this interval by 1 gear to reduce the defective rate. Therefore, it was concluded that the adjustment change of the trim circuit gear of the wafer in this interval was: standard gear - 1 gear. Table 2 refer to Figure 4 as well as Figure 5 , Figure 4 For wafers that have undergone standard testing in related technologies, a large number of defects may occur due to the failure to precisely control the relevant parameters of the process and testing. Figure 5For wafers with the same PCM parameters tested using the method provided in this application, it can be clearly seen that defects have been reduced and the yield has been significantly improved. The yield improvement of a single wafer varies depending on the PCM parameters, ranging from 15% to 60%. For wafers whose PCM parameters are not much different from the standard values, the yield improvement is slightly smaller; and the greater the difference between the PCM parameters and the standard values of the wafers, the greater the yield improvement; for the entire batch of wafers, the overall yield improvement can reach 40%.
[0045] refer to Figure 6 , which shows a block diagram of a computer device provided by an exemplary embodiment of the present application, the computer device is used to execute Figure 1 Example or Figure 2 Example. Figure 6 As shown, the computer device includes: a processor 301 and a memory 302.
[0046] Processor 301 may be a central processing unit (CPU), a network processor (NP), or a combination of a CPU and an NP. Processor 301 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.
[0047] Memory 302 is connected to processor 301 via a bus or other means. Memory 302 stores at least one instruction, at least one program, code set, or instruction set. Processor 301 loads and executes the at least one instruction, at least one program, code set, or instruction set to implement the wafer testing method provided in any of the above embodiments. Memory 302 can be volatile memory, non-volatile memory, or a combination thereof. Volatile memory can be random-access memory (RAM), such as static random access memory (SRAM) or dynamic random access memory (DRAM). Non-volatile memory can be read-only memory (ROM), such as programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), or electrically erasable programmable read-only memory (EEPROM). Non-volatile memory can also be flash memory, magnetic memory such as magnetic tape, floppy disk, or hard disk. Non-volatile memory can also be an optical disk.
[0048] The present application also provides a computer-readable storage medium, which stores at least one instruction, at least one program, code set or instruction set, and the at least one instruction, at least one program, code set or instruction set is loaded and executed by a processor to implement a wafer testing method as in any of the above embodiments.
[0049] The present application also provides a computer program product. When the computer program product is run on a computer, the computer is enabled to execute the wafer testing methods provided by the above-mentioned various method embodiments.
[0050] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.
Claims
1. A wafer testing method, characterized in that: include: Obtaining PCM parameters, where the PCM parameters are parameters obtained by performing a WAT test on a target wafer; According to the PCM parameters, the trim circuit gear is adjusted and determined by querying a preset mapping relationship, wherein the preset mapping relationship is a mapping relationship between the PCM parameters and their corresponding trim circuit gears; A CP test is performed on the target wafer according to the trim circuit gear.
2. The method according to claim 1, characterized in that The preset mapping relationship is a mapping relationship between the numerical ranges of different PCM parameters and their corresponding trim circuit gears; The adjusting and determining of the trim circuit gear by querying a preset mapping relationship according to the PCM parameters includes: Classifying the PCM parameters into the value intervals to which they belong; The preset mapping relationship is queried according to the corresponding numerical range to adjust and determine the trim circuit gear.
3. The method according to claim 2, characterized in that The PCM parameters include VTP or programming current, wherein the VTP is a threshold voltage after a programming operation is performed on a flash memory on a wafer, and the programming current is a leakage current after programming the flash memory.
4. The method according to claim 3, characterized in that The performing a CP test on the target wafer according to the trim circuit gear position includes: The standard programming voltage in the CP test is adjusted according to the adjusted trim circuit gear to obtain an adjusted programming voltage; A CP test is performed on the target wafer according to the adjusted programming voltage.
5. The method according to claim 4, characterized in that The programming voltage includes a control gate voltage and / or a bit line voltage.
6. The method according to claim 2, characterized in that Before getting the PCM parameters, also include: Obtaining PCM parameters of a sample wafer, where the PCM parameters of the sample wafer are parameters obtained by performing a WAT test on a WAT test structure on the sample wafer, wherein the sample wafer is a wafer used for testing and / or a wafer prepared before preparing the target wafer; Dividing the numerical intervals according to the PCM parameters of the sample wafer; The preset mapping relationship is set according to the numerical range.
7. The method according to claim 6, characterized in that The WAT test structure is arranged in a dicing area of the sample wafer.
8. A computer device, characterized in that: The computer device includes a processor and a memory, wherein the memory stores at least one instruction or program, and the instruction or program is loaded and executed by the processor to implement the wafer testing method according to any one of claims 1 to 7.
9. A computer-readable storage medium, characterized in that The storage medium stores at least one instruction, which is loaded and executed by a processor to implement the wafer testing method according to any one of claims 1 to 7.