Digital clock jitter measurement circuit and measurement method

Abstract

This application provides a digital clock jitter measurement circuit and method. The measurement circuit includes: a delay unit comprising an edge detection unit and multiple coarse-grained delay units and multiple fine-grained delay units connected in series; the delay units receive a signal to be measured and generate a first clock signal and a second clock signal; an adjustment control unit configured to adjust the delay of the second clock signal by controlling the coarse-grained and fine-grained delay units; and a measurement unit comprising a first ring oscillator, a second ring oscillator, a phase detector, and a counter. The clock jitter measurement circuit and method provided in this application can accurately measure clock jitter integrated within a chip, avoiding the inconvenience of requiring large instruments in existing technologies.

Description

Technical Field

[0001] This application relates to the field of digital circuit design, specifically to a digital clock jitter measurement circuit and measurement method. Background Technology

[0002] In high-speed digital system architectures, such as high-speed transceivers and system-on-a-chip (SoC), jitter in data and clock signals can have a significant adverse impact on system performance.

[0003] Specifically, the clock signals generated by clock generation units such as phase-locked loops (PLLs) and time-locked loops (DLLs) need to be distributed to various sub-modules via clock tree synthesis (CTS). However, due to the influence of various factors such as power supply noise, process deviations, and temperature variations, the clock signal at the clock output node may deviate from the ideal clock period, leading to circuit errors. Therefore, addressing the problems caused by jitter is a technical challenge that urgently needs to be solved by those skilled in the art.

[0004] When off-chip measurement systems perform jitter measurements, they are severely affected by the resistive-inductor-capacitor (RLC) effect, resulting in a significant loss of measurement accuracy and making it difficult to accurately reflect the actual jitter situation inside the chip. On-chip measurement systems, on the other hand, can measure jitter directly inside the chip, avoiding interference introduced by the external environment and during transmission, and ensuring that the measurement results are closer to the actual on-chip jitter state.

[0005] Therefore, there is a need to provide a circuit and method that can accurately measure digital clock jitter. Summary of the Invention

[0006] In view of this, this application provides a digital clock jitter measurement circuit and measurement method to solve the above-mentioned technical problems in the prior art.

[0007] According to one aspect of this application, a digital clock jitter measurement circuit is provided, the circuit comprising:

[0008] The delay unit includes an edge detection unit and multiple coarse-grained delay units and multiple fine-grained delay units connected in series. The delay unit receives the signal to be tested and generates a first clock signal and a second clock signal. The edge detection unit is used to detect the edges of the first clock signal and the second clock signal.

[0009] The adjustment control unit is configured to adjust the delay of the second clock signal by controlling the coarse-grained delay unit and the fine-grained delay unit;

[0010] The measurement unit includes a first ring oscillator and a second ring oscillator, a phase detector, and a counter. The inputs to the first ring oscillator and the second ring oscillator are a first clock signal and a second clock signal, respectively. The phase detector is used to detect the phase relationship between the oscillation signals in the first ring oscillator and the second ring oscillator. The counter is used to count the number of oscillations of the first ring oscillator and the second ring oscillator.

[0011] According to a preferred embodiment of this application, the adjustment control unit is configured to adjust the delay of the second clock signal based on the detection result of the edge detection unit, such that the delay of the second clock signal relative to the first clock signal is one clock cycle.

[0012] According to a preferred embodiment of this application, the delay time of a single coarse-grained delay unit is greater than the delay time of a single fine-grained delay unit; the sum of the delay times of multiple fine-grained delay units is greater than the delay time of a single coarse-grained delay unit.

[0013] According to a preferred embodiment of this application, the edge detection unit receives the clock output signal of each stage of a plurality of coarse-grained delay units and fine-grained delay units and outputs it in a tree structure.

[0014] According to a preferred embodiment of this application, the measurement unit further includes a first register and a second register. The input of the first register is a first clock signal, and the output of the first register is connected to a first ring oscillator. The input of the second register is a second clock signal, and the output of the second register is connected to a second ring oscillator.

[0015] According to a preferred embodiment of this application, the oscillation frequency of the first ring oscillator is lower than the oscillation frequency of the second ring oscillator.

[0016] According to another aspect of this application, a clock jitter measurement method is provided, which is executed by the aforementioned measurement circuit and includes the following steps:

[0017] Step S1: Set the delay path of the second clock signal to the minimum delay path;

[0018] Step S2, add a delay of one coarse-grained delay unit to the second clock signal;

[0019] Step S3: Detect the edges of the second clock signal and the corresponding first clock signal, and determine whether the second clock signal and the first clock signal have reached a locked state. If they have reached a locked state, continue to step S4; otherwise, jump to step S2.

[0020] Step S4: Reduce the delay of the second clock signal by one coarse-grained delay unit;

[0021] Step S5: Add a delay of one fine-grained delay unit to the second clock signal;

[0022] Step S6: Detect the edges of the second clock signal and the corresponding first clock signal, and determine whether the second clock signal and the first clock signal have reached a locked state. If they have reached a locked state, control the measurement unit to perform jitter measurement. If they have not reached a locked state, jump to step S5.

[0023] According to a preferred embodiment of this application, the condition for the second clock signal and the first clock signal to reach a locked state in step S3 is as follows:

[0024] The rising edge of the first clock of the current second clock signal precedes the rising edge of the first clock signal of the corresponding first clock signal; and

[0025] After adding a coarse-grained delay unit to the current second clock signal, the first rising edge of the second clock signal lags behind the first rising edge of the corresponding first clock signal.

[0026] According to a preferred embodiment of this application, the condition for the second clock signal and the first clock signal to reach a locked state in step S6 is as follows:

[0027] The rising edge of the first clock of the current second clock signal precedes the rising edge of the first clock signal of the corresponding first clock signal; and

[0028] After adding a fine-grained delay unit to the current second clock signal, the first rising edge of the second clock signal lags behind the first rising edge of the corresponding first clock signal.

[0029] According to a preferred embodiment of this application, the minimum delay path is the path that does not pass through the coarse-grained delay unit and the fine-grained delay unit is set to light load mode.

[0030] As can be seen from the above technical solutions, the measurement circuit provided in this application can be integrated inside the chip to quickly and accurately measure the jitter of the clock signal inside the chip. This avoids the limitations of existing technologies that require additional large instruments for monitoring and that it is difficult to directly bring the signal out of the chip for measurement for ultra-high frequency clock signals. Attached Figure Description

[0031] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application, but do not constitute a limitation on the technical solutions of this application.

[0032] Figure 1 A schematic diagram of the clock jitter measurement circuit of an exemplary embodiment of this application is shown;

[0033] Figure 2 A schematic diagram of the delay unit of an exemplary embodiment of this application is shown;

[0034] Figure 3 The diagram shows waveforms of a first clock signal and a second clock signal, representing an exemplary embodiment of this application.

[0035] Figure 4 A schematic diagram of the edge detection circuit of an exemplary embodiment of this application is shown;

[0036] Figure 5 The diagram shows a waveform of edge detection according to an exemplary embodiment of this application;

[0037] Figure 6 A schematic diagram of the structure of the measurement unit according to an exemplary embodiment of this application is shown;

[0038] Figure 7 A flowchart illustrating a clock jitter measurement method according to an exemplary embodiment of this application is shown. Detailed Implementation

[0039] Various exemplary embodiments of this application will now be described in detail with reference to the accompanying drawings. The descriptions of the exemplary embodiments are merely illustrative and are not intended to limit the scope of this application or its application or use. This application can be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided to make the application thorough and complete, and to fully express the scope of this application to those skilled in the art.

[0040] Unless explicitly stated otherwise, an element may be one or more unless otherwise specified. The terms “multiple / several” mean two or more, the term “based on” should be interpreted as “at least partially based on,” and the terms “and / or” and “at least one of…” cover any one of the listed items and all possible combinations thereof. Furthermore, expressions such as “first,” “second,” etc., are for descriptive purposes only and do not indicate or imply their relative importance or implicitly specify the number of technical features indicated.

[0041] refer to Figure 1 This illustrates a schematic diagram of the clock jitter measurement circuit according to an exemplary embodiment of this application. Figure 1 As shown, the clock jitter measurement circuit can receive the input clock signal CK_IN and measure the jitter of the input clock signal CK_IN to generate a jitter output signal J_OUT. The digital clock jitter measurement circuit includes: a delay unit, an adjustment control unit, and a measurement unit.

[0042] The delay unit includes an edge detection unit and multiple coarse-grained delay units and multiple fine-grained delay units connected in series. The delay unit receives the input clock signal CK_IN to generate a first clock signal CK1 and a second clock signal CK2. The delay unit generates a phase detection output signal PD_O through the edge detection unit. The adjustment control unit outputs a coarse-grained delay selection signal SEL_C and a fine-grained delay selection signal SEL_F based on the phase detection output signal PD_O, thereby controlling the coarse-grained and fine-grained delay units to adjust the delay of the second clock signal. When a phase-locked state is reached, the measurement unit receives the first clock signal CK1 and the second clock signal CK2 generated by the delay unit and outputs a jitter output signal J_OUT.

[0043] refer to Figure 2 This illustrates a schematic diagram of the delay unit according to an exemplary embodiment of this application. Figure 2 As shown, the delay unit includes multiple coarse-grained delay units ("M") and multiple fine-grained delay units ("N") connected in series. The delay time of a single coarse-grained delay unit is greater than the delay time of a single fine-grained delay unit, and the sum of the maximum delay times of the N fine-grained delay units is greater than the maximum delay time of a single coarse-grained delay unit. The coarse-grained delay unit receives the clock signal to be tested CK_IN, and each of the M coarse-grained delay units can generate a second clock signal C_CK2[1] to C_CK2[M] delayed by the coarse-grained delay unit, and a corresponding first clock signal C_CK1[1] to C_CK1[M] not delayed by the coarse-grained delay unit. The fine-grained delay unit receives the first clock signal C_CK1[M] and the second clock signal C_CK2[M] from the last coarse-grained delay unit. Each of the N fine-grained delay units can generate a second clock signal F_CK2[1] to F_CK2[N] delayed by the fine-grained delay unit, and a first clock signal F_CK1[1] to F_CK1[N] not delayed by the fine-grained delay unit. The edge detection unit receives the first clock signal and the second clock signal generated by each stage of the coarse-grained delay unit and the fine-grained delay unit to obtain the phase detection output signal PD_O. The automatic adjustment control unit adjusts and outputs the coarse-grained delay selection signal SEL_C and the fine-grained delay selection signal SEL_F in sequence according to the phase detection output signal PD_O. The embodiments of this application do not limit the circuit structure of the coarse-grained delay unit and the fine-grained delay unit. For example, coarse-grained delay units can use vernier delay chains of fine-grained delay units, and fine-grained delay units can use buffer delay chains of coarse-grained delay units.

[0044] refer to Figure 3The diagram illustrates the waveforms of the first clock signal C_CK1 and the second clock signal C_CK2 of the coarse-grained delay unit, and the first clock signal F_CK1 and the second clock signal F_CK2 of the fine-grained delay unit in embodiments of this application. Figure 3 As shown, the propagation delay length of a single delay module in the coarse-grained delay unit is Δt1, and the minimum adjustable delay step is... Figure 2 The length of the delay unit composed of multiple buffers is shown. This application embodiment does not limit the structure and number of delay units in the coarse-grained delay unit; for example, the delay unit can be composed of buffers or other combinational logic. The propagation delay length of the first clock signal F_CK1 in the fine-grained delay unit is Δt2, and the propagation delay length of the second clock signal F_CK2 in the fine-grained delay unit is Δt3. Therefore, the propagation delay length of a single delay module in the fine-grained delay unit is Δt3 - Δt2, and the minimum adjustable delay step is... Figure 2 The time difference between turning on and off a single stage of a switching load.

[0045] refer to Figure 4 This diagram illustrates a structural schematic of an edge detection circuit according to an exemplary embodiment of this application. The edge detection circuit is used to implement... Figure 2 The edge detection unit is shown in the image. For example... Figure 4 As shown, the edge detection circuit receives the first clock signal and the second clock signal generated by each stage of the coarse-grained delay unit and the fine-grained delay unit, and generates a phase detection output signal PD_O. This application embodiment does not limit the tree structure and hierarchy of the edge detection circuit.

[0046] refer to Figure 5The diagram illustrates a waveform of edge detection according to an exemplary embodiment of this application. In this embodiment, the condition for the phase detection output signal PD_O to be pulled high 207 (i.e., the condition for satisfying the locked state) is that the first rising edge 203 of the second clock signal C_CK2[k] of the coarse-grained adjustment unit leads the second rising edge 202 of the first clock signal C_CK1[k] of the coarse-grained adjustment unit, or the first rising edge 203 of the second clock signal F_CK2[k] of the k-th stage of the fine-grained adjustment unit leads the first clock signal F_CK1[k] of the k-th stage of the fine-grained adjustment unit. The second rising edge of clock signal C_CK2[k+1] of the coarse-grained adjustment unit 202; the first rising edge of clock signal C_CK2[k+1] of the k+1 level of the coarse-grained adjustment unit 206 lags behind the second rising edge of clock signal C_CK1[k+1] of the k+1 level of the coarse-grained adjustment unit 205, or the first rising edge of clock signal F_CK2[k+1] of the k+1 level of the fine-grained adjustment unit 206 leads the second rising edge of clock signal F_CK1[k+1] of the k+1 level of the fine-grained adjustment unit 205. Figure 5 The first rising edge of the clock for C_CK1[k] or F_CK1[k] is marked as 201, and the first rising edge of the clock for C_CK1[k+1] or F_CK1[k+1] is marked as 204.

[0047] refer to Figure 6 This illustrates a schematic diagram of the structure of a measurement unit according to an exemplary embodiment of this application. Figure 6As shown, the measurement unit includes a first register, a second register, a first ring oscillator 301 and a second ring oscillator 302 with different oscillation frequencies, a phase detector, and a counter. The input of the first register is the first clock signal, and the output of the first register is connected to the first ring oscillator. The input of the second register is the second clock signal, and the output of the second register is connected to the second ring oscillator. The inputs of the first ring oscillator and the second ring oscillator are respectively connected to the first clock signal and the second clock signal. The oscillation frequency of the first ring oscillator is F1, and the oscillation frequency of the second ring oscillator is F2. It is required that the oscillation frequency of the first ring oscillator is lower than that of the second ring oscillator, that is, F1 < F2. The phase detector is used to detect the phase relationship between the clock signals generated by the two oscillators. For example, at the beginning, the phase of the clock signal oscillated by the first ring oscillator is ahead of the phase of the clock signal oscillated by the second ring oscillator. When the phase of the clock oscillated by the first ring oscillator lags behind the phase of the clock oscillated by the second ring oscillator, the phase detector will control the two oscillators to stop oscillating, and the counter records the number of oscillations N of the oscillators. The output jitter value J_OUT = N(1 / F2 - 1 / F1). By counting the number of oscillations in each measurement process, the clock jitter information of the signal to be measured can be obtained.

[0048] Reference Figure 7 , which shows a flowchart of the clock jitter measurement method according to an exemplary embodiment of the present application. This clock jitter measurement method is executed by the measurement circuit described above. The measurement method includes the following steps:

[0049] Step S1, set the delay path of the second clock signal to the minimum delay path;

[0050] Step S2, add a delay of a coarse granularity delay unit to the second clock signal;

[0051] Step S3, detect the edges of the second clock signal and the corresponding first clock signal, and determine whether the second clock signal and the first clock signal reach the locked state. If the locked state is reached, continue to execute Step S4; if the locked state is not reached, jump to Step S2;

[0052] Step S4, subtract a delay of a coarse granularity delay unit from the second clock signal;

[0053] Step S5, add a delay of a fine granularity delay unit to the second clock signal;

[0054] Step S6, detect the edges of the second clock signal and the corresponding first clock signal, and determine whether the second clock signal and the first clock signal reach the locked state. If the locked state is reached, control the measurement unit to execute Step S7 of jitter measurement; if the locked state is not reached, jump to Step S5.

[0055] In step S1, the minimum delay path is the path that does not pass through the coarse-grained delay unit (the coarse-grained delay unit sets a selector signal to select a path without a delay unit) and the fine-grained delay unit is set to light load mode.

[0056] In step S2, a coarse-grained delay unit is set so that the second clock signal has an additional delay of one coarse-grained delay unit.

[0057] In step S3, the phase relationship between the first clock signal and the second clock signal is determined by the output signal PD_O of the edge detection unit to whether the phase relationship meets the locking condition. If the phase relationship between the first clock signal and the second clock signal does not meet the locking condition, the process jumps to step S2, and the automatic adjustment unit gradually increases the delay length of the second clock signal by the coarse-grained delay unit. If the phase relationship between the first clock signal and the second clock signal meets the locking condition, step S4 is executed. The condition for the second clock signal and the first clock signal to reach the locking condition is: the first rising edge of the current second clock signal leads the first rising edge of the corresponding first clock signal; and after adding a delay of one coarse-grained delay unit to the current second clock signal, the first rising edge of the second clock signal lags the first rising edge of the corresponding first clock signal.

[0058] In step S4, the automatic adjustment unit restores the coarse-grained delay unit configuration to the state where phase locking was not satisfied in the previous step, even if the second clock signal reduces the delay of one coarse-grained delay unit.

[0059] In step S5, the fine-grained delay unit delays the second clock signal, thereby increasing the delay of the second clock signal by the amount of a fine-grained delay unit.

[0060] In step S6, the phase relationship between the first clock signal and the second clock signal is determined by the output signal PD_O of the edge detection unit to whether the phase relationship meets the locking condition. If the phase relationship between the first clock signal and the second clock signal does not meet the locking condition, the process jumps to step S5, and the automatic adjustment unit gradually increases the delay length of the second clock signal by the fine-grained delay unit. If the phase relationship between the first clock signal and the second clock signal does not meet the locking condition, step S7 is executed. The condition for the second clock signal and the first clock signal to reach the locking condition is: the first rising edge of the current second clock signal leads the first rising edge of the corresponding first clock signal; and after adding a delay of one fine-grained delay unit to the current second clock signal, the first rising edge of the second clock signal lags the first rising edge of the corresponding first clock signal.

[0061] In step S7, the measurement unit measures the jitter information of the clock signal based on the first clock signal and the second clock signal.

[0062] The technical solutions described in this application can be supported by various configurations of the electronic device 300, and are not limited to the specific examples of the technical solutions described in this application. The descriptions and illustrations provided in the foregoing and accompanying drawings are not restrictive. It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the scope of protection claimed in this application is defined by the claims rather than the foregoing description, and all variations falling within the meaning and scope of equivalent requirements of the claims are covered within the scope of protection of this application.

Claims

1. A clock jitter measurement method, the method being executed by a digital clock jitter measurement circuit, the measurement circuit comprising: The delay unit includes an edge detection unit and multiple coarse-grained delay units and multiple fine-grained delay units connected in series. The delay unit receives the signal to be tested and generates a first clock signal and a second clock signal. The edge detection unit is used to detect the edges of the first clock signal and the second clock signal. The adjustment control unit is configured to adjust the delay of the second clock signal by controlling the coarse-grained delay unit and the fine-grained delay unit; The measurement unit includes a first ring oscillator and a second ring oscillator, a phase detector, and a counter. The inputs to the first and second ring oscillators are a first clock signal and a second clock signal, respectively. The phase detector is used to detect the phase relationship between the oscillation signals in the first and second ring oscillators. The counter is used to count the number of oscillations of the first and second ring oscillators. The method is characterized by comprising the following steps: Step S1: Set the delay path of the second clock signal to the minimum delay path; Step S2, add a delay of one coarse-grained delay unit to the second clock signal; Step S3: Detect the edges of the second clock signal and the corresponding first clock signal, and determine whether the second clock signal and the first clock signal have reached a locked state. If they have reached a locked state, continue to step S4; otherwise, jump to step S2. Step S4: Reduce the delay of the second clock signal by one coarse-grained delay unit; Step S5: Add a delay of one fine-grained delay unit to the second clock signal; Step S6: Detect the edges of the second clock signal and the corresponding first clock signal, and determine whether the second clock signal and the first clock signal have reached a locked state. If they have reached a locked state, control the measurement unit to perform jitter measurement. If they have not reached a locked state, jump to step S5.

2. The method according to claim 1, characterized in that, The condition for the second clock signal to reach a locked state with the first clock signal in step S3 is: The rising edge of the first clock of the current second clock signal precedes the rising edge of the first clock signal of the corresponding first clock signal; and After adding a coarse-grained delay unit to the current second clock signal, the first rising edge of the second clock signal lags behind the first rising edge of the corresponding first clock signal.

3. The method according to claim 1, characterized in that, The condition for the second clock signal to reach a locked state with the first clock signal in step S6 is: The rising edge of the first clock of the current second clock signal precedes the rising edge of the first clock signal of the corresponding first clock signal; and After adding a fine-grained delay unit to the current second clock signal, the first rising edge of the second clock signal lags behind the first rising edge of the corresponding first clock signal.

4. The method according to claim 1, characterized in that, The minimum delay path is the path that does not pass through coarse-grained delay units and when fine-grained delay units are set to light-load mode.

5. The method according to claim 1, characterized in that, The adjustment control unit is configured to adjust the delay of the second clock signal according to the detection result of the edge detection unit, such that the delay of the second clock signal relative to the first clock signal is one clock cycle.

6. The method according to claim 1, characterized in that, The delay time of a single coarse-grained delay unit is greater than the delay time of a single fine-grained delay unit; the sum of the delay times of the multiple fine-grained delay units is greater than the delay time of a single coarse-grained delay unit.

7. The method according to claim 1, characterized in that, The edge detection unit receives the clock output signal of each stage of the plurality of coarse-grained delay units and the fine-grained delay units and outputs it in a tree structure.

8. The method according to claim 1, characterized in that, The measurement unit further includes a first register and a second register. The input of the first register is a first clock signal, and the output of the first register is connected to a first ring oscillator. The input of the second register is a second clock signal, and the output of the second register is connected to a second ring oscillator.

9. The method according to claim 1, characterized in that, The oscillation frequency of the first ring oscillator is lower than that of the second ring oscillator.

Images