A digital port direct sampling single-bit radar system, method, terminal and computer readable storage medium

Abstract

The application discloses a kind of digital port direct sampling single-bit radar systems, methods, terminal and computer readable storage medium, the system includes digital signal processing chip, transmitting link, receiving link, automatic gain control circuit, voltage bias circuit and digital potentiometer;The digital signal processing chip is connected with the transmitting link, the transmitting link is connected with the automatic gain control circuit, the digital potentiometer is connected with the digital signal processing chip and the automatic gain control circuit respectively, and the voltage bias circuit is connected with the automatic gain control circuit and the digital signal processing chip respectively;Single-bit data is collected by single-bit radar system of digital port direct sampling.The single-bit radar system presented in the application directly realizes single-bit sampling quantization to radar echo signal through digital port, without special ADC chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of signal processing, and particularly relates to a digital port direct sampling single-bit radar system, method, terminal and computer readable storage medium. BACKGROUND

[0002] In a traditional radar system, a high-precision, high-sampling-rate ADC (Analog to Digital Converter) is usually used to sample a radar echo signal. However, as the radar signal bandwidth and data volume increase, higher performance requirements are put forward for the ADC, which is not conducive to the miniaturization, low cost and low power consumption design of the radar system. In order to solve the deficiencies of the traditional ADC sampling scheme in terms of hardware complexity and power consumption, at present, a single-bit quantization technology is used to realize real-time sampling of the radar echo signal. The single-bit quantization method greatly reduces the data volume of the system by only retaining the sign information of the analog signal.

[0003] However, the current single-bit sampling quantization scheme is simplified compared with the traditional ADC sampling scheme, but still needs an external comparator, resulting in a still relatively complex overall hardware structure, which is not conducive to further miniaturization and low power consumption application requirements.

[0004] Therefore, the prior art still needs to be improved and developed. SUMMARY

[0005] The main purpose of the present application is to provide a digital port direct sampling single-bit radar system, method, terminal and computer readable storage medium, which aims to solve the problem that the single-bit sampling quantization scheme in the prior art still needs an external comparator, resulting in a still relatively complex overall hardware structure, which is not conducive to further miniaturization and low power consumption application requirements.

[0006] To achieve the above-mentioned purpose, the present application provides a digital port direct sampling single-bit radar system, which comprises a digital signal processing chip, a transmit chain, a receive chain, an automatic gain control circuit, a voltage bias circuit and a digital potentiometer.

[0007] The digital signal processing chip is connected with the transmit chain, and is used to generate a linear frequency modulation signal waveform and output to the transmit chain. The transmit chain is used to process the linear frequency modulation signal waveform, generate a radar signal, and transmit.

[0008] The transmit chain is connected with the automatic gain control circuit, the digital potentiometer is connected with the digital signal processing chip and the automatic gain control circuit respectively, and the voltage bias circuit is connected with the automatic gain control circuit and the digital signal processing chip respectively.

[0009] The receiving link is configured to receive a radar echo signal, process the radar echo signal to obtain a first intermediate frequency signal, and input the first intermediate frequency signal to the automatic gain control circuit.

[0010] The automatic gain control circuit is configured to generate an amplitude adjustment gain according to a digital potentiometer, perform amplitude adjustment on the first intermediate frequency signal to obtain a second intermediate frequency signal, and input the second intermediate frequency signal to the voltage bias circuit.

[0011] The voltage bias circuit is configured to process the second intermediate frequency signal according to an operational amplifier to obtain a target unipolar signal.

[0012] The digital signal processing chip is further configured to perform single-bit sampling quantization on the target unipolar signal to obtain single-bit data and input the single-bit data to an upper computer.

[0013] Optionally, the digital signal processing chip comprises a first port, a second port, a preset number of third ports, and a fourth port.

[0014] The first port is configured to output a linear frequency modulation signal waveform generated according to a direct digital synthesis module to the transmitting link.

[0015] The second port is configured to generate an adjustment voltage gain according to a target communication protocol, control the digital potentiometer to generate an amplitude adjustment gain according to the adjustment voltage gain, and send the amplitude adjustment gain to the automatic gain control circuit.

[0016] The third port is configured to receive the target unipolar signal into the digital signal processing chip for single-bit sampling quantization.

[0017] The fourth port is configured to transmit the single-bit data to the upper computer in real time.

[0018] Optionally, the digital signal processing chip further comprises a Schmitt trigger structure.

[0019] The Schmitt trigger structure stores a high-level threshold value and a low-level threshold value, the third port receives the target unipolar signal into the digital signal processing chip, and the digital signal processing chip performs single-bit sampling quantization on the target unipolar signal according to the high-level threshold value and the low-level threshold value in the Schmitt trigger structure to obtain single-bit data.

[0020] In addition, to achieve the above-mentioned purpose, the application further provides a digital port direct sampling method of a single-bit radar system based on digital port direct sampling, which comprises:

[0021] Based on the digital signal processing chip, a linear frequency modulation waveform is generated, the linear frequency modulation waveform is processed according to the transmitting chain, a radar signal is obtained, and the radar signal is transmitted;

[0022] According to the receiving chain, a radar echo signal is received and processed to obtain a first intermediate frequency signal;

[0023] According to the automatic gain control circuit, the first intermediate frequency signal is amplitude adjusted to obtain a second intermediate frequency signal, and according to the voltage bias circuit, the second intermediate frequency signal is signal converted to obtain a target unipolar signal;

[0024] According to the digital signal processing chip, the target unipolar signal is single-bit sampled and quantized to obtain single-bit data, and the single-bit data is sent to an upper computer.

[0025] Optionally, the transmitting chain includes an analog-to-digital converter, a first mixer, a power amplifier, and a transmitting antenna;

[0026] The generating, by the digital signal processing chip, of a linear frequency modulation waveform, the processing, according to the transmitting chain, of the linear frequency modulation waveform, the obtaining of a radar signal, and the transmitting of the radar signal are specifically as follows:

[0027] The generating, by the digital signal processing chip, of a linear frequency modulation waveform;

[0028] The processing, by the analog-to-digital converter, of the linear frequency modulation waveform to obtain an analog signal;

[0029] The up-conversion, by the first mixer, of the analog signal to obtain a target frequency band analog signal;

[0030] The amplification, by the power amplifier, of the target frequency band analog signal to obtain the radar signal, and the transmitting of the radar signal by the transmitting antenna.

[0031] Optionally, the receiving chain includes a receiving antenna, a low-noise amplifier, a second mixer, and a band-pass filter circuit;

[0032] The receiving, according to the receiving chain, of a radar echo signal and the processing of the radar echo signal to obtain a first intermediate frequency signal specifically include:

[0033] The receiving, by the receiving antenna, of a radar echo signal;

[0034] The preliminary amplification, by the low-noise amplifier, of the radar echo signal to obtain an amplified radar echo signal;

[0035] The down-conversion, by the second mixer, of the amplified radar echo signal to obtain an intermediate frequency signal;

[0036] The intermediate frequency signal is cleared of interference signals by the band-pass filter circuit to obtain the first intermediate frequency signal.

[0037] Optionally, the single-bit sampling quantization of the target unipolar signal according to the digital signal processing chip comprises:

[0038] According to the third communication port in the digital signal processing chip, the target unipolar signal is received and sampled to obtain corresponding sampling data.

[0039] According to the two-stage flip-flop in the digital signal processing chip, all the sampling data are synchronized to the main processing clock domain and sorted to obtain single-bit data.

[0040] In addition, to achieve the above object, the application further provides a terminal, wherein the terminal comprises a memory, a processor and a digital port direct sampling program stored in the memory and executable on the processor, and the digital port direct sampling program implements the steps of the digital port direct sampling method when executed by the processor.

[0041] In addition, to achieve the above object, the application further provides a computer readable storage medium, wherein the computer readable storage medium stores a digital port direct sampling program, and the digital port direct sampling program implements the steps of the digital port direct sampling method when executed by a processor.

[0042] The digital port direct sampling single-bit radar system in the application comprises a digital signal processing chip, a transmitting link, a receiving link, an automatic gain control circuit, a voltage bias circuit and a digital potentiometer; the digital signal processing chip is connected with the transmitting link, and is used for generating a linear frequency modulation signal waveform and outputting to the transmitting link; the transmitting link is used for processing the linear frequency modulation signal waveform, generating a radar signal and transmitting; the transmitting link is connected with the automatic gain control circuit, the digital potentiometer is connected with the digital signal processing chip and the automatic gain control circuit respectively, and the voltage bias circuit is connected with the automatic gain control circuit and the digital signal processing chip respectively; wherein the receiving link is used for receiving a radar echo signal, processing the radar echo signal, obtaining a first intermediate frequency signal and inputting to the automatic gain control circuit; the automatic gain control circuit is used for adjusting the amplitude of the first intermediate frequency signal according to the amplitude gain generated by the digital potentiometer, obtaining a second intermediate frequency signal and inputting to the voltage bias circuit; the voltage bias circuit is used for processing the second intermediate frequency signal according to an operational amplifier, obtaining a target single polarity signal; the digital signal processing chip is further used for single-bit sampling and quantizing the target single polarity signal, obtaining single-bit data and inputting to an upper computer. The application directly samples and quantizes the radar echo signal based on the Schmidt trigger characteristics of the digital signal processing chip port, saves the dependence on ADC or a comparator in the traditional radar system, and through the system, the data amount of the radar system can be greatly reduced, the hardware structure can be significantly simplified, and thus a highly integrated, low-cost single-bit radar microsystem is constructed. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 is a structure diagram of a preferred embodiment of the digital port direct sampling single-bit radar system of the application;

[0044] Figure 2 is a flow framework diagram of the implementation of the digital port direct sampling single-bit radar system of the application;

[0045] Figure 3 is a single digital port direct single-bit sampling schematic diagram;

[0046] Figure 4 is a multi-channel digital port staggered high-speed single-bit sampling schematic diagram in the digital port direct sampling single-bit radar system of the application;

[0047] Figure 5 is a spectrum diagram after sampling of a single target echo signal using a comparator;

[0048] Figure 6is the spectrum diagram of the single target echo signal sampled by the port direct sampling scheme of the digital port direct sampling single-bit radar system of the present application;

[0049] Figure 7 is the pulse compression result diagram of the single target echo signal sampled by the comparator;

[0050] Figure 8 is the pulse compression result diagram of the single target echo signal sampled by the port direct sampling scheme of the present application in the digital port direct sampling single-bit radar system of the present application;

[0051] Figure 9 is the pulse compression result diagram of the multiple target echo signals sampled by the comparator;

[0052] Figure 10 is the pulse compression result diagram of the multiple target echo signals sampled by the port direct sampling scheme of the present application in the digital port direct sampling single-bit radar system of the present application;

[0053] Figure 11 is the result of the two-dimensional imaging of the multiple echo signals sampled by the port direct sampling scheme of the present application in the digital port direct sampling single-bit radar system of the present application;

[0054] Figure 12 is the flow chart of the preferred embodiment of the digital port direct sampling method of the present application;

[0055] Figure 13 is the structure diagram of the preferred embodiment of the terminal of the present application. DETAILED DESCRIPTION

[0056] In order to make the purpose, technical scheme and advantages of the present application more clear and explicit, the present application is further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0057] In a traditional radar system, a high-precision and high-sampling-rate ADC is usually used to sample the radar echo signal. However, with the increase of the radar signal bandwidth and data volume, higher performance requirements are put forward for the ADC, which is not conducive to the miniaturization, low cost and low power consumption design of the radar system. The existing single-bit sampling quantization scheme is still based on the traditional radar hardware architecture and fails to design a single-bit signal processing chain, which cannot effectively support the design of a single-bit radar microsystem. In addition, the comparator circuit method is used to realize single-bit quantization at the present stage. Compared with the traditional ADC sampling scheme, this method is simplified, but still needs an external comparator and does not fully utilize the hardware characteristics of the digital signal processing chip port (i.e. IO port), so there is still room for optimization in the hardware complexity of the system design. The single-bit quantization technology is used to realize real-time sampling of the radar echo signal. The single-bit quantization method greatly reduces the data volume of the system by only retaining the sign information of the analog signal. However, compared with the traditional ADC sampling scheme, the current single-bit sampling quantization scheme is simplified, but still needs an external comparator, resulting in a relatively complex overall hardware structure, which is not conducive to further miniaturization and low power consumption application requirements.

[0058] To solve one or more of the above problems, the present application provides a digital port direct sampling single-bit radar system, which comprises a digital signal processing chip, a transmit chain, a receive chain, an automatic gain control circuit, a voltage bias circuit and a digital potentiometer. The digital signal processing chip is connected with the transmit chain, and is used to generate a linear frequency modulation signal waveform and output to the transmit chain. The transmit chain is used to process the linear frequency modulation signal waveform, generate a radar signal and transmit. The transmit chain is connected with the automatic gain control circuit. The digital potentiometer is connected with the digital signal processing chip and the automatic gain control circuit respectively. The voltage bias circuit is connected with the automatic gain control circuit and the digital signal processing chip respectively. The receive chain is used to receive a radar echo signal, process the radar echo signal, obtain a first intermediate frequency signal and input to the automatic gain control circuit. The automatic gain control circuit is used to generate an adjusted amplitude gain according to the digital potentiometer, adjust the amplitude of the first intermediate frequency signal to obtain a second intermediate frequency signal and input to the voltage bias circuit. The voltage bias circuit is used to process the second intermediate frequency signal according to an operational amplifier to obtain a target unipolar signal. The digital signal processing chip is further used to perform single-bit sampling quantization on the target unipolar signal to obtain single-bit data and input to an upper computer.

[0059] The digital port direct sampling single-bit radar system of the preferred embodiment of the present application has the advantages of Figure 1As shown, the digital port direct sampling single-bit radar system comprises a digital signal processing chip, a transmitting link, a receiving link, an automatic gain control circuit, a voltage bias circuit and a digital potentiometer;

[0060] The digital signal processing chip is connected with the transmitting link, and is used to generate a linear frequency modulation signal waveform and output to the transmitting link.

[0061] The transmitting link is connected with the automatic gain control circuit, the digital potentiometer is connected with the digital signal processing chip and the automatic gain control circuit respectively, and the voltage bias circuit is connected with the automatic gain control circuit and the digital signal processing chip respectively.

[0062] The receiving link is used to receive a radar echo signal, process the radar echo signal to obtain a first intermediate frequency signal, and input to the automatic gain control circuit.

[0063] The automatic gain control circuit is used to generate an adjusted amplitude gain according to the digital potentiometer, and perform amplitude adjustment on the first intermediate frequency signal to obtain a second intermediate frequency signal and input to the voltage bias circuit.

[0064] The voltage bias circuit is used to process the second intermediate frequency signal according to the operational amplifier to obtain a target single polarity signal.

[0065] The digital signal processing chip is further used to perform single-bit sampling quantization on the target single polarity signal to obtain single-bit data and input to an upper computer.

[0066] The transmitting link comprises an analog-to-digital converter, a first mixer, a power amplifier and a transmitting antenna, and the receiving link comprises a receiving antenna, a low noise amplifier, a second mixer and a band-pass filter circuit.

[0067] Specifically, in the present application, the digital port direct sampling single-bit radar system comprises a digital signal processing chip, an analog-to-digital converter, a first mixer, a power amplifier, a transmitting antenna, a receiving antenna, a low noise amplifier, a second mixer, a band-pass filter circuit, an automatic gain control circuit, a voltage bias circuit and a digital potentiometer, so as to realize a lightweight, low-cost single-bit radar system architecture through these components.

[0068] As shown in the figure, Figure 2 In the present application, the digital signal processing chip generates a radar signal through the DAC, the first mixer and the power amplifier and transmits, and then realizes acquisition, storage and forwarding of single-bit data after receiving and processing the radar echo signal.

[0069] Specifically, in the single-bit radar system with direct sampling at the digital port of this invention, a linear frequency modulated signal waveform is first generated using a digital synthesis (DDS) module implemented within the digital signal processing chip. This waveform is then output as an analog signal via a DAC (analog-to-digital converter). The analog signal is then up-converted to the radar operating frequency band by a first mixer. Finally, a power amplifier drives the antenna to transmit the radar signal. The expression for the transmitted radar signal is:

[0070] ;

[0071] in, For radar signals, For the corresponding signal amplitude, Let be a rectangular function, representing the envelope of the signal. The pulse width. For radar carrier frequency, For frequency modulation slope, To save time.

[0072] Subsequently, the single-bit radar system with direct sampling via digital port receives the radar echo signal reflected from the target object through the antenna. The frequency of the received signal is within the radar's own operating frequency band, and the expression for the received radar echo signal is:

[0073] ;

[0074] in, For radar echo signals, For the corresponding signal amplitude, This is to account for the transmission delay.

[0075] Due to factors such as target distance, reflection characteristics, and environmental noise, the radar echo signal received by a single-bit radar system using direct sampling at the digital port has a relatively small amplitude, insufficient for subsequent processing. Therefore, the radar echo signal is initially amplified by a low-noise amplifier. After entering the amplifier, the signal passes through an impedance matching network and is then amplified by a low-noise transistor circuit, while simultaneously suppressing noise to the maximum extent possible. This process significantly improves the signal-to-noise ratio of the echo signal while minimizing the introduction of additional noise.

[0076] The high-frequency signal, after passing through a low-noise amplifier (i.e., the amplified radar echo signal), is input into a second mixer for down-conversion to obtain an intermediate frequency (IF) signal. The IF signal is easier to sample and quantize in subsequent processing. This process involves comparing the echo signal with the local oscillator signal. Multiplication mixing is performed, where the frequency of the local oscillator signal is... The expression of the intermediate frequency signal is as follows:

[0077] ;

[0078] Wherein, The intermediate frequency signal, The corresponding signal amplitude, The fixed phase term.

[0079] The intermediate frequency signal is input into a band-pass filter to filter out stray interference signals and out-of-band noise. After the intermediate frequency signal is input into the band-pass filter, the frequency components within the passband range will pass without significant attenuation, while the frequency components below or above the passband range will be rapidly attenuated or blocked, i.e. only the effective frequency components within the passband range are retained, thereby obtaining the corresponding first intermediate frequency signal.

[0080] Since the first intermediate frequency signal usually has a large dynamic range, there may be a situation where the voltage is not compatible with the digital signal processing chip port level. If it is directly connected to the digital port, the following three problems may occur: (1) the voltage is too low, in which case the IO port may always be recognized as a low level state; (2) the voltage exceeds the maximum input range of the port voltage, in which case there is a risk of damage to the chip port; (3) the level cannot cross the high and low level threshold of the Schmitt trigger, in which case the single-bit signal sampled is always 0 or always 1, losing effective information.

[0081] In view of the above three cases, the application introduces an automatic gain control circuit and a voltage bias circuit before sampling of the digital signal processing chip, so that the overall amplitude of the intermediate frequency signal is adjusted to within the voltage range that can be recognized by the digital signal processing chip port. The automatic gain control circuit supports dynamic gain adjustment of the amplitude of the input first intermediate frequency signal to obtain a second intermediate frequency signal, i.e. the amplitude adjustment is performed by the automatic gain control circuit constructed by the operational amplifier, to ensure that the amplitude of the input signal is controlled within a range suitable for subsequent voltage bias processing (e.g. -1.65V~+1.65V), and the gain is determined by external digital control.

[0082] Specifically, an adjustable resistance voltage division structure of an op-amp feedback network is constructed in a digital potentiometer, and the digital signal processing chip in the single-bit radar system directly sampled by the digital port adjusts the resistance value of the digital potentiometer in real time through the SPI communication protocol, thereby realizing dynamic adjustment of the amplitude of the output signal and obtaining the corresponding second intermediate frequency signal.

[0083] After obtaining the second intermediate frequency signal, it is input into the voltage bias circuit, and the same-phase addition structure constructed by the operational amplifier is used to shift the entire bipolar signal and convert it into a unipolar signal between 0 and 3.3V, i.e. the target unipolar signal.

[0084] According to the IO level standard of LVCMOS33, the typical input voltage recognition range of the IO port is 0V to 3.3V, and the maximum input voltage allowed is the minimum is and generally is -0.3V to 3.6V; in the default state, the automatic gain control circuit and the voltage bias circuit of the present application will adjust the input intermediate frequency signal amplitude to the standard amplitude range (i.e. 0V~3.3V), at this time the amplitude amplification coefficient is defined as 1; when it is needed to maintain the signal near the high and low level threshold of the Schmitt trigger for a longer time ratio, the amplification coefficient can be increased to make the signal slightly exceed the normal recognition range of the LVCMOS33 level standard, but still remain within the allowed input voltage interval; and through the over-saturation processing, the stability of the signal recognized as a logic level by the IO port can be improved, thereby effectively alleviating the information loss or misjudgment problem caused by the signal amplitude being in the middle of the high and low level threshold.

[0085] After obtaining the corresponding target unipolar signal, the amplitude thereof has been stably controlled within the voltage range allowed by the IO port of the digital signal processing chip, and then sampling is performed through the digital signal processing chip. The present application does not use traditional ADC or comparator for sampling, but directly uses the IO port to complete the single-bit sampling and quantization of the radar intermediate frequency analog signal, thereby constructing an extremely simple radar signal sampling architecture.

[0086] Specifically, the digital signal processing chip further comprises a Schmitt trigger structure.

[0087] The Schmitt trigger structure stores a high level threshold and a low level threshold, the third port receives the target unipolar signal into the digital signal processing chip, and the digital signal processing chip performs single-bit sampling and quantization on the target unipolar signal according to the high level threshold and the low level threshold in the Schmitt trigger structure, to obtain single-bit data.

[0088] As Figure 3As shown, in order to improve the anti-interference ability of the input signal and avoid misjudgment caused by level jitter, the digital signal processing chip port usually has a built-in Schmitt trigger structure. The Schmitt trigger is essentially a comparator with hysteresis, and its electrical characteristics include a certain high-level threshold and low-level threshold, which can be used to realize single-bit sampling quantization. When the external input analog signal voltage is greater than the high-level threshold, the IO port recognizes as a logic high level (i.e. "1"); when the external input analog signal voltage is less than the low-level threshold, the IO port recognizes as a logic low level (i.e. "0"); when the external input analog signal voltage is in the intermediate state between the high-level threshold and the low-level threshold, the IO port recognizes the level consistent with the previous state, thereby avoiding frequent high-low jumps in this unstable voltage interval. Specifically at the hardware implementation level, the single-bit sampling rate of the IO port is mainly limited by the clock frequency of the digital signal processing chip and the response ability of the port structure. For example, in FPGA (Field Programmable Gate Array, Field Programmable Gate Array), the IO port can be directly driven by a high-frequency system clock to achieve a sampling rate of hundreds of MHz or more, meeting the sampling requirements of most radar signal bandwidths.

[0089] Further, let , be the high and low level thresholds of the Schmitt trigger, when the target monopole signal is input to the IO port, the logic level state recognized by the IO port is as follows:

[0090] ;

[0091] wherein, is the previous logic level state of the IO port.

[0092] Let a single IO port sample the level value recognized by the IO port at a sampling period , then the discrete sampling points can be represented as:

[0093] ;

[0094] wherein, is the discrete time index, indicating the sampling time, is the logic level state recognized by the IO port, is the sampling period of the IO port, is a single-bit time sequence, i.e. the result of single-bit sampling quantization of the radar echo intermediate frequency signal.

[0095] The Schmitt trigger structure in the digital signal processing chip port is used to directly sample the radar signal by one bit, so that the traditional ADC and comparator are omitted, the complex analog-digital conversion circuit and peripheral modules are no longer needed, the high-speed sampling of the radar signal can be directly realized, and the one-bit data can be quickly transmitted to the internal memory, and the real-time radar signal processing requirement is met.

[0096] Further, the digital signal processing chip comprises a first port, a second port, a preset number of third ports and a fourth port.

[0097] The first port is used for outputting a linear frequency modulation signal waveform generated according to a direct digital synthesis module to the transmitting link.

[0098] The second port is used for generating an adjusted voltage gain according to a target communication protocol, controlling the digital potentiometer to generate an adjusted amplitude gain according to the adjusted voltage gain, and sending the adjusted amplitude gain to the automatic gain control circuit.

[0099] The third port is used for receiving the target unipolar signal into the digital signal processing chip for one-bit sampling and quantization.

[0100] The fourth port is used for transmitting the one-bit data to the host computer in real time.

[0101] The first communication port is a DDS interface, which is used for generating a linear frequency modulation signal waveform according to a direct digital synthesis module and outputting the linear frequency modulation signal waveform to the transmitting link.

[0102] Specifically, in order to break through the physical limitation of the sampling rate of the IO port of a single digital signal processing chip, the application further adopts a multi-channel digital port one-bit staggered sampling mechanism to realize high-speed one-bit sampling of the same radar echo signal. Figure 4 As shown in the figure, CLK_1, CLK_2, CLK_3, CLK_4 and CLK_5 represent different clock signals, D is the input end of the flip-flop, and Q is the output end of the flip-flop. In the application, the basic principle of the multi-channel digital port one-bit staggered sampling mechanism is to input the target unipolar signal after the gain of the automatic gain control circuit and the voltage biasing circuit into a plurality of parallel digital ports for sampling, that is, the preset number of third ports are two, and the sampling clock of each port has the same frequency but the phase is sequentially increased that is, each port has a fixed time interval The input signal is sampled so that the sampling rate is equivalent to wherein, is the number of digital ports, is the sampling frequency of each port; and during the sampling process, each port completes single-bit quantization of the analog signal based on an internal Schmitt trigger structure and outputs the sampling result under the driving of a respective clock.

[0103] Further, the sampling clock corresponding to the preset number of third ports has the same frequency and the phase sequentially increases by a target value, and a Schmitt trigger structure is set for each third port.

[0104] After the single-bit sampling quantization is completed, the digital signal processing chip synchronizes all the sampled data to the main processing clock domain according to the two-stage flip-flop in the digital signal processing chip, and sorts the data to obtain single-bit data.

[0105] Specifically, due to the fixed phase difference of the sampling clock of each port, the sampling result has an interleaving characteristic in time. In order to effectively integrate the sampling data of multiple ports into a continuous and high-speed single-bit data stream, the present application uses a cross-clock domain synchronization mechanism to integrate the data of each sampling port into the main processing clock domain, and sorts the multi-channel data in the synchronization clock domain. At the same time, considering that the bit width of the sampling data is single-bit and the data amount is small, the present application does not use the traditional asynchronous First Input First Output (FIFO) architecture, but uses a more simplified two-stage synchronous flip-flop to complete the cross-clock domain data synchronization. By setting two-stage flip-flops, the data sampled by each port is synchronized to the main processing clock domain, avoiding the metastability problem caused by clock difference; then, according to the relative phase sequence of each port in the clock cycle, the sampling data is sorted in time sequence. In an embodiment of the present application, 5-channel interleaved sampling is used, and the clock phase of each channel corresponds to 0°, 72°, 144°, 216°, and 288°, respectively. The system will sequentially sort and splice the sampling results of each port according to this order in each complete sampling period, and finally construct a continuous single-bit radar signal data stream equivalent to a sampling rate of 5 times the single-port sampling rate.

[0106] Further, the single-bit radar echo signal after sampling quantization, i.e. single-bit data, is written into the on-chip random access memory (RAM) in the digital signal processing chip in the form of a data stream for continuous caching, so as to ensure that the data will not be lost after sampling. Then, the single-bit data is transmitted to the host computer in real time through the fourth communication port, i.e. the single-bit data in the RAM is read out and transmitted to the host computer in real time through the configured universal asynchronous receiver / transmitter (UART) communication interface, so as to realize further processing and storage of the single-bit radar signal. At this time, since the data bit width after sampling quantization is 1, compared with the multi-bit data sampled by the traditional ADC, the system proposed in the application greatly reduces the transmission and storage pressure of the system.

[0107] In addition, the application verifies the effect through corresponding experiments. In the experiments, a linear frequency modulation (LFM) signal with a bandwidth of 50MHz and a pulse duration of 5us is used as a radar echo signal and is taken as a sampling object (the port sampling frequency is 100MHz), and the single-bit radar system directly sampled by the external high-speed comparator sampling path and the single-bit radar system directly sampled by the digital port proposed in the application are compared and tested respectively, and the spectrum and pulse compression processing results of the sampling data of the two are analyzed. On the basis of the digital signal processing chip port direct sampling, the distance-Doppler algorithm is further used to perform two-dimensional imaging processing on the sampling data of multiple echoes.

[0108] In the single-target echo sampling experiment, by Figure 5 and Figure 6 The spectrum results can be seen that the single-bit radar system directly sampled by the digital port proposed in the application can still retain the bandwidth information and modulation characteristics of the LFM signal, and the overall spectrum distribution shape is roughly the same as that of the external comparator scheme. As shown in Figure 7 and Figure 8 After pulse compression of the sampling results of the single-target echo, both sampling methods have obvious target main peaks, and the sidelobes are close to-13dB, which can accurately restore the target distance information, and the scheme of the application has lower system complexity and hardware resource consumption.

[0109] After completing the single-target echo experiment, the results showed that the sampling scheme proposed in this invention can accurately recover the spectral characteristics and temporal structure of the LFM signal under ideal conditions. However, in actual radar systems, the received echo signal is often formed by the superposition of reflections from multiple targets, exhibiting a more complex temporal structure and no longer a single, regularly changing LFM signal. Therefore, this invention designed and conducted a multi-target echo sampling experiment to further verify the usability of the proposed sampling scheme in complex scenarios.

[0110] In the multi-target echo sampling experiment, echo signals containing five targets were constructed and sampled. For example... Figure 9 As shown, data obtained by sampling using a comparator can also achieve pulse compression results with a clear main peak in multi-target scenarios, but its main peak width and side lobe height are not superior to the single-bit radar system with direct digital port sampling proposed in this paper, and the system complexity is higher. Figure 10 As shown, after pulse compression processing, the sampling results of this scheme have clear main peak positions for multiple targets in the matched filter output, and have good distance resolution capability.

[0111] like Figure 11 As shown in (a) and (b), there are clearly focused point targets in the two-dimensional imaging, the main lobe energy is concentrated, and the side lobes are well suppressed, which verifies that the system proposed in this invention can support effective radar imaging processing.

[0112] Therefore, a comprehensive comparison shows that, while maintaining target resolution performance, the present invention achieves higher integration and reduces hardware resource consumption by making full use of the Schmitt triggers on the digital chip ports.

[0113] The application discloses a digital port direct sampling single-bit radar system, which comprises a digital signal processing chip, a transmitting link, a receiving link, an automatic gain control circuit, a voltage bias circuit and a digital potentiometer; the digital signal processing chip is connected with the transmitting link, and is used for generating a linear frequency modulation signal waveform and outputting the linear frequency modulation signal waveform to the transmitting link; the transmitting link is used for processing the linear frequency modulation signal waveform, generating a radar signal and transmitting the radar signal; the transmitting link is connected with the automatic gain control circuit; the digital potentiometer is connected with the digital signal processing chip and the automatic gain control circuit respectively; the voltage bias circuit is connected with the automatic gain control circuit and the digital signal processing chip respectively; wherein the receiving link is used for receiving a radar echo signal, processing the radar echo signal, obtaining a first intermediate frequency signal and inputting the first intermediate frequency signal to the automatic gain control circuit; the automatic gain control circuit is used for adjusting the amplitude of the first intermediate frequency signal according to the amplitude adjustment gain generated by the digital potentiometer, obtaining a second intermediate frequency signal and inputting the second intermediate frequency signal to the voltage bias circuit; the voltage bias circuit is used for processing the second intermediate frequency signal according to an operational amplifier, obtaining a target unipolar signal; the digital signal processing chip is further used for single-bit sampling and quantizing the target unipolar signal, obtaining single-bit data and inputting the single-bit data to an upper computer. The application directly samples and quantizes the radar echo signal based on the Schmidt trigger characteristics of the digital signal processing chip port, and the dependence on ADC or a comparator in the traditional radar system is omitted. Through the system, the data amount of the radar system can be greatly reduced, and the hardware structure can be obviously simplified, so that a highly integrated and low-cost single-bit radar microsystem is constructed.

[0114] Further, as shown in Figure 12 the above-mentioned digital port direct sampling single-bit radar system, the application further correspondingly provides a digital port direct sampling method, wherein the digital port direct sampling method comprises the following steps.

[0115] Step S121, generating a linear frequency modulation waveform based on the digital signal processing chip, processing the linear frequency modulation waveform based on the transmitting link, obtaining a radar signal and transmitting the radar signal;

[0116] Step S122, receiving a radar echo signal based on the receiving link and processing the radar echo signal, obtaining a first intermediate frequency signal;

[0117] Step S123, adjusting the amplitude of the first intermediate frequency signal based on the automatic gain control circuit, obtaining a second intermediate frequency signal, and converting the second intermediate frequency signal based on the voltage bias circuit, obtaining a target unipolar signal;

[0118] Step S124, according to the digital signal processing chip, the target monopolar signal is single bit sampling quantization, and single bit data is obtained and sent to the upper computer.

[0119] Further, the transmitting link includes an analog-to-digital converter, a first mixer, a power amplifier, and a transmitting antenna.

[0120] The digital signal processing chip is used to generate a linear frequency modulation waveform, and the linear frequency modulation waveform is processed according to the transmitting link to obtain a radar signal, and the radar signal is transmitted.

[0121] The digital signal processing chip is used to generate a linear frequency modulation waveform.

[0122] The linear frequency modulation waveform is processed by the analog-to-digital converter to obtain an analog signal.

[0123] The analog signal is up-converted by the first mixer to obtain a target frequency band analog signal.

[0124] The target frequency band analog signal is amplified by the power amplifier to obtain the radar signal, and the radar signal is transmitted by the transmitting antenna.

[0125] Further, the receiving link includes a receiving antenna, a low-noise amplifier, a second mixer, and a band-pass filter circuit.

[0126] The radar echo signal is received according to the receiving link, and the radar echo signal is processed to obtain a first intermediate frequency signal.

[0127] The radar echo signal is received by the receiving antenna.

[0128] The radar echo signal is preliminarily amplified by the low-noise amplifier to obtain an amplified radar echo signal.

[0129] The amplified radar echo signal is down-converted by the second mixer to obtain an intermediate frequency signal.

[0130] The intermediate frequency signal is cleared of interference signals by the band-pass filter circuit to obtain the first intermediate frequency signal.

[0131] Further, the target monopolar signal is single bit sampling quantized according to the digital signal processing chip to obtain single bit data, and the single bit data is sent to the upper computer.

[0132] According to a predetermined number of third communication ports in the digital signal processing chip, the target monopolar signal is received and sampled to obtain corresponding sampling data.

[0133] According to the two-stage flip-flop in the digital signal processing chip, all the sampling data are synchronized to the main processing clock domain and sorted to obtain single-bit data.

[0134] Further, as shown in Figure 13 Based on the above digital port direct sampling method and the single-bit radar system directly sampled by the digital port, the application further provides a terminal, which comprises a processor 10, a memory 20 and a display 30. Figure 13 Only some components of the terminal are shown, but it should be understood that all the shown components are not required to be implemented, and more or fewer components can be alternatively implemented.

[0135] The memory 20 can be an internal storage unit of the terminal in some embodiments, such as a hard disk or a memory of the terminal. The memory 20 can also be an external storage device of the terminal in other embodiments, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card and the like equipped on the terminal. Further, the memory 20 can comprise both the internal storage unit and the external storage device of the terminal. The memory 20 is used to store application software and various data installed on the terminal, such as program codes of the terminal and the like. The memory 20 can also be used to temporarily store data that has been output or will be output. In an embodiment, the memory 20 stores a digital port direct sampling program 40, which can be executed by the processor 10 to implement the digital port direct sampling method of the application.

[0136] The processor 10 can be a central processing unit (CPU), a microprocessor or other data processing chip in some embodiments, which is used to run program codes or process data stored in the memory 20, such as to execute the digital port direct sampling method and the like.

[0137] The display 30 can be an LED display, a liquid crystal display, a touch liquid crystal display, an OLED (Organic Light-Emitting Diode) touch and the like in some embodiments. The display 30 is used to display information of the terminal and to display a visualized user interface.

[0138] In an embodiment, the processor 10 implements the steps of the above digital port direct sampling method when executing the digital port direct sampling program 40 in the memory 20.

[0139] The application further provides a computer readable storage medium, wherein the computer readable storage medium stores a digital port direct sampling program, and the digital port direct sampling program is executed by a processor to implement the steps of the above digital port direct sampling method.

[0140] It should be noted that, in this document, the terms "comprising" and "including" or any other variant thereof are intended to cover a non-exclusive inclusion, so that a process, method, article, or terminal including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent in such a process, method, article, or terminal. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or terminal including the element.

[0141] Of course, those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing relevant hardware (such as a processor, a controller, etc.) through a computer program, and the program can be stored in a computer readable computer readable storage medium, and the program can include the processes of the above-mentioned method embodiments when executed. The computer readable storage medium can be a memory, a magnetic disc, an optical disc, etc.

[0142] It should be understood that the application is not limited to the above examples, and those skilled in the art can make improvements or changes according to the above description, and all these improvements and changes should be within the protection scope of the appended claims of the application.

Claims

1. A single-bit radar system with direct sampling via digital port, characterized in that, The single-bit radar system with direct sampling via digital port includes a digital signal processing chip, a transmit link, a receive link, an automatic gain control circuit, a voltage bias circuit, and a digital potentiometer. The digital signal processing chip is connected to the transmission link. The digital signal processing chip is used to generate a linear frequency modulated signal waveform and output it to the transmission link. The transmission link is used to process the linear frequency modulated signal waveform, generate a radar signal, and transmit it. The transmit link is connected to the automatic gain control circuit, the digital potentiometer is connected to the digital signal processing chip and the automatic gain control circuit respectively, and the voltage bias circuit is connected to the automatic gain control circuit and the digital signal processing chip respectively. The receiving link is used to receive radar echo signals, process the radar echo signals to obtain a first intermediate frequency signal, and input it to the automatic gain control circuit. The automatic gain control circuit is used to adjust the amplitude of the first intermediate frequency signal according to the adjustment gain generated by the digital potentiometer to obtain a second intermediate frequency signal, which is then input to the voltage bias circuit. The voltage bias circuit is used to process the second intermediate frequency signal according to the operational amplifier to obtain the target unipolar signal; The digital signal processing chip is also used to perform single-bit sampling quantization on the target unipolar signal to obtain single-bit data and input it to the host computer. The digital signal processing chip includes a first port, a second port, a preset number of third ports and a fourth port; The first port is used to output the linear frequency modulated signal waveform generated by the direct digital synthesis module to the transmit link; The second port is used to generate an adjustable voltage gain according to the target communication protocol, control the digital potentiometer to generate an adjustable amplitude gain according to the adjustable voltage gain, and send it to the automatic gain control circuit; The third port is used to receive the target unipolar signal into the digital signal processing chip for single-bit sampling and quantization; The fourth port is used to transmit the single-bit data to the host computer in real time. The digital signal processing chip also includes a Schmitt trigger structure; The Schmitt trigger structure stores a high-level threshold and a low-level threshold. The third port receives the target unipolar signal into the digital signal processing chip. The digital signal processing chip performs single-bit sampling quantization on the target unipolar signal according to the high-level threshold and the low-level threshold in the Schmitt trigger structure to obtain single-bit data.

2. The single-bit radar system with direct digital port sampling according to claim 1, characterized in that, The sampling clocks corresponding to a preset number of the third ports have the same frequency, and the phases are sequentially increased by the target value. A Schmitt trigger structure is set for each of the third ports. After single-bit sampling and quantization is completed, the digital signal processing chip synchronizes all sampled data to the main processing clock domain and sorts them according to the two-stage flip-flops in the digital signal processing chip to obtain single-bit data.

3. A digital port direct sampling method for a single-bit radar system based on digital port direct sampling according to any one of claims 1-2, characterized in that, The direct sampling method for digital ports includes: Based on the digital signal processing chip, a linear frequency modulated waveform is generated. According to the transmission link, the linear frequency modulated waveform is processed to obtain a radar signal, which is then transmitted. The radar echo signal is received and processed according to the receiving link to obtain the first intermediate frequency signal; The automatic gain control circuit adjusts the amplitude of the first intermediate frequency signal to obtain a second intermediate frequency signal. The voltage bias circuit then performs signal conversion on the second intermediate frequency signal to obtain a target unipolar signal. The target unipolar signal is sampled and quantized by a single bit using the digital signal processing chip to obtain single-bit data, which is then sent to the host computer.

4. The direct sampling method for digital ports according to claim 3, characterized in that, The transmission link includes an analog-to-digital converter, a first mixer, a power amplifier, and a transmitting antenna; The process of generating a linear frequency modulated (LFM) waveform based on the digital signal processing chip, processing the LFM waveform according to the transmission link to obtain a radar signal, and then transmitting it specifically includes: Based on the digital signal processing chip, a linear frequency modulated waveform is generated; The analog-to-digital converter is used to process the linear frequency modulated waveform to obtain an analog signal; The analog signal is up-converted by the first mixer to obtain the target frequency band analog signal. The analog signal of the target frequency band is amplified by the power amplifier to obtain the radar signal, which is then transmitted through the transmitting antenna.

5. The direct sampling method for digital ports according to claim 3, characterized in that, The receiving link includes a receiving antenna, a low-noise amplifier, a second mixer, and a bandpass filter circuit; The step of receiving and processing the radar echo signal according to the receiving link to obtain the first intermediate frequency signal specifically includes: The radar echo signal is received based on the receiving antenna; The radar echo signal is initially amplified by the low-noise amplifier to obtain an amplified radar echo signal. The amplified radar echo signal is down-converted using the second mixer to obtain an intermediate frequency signal. The intermediate frequency signal is obtained by removing interference signals through the bandpass filter circuit.

6. The direct sampling method for digital ports according to claim 3, characterized in that, The step of performing single-bit sampling and quantization on the target unipolar signal using the digital signal processing chip to obtain single-bit data specifically includes: The target unipolar signal is received by a preset number of third communication ports in the digital signal processing chip, and the corresponding sampling data is obtained. Based on the two-stage flip-flops in the digital signal processing chip, all sampled data is synchronized to the main processing clock domain and sorted to obtain single-bit data.

7. A terminal, characterized in that, The terminal includes: a memory, a processor, and a digital port direct sampling program stored in the memory and executable on the processor, wherein when the digital port direct sampling program is executed by the processor, it implements the steps of the digital port direct sampling method as described in any one of claims 3-6.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a digital port direct sampling program, which, when executed by a processor, implements the steps of the digital port direct sampling method as described in any one of claims 3-6.

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