A bandgap reference circuit

Abstract

The application discloses a band gap reference circuit, comprising a band gap reference core circuit module, two input ends of a clamping operational amplifier feedback circuit input clamping voltages VA and VB output by positive and negative temperature coefficient voltage generating circuits, an output end of the clamping operational amplifier feedback circuit outputs a zero temperature coefficient reference voltage VREF, and the reference voltage VREF is input to input ends of the positive and negative temperature coefficient voltage generating circuits; a proportional amplifier module, which outputs a reference voltage value VX after the reference voltage VREF is amplified in proportion by a voltage negative feedback type operational amplifier circuit, and obtains a bias voltage Vb with different voltage values by dividing the reference voltage value VX through a voltage dividing network resistor; and an LDO circuit module, which clamps a node bias voltage VS1 output by a current negative feedback type operational amplifier circuit to two input ends of the LDO circuit module, and generates a reference current IREF, so that the application improves PSRR and is suitable for a low-voltage and high-noise environment.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit technology, and specifically relates to a bandgap reference circuit. Background Technology

[0002] Bandgap reference circuits are widely used in various analog circuits to provide a reference voltage that does not change with temperature. A bandgap reference circuit can provide a reference voltage for an analog-to-digital converter (ADC) and can further generate a reference current to provide bias current for other analog circuits. The performance of the bandgap reference circuit directly affects the accuracy of the ADC and the operating state of other analog circuit modules. As is well known, a negative temperature coefficient voltage is also called a CTAT voltage, and a positive temperature coefficient voltage is also called a PTAT voltage. In a traditional bandgap reference voltage circuit, the base-emitter voltage VBE of the transistor has a negative temperature coefficient, and the voltage difference ΔVBE between the base-emitter voltages of the two transistors has a positive temperature coefficient. The reference voltage is obtained by weighting the positive and negative temperature coefficient voltages together.

[0003] Despite the superior performance of bandgap reference circuits, the following technical limitations still exist:

[0004] (1) First, there is the impact of process deviation. Process deviations in resistors and BJTs will cause changes in output voltage and temperature coefficient, which need to be compensated by adjustment technology, but this increases cost and complexity.

[0005] (2) Secondly, temperature nonlinearity. Traditional first-order compensation cannot eliminate the higher-order temperature nonlinearity of VBE (such as curvature error), so higher-order compensation or nonlinear correction techniques are required.

[0006] (3) Next, power supply rejection ratio (PSRR) limitation: in low voltage or high noise environments, power supply voltage fluctuations can be coupled to the output through MOSFETs or resistors, requiring additional PSRR enhancement circuitry.

[0007] (4) Finally, low-voltage design challenges: With the reduction of power supply voltage under modern nanotechnology, traditional bandgap structures are difficult to apply directly, and low-voltage architectures (such as segmented curvature compensation or self-biased structures) are required. Summary of the Invention

[0008] The purpose of the present application is to provide a bandgap reference circuit, which solves the three technical defects of the traditional bandgap reference circuit through the cooperative design of the bandgap reference core circuit module, the proportional amplifier module and the LDO circuit module, specifically as follows: (1) solving the high-order temperature nonlinear problem (curvature error), the present application improves the temperature stability through real-time adjustment of the operational amplifier feedback, without additional high-order compensation circuit. (2) improving the power supply rejection ratio (PSRR) and the noise immunity, the present application improves the PSRR through active voltage stabilization and current mirror isolation of the LDO, and is suitable for low-voltage and high-noise environment. (3) realizing low-voltage and high-precision bias generation, the present application integrates proportional amplification and LDO to realize high-precision bias under low voltage (<1V) in a single chip, and is suitable for nanometer process.

[0009] The present application provides a bandgap reference circuit, comprising:

[0010] The bandgap reference core circuit module comprises a clamping operational amplifier feedback circuit and a positive and negative temperature coefficient voltage generating circuit; two input ends of the clamping operational amplifier feedback circuit input clamping voltages VA and VB output by the positive and negative temperature coefficient voltage generating circuit, respectively; and an output end of the clamping operational amplifier feedback circuit outputs a zero-temperature-coefficient reference voltage VREF and inputs the reference voltage VREF to an input end of the positive and negative temperature coefficient voltage generating circuit.

[0011] The proportional amplifier module outputs a reference voltage value VX after amplifying the reference voltage VREF by a voltage negative feedback type operational amplifier circuit, and obtains a bias voltage Vb of different voltage values through voltage division of the reference voltage value VX by a voltage division network resistor.

[0012] The LDO circuit module clamps a node bias voltage VS1 output by a current negative feedback type operational amplifier circuit to two input ends of itself, generates a reference current IREF, and outputs the reference current IREF through a self-biased low-voltage cascode current mirror to provide a bias current required by other modules of the chip.

[0013] Preferably, the positive and negative temperature coefficient voltage generating circuit comprises resistors R1-R2 and transistors Q1-Q2; one end of two resistors R1 is connected as an input end, the other end of two resistors R1 is connected to one end of resistor R2 and the emitter of transistor Q2, respectively, and serves as two output ends to output clamping voltages VA and VB, respectively; the other end of resistor R2 is connected to the emitter of transistor Q1; and the base and the collector of transistors Q1-Q2 are connected and grounded.

[0014] Preferably, the area ratio of the emitter of transistor Q1 to the emitter of transistor Q2 is 8:1.

[0015] Preferably, the clamping operational amplifier feedback circuit comprises MOS tubes Ma1~Ma7 and a capacitor Ca; the gates of the MOS tubes Ma1 and Ma2 are respectively used as two input ends to input clamping voltages VA and VB, the sources of the MOS tubes Ma1 and Ma2 are connected to the drain of the MOS tube Ma6, the gate of the MOS tube Ma6 is connected to a bias voltage VG3, the source of the MOS tube Ma6 is connected to a bias voltage VS3, the drain of the MOS tube Ma1 is connected to the drain and gate of the MOS tube Ma3 and the gate of the MOS tube Ma4, the sources of the MOS tubes Ma3 and Ma4 are connected and grounded, the drain of the MOS tube Ma4 is connected to the drain of the MOS tube Ma2 and the gate of the MOS tube Ma5 and one end of the capacitor Ca, the other end of the capacitor Ca is connected to the drains of the MOS tubes Ma5 and Ma7 and used as an output end to output a reference voltage VREF, the source of the MOS tube Ma5 is grounded, the gate of the MOS tube Ma7 is connected to the bias voltage VG3, and the source of the MOS tube Ma7 is connected to the bias voltage VS3.

[0016] Preferably, the proportional amplifier module comprises an operational amplifier one and a voltage negative feedback circuit; the negative input end and the output end of the operational amplifier one are respectively connected with the voltage negative feedback circuit; wherein the voltage negative feedback circuit comprises a MOS tube Mb6, resistors Rb1~Rb2 and a capacitor Cb; the gate of the MOS tube Mb6 and one end of the capacitor Cb are connected and used as an output end, the source of the MOS tube Mb6 is connected to a power supply VCC1, the drain of the MOS tube Mb6 is connected to the other end of the capacitor Cb and one end of the resistor Rb1, the other end of the resistor Rb1 is connected to the grounded resistor Rb2 and used as an input end to input a reference voltage value VX.

[0017] Preferably, the operational amplifier one comprises MOS tubes Mb1~Mb5; the sources of the MOS tubes Mb3 and Mb4 are connected to a power supply VCC1, the gate of the MOS tube Mb3 is connected to the gate and drain of the MOS tube Mb4 and the drain of the MOS tube Mb2 and used as a positive input end, the gate of the MOS tube Mb2 is used as an output end to output a reference voltage value VX, the source of the MOS tube Mb2 is connected to the source of the MOS tube Mb1 and the drain of the MOS tube Mb5, the gate of the MOS tube Mb5 is connected to a bias voltage VG4, the source of the MOS tube Mb5 is grounded, the gate of the MOS tube Mb1 is connected to a reference voltage VREF, and the drain of the MOS tube Mb1 is connected to the drain of the MOS tube Mb3 and used as a negative input end.

[0018] Preferably, the LDO circuit module comprises: an operational amplifier two and a current negative feedback circuit; the output end and the negative input end of the operational amplifier two are connected with the current negative feedback circuit respectively; wherein the current negative feedback circuit comprises: MOS tubes Mc13~Mc23 and a resistor Rc; the source of the MOS tube Mc13, the MOS tube Mc16 and the MOS tube Mc18 is connected with a power supply VCC1, the gate of the MOS tube Mc13, the MOS tube Mc16 and the MOS tube Mc18 is interconnected and connected with the drain of the MOS tube Mc14 and the MOS tube Mc15, the drain of the MOS tube Mc13 is connected with the source of the MOS tube Mc14, the drain of the MOS tube Mc16 is connected with the source of the MOS tube Mc17, the drain of the MOS tube Mc18 is connected with the source of the MOS tube Mc19, the gate of the MOS tube Mc14, the MOS tube Mc17 and the MOS tube Mc19 is connected with a bias voltage Vb, the gate of the MOS tube Mc15 is connected with an input end to input a bias voltage VG1, the source of the MOS tube Mc15 is connected with the resistor Rc grounded and connected with an output end to output a node bias voltage VS1, the drain of the MOS tube Mc17 is connected with the drain and the gate of the MOS tube Mc20, the gate of the MOS tube Mc21 and the MOS tube Mc22 and generates a bias voltage Vb1, the source of the MOS tube Mc20 is connected with the drain of the MOS tube Mc21, the source of the MOS tube Mc21 is grounded, the drain of the MOS tube Mc19 is connected with the drain of the MOS tube Mc22 and the gate of the MOS tube Mc23, the source of the MOS tube Mc22 is connected with the drain of the MOS tube Mc23, and the source of the MOS tube Mc23 is grounded.

[0019] Preferably, the operational amplifier two comprises MOS tubes Mc1~Mc10 and a capacitor Cc; the source of the MOS tube Mc1 and the MOS tube Mc2 is connected to the drain of the MOS tube Mc12, the gate of the MOS tube Mc12 is connected to a bias voltage VG3, the source of the MOS tube Mc12 is connected to the drain of the MOS tube Mc11, the gate of the MOS tube Mc11 is connected to a bias voltage VG2, the source of the MOS tube Mc11 is connected to a power supply VCC1, the gate of the MOS tube Mc1 is connected to a negative input end input node bias voltage VS1, the drain of the MOS tube Mc1 is connected to the gate and the drain of the MOS tube Mc3 and the gate of the MOS tube Mc5, the source of the MOS tube Mc3 and the MOS tube Mc5 is grounded, the drain of the MOS tube Mc5 is connected to the gate and the drain of the MOS tube Mc7 and the gate of the MOS tube Mc8, the source of the MOS tube Mc7 is connected to the drain of the MOS tube Mc9 and generates a bias voltage VS3, the gate of the MOS tube Mc9 is connected to a bias voltage VG2, the source of the MOS tube Mc9 is connected to a power supply VCC1, the gate of the MOS tube Mc2 is connected to a voltage P_G and serves as a positive input end, the drain of the MOS tube Mc2 is connected to the gate and the drain of the MOS tube Mc4 and the gate of the MOS tube Mc6, the source of the MOS tube Mc4 and the MOS tube Mc6 is grounded, the drain of the MOS tube Mc6 and the MOS tube Mc8 is connected to the capacitor Cc grounded and serves as an output end to output a bias voltage VG1, the source of the MOS tube Mc8 is connected to the drain of the MOS tube Mc10 and generates a bias voltage VS3, the gate of the MOS tube Mc10 is connected to a bias voltage VG2, and the source of the MOS tube Mc10 is connected to a power supply VCC1.

[0020] Preferably, the band gap starting circuit module further comprises a band gap starting circuit one and a band gap starting circuit two.

[0021] The band-gap starting circuit one includes MOS tubes M1-M10; the source of MOS tube M1 and MOS tube M2 is connected to power supply VCC1, the gate and drain of MOS tube M1 is connected to the gate of MOS tube M2 and the drain of MOS tube M3 and generates bias voltage VG2, the gate of MOS tube M3 is connected to bias voltage VG1, the source of MOS tube M3 is connected to bias voltage VS1, the drain of MOS tube M2 is connected to the gate and drain of MOS tube M4, the source of MOS tube M7 and MOS tube M9 and generates bias voltage VS3, the source of MOS tube M4 is connected to the gate and drain of MOS tube M5, the source of MOS tube M5 is connected to the gate and drain of MOS tube M6, the source of MOS tube M6 is grounded, the gate and drain of MOS tube M7 is connected to the gate of MOS tube M9 and the drain of MOS tube M8 and generates bias voltage VG3, the gate of MOS tube M8 is connected to bias voltage VG1, the source of MOS tube M8 is connected to bias voltage VS1, the drain of MOS tube M9 is connected to the gate and drain of MOS tube M10 and generates bias voltage VG4, the source of MOS tube M10 is grounded.

[0022] The band-gap starting circuit two includes MOS tubes M11-M16; the gate of MOS tube M11 is connected to bias voltage Vb1, the drain of MOS tube M11 is connected to the gate and drain of MOS tube M12, the drain of MOS tube M14 and the gate of MOS tube M15 and MOS tube M16 and generates bias voltage VG5, the source of MOS tube M14 is connected to the drain of MOS tube M13, the source of MOS tube M13 is connected to power supply VCC1, the gate of MOS tube M13 and MOS tube M14 is grounded, the drain of MOS tube M15 is connected to bias voltage VG2, the drain of MOS tube M16 is connected to bias voltage VG3, the source of MOS tube M11, MOS tube M12, MOS tube M15 and MOS tube M16 is grounded.

[0023] Preferably, the on-chip power supply generating circuit module further comprises MOS tubes V1-V6, capacitors Cv1-Cv3, a voltage stabilizing diode TVS and a resistor Rv; one end of the resistor Rv is connected to a working power supply VCC, the other end is connected to the source of the MOS tube V5, the gate of the MOS tube V5 is connected to a control signal D1, the drain of the MOS tube V5 is connected to the drain of the MOS tube V6, the gate of the MOS tube V6 is connected to a control signal D2, the source of the MOS tube V6 is connected to the gates of the MOS tubes V2 and V3, the drain of the MOS tube V4, one end of the voltage stabilizing diode TVS and the capacitor Cv2 connected to ground and generates a voltage V_G, the drains of the MOS tubes V2 and V3 are connected to the working power supply VCC, the source of the MOS tube V2 is connected to the capacitor Cv3 connected to ground and outputs a power supply X2_D, the gate of the MOS tube V4 is connected to the control signal D1, the source of the MOS tube V4 is connected to ground, the other end of the voltage stabilizing diode TVS is connected to the gate and drain of the MOS tube V1, the source of the MOS tube V1 is connected to ground, and the source of the MOS tube V3 is connected to the capacitor Cv1 connected to ground and outputs a power supply VCC1.

[0024] Compared with the prior art, the present application has the following beneficial effects:

[0025] 1. The present application solves the problem of high-order temperature nonlinearity (curvature error): the present application adopts a clamping operational amplifier feedback circuit to dynamically adjust the positive and negative temperature coefficient voltage, so that the output reference voltage VREF maintains zero temperature coefficient. Through operational amplifier closed-loop control, the shortcomings of traditional first-order compensation are optimized, and the error caused by high-order temperature nonlinearity is reduced.

[0026] 2. The present application improves the power supply rejection ratio (PSRR) and the anti-noise capability: the LDO circuit module of the present application adopts a current negative feedback type operational amplifier to clamp the node bias voltage to a stable value, suppresses the influence of power supply voltage fluctuation, and provides high output impedance through self-biasing common-source common-gate current mirror to reduce power supply noise coupling; the present application improves the PSRR through LDO active voltage stabilization and current mirror isolation, and is suitable for low-voltage and high-noise environments.

[0027] 3. The present application realizes low-voltage and high-precision bias generation: the proportional amplifier module of the present application flexibly generates multiple bias voltages through a voltage dividing network resistor, adapts to different module requirements; the self-biasing current mirror accurately copies the reference current to avoid mirror error caused by process deviation. The present application integrates proportional amplification and LDO to realize high-precision bias under low voltage (<1V) in a single chip, and is suitable for nanometer technology. BRIEF DESCRIPTION OF DRAWINGS

[0028] Fig. 1 is a circuit diagram of a bandgap reference core circuit module provided by the present application.

[0029] Fig. 2 is a circuit diagram of a proportional amplifier module provided by the present application.

[0030] Fig. 3 is a circuit diagram of an LDO circuit module provided by the present application.

[0031] Fig. 4 is a circuit diagram of a bandgap start-up circuit one provided by the present application.

[0032] Fig. 5 is a circuit diagram of a bandgap start-up circuit two provided by the present application.

[0033] Fig. 6 is a circuit diagram of an on-chip power supply generation circuit module provided by the present application. DETAILED DESCRIPTION

[0034] The present application will be further described below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the accompanying drawings are very simplified and use non-precise proportions, only for the purpose of conveniently and clearly assisting the description of the embodiments of the present application.

[0035] As shown in Figs. 1-6 , the present application specifically provides a bandgap reference circuit, comprising:

[0036] a bandgap reference core circuit module, comprising: a clamping operational amplifier feedback circuit and a positive and negative temperature coefficient voltage generation circuit; two input ends of the clamping operational amplifier feedback circuit input clamping voltages VA and VB output by the positive and negative temperature coefficient voltage generation circuit, respectively, an output end of the clamping operational amplifier feedback circuit outputs a zero temperature coefficient reference voltage VREF, and inputs the reference voltage VREF to an input end of the positive and negative temperature coefficient voltage generation circuit;

[0037] a proportional amplifier module, which outputs a reference voltage value VX by proportionally amplifying the reference voltage VREF through a voltage negative feedback type operational amplifier circuit, and obtains a bias voltage Vb of different voltage values by dividing the reference voltage value VX through a voltage dividing network resistor;

[0038] an LDO circuit module, which clamps a node bias voltage VS1 output to two input ends of itself through a current negative feedback type operational amplifier circuit, and generates a reference current IREF, which is copied and output through a self-biased low-voltage common-source and common-gate current mirror, to provide a bias current required by other modules of a chip.

[0039] The positive and negative temperature coefficient voltage generating circuit comprises resistors R1-R2 and transistors Q1-Q2; one end of each of the two resistors R1 is connected as an input end, the other end of each of the two resistors R1 is connected to one end of a resistor R2 and the emitter of a transistor Q2 respectively and serves as two output ends to output clamping voltages VA and VB respectively, the other end of the resistor R2 is connected to the emitter of a transistor Q1, and the base and the collector of each of the transistors Q1-Q2 are connected and grounded. The emitter area ratio of the transistors Q1 and Q2 is 8:1.

[0040] The clamping operational amplifier feedback circuit comprises MOS transistors Ma1-Ma7 and a capacitor Ca; the gates of the MOS transistors Ma1 and Ma2 serve as two input ends to input clamping voltages VA and VB respectively, the sources of the MOS transistors Ma1 and Ma2 are connected to the drain of a MOS transistor Ma6, the gate of the MOS transistor Ma6 is connected to a bias voltage VG3, the source of the MOS transistor Ma6 is connected to a bias voltage VS3, the drain and the gate of the MOS transistor Ma1 are connected to the drain of a MOS transistor Ma3 and the gate of a MOS transistor Ma4, the sources of the MOS transistors Ma3 and Ma4 are connected and grounded, the drain of the MOS transistor Ma4 is connected to the drain of the MOS transistor Ma2 and the gate of a MOS transistor Ma5 and one end of the capacitor Ca, the other end of the capacitor Ca is connected to the drains of the MOS transistors Ma5 and Ma7 and serves as an output end to output a reference voltage VREF, the source of the MOS transistor Ma5 is grounded, the gate of the MOS transistor Ma7 is connected to the bias voltage VG3, and the source of the MOS transistor Ma7 is connected to the bias voltage VS3.

[0041] The bandgap reference core circuit module uses an operational amplifier to clamp the clamping voltages VA and VB to the same voltage, at which time V BE2 =R2I+V BE1 , where V BE1 and V BE2 are the voltage differences between the bases B and the emitters E of the transistors Q1 and Q2 respectively, I=(V BE2 -V BE1 ) / R2=V T lnn / R2, because the thermal voltage V T is positively correlated with temperature, and n is the area ratio of the transistors Q1 and Q2, so we obtain an I PTAT current, VREF=V BE1 +(V T lnn)(1+R1 / R2), and by adjusting the value of lnn(1+R1 / R2), we can obtain a reference voltage independent of temperature, wherein the bias voltages VG3 and VS3 are provided by a start-up circuit.

[0042] The proportional amplifier module comprises: an operational amplifier one and a voltage negative feedback circuit; the negative input end and the output end of the operational amplifier one are connected with the voltage negative feedback circuit respectively; wherein the voltage negative feedback circuit comprises: MOS tube Mb6, resistors Rb1-Rb2 and capacitor Cb; the gate of the MOS tube Mb6 and one end of the capacitor Cb are connected and serve as an output end, the source of the MOS tube Mb6 is connected with power supply VCC1, the drain of the MOS tube Mb6 is connected with the other end of the capacitor Cb and one end of the resistor Rb1, the other end of the resistor Rb1 is connected with the grounded resistor Rb2 and serves as an input end to input the reference voltage value VX.

[0043] The operational amplifier one comprises: MOS tubes Mb1-Mb5; the sources of the MOS tubes Mb3 and Mb4 are connected with the power supply VCC1, the gate of the MOS tube Mb3 is connected with the gate and the drain of the MOS tube Mb4 and the drain of the MOS tube Mb2 and serves as a positive input end, the gate of the MOS tube Mb2 serves as an output end to output the reference voltage value VX, the source of the MOS tube Mb2 is connected with the source of the MOS tube Mb1 and the drain of the MOS tube Mb5, the gate of the MOS tube Mb5 is connected with the bias voltage VG4, the source of the MOS tube Mb5 is grounded, the gate of the MOS tube Mb1 is connected with the reference voltage VREF, the drain of the MOS tube Mb1 is connected with the drain of the MOS tube Mb3 and serves as a negative input end; the above bias voltage VG4 is provided by a starting circuit.

[0044] The LDO circuit module comprises: an operational amplifier two and a current negative feedback circuit; the output end and the negative input end of the operational amplifier two are connected with the current negative feedback circuit respectively; wherein the current negative feedback circuit comprises: MOS tubes Mc13-Mc23 and a resistor Rc; the source of the MOS tube Mc13, the MOS tube Mc16 and the MOS tube Mc18 is connected with a power supply VCC1, the gate of the MOS tube Mc13, the MOS tube Mc16 and the MOS tube Mc18 is interconnected and connected with the drain of the MOS tube Mc14 and the MOS tube Mc15, the drain of the MOS tube Mc13 is connected with the source of the MOS tube Mc14, the drain of the MOS tube Mc16 is connected with the source of the MOS tube Mc17, the drain of the MOS tube Mc18 is connected with the source of the MOS tube Mc19, the gate of the MOS tube Mc14, the MOS tube Mc17 and the MOS tube Mc19 is connected with a bias voltage Vb, the gate of the MOS tube Mc15 is connected with an input end and inputs a bias voltage VG1, the source of the MOS tube Mc15 is connected with the resistor Rc grounded and outputs a node bias voltage VS1 as an output end, the drain of the MOS tube Mc17 is connected with the drain and the gate of the MOS tube Mc20, the gate of the MOS tube Mc21 and the MOS tube Mc22 and generates a bias voltage Vb1, the source of the MOS tube Mc20 is connected with the drain of the MOS tube Mc21, the source of the MOS tube Mc21 is grounded, the drain of the MOS tube Mc19 is connected with the drain of the MOS tube Mc22 and the gate of the MOS tube Mc23, the source of the MOS tube Mc22 is connected with the drain of the MOS tube Mc23, and the source of the MOS tube Mc23 is grounded.

[0045] The operational amplifier two comprises MOS tubes Mc1-Mc10 and a capacitor Cc; the source of the MOS tube Mc1 and the source of the MOS tube Mc2 are connected to the drain of the MOS tube Mc12, the gate of the MOS tube Mc12 is connected to a bias voltage VG3, the source of the MOS tube Mc12 is connected to the drain of the MOS tube Mc11, the gate of the MOS tube Mc11 is connected to a bias voltage VG2, the source of the MOS tube Mc11 is connected to a power supply VCC1, the gate of the MOS tube Mc1 is connected to a negative input end input node bias voltage VS1, the drain of the MOS tube Mc1 is connected to the gate and the drain of the MOS tube Mc3 and the gate of the MOS tube Mc5, the sources of the MOS tube Mc3 and the MOS tube Mc5 are grounded, the drain of the MOS tube Mc5 is connected to the gate and the drain of the MOS tube Mc7 and the gate of the MOS tube Mc8, the source of the MOS tube Mc7 is connected to the drain of the MOS tube Mc9 and generates a bias voltage VS3, the gate of the MOS tube Mc9 is connected to the bias voltage VG2, the source of the MOS tube Mc9 is connected to the power supply VCC1, the gate of the MOS tube Mc2 is connected to a voltage P_G and serves as a positive input end, the drain of the MOS tube Mc2 is connected to the gate and the drain of the MOS tube Mc4 and the gate of the MOS tube Mc6, the sources of the MOS tube Mc4 and the MOS tube Mc6 are grounded, the drains of the MOS tube Mc6 and the MOS tube Mc8 are connected to the capacitor Cc grounded and serve as an output end to output a bias voltage VG1, the source of the MOS tube Mc8 is connected to the drain of the MOS tube Mc10 and generates the bias voltage VS3, the gate of the MOS tube Mc10 is connected to the bias voltage VG2, and the source of the MOS tube Mc10 is connected to the power supply VCC1.

[0046] The LDO circuit module uses the operational amplifier two with current negative feedback to clamp the positive and negative input ends to the same voltage, and a stable current IREF=VS1 / Rc can be obtained on the resistor Rc, which is output by the low-voltage self-biasing current mirror above and is copied to subsequent current mirrors to provide biasing currents for each module in the chip, wherein the bias voltages VG2, VG3 and VS3 are provided by the start-up circuit. When the bias voltage VG2 is established, a stable VG1 is output, and under the operation of the operational amplifier two, VS1 is clamped to the voltage P_G.

[0047] The application further comprises a band-gap start-up circuit module, which comprises a band-gap start-up circuit one and a band-gap start-up circuit two.

[0048] The band gap starting circuit one comprises MOS tubes M1-M10; the source of the MOS tube M1 and the MOS tube M2 is connected to the power supply VCC1, the gate and the drain of the MOS tube M1 are connected to the gate of the MOS tube M2 and the drain of the MOS tube M3 and generate a bias voltage VG2, the gate of the MOS tube M3 is connected to a bias voltage VG1, the source of the MOS tube M3 is connected to a bias voltage VS1, the drain of the MOS tube M2 is connected to the gate and the drain of the MOS tube M4, the source of the MOS tube M7 and the MOS tube M9 and generates a bias voltage VS3, the source of the MOS tube M4 is connected to the gate and the drain of the MOS tube M5, the source of the MOS tube M5 is connected to the gate and the drain of the MOS tube M6, the source of the MOS tube M6 is grounded, the gate and the drain of the MOS tube M7 are connected to the gate of the MOS tube M9 and the drain of the MOS tube M8 and generate a bias voltage VG3, the gate of the MOS tube M8 is connected to a bias voltage VG1, the source of the MOS tube M8 is connected to a bias voltage VS1, the drain of the MOS tube M9 is connected to the gate and the drain of the MOS tube M10 and generates a bias voltage VG4, and the source of the MOS tube M10 is grounded.

[0049] The band gap starting circuit two comprises MOS tubes M11-M16; the gate of the MOS tube M11 is connected to a bias voltage Vb1, the drain of the MOS tube M11 is connected to the gate and the drain of the MOS tube M12, the drain of the MOS tube M14, and the gate of the MOS tube M15 and the MOS tube M16 and generates a bias voltage VG5, the source of the MOS tube M14 is connected to the drain of the MOS tube M13, the source of the MOS tube M13 is connected to the power supply VCC1, the gates of the MOS tube M13 and the MOS tube M14 are grounded, the drain of the MOS tube M15 is connected to a bias voltage VG2, the drain of the MOS tube M16 is connected to a bias voltage VG3, and the sources of the MOS tube M11, the MOS tube M12, the MOS tube M15 and the MOS tube M16 are grounded.

[0050] In the band gap starting circuit module, the always-on branch in the starting circuit is the MOS tube M12, the MOS tube M13 and the MOS tube M14, and the detection signal of the starting circuit is Vb1 (the bias voltage of the current mirror in the LDO circuit module).

[0051] When the power supply VCC1 is low, the bias voltage Vb1 is suspended and has no effect, when the power supply VCC1 rises from 0 to the gate opening voltage of MOS transistors M13 and M14, the MOS transistors M13 and M14 will be turned on, the bias voltage VG5 is pulled high, thereby the bias voltages VG2 and VG3 are pulled low to close to 0 level, the MOS transistors M2, M4, M5 and M6 branches will be turned on (MOS transistors M1 and M3 are still not on), the power supply VCC1 continues to rise and will pull the bias voltage VS3 high to a small overdrive voltage than the power supply VCC1, the MOS transistor M9 is turned on (M7 and M8 are still not on), and the bias voltage VG4 is pulled high to a small overdrive voltage than VS3.

[0052] The bandgap circuit, the proportional amplification circuit and the LDO circuit will successively generate tail currents, when the reference current source is established, Vb1 is pulled high, VG5 is pulled low to a low level, M15 and M16 are disconnected, M3 and M8 are turned on, the drain current of the LDO circuit MC15 is copied, and stable potentials of VG2, VG3, VG4 and VS3 are provided, VG2, VG3, VG4 and VS3 provide stable bias for the operational amplifier of the bandgap reference circuit, and the bandgap reference circuit starts.

[0053] The chip power generation circuit module comprises MOS transistors V1-V6, capacitors Cv1-Cv3, a voltage stabilizing diode TVS and a resistor Rv, one end of the resistor Rv is connected to a working power supply VCC, the other end is connected to the source electrode of the MOS transistor V5, the gate electrode of the MOS transistor V5 is connected to a control signal D1, the drain electrode of the MOS transistor V5 is connected to the drain electrode of the MOS transistor V6, the gate electrode of the MOS transistor V6 is connected to a control signal D2, the source electrode of the MOS transistor V6 is connected to the gate electrodes of the MOS transistors V2 and V3, the drain electrode of the MOS transistor V4, one end of the voltage stabilizing diode TVS and the ground connected capacitor Cv2 and generates a voltage V_G, the drain electrodes of the MOS transistors V2 and V3 are connected to the working power supply VCC, the source electrode of the MOS transistor V2 is connected to the ground connected capacitor Cv3 and outputs a power supply X2_D, the gate electrode of the MOS transistor V4 is connected to the control signal D1, the source electrode of the MOS transistor V4 is grounded, the other end of the voltage stabilizing diode TVS is connected to the gate electrode and the drain electrode of the MOS transistor V1, the source electrode of the MOS transistor V1 is grounded, and the source electrode of the MOS transistor V3 is connected to the ground connected capacitor Cv1 and outputs a power supply VCC1; the capacitors Cv1-Cv3 are MOS capacitors.

[0054] The above-mentioned on-chip power supply generating circuit module converts the externally input power supply voltage VCC into different voltages required by each module inside the chip, reduces voltage fluctuation, and ensures that each part of the chip can work under stable voltage. When the external working power supply VCC is established, the control signal D1 is low, the MOS tube V5 is cut off, the control signal D2 is the output of the external under-voltage module and is also low, the voltage of V_G is clamped at the stable voltage Vr of a stable voltage diode TVS plus the gate-source voltage difference Vgs1 of the MOS tube V1, at this time the control signal D1 is low, and the MOS tube V4 is closed. The on-chip power supplies VCC1 and X2_D are both based on the voltage of V_G and subtract a gate-source voltage difference Vgs2 of the MOS tube V2 and a gate-source voltage difference Vgs3 of the MOS tube V3, respectively. If Vgs1 is approximately equal to Vgs2 or Vgs3, then the final on-chip power supplies VCC1 and X2_D are approximately equal to the voltage of a stable voltage diode TVS, i.e., approximately equal to 5.8V.

[0055] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any modification or change made by a person of ordinary skill in the art according to the above disclosure is within the protection scope of the claims.

Claims

1. A bandgap reference circuit, characterized by, The application relates to a bandgap reference core circuit module, a proportional amplifier module and an LDO circuit module. The bandgap reference core circuit module comprises a clamping operational amplifier feedback circuit and a positive and negative temperature coefficient voltage generating circuit; two input ends of the clamping operational amplifier feedback circuit input clamping voltages VA and VB output by the positive and negative temperature coefficient voltage generating circuit; and an output end of the clamping operational amplifier feedback circuit outputs a zero temperature coefficient reference voltage VREF and inputs the reference voltage VREF into an input end of the positive and negative temperature coefficient voltage generating circuit. The proportional amplifier module amplifies the reference voltage VREF by a voltage negative feedback type operational amplifier circuit and outputs a reference voltage value VX; and the reference voltage value VX is divided by a voltage dividing network resistor to obtain a bias voltage Vb with different voltage values. The LDO circuit module clamps a node bias voltage VS1 output by a current negative feedback type operational amplifier circuit to two input ends of the LDO circuit module and generates a reference current IREF; and the reference current IREF is copied and output by a self-biased low-voltage common-source and common-gate current mirror to provide a bias current required by other modules of a chip. The clamping operational amplifier feedback circuit comprises MOS tubes Ma1-Ma7 and a capacitor Ca; a gate of the MOS tube Ma1 and a gate of the MOS tube Ma2 are connected to two input ends to input the clamping voltages VA and VB; a source of the MOS tube Ma1 and a source of the MOS tube Ma2 are connected to a drain of the MOS tube Ma6; a gate of the MOS tube Ma6 is connected to a bias voltage VG3; a source of the MOS tube Ma6 is connected to a bias voltage VS3; a drain of the MOS tube Ma1 and a gate of the MOS tube Ma3 and a gate of the MOS tube Ma4 are connected to a drain of the MOS tube Ma3 and a source of the MOS tube Ma4; the source of the MOS tube Ma3 and the source of the MOS tube Ma4 are connected and grounded; a drain of the MOS tube Ma4 is connected to a drain of the MOS tube Ma2, a gate of the MOS tube Ma5 and one end of the capacitor Ca; the other end of the capacitor Ca is connected to a drain of the MOS tube Ma5 and a drain of the MOS tube Ma7 and outputs a reference voltage VREF as an output end; a source of the MOS tube Ma5 is grounded; a gate of the MOS tube Ma7 is connected to the bias voltage VG3; and a source of the MOS tube Ma7 is connected to the bias voltage VS3. The proportional amplifier module comprises an operational amplifier one and a voltage negative feedback circuit; a negative input end and an output end of the operational amplifier one are connected to the voltage negative feedback circuit; the voltage negative feedback circuit comprises MOS tubes Mb6, resistors Rb1-Rb2 and a capacitor Cb; a gate of the MOS tube Mb6 and one end of the capacitor Cb are connected and serve as an output end; a source of the MOS tube Mb6 is connected to a power supply VCC1; a drain of the MOS tube Mb6 is connected to the other end of the capacitor Cb and one end of the resistor Rb1; the other end of the resistor Rb1 is connected to the grounded resistor Rb2 and serves as an input end to input the reference voltage value VX. The LDO circuit module comprises: an operational amplifier two and a current negative feedback circuit; the output end and the negative input end of the operational amplifier two are connected with the current negative feedback circuit respectively; wherein the current negative feedback circuit comprises: MOS tubes Mc13-Mc23 and a resistor Rc; the source of the MOS tube Mc13, the MOS tube Mc16 and the MOS tube Mc18 is connected with a power supply VCC1, the gate of the MOS tube Mc13, the MOS tube Mc16 and the MOS tube Mc18 is interconnected and connected with the drain of the MOS tube Mc14 and the MOS tube Mc15, the drain of the MOS tube Mc13 is connected with the source of the MOS tube Mc14, the drain of the MOS tube Mc16 is connected with the source of the MOS tube Mc17, the drain of the MOS tube Mc18 is connected with the source of the MOS tube Mc19, the gate of the MOS tube Mc14, the MOS tube Mc17 and the MOS tube Mc19 is connected with a bias voltage Vb, the gate of the MOS tube Mc15 is connected with an input end to input a bias voltage VG1, the source of the MOS tube Mc15 is connected with the resistor Rc grounded and connected with an output end to output a node bias voltage VS1, the drain of the MOS tube Mc17 is connected with the drain and the gate of the MOS tube Mc20, the gate of the MOS tube Mc21 and the MOS tube Mc22 and generates a bias voltage Vb1, the source of the MOS tube Mc20 is connected with the drain of the MOS tube Mc21, the source of the MOS tube Mc21 is grounded, the drain of the MOS tube Mc19 is connected with the drain of the MOS tube Mc22 and the gate of the MOS tube Mc23, the source of the MOS tube Mc22 is connected with the drain of the MOS tube Mc23, and the source of the MOS tube Mc23 is grounded.

2. A bandgap reference circuit as claimed in claim 1, characterized in that The positive and negative temperature coefficient voltage generating circuit comprises: resistors R1-R2 and transistors Q1-Q2; one end of two resistors R1 is connected as an input end, the other end of two resistors R1 is connected with one end of a resistor R2 and the emitter of a transistor Q2 respectively and is connected as two output ends to output clamping voltages VA and VB respectively, the other end of the resistor R2 is connected with the emitter of a transistor Q1, and the base and the collector of the transistors Q1-Q2 are connected and grounded.

3. A bandgap reference circuit as claimed in claim 2, characterized in that The emitter area ratio of the transistors Q1 and Q2 is 8:

1.

4. A bandgap reference circuit as claimed in claim 1, characterized in that The operation amplifier one comprises MOS tubes Mb1-Mb5; the source of the MOS tube Mb3 and the MOS tube Mb4 is connected to the power supply VCC1, the gate of the MOS tube Mb3 is connected to the gate and drain of the MOS tube Mb4, the drain of the MOS tube Mb2 and the positive input end, the gate of the MOS tube Mb2 is the output end outputting the reference voltage value VX, the source of the MOS tube Mb2 is connected to the source of the MOS tube Mb1 and the drain of the MOS tube Mb5, the gate of the MOS tube Mb5 is connected to the bias voltage VG4, the source of the MOS tube Mb5 is grounded, the gate of the MOS tube Mb1 is connected to the reference voltage VREF, and the drain of the MOS tube Mb1 is connected to the drain of the MOS tube Mb3 and the negative input end.

5. A bandgap reference circuit as claimed in claim 1, characterized in that The operation amplifier two comprises MOS tubes Mc1-Mc10 and a capacitor Cc; the source of the MOS tube Mc1 and the MOS tube Mc2 is connected to the drain of the MOS tube Mc12, the gate of the MOS tube Mc12 is connected to the bias voltage VG3, the source of the MOS tube Mc12 is connected to the drain of the MOS tube Mc11, the gate of the MOS tube Mc11 is connected to the bias voltage VG2, the source of the MOS tube Mc11 is connected to the power supply VCC1, the gate of the MOS tube Mc1 is the negative input end inputting the node bias voltage VS1, the drain of the MOS tube Mc1 is connected to the gate and drain of the MOS tube Mc3 and the gate of the MOS tube Mc5, the source of the MOS tube Mc3 and the MOS tube Mc5 is grounded, the drain of the MOS tube Mc5 is connected to the gate and drain of the MOS tube Mc7 and the gate of the MOS tube Mc8, the source of the MOS tube Mc7 is connected to the drain of the MOS tube Mc9 and generates the bias voltage VS3, the gate of the MOS tube Mc9 is connected to the bias voltage VG2, the source of the MOS tube Mc9 is connected to the power supply VCC1, the gate of the MOS tube Mc2 is connected to the voltage P_G and is the positive input end, the drain of the MOS tube Mc2 is connected to the gate and drain of the MOS tube Mc4 and the gate of the MOS tube Mc6, the source of the MOS tube Mc4 and the MOS tube Mc6 is grounded, the drain of the MOS tube Mc6 and the MOS tube Mc8 is connected to the grounded capacitor Cc and is the output end outputting the bias voltage VG1, the source of the MOS tube Mc8 is connected to the drain of the MOS tube Mc10 and generates the bias voltage VS3, the gate of the MOS tube Mc10 is connected to the bias voltage VG2, and the source of the MOS tube Mc10 is connected to the power supply VCC1.

6. A bandgap reference circuit as claimed in claim 1, characterized in that The band gap starting circuit module comprises a band gap starting circuit one and a band gap starting circuit two. The band gap starting circuit one comprises MOS tubes M1-M10; the source of MOS tube M1 and MOS tube M2 is connected to power supply VCC1, the gate and drain of MOS tube M1 are connected to the gate of MOS tube M2 and the drain of MOS tube M3 and generate bias voltage VG2, the gate of MOS tube M3 is connected to bias voltage VG1, the source of MOS tube M3 is connected to bias voltage VS1, the drain of MOS tube M2 is connected to the gate and drain of MOS tube M4, the source of MOS tube M7 and MOS tube M9 and generates bias voltage VS3, the source of MOS tube M4 is connected to the gate and drain of MOS tube M5, the source of MOS tube M5 is connected to the gate and drain of MOS tube M6, the source of MOS tube M6 is grounded, the gate and drain of MOS tube M7 are connected to the gate of MOS tube M9 and the drain of MOS tube M8 and generate bias voltage VG3, the gate of MOS tube M8 is connected to bias voltage VG1, the source of MOS tube M8 is connected to bias voltage VS1, the drain of MOS tube M9 is connected to the gate and drain of MOS tube M10 and generates bias voltage VG4, and the source of MOS tube M10 is grounded; The band gap starting circuit two comprises MOS tubes M11-M16; the gate of MOS tube M11 is connected to bias voltage Vb1, the drain of MOS tube M11 is connected to the gate and drain of MOS tube M12, the drain of MOS tube M14 and the gate of MOS tube M15 and MOS tube M16 and generates bias voltage VG5, the source of MOS tube M14 is connected to the drain of MOS tube M13, the source of MOS tube M13 is connected to power supply VCC1, the gates of MOS tube M13 and MOS tube M14 are grounded, the drain of MOS tube M15 is connected to bias voltage VG2, the drain of MOS tube M16 is connected to bias voltage VG3, and the sources of MOS tube M11, MOS tube M12, MOS tube M15 and MOS tube M16 are grounded.

7. A bandgap reference circuit as claimed in any one of claims 1 to 6, wherein the first and second bandgap circuits are connected in series. The chip-in power supply generating circuit module comprises MOS tubes V1-V6, capacitors Cv1-Cv3, a voltage stabilizing diode TVS and a resistor Rv; one end of the resistor Rv is connected to a working power supply VCC, the other end is connected to the source of the MOS tube V5, the gate of the MOS tube V5 is connected to a control signal D1, the drain of the MOS tube V5 is connected to the drain of the MOS tube V6, the gate of the MOS tube V6 is connected to a control signal D2, the source of the MOS tube V6 is connected to the gate of the MOS tube V2 and the MOS tube V3, the drain of the MOS tube V4, one end of the voltage stabilizing diode TVS and the ground capacitor Cv2 and generates a voltage V_G, the drains of the MOS tube V2 and the MOS tube V3 are connected to the working power supply VCC, the source of the MOS tube V2 is connected to the ground capacitor Cv3 and outputs a power supply X2_D, the gate of the MOS tube V4 is connected to the control signal D1, the source of the MOS tube V4 is grounded, the other end of the voltage stabilizing diode TVS is connected to the gate and the drain of the MOS tube V1, the source of the MOS tube V1 is grounded, and the source of the MOS tube V3 is connected to the ground capacitor Cv1 and outputs a power supply VCC1.

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