Cross-clock domain data transmission method and apparatus

Abstract

According to an embodiment of the present disclosure, a cross-clock-domain data transmission method and device are provided. The method comprises sampling a first clock of a first clock domain with a second clock of a second clock domain and outputting a sampling signal; moving a second clock edge of the second clock according to the sampling signal, from one side of a first clock edge of the first clock to the other side; repeating the steps of sampling the first clock with the second clock and outputting the sampling signal, and moving the second clock edge of the second clock according to the sampling signal, so that the second clock edge reciprocates between the two sides of the first clock edge; determining whether to generate a clock lock signal; after the clock lock signal is generated, starting data transmission in a data path between the first clock domain and the second clock domain. The method and device of the present disclosure do not rely on traditional asynchronous handshake or FIFO buffer mechanism, avoid the delay required by synchronous logic, and are suitable for high-speed communication requirements.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of communication technology, and in particular, to a cross-clock-domain data transmission method and device. BACKGROUND

[0002] In integrated circuit design, different functional modules often work in different clock domains. Due to the frequency difference, phase offset or complete asynchronism between the clocks, a specific synchronization and handshaking mechanism needs to be adopted when transmitting data across clock domains to avoid metastability or false sampling.

[0003] There are mainly the following methods for existing cross-clock-domain data transmission:

[0004] 1. Handshake synchronization method

[0005] For two asynchronous clocks, the sending clock domain is ready to send data, and notifies the receiving clock domain through a data valid signal. The receiving end samples and synchronizes the valid signal and then latches the data, and returns a confirmation signal of latch completion. The sending end receives the confirmation signal and gets a sending confirmation signal. When the sending confirmation signal is 1, the data valid signal returns to the invalid state, and the above process is repeated.

[0006] 2. Phase buffer method

[0007] For two asynchronous clocks with the same frequency but uncertain phase, a method of phase buffer and synchronization enable signal is usually adopted. The sending end writes one or more taps of data into the buffer unit FIFO, and transmits the write enable signal through the synchronization logic. The receiving end reads the data in the buffer FIFO according to the signal.

[0008] 3. Asynchronous FIFO method

[0009] When two clocks are completely asynchronous or frequency is not synchronized, an asynchronous FIFO structure is usually adopted. The sending end writes data into the FIFO, and synchronizes the write address of the FIFO to the receiving end through Gray code conversion. The receiving end can read the data as long as the read and write addresses are detected to be different.

[0010] However, the above methods have the common shortcoming that the receiving end needs to be delayed for a certain period to latch the valid data from the sending end due to the existence of the synchronization circuit. Usually, a delay of two to three taps is needed to form a stable valid sampling signal, and then the signal is used to determine whether to latch the data. This delay reduces the data transmission efficiency and does not meet the demand of high-speed communication. SUMMARY

[0011] Based on the defects of the prior art, there is an urgent need for a low-delay cross-clock-domain data transmission method and device for high-speed communication.

[0012] The first aspect of the embodiments of the present disclosure provides a cross-clock-domain data transmission method, which comprises: sampling a first clock of a first clock domain by a second clock of a second clock domain and outputting a sampling signal to represent a phase relationship between the first clock and the second clock at a current time; moving a second clock edge of the second clock from one side of a first clock edge of the first clock to the other side of the first clock edge according to the sampling signal; repeatedly performing the steps of sampling the first clock by the second clock and outputting the sampling signal and moving the second clock edge of the second clock according to the sampling signal, so as to move the second clock edge back and forth between the two sides of the first clock edge; determining whether to generate a clock lock signal; after the clock lock signal is generated, starting data transmission in a data path between the first clock domain and the second clock domain, wherein a second data latch register driven by the second clock directly latches data of a first data latch register driven by the first clock and / or the first data latch register directly latches data of the second data latch register driven by the second clock.

[0013] The cross-clock-domain data transmission method of the embodiments of the present disclosure is applicable to the field of high-speed data communication, and enables direct latching of data between two asynchronous high-speed clock domains, thereby eliminating synchronous beat delay.

[0014] Optionally, in the cross-clock-domain data transmission method according to the first aspect of the embodiments of the present disclosure, a delay greater than or equal to a maximum deviation between the first clock edge and the second clock edge is additionally added in the data path between the first clock domain and the second clock domain.

[0015] Optionally, in the cross-clock-domain data transmission method according to the first aspect of the embodiments of the present disclosure, the determination of whether to generate the clock lock signal comprises: when a number of movements of the back-and-forth movement reaches a preset threshold, or when a time of the back-and-forth movement reaches a preset time, or according to a sampling value change rate obtained from continuous sampling signals, generating the clock lock signal when the sampling value change rate is less than or equal to a preset change rate threshold.

[0016] According to an embodiment of the present disclosure, a counter can be used to accumulate the number of movements of the back-and-forth movement. This flipping number locking method is efficient and simple to implement in hardware. In addition, the time of the back-and-forth movement can be measured and compared with a preset time, which can be used as an optional determination method for generating the clock lock signal. Furthermore, the sampling value change rate can be used to determine whether to generate the clock lock signal, for example, the sampling value change rate can be obtained by sorting and integrating the sampling signals, and then taking an absolute value of the result after filter processing. If the absolute value is less than or equal to a preset locking threshold, it is determined to generate the clock lock signal.

[0017] Optionally, the cross-clock-domain data transmission method according to the first aspect of the embodiments of the present disclosure, wherein the sampling of the second clock to the first clock and the output of the sampling signal are implemented using a D flip-flop, the first clock is connected to a data input end of the D flip-flop, the second clock is connected to a clock input end of the D flip-flop, and the D flip-flop samples a level of the first clock according to the second clock and outputs the sampling signal.

[0018] The embodiments of the present disclosure sample the first clock using the second clock, obtain a relative phase relationship between clock edges of the two clocks, and output a sampling result that can represent that the clock edge of the second clock is on the left side or the right side of the clock edge of the first clock. Optionally, a D flip-flop can be used to implement the sampling of the first clock by the second clock, without the need for complex circuits and logic.

[0019] Optionally, the cross-clock-domain data transmission method according to the first aspect of the embodiments of the present disclosure, wherein the moving of the second clock edge is implemented using a phase shifter.

[0020] Optionally, the cross-clock-domain data transmission method according to the first aspect of the embodiments of the present disclosure, wherein the number of times of moving is counted by a counter, and the counter increases the number of times of moving by one when the sampling signal changes from high to low or from low to high.

[0021] The embodiments of the present disclosure use a phase shifter to adjust the second clock edge of the second clock in the direction of the first clock edge of the first clock. Even if the first clock and the second clock are two asynchronous clocks, by continuously judging the phases of their clock edges and reciprocally approaching the clock edges, the two clocks can be used as a synchronous clock combination. Further, the counting result of the counter is used as a decision condition, and after the number of times of reciprocally adjusting satisfies a configurable number, the two clocks are regarded as synchronous clocks, at which time data transmission can be performed without the need for other additional synchronization methods.

[0022] Optionally, the cross-clock-domain data transmission method according to the first aspect of the embodiments of the present disclosure, wherein the first clock and the second clock are asynchronous clocks or the first clock and the second clock are not synchronized.

[0023] Optionally, the cross-clock-domain data transmission method according to the first aspect of the embodiments of the present disclosure, wherein the reciprocally moving of the second clock edge on both sides of the first clock edge is not implemented using a phase-locked loop, and the data path does not include a data buffer.

[0024] The second aspect of the embodiments of the present disclosure provides a cross-clock-domain data transmission device, comprising a sampling module, configured to sample a first clock of a first clock domain by a second clock of a second clock domain and output a sampling signal to represent a phase relationship between the first clock and the second clock at a current time; a phase shifter, configured to move a second clock edge of the second clock according to the sampling signal, so that the second clock edge moves from one side of a first clock edge of the first clock to the other side of the first clock edge; a lock control module, configured to determine whether to generate a clock lock signal; and a transmission control module, configured to start data transmission in a data path between the first clock domain and the second clock domain after the clock lock signal is generated, wherein a second data latch register driven by the second clock directly latches data of a first data latch register driven by the first clock and / or the first data latch register directly latches data of the second data latch register driven by the second clock.

[0025] Optionally, the cross-clock-domain data transmission device according to the second aspect of the embodiments of the present disclosure further comprises a delay module, configured to add a delay in the data path between the first clock domain and the second clock domain, and the delay is greater than or equal to a maximum deviation between the first clock edge and the second clock edge.

[0026] Optionally, the cross-clock-domain data transmission device according to the second aspect of the embodiments of the present disclosure further comprises a counter, configured to count a number of reciprocating movements of the second clock edge on both sides of the first clock edge, and the lock control module determines whether to generate the clock lock signal, including generating the clock lock signal when the number of reciprocating movements reaches a preset threshold.

[0027] Optionally, the cross-clock-domain data transmission device according to the second aspect of the embodiments of the present disclosure, the lock control module determines whether to generate the clock lock signal, including generating the clock lock signal when a reciprocating time reaches a preset time; or the lock control module further comprises a filter, and the lock control module integrates a plurality of continuous sampling signals to obtain a change rate of a sampling value, and generates the clock lock signal when the change rate of the sampling value is less than or equal to a preset lock threshold.

[0028] Optionally, the cross-clock-domain data transmission device according to the second aspect of the embodiments of the present disclosure, the sampling module is a D flip-flop, the first clock is connected to a data input end of the D flip-flop, the second clock is connected to a clock input end of the D flip-flop, and the D flip-flop samples a level of the first clock according to the second clock and outputs the sampling signal. Optionally, the sampling module and the phase shifter do not comprise a phase-locked loop, and the data path does not comprise a data buffer.

[0029] In the prior art, it is usually required to lock the frequency and phase of two clocks completely through handshaking or using a complex circuit such as a phase-locked loop (PLL), so as to realize cross-clock-domain data transmission. Such a scheme is complex in design, large in resource consumption, and introduces large delay.

[0030] In contrast, in the embodiment of the present disclosure, the phase shifter adjusts the phase of the second clock, and further, the counter counts and judges the number of times that the clock edge of the second clock crosses the clock edge of the first clock, and when the clock edge of the second clock reciprocates on both sides of the clock edge of the first clock and reaches the set crossing number of times, the two clocks can be regarded as a "synchronous clock group". On this basis, the time node at which the data can start to be transmitted correctly can be determined, without additional handshake logic or phase-locked circuit, to complete the synchronization control in the cross-clock-domain data transmission process.

[0031] Therefore, the scheme of the present disclosure can realize data synchronization transmission only by using a relatively simple circuit structure and control logic, effectively improves the delay problem in the high-speed asynchronous cross-clock-domain data transmission process, and improves the overall reliability and realizability of the system.

[0032] Implementing any device or method of the present disclosure does not necessarily achieve all the advantages described above. Other features and advantages of the present disclosure will be described in the following embodiments, and some will become apparent from the embodiments, or will be understood by those skilled in the art. The purposes and advantages of the embodiments of the present disclosure can be achieved and obtained by the structures indicated in the specification, claims and drawings. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present disclosure, but not limit the present disclosure.

[0034] Figure 1 A schematic flowchart of a cross-clock-domain data transmission method according to an embodiment of the present disclosure is shown;

[0035] Figure 2 A circuit schematic diagram of sampling of the first clock by the second clock according to an embodiment of the present disclosure is shown;

[0036] Figure 3 A phase relationship diagram of the first clock and the second clock according to an embodiment of the present disclosure is shown;

[0037] Figure 4 A circuit schematic diagram of delaying the data transmission path between the first and second clock domains according to an embodiment of the present disclosure is shown;

[0038] Figure 5 A structural schematic diagram of a cross-clock-domain data transmission apparatus is shown according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Various different embodiments can be combined with each other to form other embodiments not shown in the following description. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative effort fall within the scope of protection of the present disclosure.

[0040] Unless otherwise defined, technical terms or scientific terms used herein should be understood as having the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms "first", "second" and similar terms used in the description and the claims of the present disclosure do not necessarily mean any order, number or importance, but are only used to distinguish different components. Similarly, the terms "one" or "a" or similar terms do not necessarily mean a quantity restriction. The terms "including", "containing" and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, without excluding other elements or objects. The terms "connected" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "up", "down", "left", "right" and the like only represent relative positional relationships, which can change accordingly when the absolute positions of the described objects change.

[0041] Cross-clock-domain generally refers to the process of signal or data transmission or interaction between different clock domains in digital circuits, which needs to ensure reliable delivery of data in asynchronous or different clock environments.

[0042] Figure 1 A schematic flowchart of a cross-clock-domain data transmission method is shown according to an embodiment of the present disclosure. In this embodiment, data transmission is performed between a first clock domain and a second clock domain, wherein the first clock domain includes a first clock and the second clock domain includes a second clock. The first clock and the second clock can be asynchronous clocks or the two clocks can be out of sync.

[0043] In step S11, the second clock samples the first clock to obtain a sampled signal. Based on this sampled signal, the phase relationship between the clock edges of the first clock and the second clock at the current moment can be determined. The sampled signal can be either a high level or a low level. For example, the sampling of the first clock by the second clock can be done using... Figure 2 The circuit shown has a first clock connected to the data input of a D flip-flop and a second clock connected to its clock input. A high output signal indicates that the first clock edge precedes the second clock edge, and a low output signal indicates that the second clock edge precedes the first clock edge. The output of the D flip-flop can be used to determine the phase relationship between the current clock edges of the two clocks. The D flip-flop circuit is simple, stable, and provides instant feedback. Alternatively, other circuits can be used to determine the phase relationship between the clock edges of the first and second clocks.

[0044] In step S12, when the clock edge of the second clock is to the right of the first clock, the second clock moves to one side through the phase shifter until the clock edge of the second clock is to the left of the first clock; when the clock edge of the second clock is to the left of the first clock, the second clock moves to one side through the phase shifter until the clock edge of the second clock is to the right of the first clock.

[0045] For example, if using Figure 2 When the D flip-flop samples the first clock with the second clock, it outputs a high level, which determines that the clock edge of the second clock is to the right of the clock edge of the first clock (e.g., Figure 3 As shown in scenario (1)). The clock edge of the second clock is offset to the right by X1 relative to the clock edge of the first clock. At this time, in order to bring the second clock closer to the first clock, the phase shifter can move the clock edge of the second clock to the left until the clock edge of the second clock moves to the left of the first clock. When the sampling result outputs a low level, it can be determined that the clock edge of the second clock is to the left of the first clock (e.g., Figure 3 As shown in scenario (2)). The clock edge of the second clock is shifted to the left by X2 relative to the clock edge of the first clock. At this time, the phase shifter can move the second clock to the right until the clock edge of the second clock moves to the right of the first clock.

[0046] Steps S11 and S12 will be repeated, causing the clock edge of the second clock to move back and forth on both sides of the clock edge of the first clock.

[0047] In step S13, it is determined whether the clock lock signal is generated. If it is determined that the clock lock signal is not generated, steps S11 and S12 are repeated. The determination of whether the clock lock signal is generated can be performed in various ways. Alternatively, it is determined whether the number of times the phase shifter moves the clock edge of the second clock reaches a threshold value. If the number of times the phase shifter moves the clock edge of the second clock reaches the threshold value, it is determined that the clock lock signal is generated, otherwise, the clock lock signal is not generated. The number of times the phase shifter moves the clock edge of the second clock can be counted by a counter. When the sampling signal changes from high to low or from low to high, the counter is increased by one, i.e. each time the clock edge of the second clock crosses the clock edge of the first clock, the counter is increased by one.

[0048] Alternatively, it can be determined whether the time the phase shifter moves the clock edge of the second clock reaches a predetermined time. If the time the phase shifter moves the clock edge of the second clock reaches the predetermined time, it is determined that the clock lock signal is generated, otherwise, the clock lock signal is not generated. The time can be measured by the first clock, the second clock or another clock, for example, the time can be measured by counting the rising edge or the falling edge of the clock signal.

[0049] Further alternatively, the rate of change of the sampling signal can be obtained by processing the sampling signal to determine whether the clock lock signal is generated. For example, the sampling signal is first processed to obtain a series of continuous sampling values, the sampling values are integrated; the result of the integration is input to an infinite impulse response (IIR) filter for filtering; the absolute value of the result of the filtering is obtained, if the absolute value is less than or equal to a preset lock threshold, it is determined that the clock signal is locked. This way, by calculating the rate of change of the sampling value, it is confirmed whether the change of the sampling value is relatively low, for example, whether it is close to 0, thereby determining whether the clock edge of the second clock moves regularly on both sides of the clock edge of the first clock. When the clock lock condition between the two clocks is reached, the clock is locked.

[0050] When it is determined that the clock lock signal is generated, in step S14, the clock lock signal is generated, which indicates that the first and second clocks can be regarded as synchronous clocks.

[0051] In step S15, when the lock signal is generated, i.e. the first and second clocks can be regarded as synchronous clocks, data transmission is started.

[0052] Further, according to the reciprocal shift of the clock edge of the second clock relative to the clock edge of the first clock, a delay greater than or equal to the shift can be added to the data path transmitted between the first clock domain and the second clock domain. Alternatively, the data path can be added with a delay greater than or equal to the delay corresponding to the maximum shift between the clock edge of the first clock and the clock edge of the second clock. At this time, the data latch register driven by the second clock directly latches the data of the data register driven by the first clock. Similarly, the data latch register driven by the first clock directly latches the data of the data register driven by the second clock. Here, data synchronous transmission can be achieved between the first clock domain and the second clock domain without using other synchronization methods.

[0053] The maximum shift between the clock edge of the first clock and the clock edge of the second clock can be affected by the clock frequency, response speed, etc. of the system, which can be estimated in advance as a determined value.

[0054] Figure 4 A circuit schematic diagram for adding delay to the data transmission path between the first and second clock domains according to an embodiment of the present disclosure is shown. The data latch register is implemented using a D flip-flop. When the first clock domain is the sending end and the second clock domain is the receiving end, the data of the first clock domain and the first clock of the first clock domain are connected to the data end and the clock end of the first D flip-flop 41 respectively, obtaining the first output data of the first clock domain. The first output data is connected to the data end of the second D flip-flop 43 via the first delay module 42, and the second clock of the second clock domain is connected to the clock end of the second D flip-flop, obtaining the second output data, so that the data latch register driven by the second clock directly latches the data of the data register driven by the first clock. Similarly, when the second clock domain is the sending end and the first clock domain is the receiving end, the data of the second clock domain and the second clock of the second clock domain are connected to the data end and the clock end of the third D flip-flop 44 respectively, obtaining the third output data of the second clock domain. The third output data is connected to the data end of the fourth D flip-flop 46 via the second delay module 45, and the first clock of the first clock domain is connected to the clock end of the fourth D flip-flop, obtaining the fourth output data, so that the data latch register driven by the first clock directly latches the data of the data register driven by the second clock.

[0055] Figure 5 A structural schematic diagram of a cross-clock domain data transmission device 50 according to an embodiment of the present disclosure is shown. The device includes a sampling module 51, a phase shifter 52, a counter 53, a lock control module 54, a delay module 55, and a transmission control module 56.

[0056] The sampling module 51 receives the first clock of the first clock domain and the second clock of the second clock domain, and the output signal of the sampling module 51 can represent the phase relationship between the clock edges of the first clock and the second clock. For example, the sampling module 51 can sample the first clock with the second clock. More specifically, the sampling module 51 can be implemented by a D flip-flop, and the first clock and the second clock are connected to the data input terminal and the clock input terminal of the D flip-flop respectively, and the sampling signal output from the output terminal represents whether the clock edge of the second clock is earlier or later than the clock edge of the first clock.

[0057] According to the sampling signal output by the sampling module 51, the phase shifter 52 performs phase shift on the second clock. When the phase relationship indicates that the clock edge of the second clock is on the right side of the clock edge of the first clock, the phase shifter moves the clock edge of the second clock to one side until the clock edge of the second clock moves to the left side of the clock edge of the first clock; when the phase relationship indicates that the clock edge of the second clock is on the left side of the clock edge of the first clock, the phase shifter moves the clock edge of the second clock to one side until the clock edge of the second clock moves to the right side of the clock edge of the first clock.

[0058] The counter 53 records the number of times the phase shifter 52 reciprocally moves the clock edge of the second clock, and generates the clock lock signal when it is determined that the number of times the phase shifter moves the clock edge of the second clock is greater than a threshold value. The number of times the phase shifter moves the clock edge of the second clock can be counted according to the number of times the sampling signal changes from high to low or from low to high. The lock signal is used to indicate that the first and second clocks can be regarded as a group of synchronous clocks. If the threshold value is not reached, the counting of the reciprocally moving clock edge continues. The counter counts the number of times the sampling signal changes, and determines whether to generate the clock lock signal based on the number of times the sampling signal changes. This way, the circuit structure and control logic required are relatively simple, and the synchronous transmission of data can be easily realized.

[0059] The lock control module 54 is used to determine whether to generate the clock lock signal, and control the generation of the clock lock signal when it is determined that the clock lock signal is to be generated. In this embodiment, whether to generate the clock lock signal can be determined by judging whether the number of movements reaches a preset threshold value.

[0060] The delay module 55 is located in the transmission path of the first clock domain and the second clock domain. The delay size of the delay module 55 is determined according to the maximum offset X between the clock edge of the first clock and the clock edge of the second clock, so as to add a delay to the data path, which is greater than or equal to the delay corresponding to or the same as the maximum offset.

[0061] Since the first clock domain and the second clock domain can be the receiving end and the sending end respectively, when the second clock domain is the receiving end and the first clock domain is the sending end, the delay module 55 can be arranged on the path through which the first clock domain sends data to the second clock domain. Similarly, for the data driven by the second clock, the delay module 55 can be arranged on the path through which the second clock domain sends data to the first clock domain.

[0062] For a specific example of delay module 55, please refer to the above text. Figure 4 The descriptions of the first delay module 42 and the second delay module 45 are not repeated here. Delay module 55 adjusts the data to a stable sampling window, ensuring that the sampling operation falls within the stable data region and preventing metastability issues. Delay module 55 can be implemented using a digital delay unit or a mixed-signal delay unit; no restriction is placed here.

[0063] The transmission control module 56, after generating a clock lock signal, initiates data transmission in the data path between the first clock domain and the second clock domain. This is achieved by the second data latch register driven by the second clock directly latching the data in the first data latch register driven by the first clock, and / or by the first data latch register driven by the first clock directly latching the data in the second data latch register driven by the second clock. The lock control module 54 and the transmission control module 56 can be implemented using a processor or through specific logic circuitry. The lock control module 54 and the transmission control module 56 can be implemented as a single circuit module or as separate, independent circuit modules.

[0064] Optionally, the cross-clock domain data transmission device may not include a counter 53 for counting the number of clock edges that the phase shifter 52 reciprocates along the second clock edge. The locking control module can determine whether to generate a clock lock signal by determining whether the time for the phase shifter to move the second clock edge reaches a predetermined time; if the predetermined time is reached, it determines to generate a clock lock signal. Time measurement can be performed using a first clock, a second clock, or another clock; for example, time can be measured by counting the rising or falling edges of the clock signal.

[0065] Furthermore, optionally, the cross-clock domain data transmission device can determine whether to generate a clock lock signal by processing the sampled signal to obtain the rate of change of the sampled signal. The lock control module may include an integrator circuit and a filter (not shown). For example, the sampled signal is first serialized to obtain a set of continuous sampled values, and then integrated. The result of the integration is input into an infinite impulse response (IIR) filter for filtering. The absolute value of the filtered result is taken, and if the absolute value is less than or equal to a preset lock threshold, clock signal lock is determined. This method determines whether the second clock edge moves regularly on both sides of the first clock edge by calculating the rate of change of the sampled value. When the lock condition between the two clocks is met, clock lock is performed.

[0066] The clock of the embodiment of the present disclosure can be an original clock signal, or an inverse signal of the original clock signal, depending on the actual circuit design requirement. Generally, to ensure the stability of the sampling and the accuracy of the phase relationship determination, the first clock edge and the second clock edge can be of the same type, i.e., both can be rising edges or both can be falling edges.

[0067] The embodiment of the present disclosure utilizes the phase shifter to reciprocate the clock edges of two asynchronous clocks, and when the reciprocation times reach a predetermined number, the two clocks are considered as a synchronous clock combination for use, which determines the starting node at which the data can be correctly transmitted, and does not require additional or other complex synchronization mechanisms. Compared with the cross-clock domain data transmission method of the prior art, the present disclosure uses a simple phase shifter and a counter to achieve delay improvement for a high-speed asynchronous cross-clock domain data transmission system, avoids complex circuit logic and complex clock locking relationship of the existing design, and does not need to use a phase-locked loop or a data buffer to achieve synchronous data transmission. Since the above-mentioned method and device of the present disclosure no longer rely on the traditional asynchronous handshake method or the FIFO buffer mechanism, the delay required by the synchronization logic is avoided, and the demand for high-speed communication is met.

[0068] The embodiments of the present disclosure can be modified and changed in various ways without departing from the spirit and scope of the present disclosure. Therefore, it should be understood that the protection scope of the present disclosure should not be limited to the above exemplary embodiments, but should cover the full scope defined by the claims and their equivalents.

Claims

1. A method for cross-clock-domain data transfer, the method comprising: The method comprises the following steps: sampling a first clock of a first clock domain by a second clock of a second clock domain and outputting a sampling signal to represent a phase relationship between the first clock and the second clock at a current time, wherein the sampling of the first clock by the second clock and the outputting of the sampling signal are implemented by using a D flip-flop which samples a level of the first clock according to the second clock and outputs the sampling signal; moving a second clock edge of the second clock according to the sampling signal, so that the second clock edge moves from one side of a first clock edge of the first clock to the other side of the first clock edge; repeating the steps of sampling the first clock by the second clock and outputting the sampling signal and the step of moving the second clock edge of the second clock according to the sampling signal, so that the second clock edge reciprocally moves on both sides of the first clock edge; determining whether to generate a clock lock signal; after the clock lock signal is generated, enabling data transmission in a data path between the first clock domain and the second clock domain, wherein a second data latch register driven by the second clock directly latches data of a first data latch register driven by the first clock and / or the first data latch register directly latches data of the second data latch register driven by the second clock.

2. The method of claim 1, wherein, attaching a delay in the data path between the first clock domain and the second clock domain, the delay being greater than or equal to a maximum deviation between the first clock edge and the second clock edge, the reciprocally moving of the second clock edge on both sides of the first clock edge being implemented without using a phase-locked loop, and the data path not including a data buffer.

3. The method of claim 1, wherein the method further comprises: The determination of whether to generate the clock lock signal comprises: when a moving number of the reciprocally moving reaches a preset threshold, or when a time of the reciprocally moving reaches a preset time, or according to a sampling value change rate obtained according to a plurality of continuous sampling signals, generating the clock lock signal when the sampling value change rate is less than or equal to a preset change rate threshold.

4. The method of claim 1, wherein, The first clock is connected to a data input end of the D flip-flop, and the second clock is connected to a clock input end of the D flip-flop.

5. The method of claim 1, wherein, The moving of the second clock edge is implemented by using a phase shifter, and / or the moving number of the reciprocally moving is counted by a counter, and the moving number is increased by one when the sampling signal changes from high to low or from low to high.

6. A cross-clock domain data transfer apparatus, characterized by, The method comprises the following steps: sampling a first clock of a first clock domain by a second clock of a second clock domain and outputting a sampling signal to represent a phase relationship between the first clock and the second clock at a current time, wherein the sampling module is a D flip-flop which samples a level of the first clock according to the second clock and outputs the sampling signal; moving a second clock edge of the second clock according to the sampling signal, so that the second clock edge moves from one side of a first clock edge of the first clock to the other side of the first clock edge; determining whether to generate a clock lock signal; a transmission control module configured to start data transmission in a data path between the first clock domain and the second clock domain after the clock lock signal is generated, wherein the second clock driven second data latch register directly latches data of the first clock driven first data latch register and / or the first clock driven first data latch register directly latches data of the second clock driven second data latch register, wherein the second clock repeatedly samples the first clock to output the sampling signal and moves the second clock edge of the second clock according to the sampling signal, so that the second clock edge reciprocates on both sides of the first clock edge.

7. The cross-clock domain data transfer apparatus of claim 6, wherein, The delay module is further configured to add delay in the data path between the first clock domain and the second clock domain, the delay being greater than or equal to the maximum deviation between the first clock edge and the second clock edge, the reciprocation of the second clock edge on both sides of the first clock edge is achieved without using a phase-locked loop, and the data path does not include a data buffer.

8. The cross-clock domain data transfer apparatus of claim 6, wherein, The counter is further configured to count the number of reciprocations of the second clock edge on both sides of the first clock edge, and the lock control module is configured to determine whether to generate the clock lock signal, including generating the clock lock signal when the number of reciprocations reaches a preset threshold.

9. The cross-clock domain data transfer apparatus of claim 6, wherein, The lock control module is configured to determine whether to generate the clock lock signal, including generating the clock lock signal when the time of reciprocation of the second clock edge on both sides of the first clock edge reaches a preset time; or the lock control module further includes a filter, the lock control module integrates a plurality of continuous sampling signals to obtain a change rate of the sampling value, and generates the clock lock signal when the change rate of the sampling value is less than or equal to a preset lock threshold.

10. The cross-clock domain data transfer apparatus of claim 6, wherein, The first clock is connected to a data input end of the D flip-flop, and the second clock is connected to a clock input end of the D flip-flop.

Images