A multi-precision floating point fused multiply-add structure and microprocessor architecture

Abstract

The application provides a multi-precision floating point fused multiply-add structure and a microprocessor architecture, the floating point fused multiply-add structure comprising: in the first stage pipeline, an input preprocessing module decomposes input operands to obtain a sign bit, an exponent bit and a mantissa bit; a Booth encoder generates partial products through a base-4 Booth encoding algorithm, and a tree array multiplier compresses the partial products into three groups; in the second stage pipeline, a CSA4-2 compression adder compresses the three groups of partial products and the mantissa bit after shift alignment into two groups; an adder module sums the two groups of partial products to obtain a mantissa summation result; in the third stage pipeline, a leading zero detection module detects the leading zero of the mantissa summation result, and adjusts the exponent and the mantissa to obtain a normalized result; in the fourth stage pipeline, the floating point data is rounded. The application improves the operation performance, energy efficiency ratio and adaptability of the floating point fused multiply-add structure, thereby balancing the high performance and high energy efficiency of the microprocessor.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of computer technology, and particularly relates to a multi-precision floating point fused multiply-add structure and a microprocessor architecture. BACKGROUND

[0002] In emerging applications such as Internet of Things, artificial intelligence and edge computing, embedded processors have higher requirements for floating point operation capability, especially in computationally intensive tasks such as image processing, signal processing and machine learning inference, the floating point multiply-add (Fused Multiply-Add, FMA) operation has become a core computing unit. FMA fuses multiplication and addition into one operation, which can effectively reduce the number of instructions and intermediate rounding errors, thereby significantly improving the computing throughput. IEEE 754 standard specifies the mathematical behavior and rounding rules of floating point multiply-add operations, and RISC-V instruction set extends instructions such as FMUL, FMADD, etc. on this basis to support efficient hardware implementation.

[0003] Single precision format (such as FP32) is difficult to achieve an ideal balance between performance and power consumption, and floating point operation units supporting multiple precision formats (such as FP32, FP16, BF16) have become an important trend in modern processor design. Low-precision operations not only help to reduce hardware complexity and power consumption, but are also particularly suitable for edge devices that are sensitive to energy efficiency. RISC-V, as an open and modular instruction set architecture, has a flexible ISA extension mechanism, which facilitates customized instruction extension according to specific application requirements. Although current research and application of low-precision floating point calculation in academia and industry have achieved remarkable results, in the implementation of processors under the RISC-V architecture, the basic precision of FP32 is still supported, and the native support for low-precision formats such as FP16 and BF16 is limited. Especially in resource-constrained and power-sensitive edge computing scenarios, there is still a lack of optimized design that balances flexibility, energy efficiency and resource occupation.

[0004] Therefore, in view of the problems of insufficient support for multi-precision floating point multiply-add operation, low instruction scheduling efficiency and low resource utilization, a solution is urgently needed. SUMMARY

[0005] The present application discloses a multi-precision floating point fused multiply-add structure and a microprocessor architecture, which can improve the operation performance, energy efficiency ratio and adaptability of the floating point fused multiply-add structure, and balance the high performance and high energy efficiency of the floating point fused multiply-add structure in the microprocessor.

[0006] Other purposes and advantages of the present application can be further understood from the technical features disclosed in the present application.

[0007] To achieve one or some or all of the above purposes or other purposes, in a first aspect, the application provides a multi-precision floating point fused multiply-add structure, comprising:

[0008] a first stage pipeline comprising an input preprocessing module, a Booth encoder, a tree array multiplier, an exponent difference module, and a sign logic module, the input preprocessing module being configured to decompose input operands to obtain sign bits, exponent bits, and mantissa bits; the sign logic module being configured to determine the sign bits of the operands; the exponent difference module being configured to calculate the difference between the exponent bits in combination with the sign bits to determine an exponent difference; the Booth encoder being configured to encode the mantissa bits by a base-4 Booth encoding algorithm to generate partial products, and the tree array multiplier being configured to compress the partial products into three groups of partial products;

[0009] a second stage pipeline comprising a CSA 4-2 compression adder, an alignment shift module, and an adder module, the alignment shift module being configured to calculate the size of an alignment shift according to the exponent difference and to perform shift alignment on the mantissa bits; the CSA 4-2 compression adder being configured to compress the three groups of partial products and the shift-aligned mantissa bits into two groups of partial products; and the adder module being configured to sum the two groups of partial products to obtain a mantissa sum result;

[0010] a third stage pipeline comprising a leading zero detection module, an exponent logic module, and a shift logic module, the leading zero detection module being configured to perform leading zero detection on the mantissa sum result to output the number of leading zeros, the exponent logic module being configured to adjust the number of leading zeros, and the shift logic module being configured to adjust the number of leading zeros to obtain a normalized result;

[0011] a fourth stage pipeline comprising a rounding module, the rounding module being configured to round floating point data according to the normalized result and a rounding mode instruction.

[0012] Further, in the first stage pipeline, the input preprocessing module is configured to perform exception determination on the input operands according to the decomposed sign bits, exponent bits, and mantissa bits, and if the operands are NAN values or infinite values, the operation is stopped and the result and a state exception are directly output.

[0013] Further, in the first stage pipeline, the first stage pipeline comprises a buffer configured to buffer floating point instructions and operands contained in the floating point instructions and transmit the floating point instructions and the operands to the second stage pipeline.

[0014] Further, in low-precision floating-point multiply-add operations, an 11×11 bit multiplier is used; in floating-point mantissa multiplication, two low-precision mantissa multiplication results are generated in parallel and implemented using single-precision floating-point mantissa multiplication, and the 11×11 bit multiplier uses a Booth encoder.

[0015] Further, the expression for the tree array multiplier to compress the partial products into three groups of partial products is:

[0016] ;

[0017] Among them, the partial products compressed by the tree array multiplier are determined by the maximum height sequence d decides, and j is the initial value satisfying the maximum value of d j < min(n1, n2), where n1 and n2 are the number of bits of the input multiplicand and multiplier respectively.

[0018] Further, in single-precision floating-point multiply-add operations, single-precision floating-point mantissa multiplication is implemented using 4 11×11 bit multipliers, 4 2×11 bit multipliers, and 1 2×2 bit multiplier.

[0019] Further, the 2×11 bit multiplier includes two 13-bit data selectors and one adder, the input multipliers of the data selectors are all 11 bits, and the control signals of the data selectors are all 2 bits.

[0020] Further, in the second-level pipeline, the floating-point instructions include at least one of floating-point multiplication instructions, floating-point addition instructions, and floating-point multiply-add instructions;

[0021] If there are two consecutive related floating-point instructions and there is a register conflict, when the first instruction contains a floating-point multiplication instruction and the second instruction is a floating-point addition instruction, the floating-point multiplication is executed first, and the floating-point addition is executed in the next clock cycle;

[0022] If there are two consecutive related floating-point instructions and there is a register conflict, when the first instruction is a floating-point addition instruction and the second instruction contains a floating-point multiplication instruction, the floating-point addition is executed first, paused in the next clock cycle, and the result of the floating-point addition is forwarded to the first-level pipeline before executing the floating-point multiplication;

[0023] If the two floating-point instructions are not related, they are executed according to the original order. <00°00055>Further, in the second-level pipeline, the execution of floating-point multiplication and floating-point addition is controlled by a state machine. [[ID=Further, if there are two related consecutive floating-point instructions, and the first instruction is a floating-point multiplication instruction, and the second floating-point instruction is a floating-point addition instruction, in the first clock cycle, the floating-point multiplication is executed;

[0026] In the second clock cycle, the CSA 4-2 compression adder performs floating-point addition based on the first addition operand shift result of the first stage pipeline, the floating-point mantissa multiplication result generated by the second stage pipeline in the first clock cycle, and the second addition operand shift result, wherein the first addition operand shift result represents the exponent difference of the exponent of the largest operand in the two related consecutive floating-point instructions in the first stage pipeline in the second clock cycle, the second addition operand shift result represents the exponent difference of the exponent of the largest operand in the two related consecutive floating-point instructions in the second stage pipeline in the first clock cycle, and four input ports of the CSA 4-2 compression adder are used.

[0027] Further, if the first floating-point instruction is a floating-point multiplication instruction, the second floating-point instruction is a floating-point multiply-add instruction, and the result of the floating-point multiplication instruction is the addition operand of the second floating-point instruction, in the second clock cycle, the floating-point multiplication of the first floating-point instruction is calculated to obtain the floating-point mantissa multiplication result.

[0028] The floating-point mantissa multiplication result of the first floating-point instruction is used as the addition operand of the second floating-point instruction, and a shift operation is performed based on the exponent difference of the largest exponent of the two instructions.

[0029] In the third clock cycle, the CSA 4-2 compression adder performs floating-point addition based on the three floating-point mantissa multiplication partial products of the second floating-point instruction and the floating-point mantissa multiplication result of the first floating-point instruction, and four input ports of the CSA 4-2 compression adder are used.

[0030] Further, if the first floating-point instruction of the two floating-point instructions is a floating-point addition instruction, the second floating-point instruction is a floating-point multiplication instruction or a floating-point multiply-add instruction, and the multiplication operand used by the second floating-point instruction is generated by the first floating-point instruction, the pipeline is stalled for one cycle when the second floating-point instruction is executed.

[0031] Further, the rounding at least includes one of round to nearest, round to zero, round down, round up, and round to nearest.

[0032] In a second aspect, the present application provides a microprocessor architecture, which comprises the multi-precision floating-point fused multiply-add structure according to any one of the first aspect.

[0033] Further, the microprocessor architecture comprises:

[0034] The instruction fetching module is configured to fetch a floating-point instruction, and the instruction fetching module comprises a pre-decoding unit configured to decode a source register address; wherein the floating-point instruction comprises at least one of a floating-point multiply-add instruction, a floating-point multiply instruction and a floating-point add instruction;

[0035] The decoding module comprises a buffering unit configured to buffer a destination register address of the floating-point instruction; the decoding module is configured to determine whether the destination register address is the same as the source register address, and determine whether there is a register conflict between the current floating-point instruction and a next floating-point instruction, so as to determine whether to stall the pipeline.

[0036] The execution module is configured to send the current floating-point instruction into the floating-point fused multiply-add structure, and obtain an execution result.

[0037] The memory accessing module is configured to write the execution result back to a register file, and complete the instruction execution.

[0038] Further, the decoding module is configured to determine whether there is a register conflict between the current floating-point instruction and the next floating-point instruction, and if there is a register conflict and the next instruction comprises a floating-point multiply instruction, stall the pipeline for one cycle.

[0039] The above multi-precision floating-point fused multiply-add structure and the microprocessor architecture are implemented in a multi-cycle form in the floating-point multiply partial product summation stage and the floating-point addition stage through a four-stage pipeline; the tree array multiplier is used to quickly compress the partial product in the multiplication stage, so that the operation speed is improved, the number of full adders and half adders required is reduced, and the hardware area power consumption is reduced; meanwhile, the hierarchical tree array multiplier effectively relieves the delay bottleneck of the first-stage pipeline, and reasonably allocates the partial multiplication delay to the addition stage of the second-stage pipeline, so that the second-stage pipeline reduces the hardware resources and realizes balanced optimization of the overall delay. Therefore, the operation performance, the energy efficiency ratio and the adaptability of the floating-point fused multiply-add structure are improved, so that the high performance and the high energy efficiency of the floating-point fused multiply-add structure in the microprocessor are balanced.

[0040] In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the following preferred embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings described below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creating any creative labor.

[0042] Figure 1 The figure is a structural block diagram of the multi-precision floating-point fused multiply-add structure of the present application.

[0043] Figure 2 A single precision multiplier result diagram for the present application.

[0044] Figure 3 A 2x11 bit multiplier implementation framework diagram for the present application.

[0045] Figure 4 A block diagram of the microprocessor architecture for the present application.

[0046] Figure 5 A floating point multiply-add, floating point add instruction execution diagram for the present application when a register conflict occurs.

[0047] Figure 6 A floating point add, floating point multiply instruction execution diagram for the present application when a register conflict occurs.

[0048] Figure 7 A floating point multiply-add or add, floating point multiply-add instruction execution diagram for the present application when a register conflict occurs. DETAILED DESCRIPTION

[0049] The foregoing and other technical contents, features and effects of the present application will be clearly presented in the following detailed description of a preferred embodiment in conjunction with the accompanying drawings. The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged under appropriate circumstances, which is only a way of distinguishing the objects with the same properties in the description of the embodiments of the present application.

[0050] The multi-precision floating point fused multiply-add structure provided by the embodiment of the present application includes a four-stage pipeline. The first stage pipeline includes an input preprocessing module, a Booth encoder, a tree array multiplier, an exponent difference module, and a sign logic module. The input preprocessing module is used to decompose the input operand to obtain the sign bit, the exponent bit and the mantissa bit. The sign logic module is used to determine the sign bit of the operand. The exponent difference module is used to calculate the difference between the exponents in combination with the sign bit to determine the exponent difference. The Booth encoder encodes the mantissa bit to generate partial products by the base-4 Booth encoding algorithm. The tree array multiplier is used to compress the partial products into three groups of partial products.

[0051] The second stage pipeline includes a CSA 4-2 compression adder, an alignment shift module, and an adder module. The alignment shift module is used to calculate the size of the alignment shift according to the exponent difference and to shift and align the mantissa bit. The CSA 4-2 compression adder is used to compress the mantissa bit after the three groups of partial products are compressed and shifted and aligned into two groups of partial products. The adder module is used to sum the data after the shift and alignment to obtain the sum of the mantissa.

[0052] The third stage pipeline includes a leading zero detection module, an exponent logic module and a shift logic module. The leading zero detection module is configured to detect leading zeros of the sum of the mantissas and output the number of leading zeros. The exponent logic module is configured to adjust the number of leading zeros. The shift logic module is configured to adjust the mantissa based on the number of leading zeros to obtain a normalized result.

[0053] The fourth stage pipeline includes a rounding module. The rounding module is configured to round the floating point data based on the normalized result and a rounding mode instruction.

[0054] The multi-precision floating point fused multiply-add structure of the present application is implemented in a multi-cycle form in the floating point multiplication partial product summation stage and the floating point addition stage through a four-stage pipeline. In the multiplication stage, a tree array multiplier is used to quickly compress the partial products, thereby improving the operation speed, reducing the number of full adders and half adders required, and reducing the hardware area power consumption. Meanwhile, the hierarchical tree array multiplier effectively alleviates the delay bottleneck of the first stage pipeline, reasonably allocates the partial multiplication delay to the addition stage of the second stage pipeline, and balances the overall delay by using the multi-cycle multiplexing of the second stage pipeline to reduce the hardware resources.

[0055] Specifically, referring to Figure 1 is a structure diagram of a multi-precision floating point fused multiply-add structure of the present application. The first stage pipeline is configured to decompose three input floating point operands (op-a / op-b / op-c). The pre-processing module decomposes each floating point operand into a sign bit Sign, an exponent bit Exp and a mantissa bit Man3, and performs an exception judgment based on the decomposed result. If the input data is NAN or infinite, the calculation path operation is stopped, and the result and state exception are directly output. The buffer is configured to buffer the operands and other input information when the instruction includes multiplication. The exponent difference module is configured to perform an exponent difference calculation to determine the shift distance. The sign logic module is configured to determine the sign bit based on the input three operand signals. The Booth encoder is configured to use base 4 Booth encoding to generate partial products, and the tree array multiplier is configured to compress the partial products to three groups. In this embodiment, the tree array multiplier is preferably a DaddaTree compressor.

[0056] In the second stage pipeline, the CSA 4-2 compression adder receives three groups of partial products from the first stage pipeline; and is compressed to two groups, the alignment shift module calculates the size of the alignment shift according to the index difference from the first stage, and simultaneously shifts and aligns the tail number of the operand op-c, and transmits the result to the CSA 4-2 compression adder; the CSA 4-2 compression adder compresses the received three groups of partial products and the tail number after the shift and alignment to two groups, and the adder module receives two groups of partial products, and performs summation to obtain the tail number summation result. In the second stage pipeline, whether a floating point multiplication instruction or a floating point addition instruction is executed is controlled by a state machine, and the judgment condition is distinguished according to the different execution sequences of two related floating point instructions or a single instruction. Among them, the floating point instruction includes at least one of the floating point fused multiply-add instruction, the floating point multiplication instruction, and the floating point addition instruction.

[0057] Further, if there are two floating point instructions in succession and there is a register conflict, the floating point multiplication state is entered first, and the next clock cycle enters the floating point addition state, if the instructions are not related, the original sequence is executed, and the pipeline is paused as needed. When a single-instruction floating point multiply-add operation is executed, in the next clock cycle, the CSA 4-2 compression adder receives the result from the third addition operand after the shift and the floating point tail number multiplication result generated by the second stage pipeline in the last clock cycle, the tail number multiplication is subtracted from the index corresponding to the third addition operand to generate an index difference, and the third tail number addition operand is shifted according to the index difference, at this time, 2 of the four input ports of the CSA 4-2 compression adder are used, and the other 2 ports are zeroed.

[0058] When the floating point fused multiply-add instruction is executed, if it is two consecutive floating point instructions, and the first instruction contains a floating point multiplication instruction (floating point multiplication instruction or floating point multiply-add instruction), and the second instruction is a floating point addition instruction, the operation in the first clock cycle is unchanged, that is, the floating point multiplication is executed. In the second clock cycle, the CSA 4-2 compression adder receives the result of the third addition operand after the shift from the first stage pipeline (the shift length is the index difference formed by taking the index of the largest operand in the two instructions as the standard in the second clock cycle of the first stage pipeline), the floating point tail number multiplication result generated by the second stage pipeline in the first clock cycle, and the result of the third addition operand after the shift (the shift length is the index difference formed by taking the index of the largest operand in the two instructions as the standard in the first clock cycle of the second stage pipeline), at this time, 3 of the four input ports of the CSA 4-2 compression adder are used, and the other 1 port is zeroed.

[0059] If the first instruction is a floating point multiply instruction, the second instruction is a floating point multiply-add instruction, and the result of the floating point multiply is the addend of the second instruction, the first clock cycle operation is unchanged, i.e. the floating point multiply is executed, the second instruction calculates the floating point mantissa multiplication of the first instruction in the second instruction cycle, and the addend of the second instruction is replaced by the result of the floating point mantissa multiplication of the first instruction at this time, and the exponent difference is obtained according to the maximum exponent of the two instructions for the shifting operation. In the third cycle, the CSA 4-2 compression adder receives the 3 floating point mantissa multiplication partial products of the second instruction and the mantissa multiplication result of the first instruction, at this time, the four input ports of the CSA 4-2 compression adder use 4, and then the mantissa addition operation is performed again in the adder module to obtain the calculation result of the two instructions without normalization and rounding.

[0060] When the first instruction of the two instructions is a floating point addition instruction, the second instruction contains a floating point multiplication instruction (a floating point multiplication instruction or a floating point multiply-add instruction), and one of the multiplication operation operands is the result generated by the previous instruction, the floating point addition is executed first, and the pipeline needs to be stopped for one cycle when the second instruction is executed, so that the result of the first instruction is forwarded to the a operand port of the first stage pipeline, the b operand port is another unrelated multiplication operand, and the floating point multiplication is executed.

[0061] In the third stage pipeline, the leading zero detection module receives the result after the mantissa calculation of the previous stage, performs leading zero detection, and the exponent logic module and the shifting logic module respectively adjust the exponent or the mantissa according to the number of leading zeros output by the leading zero detection module to obtain the normalized result.

[0062] In the fourth stage pipeline, the rounding module performs rounding of the floating point data in the normalized result according to the normalized result transmitted by the previous stage pipeline and the rounding mode instruction, and the rounding includes 5 states of rounding to the nearest (associated to even), rounding to zero, rounding down, rounding up and rounding to the nearest (associated to the maximum amplitude).

[0063] In some embodiments, as shown in Table 1, the partial products generated by the Booth encoder of the present application through the base-4 Booth encoding algorithm are shown as an example. Wherein X represents the current data is the first bit, Z represents the operation to be performed on this group of data, wherein 0 represents that the data result is 0, +A represents that the data is unchanged, -A represents that the data is inverted and then added by 1, 2A represents that the data is left shifted by one bit, -2A represents that the data is left shifted by one bit and then inverted and added by 1, and when the first group of data is operated, 0 needs to be supplemented at the end (X-1; when X is 1, the 0th bit of data needs to be supplemented).

[0064] Table 1

[0065]

[0066] In the present embodiment, the partial products are compressed to 3 groups using a tree array multiplier. The tree array multiplier is preferably a Dadda Tree compressor, and the reduced partial products are determined by a maximum height sequence d Control, resulting in the sequence d1=2, d2=3, d3=4, d4=6, d5=9, etc. The tree array multiplier compresses the partial products to three groups of partial products, and the expression (1) for the tree array multiplier is:

[0067] Expression (1);

[0068] wherein the partial products compressed by the tree array multiplier are determined by a maximum height sequence d j determined, and j is an initial value satisfying d j <max(n1, n2), n1, n2 are the bit numbers of the input multiplicand and multiplier, respectively.

[0069] In the present embodiment, the Booth encoder includes an 11x11 bit multiplier, and using the base 4 Booth algorithm results in 6 groups of partial products, the partial products P0, P1, P2, P3, P4, P5 being arranged as shown in Table 2, wherein S represents the sign bit of the current partial product, 1 representing a negative number and 0 representing a positive number. The tree array multiplier compresses the 6 groups of partial products, and the first compression needs to satisfy d3=4, so the 6 groups of partial products need to be compressed to 4 groups; the second compression needs to compress the 4 groups of partial products to 3 groups; in the architecture of the present embodiment, the partial products are compressed to 3 groups.

[0070] Table 2

[0071]

[0072] More specifically, in the first compression, the 6-9 columns in the partial products P0 and P1 are summed using a half adder, the 15 columns in the partial products P4 and P5 are summed using a half adder, the 17 columns in the partial products P2 and P3 are summed using a half adder, the 10-14 columns in the partial products P0, P1 and P2 are summed using a full adder, the 8-9 columns in the partial products P2, P3 and P4 are summed using a full adder, the 10-14 columns in the partial products P3, P4 and P5 are summed using a full adder, the 15 columns in the partial products P1, P2 and P3 are summed using a full adder, the 16 columns in the partial products P2, P3 and P4 are summed using a full adder, and the results and the carries of the summation using the full adder and the half adder are respectively fed to the next column, resulting in the 4-stage partial product compression sequence shown in Table 3. The summation of the full adder is generated by 2 XOR gates, and the carry is generated by 2 AND gates and an OR gate. The summation of the half adder is generated by an XOR gate, and the carry is generated by an AND gate.

[0073] Table 3

[0074]

[0075] The partial product sequence in Table 3 is compressed in the second compression, the 4-5 and 19 columns of L0 and L1 in the partial product are summed using a half adder, the 6-18 columns of L0, L1 and L2 in the partial product are summed using a full adder, and the summed results and the carry of the full adder and the half adder are respectively fed to the next column to generate three groups of partial product compression sequences as shown in Table 4. All • in Tables 2, 3 and 4 represent partial product data, S represents an operator symbol, and the blank is filled with 0.

[0076] Table 4

[0077]

[0078] In the single-precision floating-point multiplication and addition operation, the floating-point mantissa multiplication needs to be implemented by 4 11*11 bit multipliers, 4 2*11 bit multipliers and 1 2*2 bit multiplier. As shown in FIG. 2, the single-precision floating-point multiplication mantissa product generation diagram is shown, wherein P0, P1, P3 and P4 are the operation results of the 11*11 bit multiplier, P2, P5, P6 and P7 are the operation results of the 2*11 bit multiplier, and P8 is the operation result of the 2*2 bit multiplier. Only the 11 bit wide multiplier in the above multipliers is implemented by using the base 4 Booth algorithm and the Dadda Tree compressor, and the multipliers of other bit widths are implemented by using 13 bit or 4 bit input adders and data selectors. Figure 2 As shown in FIG. 3, the 2*11 bit multiplier in the embodiment is implemented by using two 13 bit data selectors and one adder, the 2 bit multiplication inputs are respectively used as the control signals of the data selectors, the two inputs of the first data selector are respectively {2’b0, A} and 13’b0, the two inputs of the second data selector are respectively {1’b0, A, 1’b0} and 13’b0, wherein A represents the 11 bit input multiplier. The 2*2 bit multiplier is implemented by shifting and summing, and the basic implementation manner is similar to that of the 2*11 bit multiplier.

[0079] Figure 3 As shown in FIG. 3, the 2*11 bit multiplier in the embodiment is implemented by using two 13 bit data selectors and one adder, the two inputs of the first data selector are respectively {2’b0, A} and 13’b0, the two inputs of the second data selector are respectively {1’b0, A, 1’b0} and 13’b0, wherein A represents the 11 bit input multiplier. The 2*2 bit multiplier is implemented by shifting and summing, and the basic implementation manner is similar to that of the 2*11 bit multiplier.

[0080] In other low-precision floating-point multiplication and addition operations, since the mantissa bit width of the low-precision format is less than or equal to 10 bits, the 11*11 bit multiplier can be directly used, and in the floating-point mantissa multiplication, two low-precision mantissa multiplication results can be generated in parallel, and the results of P0 and P4 in the single-precision floating-point mantissa multiplication calculation can be directly used. For example, when two single-precision floating-point multiplication instructions are executed continuously and without data conflict in a super-scalar processor, the results of the two instructions can be generated simultaneously, and the data results are written into the multi-port register. The floating-point multiplication and addition structure designed in the application can also be integrated into the super-scalar processor for high-speed data processing.​

[0081] In this embodiment, floating-point mantissa multiplication is implemented using an 11×11 bit multiplier, applicable to various precisions such as FP32 / TF32 / Bfloat16 / DLFloat / FP16. It achieves full utilization, especially in mantissa multiplication calculations of TF32 and FP16 precisions. In other precision calculations, at least 2 bits of circuit resources can be saved per calculation cycle while maintaining the same calculation efficiency. For single-precision calculations, mantissa multiplication is implemented using four 11×11 bit multipliers, four 2×11 bit multipliers, and one 2×2 bit multiplier. The 2×11 bit multiplier is implemented using two selectors and one adder to ensure that resource consumption is minimized while making full use of the multiplier bit width.

[0082] Based on the same inventive concept, embodiments of this application also provide a microprocessor architecture, which includes any of the above-described multi-precision floating-point fused multiply-accumulate structures.

[0083] In one embodiment, such as Figure 4 As shown, the microprocessor architecture includes an instruction fetch module, a decoding module, an execution module, and a memory access module. The instruction fetch module fetches floating-point instructions and includes a pre-decoding unit for decoding the source register address. The floating-point instructions include at least one of floating-point multiply-accumulate instructions, floating-point multiplication instructions, and floating-point addition instructions. The decoding module includes a buffer unit for caching the destination register address of the floating-point instructions. The decoding module determines whether the destination register address is the same as the source register address and whether there is a register conflict between the current floating-point instruction and the next floating-point instruction to determine whether to pause the pipeline. The execution module loads the current floating-point instruction into the floating-point fused multiply-accumulate structure and obtains the execution result. The memory access module writes the execution result back to the register file, completing instruction execution.

[0084] In one embodiment, if the decoding module determines that there is a register conflict between the current floating-point instruction and the next floating-point instruction, and the current floating-point instruction is a floating-point multiply-accumulate instruction, while the next instruction is a floating-point addition instruction or a floating-point multiplication instruction, the pipeline will not be paused. If the decoding module determines that the conflict is invalid, the pipeline will be paused, and execution will continue until the current floating-point instruction is completed before continuing with the next floating-point instruction. This microprocessor architecture precisely controls the execution of the floating-point multiplication and addition stages through control instructions, using the same hardware architecture to complete different computational tasks, effectively mitigating processor resource overflow issues. This allows floating-point multiplication instructions to continue execution even when they are issued consecutively and register conflicts occur, improving processor execution efficiency.

[0085] Specifically, the instruction fetch module is used to execute the instruction fetch stage and alleviates the pressure on the decoding stage through the pre-decoding unit. The pre-decoding unit decodes the source register addresses, with signal names rs1, rs2, and rs3, respectively. The decoding module is used to execute the decoding stage and caches the destination register address of the current instruction and the enable signals for floating-point fused multiply-accumulate, floating-point multiplication, and floating-point addition instructions through the buffer unit, with signal names rd-buf, fmadd-buf, fmul-buf, and fadd-buf, respectively. During the decoding stage, a register conflict is determined by checking whether rd-buf is the same as one of the addresses of rs1, rs2, or rs3. Simultaneously, the decoding stage generates the specific floating-point instruction type. If the enable signal fmadd-buf of the previous floating-point fused multiply-accumulate instruction and the enable signal of the current floating-point multiplication or addition instruction are both high, the execution stage of the floating-point multiplication unit structure of this application begins. If a register conflict exists between the current instruction and the next instruction, and the next instruction contains a floating-point multiplication instruction (either a floating-point multiplication instruction or a floating-point multiply-add instruction), the pipeline will pause for one cycle in the next clock cycle, allowing the addition result to be passed to the first stage of the pipeline before execution continues. However, if the current instruction includes a floating-point multiplication instruction (either a floating-point multiply-add instruction or a floating-point multiplication instruction), and the next instruction is a floating-point addition instruction, the pipeline will not pause; the floating-point multiplication will be executed first, and the floating-point addition will be executed in the next clock cycle. The floating-point fused multiply-add structure of this application can calculate the final result of two instructions and write it to the destination register of the next instruction. If the check fails, the current pipeline will be paused, waiting for the current instruction to complete before continuing execution of the next instruction.

[0086] In this embodiment, the pre-decoding unit is preferably suitable for processor cores that do not include instruction caches and branch predictors. If these two components are included, adding pre-decoding during the instruction fetch stage increases fetch latency and reduces processor performance. In this case, pre-decoding is not performed; instead, the source operand, destination operand, and enable signals for the three floating-point instructions are generated during the decoding stage and input into the buffer unit. These signals are then compared with the decoding signal of the next cycle to generate control logic. These two implementations are tailored to devices with different processor cores, expanding the application scope and scenarios of this application.

[0087] More specifically, such as Figure 5 As shown, the states of the two related instructions when executed in the processor architecture of this application are shown. The first instruction A is shown in expression (2), where R0 is the destination register number, R1, R2, and R3 are the source register numbers, and FMADD indicates that this instruction is a floating-point fused multiply-add instruction. The second instruction B is shown in expression (3), where R5 is the destination register number, R0 and R2 are the source register numbers, and FADD indicates that this instruction is a floating-point addition instruction.

[0088] Expression (2);

[0089] Expression (3);

[0090] In the execution process, the A instruction first enters the processor of the present application, the B instruction is fetched after one clock cycle, the two instructions pass through the decoding stage in turn, the A instruction first reaches the execution stage, is sent into the floating point multiply-add fusion structure of the present application, and experiences the first stage pipeline to perform data preprocessing and partial multiplication pre-operation. The next clock cycle (cycle 2) reaches the second stage pipeline to perform multiplication operation, at this time the B instruction enters the first stage pipeline of the present application, the A instruction completes the floating point mantissa multiplication and related shift operation. The next clock cycle (cycle 3), the A instruction starts to execute the floating point addition, and the B instruction also starts to execute the floating point addition, at this time the operation is a+b+c, wherein a is the operand required by the floating point multiply-add calculation of the A instruction, b is the multiplication part result of the floating point multiply-add of the A instruction, and the B instruction needs to calculate (a+b)+c. The CSA 4-2 compression adder of the present application inputs the values of a, b and c together to perform compression, so as to avoid wasting time of executing the B instruction after the A instruction is executed, and the output result is input into the adder of cycle 2 to perform calculation, so as to obtain the final calculation result of the floating point instructions A and B. Then, in the fourth clock cycle, the normalization stage is entered to perform floating point number normalization processing. In the fifth cycle, the rounding stage is entered to perform rounding calculation on the calculation result according to the requirement of the B instruction decoding. Other instructions such as FMUL followed by FADD instruction have similar calculation modes as the above FMADD instruction followed by FADD instruction, and the difference is that the input conditions of the CSA 4-2 compression adder are different, and the selection of the result of the DaddaTree compressor of the upper stage is different, which are introduced above, and will not be described here. The present application only needs 5 cycles to complete this type of instruction, and does not need to consider the register conflict.

[0091] As shown in Figure 6 , it is a floating point addition followed by a floating point multiplication instruction, and register conflict occurs. Since the second stage pipeline execution part of the present application performs mantissa multiplication and addition operation, it is necessary to perform pipeline pause in the third cycle to forward the result of the addition operation to the first stage, so that the first stage partial product operation obtains correct result. Other operations and the operation result in the above Figure 5 are the same. The present application needs 6 cycles to implement this type of instruction, and does not consider the register conflict.

[0092] As shown in Figure 7As shown, it is a floating point multiplication or floating point addition followed by a floating point multiply-add instruction, and a register conflict occurs, since the second stage pipeline execution part of the present application performs the fraction multiplication and addition operation, so a pipeline stall is needed in the third clock cycle, the result of the addition operation is forwarded to the first stage pipeline, so that the partial product operation of the first stage pipeline gets the correct result, and because of the design characteristics of the present application, the second stage pipeline needs to do partial multiplication summation and addition operation, so the last two instructions together need 2 cycles, a total of 7 cycles to complete 2 instructions, and without considering the register conflict. The present application greatly improves the efficiency of the processor in executing floating point multiply-add related instructions, greatly reduces the execution period.

[0093] In summary, the microprocessor architecture of the present application, through the pre-decoding unit of the instruction fetching stage and the buffer module of the decoding stage, enables the floating point fused multiply-add, floating point multiplication and floating point addition instructions to maintain uninterrupted pipeline operation when a register conflict occurs, significantly improving the execution efficiency of the processor; under the same number of pipeline stages, the number of cycles required to execute two related instructions is at least 5 cycles and at most 7 cycles, avoiding the problem that floating point multiply-add operation instructions with similar pipeline stages in the prior art require at least 9 cycles when a register conflict occurs, thereby shortening the execution period, improving the instruction running efficiency, and balancing the high performance and high energy efficiency of the microprocessor.

[0094] It should be noted that, for those skilled in the art, without departing from the principles of the present application, the present application can be improved and modified in several ways, and these improvements and modifications also fall within the scope of protection of the claims of the present application. It should be understood that certain features of the present disclosure described in the context of separate embodiments can also be provided by combining, for the sake of clarity. Conversely, various features of the present disclosure described in the context of a single embodiment can also be provided separately or by any suitable combination or as an embodiment of any other description of the present disclosure.

Claims

1. A multi-precision floating-point fused multiply-add structure, comprising: Comprise: The first stage pipeline comprises an input preprocessing module, a Booth encoder, a tree array multiplier, an exponent difference module, and a sign logic module, the input preprocessing module is used to decompose the input operand to obtain a sign bit, an exponent bit, and a mantissa bit; the sign logic module is used to determine the sign bit of the operand; the exponent difference module is used to calculate the difference of the exponent bit in combination with the sign bit to determine the exponent difference; the Booth encoder encodes the mantissa bit by using a base-4 Booth encoding algorithm to generate a partial product, and the tree array multiplier is used to compress the partial product into three groups of partial products; in single-precision floating-point multiplication and addition operation, the tree array multiplier comprises four 11×11 bit multipliers, four 2×11 bit multipliers, and one 2×2 bit multiplier, the 2×11 bit multiplier comprises two 13 bit data selectors and one adder, the input multipliers of the data selectors are 11 bit, and the control signals of the data selectors are 2 bit; The second stage pipeline comprises a CSA 4-2 compression adder, an alignment shift module, and an adder module, the alignment shift module is used to calculate the size of the alignment shift according to the exponent difference and to perform shift alignment on the mantissa bit; the CSA 4-2 compression adder is used to compress the three groups of partial products and the mantissa bit after shift alignment into two groups of partial products; and the adder module is used to sum the two groups of partial products to obtain a mantissa summation result. The third stage pipeline comprises a leading zero detection module, an exponent logic module, and a shift logic module, the leading zero detection module is used to perform leading zero detection on the mantissa summation result to output the number of leading zeros, the exponent logic module is used to perform exponent adjustment on the number of leading zeros, and the shift logic module is used to perform mantissa adjustment on the number of leading zeros to obtain a normalized result. The fourth stage pipeline comprises a rounding module, which performs rounding of the floating-point data according to the normalized result and a rounding mode instruction.

2. A multi-precision floating point fused multiply-add structure as defined in claim 1, wherein, In the first stage pipeline, the input preprocessing module performs exception judgment on the input operand according to the decomposed sign bit, exponent bit, and mantissa bit, if the operand is a NAN value or an infinite value, the operation is stopped, and the result and the state exception are directly output.

3. A multi-precision floating point fused multiply-add structure as defined in claim 1, wherein, In the first stage pipeline, the first stage pipeline comprises a buffer, which is used to buffer a floating-point instruction and an operand contained in the floating-point instruction and transmit the floating-point instruction and the operand to the second stage pipeline.

4. A multi-precision floating point fused multiply-add structure as defined in claim 1, wherein, In low-precision floating-point multiplication and addition operation, an 11×11 bit multiplier is used; in floating-point mantissa multiplication, two low-precision mantissa multiplication results are generated in parallel and single-precision floating-point mantissa multiplication is used, and the 11×11 bit multiplier uses a Booth encoder.

5. A multiple precision floating point fused multiply-add structure as defined in claim 4 wherein, The expression for compressing the partial product into three groups of partial products by the tree array multiplier is: ； wherein the partial products compressed by the tree array multiplier are of maximum height sequence d j determined, j is the initial value satisfying d j <max(min(n1, n2), min(n1, n2)) where n1 and n2 are the bit lengths of the input multiplicand and multiplier respectively.

6. The multi-precision floating-point fused multiply-add structure according to claim 1, characterized in that, In the second pipeline, the floating point instruction includes at least one of floating point multiplication instruction, floating point addition instruction, floating point multiply-add instruction; If there are two relevant consecutive floating point instructions and there is a register conflict, when the first instruction contains a floating point multiplication instruction and the second instruction is a floating point addition instruction, the floating point multiplication is executed first, and the floating point addition is executed in the next clock cycle; If there are two relevant consecutive floating point instructions and there is a register conflict, when the first instruction is a floating point addition instruction and the second instruction contains a floating point multiplication instruction, the floating point addition is executed first, and the floating point multiplication is executed after the result of the floating point addition is forwarded to the first pipeline in the next clock cycle; If the two floating point instructions are not relevant, they are executed according to the original order.

7. A multiple precision floating point fused multiply-add structure as defined in claim 6 wherein, In the second pipeline, the execution of floating point multiplication and floating point addition is controlled by a state machine.

8. The multi-precision floating point fused multiply-add structure according to claim 6, wherein, If there are two relevant consecutive floating point instructions, and the first instruction is a floating point multiplication instruction and the second floating point instruction is a floating point addition instruction, in the first clock cycle, the floating point multiplication is executed; In the second clock cycle, the CSA 4-2 compression adder performs floating point addition based on the first addition operand shift result of the first pipeline, the floating point mantissa multiplication result generated by the second pipeline in the first clock cycle, and the second addition operand shift result; wherein the first addition operand shift result represents the exponent difference of the exponent of the largest operand in the two relevant consecutive floating point instructions in the second clock cycle, the second addition operand shift result represents the exponent difference of the exponent of the largest operand in the two relevant consecutive floating point instructions in the first clock cycle, and three of the four input ports of the CSA 4-2 compression adder are used.

9. The multi-precision floating point fused multiply-add structure according to claim 8, wherein, If the first floating point instruction is a floating point multiplication instruction, the second floating point instruction is a floating point multiply-add instruction, and the result of the floating point multiplication instruction is the addition operand of the second floating point instruction, in the second clock cycle, the floating point multiplication of the first floating point instruction is calculated to obtain a floating point mantissa multiplication result; The floating point mantissa multiplication result of the first floating point instruction is used as the addition operand of the second floating point instruction, and a shift operation is performed based on the exponent difference of the largest exponent of the two instructions; In the third clock cycle, the CSA 4-2 compression adder performs floating point addition based on the three floating point mantissa multiplication partial products of the second floating point instruction and the floating point mantissa multiplication result of the first floating point instruction, and four of the four input ports of the CSA 4-2 compression adder are used.

10. The multi-precision floating point fused multiply-add structure according to claim 8, wherein, If the first floating point instruction of the two floating point instructions is a floating point addition instruction, the second floating point instruction is a floating point multiplication instruction or a floating point multiply-add instruction, and the multiplication operand used by the second floating point instruction is generated by the first floating point instruction, the pipeline is stopped for one cycle when the second floating point instruction is executed.

11. A multi-precision floating point fused multiply-add structure as defined in claim 1, wherein, The rounding includes at least one of round to nearest, round to zero, round down, round up, and round to nearest.

12. A microprocessor architecture, characterized by The microprocessor architecture includes a multiple precision floating point fused multiply-add structure as claimed in any one of claims 1-11.

13. The microprocessor architecture of claim 12, wherein, The microprocessor architecture includes: A fetch module for fetching a floating point instruction, the fetch module including a predecode unit for decoding a source register address; wherein the floating point instruction includes at least one of a floating point multiply-add instruction, a floating point multiply instruction, and a floating point add instruction; A decode module including a buffer unit for buffering a destination register address of the floating point instruction; the decode module for determining whether the destination register address is the same as the source register address, and determining whether there is a register conflict between a current floating point instruction and a next floating point instruction, to determine whether to stall a pipeline; An execution module for sending the current floating point instruction into the floating point fused multiply-add structure, to obtain an execution result; A memory access module for writing the execution result back to a register file, to complete instruction execution.

14. The microprocessor architecture of claim 13, wherein, The decode module is for determining whether there is a register conflict between the current floating point instruction and the next floating point instruction, and if there is a register conflict and the next instruction includes a floating point multiply instruction, then stalling a one-cycle pipeline.

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