Instruction transmission method and device, electronic equipment and readable storage medium

Abstract

Embodiments of the present application provide an instruction transmitting method and device, electronic equipment and readable storage medium, relating to the technical field of computer. In the method, the wake-up instruction is determined based on the number of micro-instructions of instructions in the non-wake-up instruction set and the number of used operation units of the operation array. The wake-up flag bit of the micro-instruction of the wake-up instruction in the transmitting queue is set to a first flag value; the first flag value is used to represent that the operation array currently has unused operation units required for processing the micro-instruction of the wake-up instruction. For any micro-instruction of the transmitting queue, if the wake-up flag bit of the micro-instruction is the first flag value and the operand flag bit represents that the operand is ready, the micro-instruction is transmitted to the operation array. In this way, the transmitting efficiency can be improved, and the overall execution efficiency of the instruction is further improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method, apparatus, electronic device and readable storage medium for issuing instructions. Background Technology

[0002] In the instruction pipeline, the microinstructions obtained by decoding an instruction (one instruction may be decoded into multiple microinstructions) are renamed and written into the issue queue in the issue queue unit, and then issued to the arithmetic array for execution.

[0003] Since the efficiency of microinstruction issuance has a significant impact on the overall processing efficiency of instructions, how to issue microinstructions efficiently has become an urgent technical problem to be solved. Summary of the Invention

[0004] This invention provides a command issuing method, apparatus, electronic device, and readable storage medium, which can solve the problem of how to efficiently issue micro-instructions.

[0005] To address the above problems, this invention discloses a command issuing method, the method comprising:

[0006] Based on the information representing the number of microinstructions in the unwakeable instruction set and the number of used arithmetic units in the arithmetic array, wakeable instructions are determined.

[0007] Set the wake-up flag of the microinstruction of the wakeable instruction in the launch queue to a first flag value; the first flag value is used to indicate that the computing array currently has unused computing units required to process the microinstruction of the wakeable instruction;

[0008] For any microinstruction in the transmit queue, if the wake-up flag of the microinstruction is the first flag value and the operand flag indicates that the operand is ready, the microinstruction is transmitted to the arithmetic array.

[0009] On the other hand, embodiments of the present invention disclose a command issuing device, the device comprising:

[0010] The determination module is used to determine the wakeable instructions based on the number of microinstructions in the non-wakeable instruction set and the number of used arithmetic units in the arithmetic array.

[0011] The setting module is used to set the wake-up flag bit of the microinstruction of the wakeable instruction in the launch queue to a first flag value; the first flag value is used to indicate that the computing array currently has unused computing units required to process the microinstruction of the wakeable instruction;

[0012] The transmitting module is configured to transmit any microinstruction in the transmitting queue to the arithmetic array when the wake-up flag of the microinstruction is the first flag value and the operand flag indicates that the operand is ready.

[0013] In another aspect, embodiments of the present invention disclose an electronic device, including: a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, which cause the processor to execute the aforementioned method.

[0014] This invention also discloses a readable storage medium storing executable instructions that, when executed by one or more processors, cause the processors to perform the method described above.

[0015] The embodiments of the present invention have the following advantages: In the instruction issuance method provided by the embodiments of the present invention, a wake-upable instruction is determined based on the number of microinstructions in the unwakeable instruction set and the number of used arithmetic units in the arithmetic array. The wake-up flag bit of the microinstruction of the wake-upable instruction in the issuance queue is set to a first flag value; the first flag value is used to indicate that the arithmetic array currently has unused arithmetic units required to process the microinstruction of the wake-upable instruction. For any microinstruction in the issuance queue, if the wake-up flag bit of the microinstruction is the first flag value and the operand flag bit indicates that the operand is ready, the microinstruction is issued to the arithmetic array. In this way, if the arithmetic array currently has unused arithmetic units required to process the microinstruction of the wake-upable instruction, the microinstruction of the wake-upable instruction is woken up, and if the microinstruction is woken up and the operand flag bit indicates that the operand is ready, the microinstruction is issued. This can avoid the problem of blocking between multiple UOPs generated by one instruction, which leads to low issuance efficiency, thereby improving issuance efficiency and thus improving the overall execution efficiency of the instruction. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart of the steps of an instruction issuing method provided in an embodiment of the present invention;

[0018] Figure 2 This is a schematic diagram of a unidirectional ring topology provided in an embodiment of the present invention;

[0019] Figure 3 This is a schematic diagram of a judgment circuit provided in an embodiment of the present invention;

[0020] Figure 4 This is a schematic diagram of a launch provided in an embodiment of the present invention;

[0021] Figure 5 This is a schematic diagram of a microinstruction processing procedure provided in an embodiment of the present invention;

[0022] Figure 6 This is a schematic diagram of another microinstruction processing procedure shown in an embodiment of the present invention;

[0023] Figure 7 This is a schematic diagram of a processing procedure provided in an embodiment of the present invention;

[0024] Figure 8 This is a schematic diagram illustrating a data rearrangement according to an embodiment of the present invention;

[0025] Figure 9 This is a schematic diagram of an architecture provided by an embodiment of the present invention;

[0026] Figure 10 This is another schematic diagram of the architecture provided in the embodiment of the present invention;

[0027] Figure 11 This is a block diagram of a command issuing device provided in an embodiment of the present invention;

[0028] Figure 12 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] First, the application scenarios involved in the embodiments of the present invention will be described. When an on-chip network processes instructions, in the decoding stage of the instruction pipeline, one instruction (Macro Operation, MOP) may generate one or more micro operations (UOPs), where UOP is the smallest unit actually executed by the processor. For example, decoding an addition instruction will generate multiple UOPs, and decoding a permutation instruction may also generate multiple UOPs. Permutation instructions are used to rearrange vector data according to rules, such as the TBL and ZIP2 instructions in the ARM instruction set, and the GATHER instruction in the Vector Instruction Extended Set (RVV) used to perform permutation operations on the data in the vector register.

[0031] If all operands of a UOP generated by the instruction are ready before the microinstructions are issued sequentially according to the order of their operands, this can sometimes lead to low issuance efficiency in the issuance phase, thus affecting the overall execution efficiency of the instruction. For example, if operands v5 and v3 of UOP1 are ready, the system will continue to wait until operands v4 and v2 of UOP0 are also ready before issuing UOP0 in ascending order of operand register numbers, followed by UOP1.

[0032] Therefore, embodiments of the present invention provide a command issuing method.

[0033] Reference Figure 1 The diagram illustrates a flowchart of a command issuance method provided by an embodiment of the present invention, as follows: Figure 1 As shown, the method may specifically include the following steps:

[0034] Step 101: Determine the wake-up instructions based on the number of microinstructions in the unwakeable instruction set and the number of used arithmetic units in the arithmetic array.

[0035] Step 102: Set the wake-up flag of the microinstruction of the wakeable instruction in the launch queue to a first flag value; the first flag value is used to indicate that the arithmetic array currently has unused arithmetic units required to process the microinstruction of the wakeable instruction.

[0036] Step 103: For any microinstruction in the transmit queue, if the wake-up flag of the microinstruction is the first flag value and the operand flag indicates that the operand is ready, the microinstruction is transmitted to the arithmetic array.

[0037] In this embodiment of the invention, the number of microinstructions refers to the number of UOPs generated by the MOP. The unwakeable instruction set includes MOPs in an unwakeable state. When an MOP is determined to be a wakeable instruction, it can be marked as a wakeable state. For example, a first wake-up flag, such as "awake" or "1", can be used to indicate a wakeable state, and a second wake-up flag, such as "unawake" or "0", can be used to indicate an unwakeable state.

[0038] Currently, after the MOP is decoded by the decoding unit, it generates at least one UOP. The UOP then passes through the renaming unit and enters the dispatch unit. The dispatch unit assigns the UOP to the issue queue. Simultaneously, the dispatch unit records the instruction information of the MOP corresponding to each UOP in the reorder buffer. In the reorder buffer, the instruction status of the MOPs in the instruction queue is divided into "not executed" and "executed but not retired," meaning the instruction queue includes both unexecuted and executed instructions. It also records the number of unexecuted UOPs. After executing a UOP, the arithmetic unit returns an executed signal to the reorder buffer. This executed signal includes the instruction sequence number of the MOP corresponding to the executed UOP. This instruction sequence number can be the ROB sequence number of the instruction in the instruction queue of the reorder buffer. The ROB sequence number can be used to flush UOPs on erroneous paths during redirection. In response to this executed signal, the reorder buffer decrements the number of unexecuted UOPs corresponding to the MOP with the carried ROB sequence number by 1. When the number of unexecuted UOPs is 0, the instruction status of the MOP is set to "executed but not retired". When the first MOP to enter the reordering cache is in the "executed but not retired" state, the instruction will be removed from the reordering cache. In this embodiment of the invention, instructions in the "unexecuted" state in the instruction queue of the reordering cache can be woken up, that is, the set of unwakeable instructions includes unexecuted instructions whose wake-up flag is the second wake-up flag.

[0039] The arithmetic array comprises multiple arithmetic units, each responsible for executing a single unit operation (UOP). When UOPs need to transfer data, this data transfer within the arithmetic array, formed by connecting arithmetic units, improves the execution efficiency of multiple UOPs derived from a single instruction, thereby accelerating instruction execution. Used arithmetic units refer to those currently in operation, executing a UOP. Conversely, unused arithmetic units refer to those currently idle, not executing a UOP. The quantity of used arithmetic units indicates the number of currently active arithmetic units in the array, reflecting the current load. A wake-up instruction is one whose number of microinstructions does not exceed the number of currently unused arithmetic units in the array. Specifically, if the sum of the number of microinstructions for the wake-up instruction and the number of used arithmetic units (i.e., the quantity indicated by the quantity information) does not exceed the total number of arithmetic units, the arithmetic array is determined to have all the unused arithmetic units required to process the wake-up instruction's microinstructions.

[0040] Accordingly, the wake-up flag bits of all microinstructions of the wakeable instruction can be set to a first flag value to indicate that the arithmetic array currently has unused arithmetic units required to process all microinstructions of the wakeable instruction. This is equivalent to allocating arithmetic units to the microinstructions of the wakeable instruction. The first flag value can be 1. In this embodiment of the invention, the wake-up flag bits of all microinstructions of the wakeable instruction are set to the first flag value only when there are currently unused arithmetic units required to process all microinstructions of the wakeable instruction, ensuring that the UOP of the wakeable instruction can be normally executed by the arithmetic array after it is sent to the arithmetic array. It should be noted that in the implementation of this invention, when the wake-up flag of the microinstruction of the wakeable instruction is set to the first flag value, the microinstruction of the wakeable instruction may have been assigned to the transmission queue by the dispatch unit, or it may not have been assigned to the transmission queue yet. Accordingly, if the microinstruction of the wakeable instruction is in the dispatch unit, the wake-up flag of the microinstruction of the wakeable instruction can be set to the first flag value directly in the dispatch unit, or the wake-up flag can be passed to the transmission queue after the microinstruction of the wakeable instruction has been assigned to the transmission queue.

[0041] In this invention, the issue queue is a queue storing Unit Operators (UOPs) in the out-of-order processor. In this embodiment, when a microinstruction in the issue queue satisfies the condition that the wake-up flag is at the first flag value and the operand flag indicates that the operand is ready, the microinstruction is issued to the arithmetic array. Thus, for multiple UOPs derived from a wakeable instruction, in the woken-up state, they can be selected and issued as long as the operand is ready, achieving out-of-order transmission between UOPs, thereby improving the issuance efficiency of the issue process and the execution efficiency of the instruction. This embodiment of the invention can realize out-of-order issuance of UOPs using the arithmetic array. Since current high-performance processors often adopt out-of-order scheduling architectures, it can be easily integrated with processor cores that support out-of-order execution, reducing the hardware area overhead introduced by integration.

[0042] In summary, the instruction issuance method provided in this embodiment of the invention determines a wakeable instruction based on the number of microinstructions in the unwakeable instruction set and the number of used arithmetic units in the arithmetic array. The wake-up flag of the microinstruction of the wakeable instruction in the issuance queue is set to a first flag value; the first flag value indicates that the arithmetic array currently has unused arithmetic units required to process the wakeable instruction's microinstruction. For any microinstruction in the issuance queue, if the microinstruction's wake-up flag is the first flag value and the operand flag indicates that the operand is ready, the microinstruction is issued to the arithmetic array. Thus, if the arithmetic array currently has unused arithmetic units required to process the wakeable instruction's microinstruction, the wakeable instruction's microinstruction is woken up; if the microinstruction is woken up and the operand flag indicates that the operand is ready, the microinstruction is issued. This avoids the problem of blocking between multiple UOPs generated by a single instruction, leading to low issuance efficiency, thereby improving issuance efficiency and ultimately improving the overall execution efficiency of the instruction.

[0043] Optionally, the above-mentioned determination of wakeable instructions based on the number of microinstructions in the unwakeable instruction set and the number of used arithmetic units in the arithmetic array specifically includes:

[0044] Step 1011: Select an instruction from the set of unwakeable instructions as the target instruction, and determine whether there are m consecutive unused arithmetic units based on the quantity representation information; where m is the number of microinstructions of the target instruction.

[0045] Step 1012: If it exists, the target instruction is determined as a wake-up instruction, and the quantity representation information is updated based on the relevant information of the m consecutive unused arithmetic units.

[0046] Step 1013: Update the target instruction to the next instruction in the unwakeable instruction set, and return to the step of determining whether there are currently m consecutive unused operation units based on the quantity representation information, until there are currently no consecutive m unused operation units.

[0047] The first unwake-up instruction (i.e., the instruction in the unwake-up instruction set) can be used as the target instruction, following the order of the unwake-up instructions. Let m represent the number of micro-instructions in the target instruction, meaning that m UOPs are generated by decoding the target instruction. Since multiple UOPs split from a single MOP sometimes require data transfer between the multiple arithmetic units responsible for processing them, this embodiment directly determines whether there are m consecutive unused arithmetic units based on the quantity representation information. This ensures that these m unused arithmetic units can properly process the multiple UOPs split from various instructions, guaranteeing that the instructions can be executed correctly. Of course, if there is no data dependency between the multiple UOPs split from a single MOP, synchronization between arithmetic units is not required; this embodiment does not impose any restrictions on this.

[0048] The existence of m consecutive unused arithmetic units indicates that the arithmetic array currently possesses all the unused arithmetic units required to process the target instruction's microinstructions. Accordingly, the target instruction can be designated as a wake-upable instruction. After identifying the target instruction as a wake-upable instruction, it can be marked as awakened. Since these m unused arithmetic units will be subsequently allocated to this wake-upable instruction, the quantity representation information can be updated based on the relevant information of these m consecutive unused arithmetic units. The quantity represented by the updated quantity representation information is the quantity represented before the update + m. At this point, these m unused arithmetic units are equivalent to being pre-allocated to this wake-upable instruction.

[0049] Furthermore, after the update, subsequent instructions in the set of unwakeable instructions can be checked to determine if any wakeable instructions exist. Specifically, the next unwakeable instruction following the currently determined wakeable instruction can be used as the new target instruction. Then, execution continues from the step of determining whether there are m consecutive unused computation units based on the quantity representation information. It should be noted that the target instruction is different in each loop, and the specific value of the number m of micro-instructions of the target instruction may be the same or different. After loop processing, if it is detected that there are no consecutive m unused computation units, the process of determining wakeable instructions is paused, and the process waits for the next clock cycle. In the next clock cycle or if the quantity representation information is updated, execution can continue from step 1011. In this way, by cyclically updating the quantity representation information and cyclically determining wakeable instructions based on the updated quantity representation information, it can be ensured that all determined wakeable instructions have sufficient unused computation units, thereby avoiding the deadlock problem caused by multiple micro-instructions split from multiple wakeable instructions competing for computation units.

[0050] In this embodiment of the invention, by updating the quantity representation information, the wakeable instructions are determined cyclically based on the quantity representation information in the set of never-wake-up instructions. This can, to a certain extent, ensure that a sufficient number of wakeable instructions can be selected, thereby avoiding the problem of wasting computing power of the computing array.

[0051] Optionally, when the computation array adopts a fully interconnected topology, each computation unit in the array is directly connected to all other computation units, forming a fully interconnected network structure. Therefore, with this topology, any number of computation units in the array are interconnected. For example, if there are four unused computation units in the array, these four unused computation units can be considered consecutive, with any two or three unused computation units being consecutive. Accordingly, in this case, the quantity representation information is the number of currently used units in the computation array. With a fully interconnected topology, as long as n computation units are idle, the array can receive all UOPs (User Operations Points) with a microinstruction count ≤ n for computation.

[0052] The above method for determining whether there are currently m consecutive unused computation units based on the quantity representation information specifically includes: step 1011a, taking the sum of the number of used units and m as a first quantity, and determining that there are currently m consecutive unused computation units if the first quantity is not greater than the total number of computation units.

[0053] The above-mentioned update of the quantity representation information based on the relevant information of the m consecutive unused computing units specifically includes: step 1012a, updating the number of used units to the first quantity.

[0054] For example, let Gn represent the number of used units. The number of allocated functional units Gn can be set to 0 after power-on by the wake-up unit. Then, a judgment is made in each clock cycle to determine the wake-up instruction. Accordingly, the first quantity can be represented as Gn+m, and Gmax represents the total number of arithmetic units. Then Gmax-Gn can represent the number of unused arithmetic units. If Gn+m≤Gmax, it means m≤Gmax-Gn, and the currently available unused arithmetic units are sufficient to process all UOPs of the target instruction; that is, idle arithmetic units can receive and process m UOPs of the target instruction. Therefore, if the first quantity is not greater than the total number of arithmetic units, it can be determined that there are currently m consecutive unused arithmetic units, and thus the target instruction can be determined as a wake-up instruction. Next, Gn can be updated to Gn+m to update the quantity representation information.

[0055] In this embodiment of the invention, a fully connected topology computing array is used. Only the number of used units needs to be maintained, and the relationship between the sum of the number of used units and m and the total number of computing units needs to be determined to decide whether a target instruction can be activated. Therefore, the determination efficiency is higher, and information updates can be achieved simply by updating the number of used units to a first quantity, resulting in high update efficiency and thus improving overall processing efficiency to some extent.

[0056] In this embodiment of the invention, the instruction issuance method can be applied to an electronic device equipped with a wake-up unit, which in turn includes a sorting cache. Specifically, in this embodiment, for unexecuted instructions in the reordering cache, the sorting cache can be further distinguished between unwakeable and wakeable states, and the corresponding number of UOPs can be recorded. For example, the unexecuted instructions, wake-up flags, and the number of UOPs in the reordering cache can be written into the sorting cache. When the unexecuted instruction has not yet been woken up, the wake-up flag is set to a second wake-up flag; when the unexecuted instruction is determined to be a wake-up instruction, the wake-up flag is set to a first wake-up flag. The sorting cache may also include the ROB sequence number of each unexecuted instruction. Different MOPs have different ROB sequence numbers, and all UOPs processed by the dispatch unit will obtain a ROB sequence number corresponding to the instruction of the UOP; that is, UOPs split from the same MOP have the same ROB sequence number.

[0057] The unwakeable instruction set may also include MOPs in the dispatch phase. That is, the unwakeable instruction set includes MOPs in the dispatch phase and MOPs in the sorting cache marked with the second wake-up flag. The order of these MOPs in the unwakeable instruction set can be either MOPs in the dispatch phase followed by MOPs marked with the second wake-up flag, or MOPs marked with the second wake-up flag followed by MOPs in the dispatch phase. Specifically, MOPs in the dispatch phase are arranged according to the order in which they entered the dispatch unit, and MOPs marked with the second wake-up flag are arranged according to the order in which they entered the sorting cache.

[0058] For example, wakeable instructions can be identified from the MOPs in the dispatch phase. Specifically, when there is an MOP to be dispatched in the dispatch phase, the MOP can be used as the target instruction, and it can be determined whether the target instruction can be identified as a wakeable instruction based on the above method. If so, the wake-up flag bits of all UOPs of the MOP in the dispatch are set to the first flag value, and Gn = Gn + m1 is set. Here, m1 represents the number of microinstructions of the target instruction in the dispatch phase.

[0059] If not, the MOP flag needs to be woken up. That is, after the MOP is dispatched and enters the reordering cache, a second wake-up flag is added to the MOP (which is currently an unexecuted instruction) recorded in the reordering cache to indicate that the MOP needs to be woken up. Simultaneously, the number of micro-instructions for the MOP is recorded. After identifying the MOPs in the dispatch phase, the unwakeable instructions in the reordering cache can be identified. Let m2 represent the number of micro-instructions corresponding to the first MOP to enter the reordering cache. If Gn+m2≤Gmax, the unwakeable instruction is determined to be a wakeable instruction. If Gn+m2>Gmax or there are currently no unwakeable instructions, wait one clock cycle and then continue identifying the first instruction in the unwakeable instruction set.

[0060] Optionally, when the computation array adopts a non-fully connected topology, the quantity representation information includes the state values ​​of the state bits of each computation unit in the computation array. For example, the computation array is composed of a ring topology. In this way, the wake-up unit maintains the state bits of each computation unit in the computation array. Accordingly, the number of state bits representing the used state is the number of used computation units, and the number of state bits representing the unused state is the number of unused computation units. Therefore, the state values ​​of the state bits of each computation unit in the computation array can be regarded as quantity representation information. For a non-fully connected topology computation array, there must be n idle computation units in the computation array connected in sequence in order to be able to receive instructions with a microinstruction number ≤ n and perform operations on all UOPs.

[0061] The above-mentioned determination of whether there are m consecutive unused computation units based on the quantity representation information specifically includes: step 1011b, in the case that there are m consecutive state bits with the state value of the first state value, determining that there are m consecutive unused computation units; the first state value represents the unused state.

[0062] The above determination of whether there are m consecutive unused computation units based on the quantity representation information specifically includes: step 1012b, updating the status bits of the m consecutive unused computation units to a second status value, whereby the second status value represents the used status.

[0063] The first state value can be 1, and the second state value can be 0. Figure 2 This is a schematic diagram of a unidirectional ring topology provided in an embodiment of the present invention, such as... Figure 2 As shown, the wake-up unit can maintain a status bit for each of the eight arithmetic units C0 to C7. For any arithmetic unit, when the status bit of the arithmetic unit is 1, it indicates that the arithmetic unit is idle; when the status bit of the arithmetic unit is 0, it indicates that the arithmetic unit is not idle.

[0064] In this embodiment of the invention, a non-fully connected topology computational array is used, resulting in lower complexity. By maintaining the status bits of each computational unit in the array, it is possible to accurately determine which computational units are available / unavailable, thereby ensuring accurate identification of whether there are currently m consecutive unused computational units. It should be noted that even when the computational array uses a fully connected topology, the processing method used for non-fully connected topologies can also be adopted, i.e., the implementation methods of steps 1011b and 1012b described above. This embodiment of the invention does not impose any limitations on this approach.

[0065] Suppose that four arithmetic units C2, C3, C4, and C5 have been allocated to either one instruction with 4 UOPs or two instructions with 2 UOPs each. In this case, if the m value of the first target instruction is 4, the wake-up unit can determine that the target instruction is a wake-upable instruction and continue to determine whether to wake up the next instruction in the next clock cycle. If the m value of the first target instruction (denoted as MOP1) is 2, then MOP1 can be determined as a wake-upable instruction. If the m value of the updated target instruction (denoted as MOP2) is also 2, then MOP2 can be determined as a wake-upable instruction. That is, currently, one instruction with 4 UOPs or two instructions with 2 UOPs can be allocated. This is equivalent to grouping unused arithmetic units for use. Correspondingly, when multiple wake-upable instructions are determined consecutively, multiple UOPs derived from the splitting of these instructions will be woken up. For any UOP derived from these multiple instruction splitting, it will be issued if the operands are ready. This is equivalent to achieving out-of-order issuance of multiple instructions, thereby improving the processor's instruction execution efficiency.

[0066] It should be noted that in this embodiment of the invention, when there are no unused arithmetic units (for example, the number of used units represented by the updated quantity representation information is the total number of arithmetic units), if the number of microinstructions of the last determined wakeable instruction is 1, then instructions with a consecutive number of microinstructions of 1 after the last determined wakeable instruction can be determined as wakeable instructions. For example, if the m of the first target instruction (denoted as MOP1) is 3, then MOP2 can be determined as a wakeable instruction. At this time, based on the updated quantity representation information, the number of unused arithmetic units can be determined to be 1. If the m of the updated target instruction (denoted as MOP2) is 1, then MOP2 can continue to be determined as a wakeable instruction. At this time, the number of unused arithmetic units is 0, but since the number of microinstructions of MOP2 is 1, then any number of consecutive instructions with a number of microinstructions of 1 after MOP2 can continue to be determined as wakeable instructions. Assuming that the number of microinstructions of MOP3~5 after MOP2 is all 1, then MOP3~5 can also be determined as wakeable instructions. Assuming that the number of microinstructions for MOP3~10 after MOP2 is 1, then MOP3~10 can also be identified as wake-up instructions. This is equivalent to waking up the target instruction and all subsequent instructions with a microinstruction count of 1 when there is currently 1 unused arithmetic unit and the target instruction has a microinstruction count of 1.

[0067] Since a single microinstruction instruction (MOP) is split into only one unit instruction (UOP), this UOP can enter any arithmetic unit. This UOP can complete its operation in one cycle and will not block the arithmetic array. Therefore, there will be no deadlock caused by multiple UOPs of a single-microinstruction MOP competing for arithmetic units. In this embodiment of the invention, instruction wake-up efficiency can be improved by continuously waking up the target instruction and its subsequent consecutive single-microinstruction instructions.

[0068] Furthermore, assuming C0 and C1 have already been assigned to an instruction with a UOP quantity of 2, and C4 and C5 have already been assigned to an instruction with a UOP quantity of 2, the wake-up unit, if the m of the first target instruction is determined to be 4, will not identify that target instruction as a wake-upable instruction. It will continue to determine whether the target instruction can be woken up in the next clock cycle (at which point, new unused arithmetic units may appear). If the m of the first target instruction (denoted as MOP1) is 2, then MOP1 can be identified as a wake-upable instruction. If the m of the updated target instruction (denoted as MOP2) is also 2, then MOP2 will also be identified as a wake-upable instruction. That is, currently, two instructions with a UOP quantity of 2 can be assigned.

[0069] Alternatively, assuming the first target instruction (denoted as MOP1) has a value of 2 (m), then MOP1 can be identified as a wake-upable instruction. If the updated target instruction (denoted as MOP2) has a value of 1 (m), then MOP2 can also be identified as a wake-upable instruction. In this case, based on the updated quantity representation information, the number of unused arithmetic units can be determined to be 1. If the updated target instruction (denoted as MOP3) has a value of 1 (m), then MOP3 and all subsequent consecutive instructions with a value of 1 can be identified as wake-upable instructions.

[0070] In this embodiment of the invention, when allocating arithmetic units to a wakeable instruction, starting with the arithmetic unit with the smallest number whose status bit is the first state value, m consecutive arithmetic units with the first state value are allocated to the target instruction. Correspondingly, when updating the quantity representation information, starting with the arithmetic unit with the smallest number whose status bit is the first state value, the status bits of the m consecutive arithmetic units with the first state value are modified to the second state value.

[0071] In this embodiment of the invention, the wake-up unit can set the status bits sequentially according to the connection order of the arithmetic units and in ascending order of the unit numbers. The number of UOPs split from the MOP can be divided into various specifications, each specification representing a certain number of UOPs, such as 1, 2, 6, 8, etc. For any specification, every x adjacent status bits can be grouped together, where x represents the number of UOPs corresponding to that specification. There are x-1 repeated status bits between adjacent groups, that is, each group is staggered by one status bit. A group is used as the input of an AND gate, and the outputs of all AND gates are used as the input of an OR gate, thereby forming a judgment circuit for x consecutive unused arithmetic units corresponding to that specification. Accordingly, for any target instruction, the output of the judgment circuit for x=m consecutive unused arithmetic units (i.e., the output of the OR gate in this circuit) is obtained. If the output of the OR gate is 1, it can be determined that there are currently m consecutive unused arithmetic units. Otherwise, it is determined that there are currently no m consecutive unused arithmetic units.

[0072] Taking x=2, using a unidirectional ring topology, the wake-up unit uses 8 bits of storage space to record the idle state of the arithmetic unit, with C0, C1, C4 and C5 already allocated, and the status bits of C0, C1, C4 and C5 being 0, as an example. Figure 3 This is a schematic diagram of a judgment circuit provided in an embodiment of the present invention, such as... Figure 3 As shown, each pair of vector state bits is used as an AND gate ( Figure 3 The input of the AND gate is used to treat all the outputs of the AND gate as an OR gate. Figure 3 The input of the OR gate is used. Since the output of the OR gate is 1 at this time, it can be determined that there are currently two consecutive unused operation units. It should be noted that, for ease of representation, C0' and C7, represented by the dashed box in the figure, are connected as a group of AND gates, indicating that C7 and C0 are connected as a group of AND gates.

[0073] In this embodiment of the invention, steps 1011 to 1013 can be implemented by adding relevant control logic based on the topology.

[0074] Optionally, in embodiments of the present invention, the following steps are further included:

[0075] Step S21: Receive an update signal returned by a computing unit in the computing array.

[0076] Step S22: If the update signal is sent when the arithmetic unit ends the used state, then directly respond to the update signal and update the quantity representation information.

[0077] Step S23: If the update signal is sent when the computing unit begins to enter the used state, then after a preset period following the receipt of the update signal, the quantity representation information is updated in response to the update signal.

[0078] The update signal can be sent to the wake-up unit, which updates the quantity representation information based on the update signal. The update signal can be returned at different times. When the update signal is sent when the arithmetic unit ends its used state, for example, the arithmetic unit can return the update signal after writing back the execution result to indicate that a reclaimable arithmetic unit exists. Accordingly, the operation of updating the quantity representation information can be performed directly upon receiving the update signal in response to the update signal. When the update signal is sent when the arithmetic unit begins to enter its used state, the operation of updating the quantity representation information can be performed after waiting for a preset period after receiving the update signal in response to the update signal. The wake-up unit can implement steps S22 and S23 based on different control circuits.

[0079] The preset period includes p periods, where p is the difference between the period required for the computing unit to execute a UOP and the period required for a UOP to be executed from transmission. For example, assuming a UOP requires 3 periods and a UOP requires 4 periods from transmission to execution, the quantity representation information can be updated 1 period after receiving the update signal. Thus, after waiting 1 period, if a UOP is woken up and sent to the computing unit after 3 periods, 4 periods have already elapsed. At this point, the computing unit ends its used state and transitions to an unused state. Therefore, it can be ensured that the UOP can be executed normally. In this embodiment of the invention, an update signal is sent when the computing unit begins to enter the used state, and the quantity representation information is updated in response to the update signal 10 ...

[0080] In this embodiment of the invention, by returning an update signal and updating the quantity representation information based on the update signal, the accuracy of the quantity representation information can be ensured, thereby ensuring that the wakeable command can be accurately identified based on the quantity representation information.

[0081] Optionally, when the computing array adopts a fully connected topology, the quantity representation information is the number of used units in the computing array that are currently in a used state. The step of updating the quantity representation information in response to the update signal may include: decrementing the number of used units by one.

[0082] For a fully connected topology computing array, the update signal returned by the computing unit to the wake-up unit is a 1-bit message, indicating that one computing unit has become idle. Specifically, for any clock cycle, if a responsive update signal exists, Gn = Gn-1 is set, which reduces the number of used units by 1, thus implementing the update operation. If no responsive update signal exists, the update operation is skipped.

[0083] When the computing array adopts a non-fully connected topology, the quantity representation information includes the state value of the state bit of each computing unit in the computing array. The step of updating the quantity representation information in response to the update signal may include: updating the state bit corresponding to the computing unit indicated by the update signal to a first state value.

[0084] For a unidirectional ring topology, the arithmetic unit needs to return its unit number to the wake-up unit to indicate that the arithmetic unit with that unit number is in an idle state. That is, the update signal will include the unit number. The arithmetic unit represented by the unit number included in the update signal is the arithmetic unit indicated by the update signal. Accordingly, the status bit corresponding to that unit number can be modified to the first status value.

[0085] In this embodiment of the invention, in response to the update signal, the number of used units is reduced by one, or the status bit corresponding to the operation unit indicated by the update signal is updated to the first status value, thereby updating the quantity representation information. In this way, the accuracy of the quantity representation information can be ensured.

[0086] It should be noted that the wake-up unit will perform the following operations in each cycle in response to the update signal: updating the quantity representation information (referred to as operation 1), identifying wakeable instructions from the MOP in the dispatch phase (referred to as operation 2), and identifying wakeable instructions from the sorting cache (referred to as operation 3). The order of these three operations can be set as needed. For example, they can be executed in parallel, or in the order of operation 1-operation 2-operation 3, or in the order of operation 3-operation 2-operation 1. This embodiment of the invention does not impose any restrictions on this.

[0087] In this embodiment of the invention, when waking up a UOP of a wakeable instruction, all UOPs of the wakeable instruction can be woken up in the same clock cycle, or the UOPs of the wakeable instruction can be woken up one by one in multiple cycles, so as to achieve finer-grained allocation of arithmetic units, improve the utilization rate of arithmetic units, and thus improve the computing efficiency.

[0088] Optionally, setting the wake-up flag of the micro-instruction of the wakeable instruction in the transmit queue to a first flag value specifically includes:

[0089] Step 1021: For any microinstruction configuration item, if the instruction number in the microinstruction configuration item is the same as the instruction number of the wake-up instruction, set the wake-up flag bit in the microinstruction configuration item to the first flag value; one microinstruction configuration item represents one microinstruction.

[0090] In this embodiment of the invention, each microinstruction has a microinstruction configuration item, which includes at least the instruction sequence number and a wake-up flag of the microinstruction. The instruction sequence number of the microinstruction can be its ROB sequence number, and the ROB sequence numbers included in the microinstruction configuration items of microinstructions split from the same MOP are all the same. Thus, waking up the UOP based on the ROB sequence number reuses the existing ROB sequence number, eliminating the need to add other signals stored for wake-up, resulting in lower implementation costs.

[0091] For any wakeable instruction, the microinstruction configuration item whose ROB sequence number is the same as that of the wakeable instruction is the microinstruction configuration item corresponding to that wakeable instruction, representing the microinstruction of that wakeable instruction. Accordingly, the ROB sequence number is compared. If the ROB sequence number in the microinstruction configuration item is the same as the ROB sequence number of the wakeable instruction, then the wake-up flag bit in the microinstruction configuration item is set to the first flag value.

[0092] In this embodiment of the invention, when waking up, the microinstruction configuration item of the microinstruction of the wakeable instruction can be identified by comparing the instruction sequence number of the wakeable instruction. By setting the wake-up flag bit in the microinstruction configuration item to the first flag value, wake-up can be achieved, which can ensure wake-up efficiency to a certain extent.

[0093] Optionally, if the instruction number in the microinstruction configuration item is the same as the instruction number of the wake-up instruction, the wake-up flag bit in the microinstruction configuration item is set to the first flag value, specifically including:

[0094] Step 1021a: The wake-up unit inputs a wake-up valid signal and the instruction number of the wakeable instruction to the wake-up circuit of each of the micro-instruction configuration items.

[0095] Step 1021b: For any of the microinstruction configuration items' wake-up circuits, if the wake-up circuit receives the wake-up valid signal and the received instruction number is the same as the instruction number in the microinstruction configuration item, the wake-up flag bit in the microinstruction configuration item is set to the first flag value.

[0096] In this embodiment of the invention, the wake-up unit can broadcast a wake-up valid signal and the instruction number of the wakeable instruction to each wake-up circuit. Each microinstruction configuration item is equipped with a wake-up circuit. The input of the wake-up circuit includes the wake-up valid signal, the instruction number of the wakeable instruction, and the instruction number in the microinstruction configuration item, and the output is 0 or 1. For any microinstruction configuration item's wake-up circuit, when the wake-up circuit outputs 1, the wake-up flag bit in the microinstruction configuration item is set to 1, i.e., the first flag value. When the wake-up circuit outputs 0, the wake-up flag bit in the microinstruction configuration item is set to 0, i.e., the second flag value. The wake-up flag bit in each microinstruction configuration item is initially 0. Specifically, the wake-up circuit is used to determine whether the instruction number in the microinstruction configuration item is equal to the received instruction number. And, if they are equal, it outputs 1 in response to the wake-up valid signal. If they are not equal, it outputs 0 in response to the wake-up valid signal. In this way, by controlling the wake-up circuit to output through the wake-up valid signal, the problem of the wake-up circuit continuously outputting based on the comparison result can be avoided.

[0097] In this embodiment of the invention, the wake-up circuit of each micro-instruction configuration item is used to input a wake-up valid signal and the instruction number of the wakeable instruction. With the help of the wake-up circuit, the wake-up flag bit in the micro-instruction configuration item corresponding to the wakeable instruction can be set to the first flag value, which is more convenient.

[0098] For example, taking a microinstruction configuration item as a launch queue in the launch queue as an example, Figure 4 This is a schematic diagram of a launch provided by an embodiment of the present invention, such as... Figure 4 As shown, the section between the wake-up unit and the transmit queue item represents the wake-up circuit. When the wake-up unit inputs the ROB number of the wake-up instruction and a wake-up valid signal to each wake-up circuit, if the ROB number of the wake-up instruction is the same as the ROB number in the transmit queue item, the AND gate in the wake-up circuit outputs 1, setting the wake-up flag bit in the transmit queue item to 1. Otherwise, it is set to 0. The wake-up valid signal is 1. Further, this wake-up flag bit, together with the operand flag bit and the item valid bit, forms a selection signal for selecting UOP transmission. The operand flag bit in the transmit queue item (i.e....) Figure 4 When both operand 1 and operand 2 are ready, and the item validity bit is 1, a signal 1 will be output to the transmit queue selection module, causing the transmit queue selection module to issue the microinstruction represented by the transmit queue item. The item validity bit is 1 when the transmit queue item stores a microinstruction, and 0 when no microinstruction is stored.

[0099] In this embodiment of the invention, 1 bit is added to the transmit queue entry as a wake-up flag and a corresponding wake-up circuit. The added sorting buffer is in units of MOPs rather than UOPs. All UOPs of one MOP are woken up at a time in units of MOPs, which can reduce the overhead of integrated circuit implementation to a certain extent.

[0100] It should be noted that for microinstructions in the dispatch unit, a microinstruction configuration item in the dispatch unit may only include the instruction sequence number of the microinstruction and the wake-up flag. The wake-up flag of the microinstruction configuration item is connected to the wake-up flag in the corresponding launch queue item of the microinstruction, thereby setting the wake-up flag of the microinstruction to the first flag value in the dispatch unit. After the microinstruction is dispatched to the launch queue, it is passed to the wake-up flag in the launch queue.

[0101] Taking the example that a microinstruction takes three cycles from being issued to entering the arithmetic unit, Figure 5 This is a schematic diagram of a microinstruction processing procedure provided in an embodiment of the present invention, such as... Figure 5 As shown, suppose a MOP is split into four microinstructions: microinstruction 0 to microinstruction 3. These four microinstructions are assigned to four arithmetic units: arithmetic units 4 to arithmetic units 7. After the instruction is determined to be a wake-up instruction, at time 0, the wake-up flag bits of microinstructions 0 to 3 are all set to the first flag value. At time 2, the operand of microinstruction 2 is ready and is issued from the issue queue. After three cycles, execution begins at time 5. At time 4, the operand of microinstruction 1 is ready and is issued from the issue queue. After three cycles, execution begins at time 7. At time 5, the operand of microinstruction 3 is ready and is issued from the issue queue. After three cycles, execution begins at time 8. At time 7, the operand of microinstruction 0 is ready and is issued from the issue queue. After three cycles, execution begins at time 10. The arithmetic array can complete the execution of the first microinstruction that entered the array and write it back in the next cycle after collecting all the data of the four microinstructions (e.g., time 11). After that, each cycle completes the execution of one microinstruction and writes it back.

[0102] Figure 6 This is a schematic diagram illustrating another microinstruction processing procedure according to an embodiment of the present invention, such as... Figure 6As shown, at times 2, 4, 5, and 7, the operands of microinstructions 2, 1, 3, and 0 are ready in sequence. Because microinstructions 0 through 3 have sequential dependencies, each microinstruction can only be issued after the microinstruction with the smaller sequence number. The microinstruction sequence number indicates which microinstruction it is derived from. For example, existing methods use a sequential issuance queue, where the next microinstruction can only be issued after the previous one, and there are sequential dependencies between the microinstructions derived from a single instruction. Therefore, at time 7 and the following three times, microinstructions 0, 1, 2, and 3 are issued sequentially. After three cycles, at times 10, 11, 12, and 13, microinstructions 0, 1, 2, and 3 enter the arithmetic array for execution. Similarly, in the next cycle (time 14) after collecting all the data for the four microinstructions, the arithmetic array completes the execution of the first microinstruction that entered the array and writes it back. Subsequently, one microinstruction is executed and written back in each cycle. By comparison, it can be seen that in the out-of-order microinstruction issuance method of this embodiment, microinstructions do not need to wait for microinstructions with smaller sequence numbers to be issued; they can be issued from the issuance queue as soon as their operands are ready. Therefore, issuance efficiency can be improved, the overall processing flow shortened, and instruction execution accelerated.

[0103] For a wakeable instruction, after multiple Units of Operations (UOPs) of the wakeable instruction are sent to the computing array, the processing method of the computing array can refer to the existing method. Specifically, when data needs to be transferred between multiple UOPs, compared with the existing method, the order in which the multiple UOPs of the wakeable instruction are received by the computing array is different. The multiple computing units processing these multiple UOPs can adopt the existing synchronization mechanism to realize the execution of UOPs. That is to say, as long as these multiple UOPs are sent to the computing array, as long as the computing units can synchronize data, it can be ensured that the UOPs are executed normally. Alternatively, the control unit can synchronize the data defined in all other UOPs for each computing unit to ensure that multiple UOPs are executed smoothly. This embodiment of the invention does not limit this.

[0104] Figure 7 This is a schematic diagram of a processing procedure provided by an embodiment of the present invention, such as... Figure 7 As shown, corresponding to the above Figure 5Microinstructions 2, 1, 3, and 0 enter the arithmetic array at times 5, 7, 8, and 10, respectively. Assuming the arithmetic array enters from the smallest numbered arithmetic unit, microinstructions 2, 1, 3, and 0 enter arithmetic unit 4 sequentially at times 5, 7, 8, and 10. Then, starting from arithmetic unit 4, microinstructions 2, 1, 3, and 0 are passed sequentially between arithmetic units 4 and 7. Specifically, this can involve passing data required to execute any one of these four microinstructions, as defined in microinstructions 2, 1, 3, and 0; for example, data elements defined in the microinstructions. If this corresponds to the above... Figure 6 The microinstructions are entered into the arithmetic unit 0 in the order of microinstruction 0, microinstruction 1, microinstruction 2, and microinstruction 3, and the processing method can be the same.

[0105] The computing array may include an array control unit. After each UOP is transmitted, it first enters the array control unit, which then allocates the UOP to a computing unit. The array control unit can maintain the cell numbers of the idle computing units in the array, and can send the UOP to the idle computing unit with the smallest cell number.

[0106] For example, in this embodiment of the invention, the wake-up unit may send control information to the array control unit of the computing array; the control information includes the instruction sequence number of the wake-up instruction and the numbering information of the m consecutive unused computing units. Accordingly, the above-mentioned transmission of the microinstruction to the computing array specifically includes: step 1031, sending the microinstruction to the array control unit to control the control unit to send the microinstruction according to the numbering information in the target control information; wherein, the instruction sequence number in the target control information is the same as the instruction sequence number of the microinstruction.

[0107] Specifically, the numbering information of the m consecutive unused arithmetic units refers to the unit number of the smallest unused arithmetic unit among the m consecutive unused arithmetic units assigned to the wake-up command. In one approach, multiple UOPs split from an MOP will enter and begin operation from the same arithmetic unit. Therefore, only the instruction sequence number of the wake-up command and the unit number of the smallest unused arithmetic unit need to be sent to the array control unit. The control unit stores each received control signal locally. When a UOP is received, it searches for control information whose instruction sequence number matches that of the UOP as the target control information and sends the UOP to the arithmetic unit with the unit number in the target control information.

[0108] Assume that wakeable instruction 1 is split into four Units of Operation (UOPs): UOP0 to UOP3. Four consecutive arithmetic units (ANOVAs) are assigned to wakeable instruction 1: ANOVA 4 to ANOVA 7. Correspondingly, the control information sent to the control unit includes the instruction sequence number of wakeable instruction 1 and the unit number of ANOVA 4. Upon receiving any UOP from UOP0 to UOP3, that UOP is sent to ANOVA 4; that is, all four ANOVAs begin their operations from ANOVA 4. For any ANOVA, the required operands carried in the UOP entering that ANOVA can be recorded, for example, the data vector. Then, the UOP is sent to the connected ANOVA.

[0109] Alternatively, it can include the unit numbers of all arithmetic units in a consecutive set of m unused arithmetic units. Accordingly, the array control unit can send the UOPs sequentially to the arithmetic units in ascending order. For example, the control information sent to the array control unit includes the instruction number of the wake-up instruction 1 and the unit numbers of arithmetic units 4-7. Upon receiving UOP2, UOP0 is sent to arithmetic unit 4; upon receiving UOP1, UOP1 is sent to arithmetic unit 5; and upon receiving UOP3, UOP3 is sent to arithmetic unit 6. Then, any arithmetic unit can transmit the data from the UOP sent by the control unit to the connected arithmetic unit. After receiving data from a UOP sent by one arithmetic unit, the data can be stored within that arithmetic unit and forwarded to other connected arithmetic units, thus enabling the four UOPs processing these four UOPs to share the required data.

[0110] In one implementation scenario, all unwakeable instructions can be GATHER instructions. The aforementioned arithmetic array can be a GATHER array, which consists of several GATHER arithmetic units connected in a certain topology. This array supports the simultaneous out-of-order reception and processing of multiple UOPs containing GATHER instructions. The GATHER arithmetic units in this array are used to process the UOPs obtained by splitting GATHER instructions. The aforementioned transmit queue can be a vector transmit queue. The GATHER instructions in RVV can include vrgather.vv instructions and vrgatherei16.vv instructions, whose instruction formats are represented as vrgather.vvvd, vs2, vs1 and vrgatherei16.vv vd, vs2, vs1, respectively.

[0111] In RVV, instructions use a separate vector configuration instruction to set the vector configuration register (VTYPE CSR). The vector configuration register is a register defined in RVV that controls vector configuration. The VTYPE register includes a vector length multiplier (LMUL) field and a selected element width (SEW) field. Both LMUL and SEW are 3 bits. SEW specifies the bit width of the operands for the vector instruction, and LMUL specifies the number of vector registers for the vector instruction's operands. Vector registers are user-programmable registers defined in RVV; RVV defines 32 vector registers for user use.

[0112] In the RVV instruction set, a vector instruction uses LMUL consecutively numbered vector registers. For example, in the instruction "vrgather.vv v24,v8,v16", with LMUL=8, the vs1 register set contains 8 vector registers (v16~v23), the vs2 register set contains 8 vector registers (v8~v15), and the vd register set contains 8 vector registers (v24~v31). For the GATHER instruction, the data in the vs1 register set can be considered as an index vector, the data in the vs2 register set can be considered as a data table vector, and the data in the vd register set can be considered as a destination vector. The maximum number of elements represented by a single vector register number that a vector instruction can operate on can be expressed as VLMAX. Here, VLMAX = VLEN * LMUL / SEW, where VLEN represents the vector register length (in bits).

[0113] Specifically, the `vrgather.vv` instruction is a data rearrangement instruction used in vector extensions for batch querying the values ​​of index vectors in a data table vector. The bit width of a single index element in the `vrgather.vv` instruction's `vs1` register set, the bit width of a single data element provided by the `vs2` register set, and the bit width of a single element provided by the `vd` register set are specified by `SEW` in `VTYPE`. For example, when `SEW` is 32, the bit width of the index element, data element, and `vd` register set are all 32 bits. A vector register in the `vs1` register set includes `VLEN / SEW` index elements, and the total number of index elements in the `vs1` register set is `VLEN*LMUL / SEW`. All the index elements in the `vs1` register set constitute the index vector. A vector register in the `vs2` register set includes `VLEN / SEW` data elements, and the total number of data elements in the `vs2` register set is `VLEN*LMUL / SEW`. All the data elements in the `vs2` register set constitute the data table vector.

[0114] The `vrgather.vv` instruction uses the index element in `vs1` to query the data element in `vs2`, and stores the query result in `vd` at the corresponding position in `vs1`. It splits the elements in `vd`, `vs2`, and `vs1` into several elements using SEW. `vd[i]`, `vs2[i]`, and `vs1[i]` represent the i-th element in the `vd` register group, the i-th element in the `vs2` register group, and the i-th element in the `vs1` register group, respectively. If `vs1[i]` >= `VLMAX`, the value of `vd[i]` is set to 0; otherwise, the value of `vd[i]` is set to `vs2[vs1[i]]`.

[0115] Taking vrgather.vv v6, v2, v4 with VLEN=128, SEW=32, LMUL=2 as an example, Figure 8 This is a schematic diagram of data rearrangement shown in an embodiment of the present invention, such as... Figure 8 As shown, the vs1 register group (v4 and v5) contains 8 index elements: vs1[0]~vs1[7], and the specific values ​​of vs1[0]~vs1[7] are 1, 8, 7, 19, 2, 3, 0, 5 respectively. The vs2 register group (v2 and v3) contains 8 data elements: vs2[0]~vs2[7], and the specific values ​​of vs2[0]~vs2[7] are 10, 32, 54, 76, 98, BA, DC, FE respectively. When this instruction is executed, each index element in v4 and v5 is used to find the element at the corresponding position in the v2 and v3 registers. In this example, since vs1[1] and vs1[3] satisfy the condition >= VLMAX, the corresponding elements vd[1] and vd[3] of vs1[1] and vs1[3] in the destination register group are both set to 0. The positions of vd[0], vd[2], vd[4], vd[5], vd[6], and vd[7] are filled with the specific values ​​of vs2[1], vs2[7], vs2[2], vs2[3], vs2[0], and vs2[5] respectively: 32, FE, 54, 76, 10, and BA.

[0116] The vrgatherei16.vv instruction is a special version of the vrgather.vv instruction. The vrgatherei16.vv instruction fixes the bit width of the index element in the vs1 register group to 16 bits. SEW is only used to specify the data bit width in the vs2 and vd register groups. Corresponding to the vrgatherei16.vvv6,v2,v4 instructions, according to the principle in the RISC-V specification that the number of registers operated on by a register number must satisfy the principle of equal number of elements, the consecutive vector registers represented by register number v6 have a total of 8 elements, and the consecutive vector registers represented by register number v4 only need to contain 8 elements. In this example, v4 includes 128 / 16=8 elements. Therefore, the v4 register includes vs1[0]~vs1[7]. The vrgatherei16.vv instruction is executed in the same way as the vrgather.vv instruction, which will not be described again here.

[0117] As seen in the examples above, each index vector requires searching through LMUL indexed vs2 registers. Therefore, the larger the LMUL, the greater the lookup volume. Consequently, a single GATHER instruction is often split into multiple UOPs, where the number of index elements defined in a UOP can be the same as the number of elements contained in a single vs2 register. For example, for the vrgather.vv v6,v2,v4 instruction in the example above, two UOPs, UOP0 and UOP1, can be generated. UOP0 defines operands v4, v2, and v6, while UOP1 defines operands v5, v3, and v7. That is, UOP0 defines index elements as the four elements contained in v4 and data elements as the four elements contained in v2. After using the values ​​of the four index elements in v4 as indices to look up the corresponding elements in the vs2 register set, the value of each element in register v6 is obtained, thus yielding the execution result. The execution result can then be written back, completing the execution of the UOP.

[0118] Taking UOP0~UOP3 as an example obtained by splitting the GATHER instruction, the arithmetic unit can maintain the number of queried data tables, q. Initially, q=0. The index vectors in the UOPs are sent to the arithmetic unit through the data path. The length of the data path (DLEN) can be equal to VLEN, where DLEN represents the maximum amount of data that the data path can transmit in one clock cycle. The arithmetic unit uses the index vector in its own UOP to query the data vector in its own UOP. After receiving data vectors from other UOPs (e.g., data vectors synchronized from the array control unit), it continues to use the index vector in its own UOP to query the synchronized data vector. After each query, q is incremented by 1. When the number of q equals the number of UOPs in the MOP corresponding to the arithmetic unit's own UOP, the execution is considered complete. Alternatively, after the central control unit sends data vectors defined in other UOPs to the arithmetic unit multiple times, the central control unit controls the arithmetic unit to write back. Accordingly, the final query result can be used as the execution result and written back.

[0119] Figure 9 This is a schematic diagram of an architecture provided by an embodiment of the present invention, such as... Figure 9 As shown, the electronic device includes a decoding unit, a renaming unit, a dispatch unit, a reordering buffer, a wake-up unit, a vector transmission queue, a non-vector transmission queue, a vector physical register file, a non-vector physical register file, a non-vector operation unit, and a vector operation unit. The vector operation unit includes a target operation array (i.e., a GATHER operation array) and other vector operation units. Figure 10 This is another architectural schematic diagram provided by an embodiment of the present invention, such as... Figure 10As shown, the target arithmetic array includes a control unit. For a GATHER instruction, it first enters the decoding unit for decoding and is split into UOPs. For example, it is split into VLEN / DLEN*LMUL UOPs with DLEN as the granularity. Each UOP passes an index element (a consecutive partial index element in the register when VLEN>DLEN) and a data element (a consecutive partial data element in the register when VLEN>DLEN) from a vs1 register to the target arithmetic array. After execution, the result is the query result corresponding to the index element (a consecutive partial index element in the register when VLEN>DLEN) in the vs1 register. The split UOPs are then renamed by the renaming unit to replace their register numbers. Specifically, the renaming unit queries the speculative renaming table, converts the logical register number of the source operand of the UOP into the corresponding physical register number, allocates a new physical register number for the destination register of the UOP through the physical register free queue, and records it in the speculative renaming table. After renaming, the UOPs obtained from splitting the GATHER instruction will be assigned to the vector emission queue. At the same time, the GATHER instruction will enter the reordering cache, where the GATHER instructions will be arranged in the order of their program sequence for instruction order retirement.

[0120] The wake-up unit can wake up the Units of Operations (UOPs) of the GATHER instruction. For any UOP that has been woken up, it can be selected for issuance by the issue queue if all operands are ready or about to be ready (i.e., the operand flag is set to 1). After issuance, the operands are read from the vector physical register file or data bypass and then executed in the GATHER array. After a UOP of a GATHER instruction is woken up, there are no data or control dependencies between UOPs of the same GATHER instruction. As long as the operand flag of the UOP is set to 1, it will be issued. That is, UOPs of the same GATHER instruction can be executed in the GATHER array in any order. After the UOP is executed, the arithmetic unit can write the execution result back to the vector physical register file, return an update signal to the wake-up unit, and return an executed signal to the reorder cache.

[0121] In this embodiment of the invention, compared to the dispatch unit sending the UOP of the GATHER instruction to the launch queue only after the GATHER instruction is determined to be wakeable, which leads to blocking during the dispatch phase and affects the execution method, this embodiment of the invention allows the dispatch unit to directly send the UOP to the launch queue, where the UOP waits to be launched. This avoids blocking during the dispatch phase.

[0122] Reference Figure 11 The diagram shows a block diagram of a command issuing device provided in an embodiment of the present invention, such as... Figure 11 As shown, the device may specifically include:

[0123] The determination module 201 is used to determine the wakeable instructions based on the number of microinstructions in the non-wakeable instruction set and the number of used arithmetic units in the arithmetic array.

[0124] Setting module 202 is used to set the wake-up flag bit of the microinstruction of the wakeable instruction in the launch queue to a first flag value; the first flag value is used to indicate that the computing array currently has unused computing units required to process the microinstruction of the wakeable instruction;

[0125] The transmitting module 203 is used to transmit the microinstruction to the arithmetic array for any microinstruction in the transmitting queue, provided that the wake-up flag bit of the microinstruction is the first flag value and the operand flag bit indicates that the operand is ready.

[0126] Optionally, the determining module 201 is specifically used for:

[0127] Select one instruction from the set of unwakeable instructions as the target instruction, and determine whether there are m consecutive unused arithmetic units based on the quantity representation information; where m is the number of microinstructions of the target instruction.

[0128] If it exists, the target instruction is determined as a wake-up instruction, and the quantity representation information is updated based on the relevant information of the m consecutive unused arithmetic units;

[0129] The target instruction is updated to the next instruction in the set of unwakeable instructions, and the process returns to the step of determining whether there are currently m consecutive unused computational units based on the quantity representation information, until there are no longer any consecutive m unused computational units.

[0130] Optionally, when the computing array adopts a fully connected topology, the quantity representation information is the number of used units in the computing array that are currently in a used state; the determining module 201 is further configured to: take the sum of the number of used units and m as a first quantity, and determine that there are currently m consecutive unused computing units if the first quantity is not greater than the total number of computing units.

[0131] Update the number of used units to the first number.

[0132] Optionally, when the computing array adopts a non-fully connected topology, the quantity representation information includes the state value of the state bit of each computing unit in the computing array. The determining module 201 is further configured to: determine that there are currently m consecutive unused computing units when there are m consecutive state bits with the first state value; the first state value represents the unused state.

[0133] The state bits of the m consecutive unused computation units are updated to a second state value, which represents the used state.

[0134] Optionally, the device further includes:

[0135] A receiving module is used to receive an update signal returned by a computing unit in the computing array;

[0136] An update module is configured to, if the update signal is sent when the arithmetic unit ends its used state, directly respond to the update signal and update the quantity representation information; if the update signal is sent when the arithmetic unit begins to enter its used state, then, after a preset period following the receipt of the update signal, respond to the update signal and update the quantity representation information.

[0137] Optionally, when the computing array adopts a fully connected topology, the quantity representation information is the number of used units in the computing array that are currently in a used state, and the update module is specifically used to: decrement the number of used units by one;

[0138] When the computing array adopts a non-fully connected topology, the quantity representation information includes the state value of the state bit of each computing unit in the computing array. The update module is specifically used to update the state bit corresponding to the computing unit indicated by the update signal to the first state value.

[0139] Optionally, the setting module 202 is specifically used for:

[0140] For any microinstruction configuration item, if the instruction number in the microinstruction configuration item is the same as the instruction number of the wake-up instruction, the wake-up flag bit in the microinstruction configuration item is set to the first flag value; one microinstruction configuration item represents one microinstruction.

[0141] Optionally, the setting module 202 is further configured to:

[0142] The wake-up unit inputs a wake-up valid signal and the instruction number of the wakeable instruction to the wake-up circuit of each of the micro-instruction configuration items;

[0143] For any of the microinstruction configuration items' wake-up circuits, if the wake-up circuit receives the wake-up valid signal and the received instruction number is the same as the instruction number in the microinstruction configuration item, the wake-up flag bit in the microinstruction configuration item is set to the first flag value.

[0144] In summary, the instruction issuing apparatus provided in this embodiment of the invention determines a wakeable instruction based on the number of microinstructions in the unwakeable instruction set and the number of used arithmetic units in the arithmetic array. The wake-up flag of the microinstruction of the wakeable instruction in the issuing queue is set to a first flag value; the first flag value indicates that the arithmetic array currently has unused arithmetic units required to process the wakeable instruction's microinstruction. For any microinstruction in the issuing queue, if the microinstruction's wake-up flag is the first flag value and the operand flag indicates that the operand is ready, the microinstruction is issued to the arithmetic array. Thus, if the arithmetic array currently has unused arithmetic units required to process the wakeable instruction's microinstruction, the wakeable instruction's microinstruction is woken up; if the microinstruction is woken up and the operand flag indicates that the operand is ready, the microinstruction is issued. This avoids the problem of blocking between multiple UOPs generated by a single instruction, leading to low issuing efficiency, thereby improving issuing efficiency and ultimately improving the overall execution efficiency of the instruction.

[0145] Reference Figure 12 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention. Figure 12 As shown, the electronic device includes a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other via the communication bus. The memory stores executable instructions, which cause the processor to execute the instruction issuance method described in the preceding embodiments. The executable instructions can form a program.

[0146] This invention provides a readable storage medium storing executable instructions that, when executed by one or more processors, cause the processors to perform the instruction issuance method described in the foregoing embodiments.

[0147] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0148] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. It should be noted that all actions involving the acquisition of signals, information, or data in this application are performed in compliance with the relevant data protection laws and regulations of the country where the application is located, and with authorization from the owner of the corresponding device. Embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0149] These computer program instructions may also be stored in a computer-readable storage medium capable of directing a computer or other programmable data processing terminal device to operate in a predictive manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0150] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0151] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0152] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0153] The foregoing has provided a detailed description of the command issuing method, command issuing device, electronic device, and readable storage medium provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. An instruction transmission method characterized by comprising: The method comprises: determining a wake-up instruction based on the number of micro-instructions of the instruction in the non-wake-up instruction set and the number of used operation units of the operation array; the wake-up instruction is determined in the case that there are m unused operation units in succession at present; setting the wake-up flag bit of the micro-instruction of the wake-up instruction in the transmission queue to a first flag value; the first flag value is used to represent that the operation array currently has the unused operation unit required for processing the micro-instruction of the wake-up instruction; for any micro-instruction of the transmission queue, in the case that the wake-up flag bit of the micro-instruction is the first flag value and the operand flag bit represents that the operand is ready, transmitting the micro-instruction to the operation array.

2. The method of claim 1, wherein, The method comprises: selecting an instruction from the non-wake-up instruction set as a target instruction, and determining whether there are m unused operation units in succession at present based on the number representation information; m is the number of micro-instructions of the target instruction; if yes, determining the target instruction as a wake-up instruction, and updating the number representation information based on the related information of the m unused operation units in succession; updating the target instruction to the next instruction in the non-wake-up instruction set, and returning to the step of determining whether there are m unused operation units in succession at present based on the number representation information until there are not m unused operation units in succession at present.

3. The method of claim 2, wherein, In the case that the operation array adopts a full-connected topology, the number representation information is the number of used units in the operation array which are in a used state at present, and the step of determining whether there are m unused operation units in succession at present based on the number representation information comprises: taking the sum of the number of used units and m as a first number, and determining that there are m unused operation units in succession at present in the case that the first number is not greater than the total number of operation units; the step of updating the number representation information based on the related information of the m unused operation units in succession comprises: updating the number of used units to the first number.

4. The method of claim 2, wherein, In the case that the operation array adopts a non-full-connected topology, the number representation information comprises the state values of the state bits of each operation unit in the operation array, and the step of determining whether there are m unused operation units in succession at present based on the number representation information comprises: determining that there are m unused operation units in succession at present in the case that there are m state bits whose state values are a first state value in succession; the first state value represents an unused state; the step of updating the number representation information based on the related information of the m unused operation units in succession comprises: updating the state bits of the m unused operation units in succession to a second state value, and the second state value represents a used state.

5. The method according to any of claims 1 to 4, characterized in that, The method further comprises: receiving an update signal returned by an operation unit in the operation array; If the update signal is sent when the operation unit ends the used state, the quantity characteristic information is updated directly in response to the update signal; If the update signal is sent when the operation unit starts to enter the used state, the quantity characteristic information is updated in response to the update signal after a preset period after the update signal is received.

6. The method of claim 5, wherein, In the case where the operation array adopts a full-connection topology, the quantity characteristic information is the quantity of used units in the operation array currently in the used state, and the updating of the quantity characteristic information in response to the update signal comprises: reducing the quantity of used units by one. In the case where the operation array adopts a non-full-connection topology, the quantity characteristic information comprises the state values of the state bits of each operation unit in the operation array, and the updating of the quantity characteristic information in response to the update signal comprises: updating the state bit corresponding to the operation unit indicated by the update signal to a first state value.

7. The method of claim 1, wherein, The setting of the wake-up flag bit of the microinstruction of the wake-up instruction in the launch queue to the first flag value comprises: For any microinstruction configuration item, the wake-up flag bit in the microinstruction configuration item is set to the first flag value in the case where the instruction sequence number in the microinstruction configuration item is the same as the instruction sequence number of the wake-up instruction; one microinstruction configuration item represents one microinstruction.

8. The method of claim 7, wherein, The setting of the wake-up flag bit in the microinstruction configuration item to the first flag value in the case where the instruction sequence number in the microinstruction configuration item is the same as the instruction sequence number of the wake-up instruction comprises: The wake-up unit inputs a wake-up valid signal and the instruction sequence number of the wake-up instruction to the wake-up circuit of each microinstruction configuration item; For the wake-up circuit of any microinstruction configuration item, the wake-up flag bit in the microinstruction configuration item is set to the first flag value in the case where the wake-up circuit receives the wake-up valid signal and the received instruction sequence number is the same as the instruction sequence number in the microinstruction configuration item.

9. An instruction transmitting apparatus characterized by comprising: The apparatus comprises: The determining module is configured to determine a wake-up instruction based on the quantity of microinstructions of the non-wake-up instruction set and the quantity characteristic information of the used operation units of the operation array; the wake-up instruction is determined in the case where there are continuously the quantity of non-used operation units of the wake-up instruction microinstruction at present; The setting module is configured to set the wake-up flag bit of the microinstruction of the wake-up instruction in the launch queue to a first flag value; the first flag value is used to represent that the operation array currently has the non-used operation unit required for processing the microinstruction of the wake-up instruction; The launching module is configured to, for any microinstruction of the launch queue, launch the microinstruction to the operation array in the case where the wake-up flag bit of the microinstruction is the first flag value and the operand flag bit represents that the operand is ready.

10. An electronic device, comprising: The apparatus comprises: A processor, a memory, a communication interface and a communication bus, the processor, the memory and the communication interface complete communication with each other through the communication bus; The memory is configured to store executable instructions that cause the processor to perform the method of any of claims 1-8.

11. A readable storage medium, characterized by, A non-transitory computer-readable medium having stored thereon executable instructions that, when executed by one or more processors, cause the processors to perform the method of any of claims 1-8.

Images