UVM verification platform reference model hardware architecture supporting multistage dynamic configuration

Abstract

The invention provides a UVM verification platform reference model hardware architecture supporting multi-stage dynamic configuration, which belongs to the technical field of UVM verification platforms, and comprises the following steps: S1, a hierarchical reference model construction step which comprises a model splitting link and a cascade connection link, S2, a dynamic configuration mechanism implementation step which comprises a multi-stage dynamic configuration mechanism implementation step, and S3, a multi-stage dynamic configuration mechanism implementation step. The step comprises a configuration centralization link, a tagging distribution link and a real-time reconfiguration link, the step of S3 hierarchical irrelevant processing comprises a general model template link and a differentiation injection link, aiming at the fact that a traditional verification platform is generally a single-stage reference model, and for some hardware designs with multi-stage similar structures, the step of S3 hierarchical irrelevant processing is carried out. The problem of low efficiency caused by direct integration of all the reference models is solved, the verification platform with the multi-level reference model is constructed through a hardware design structure of a multi-level structure, and the problems of low reusability and low efficiency of codes of a traditional platform are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of UVM verification platforms, and in particular to a UVM verification platform reference model hardware architecture supporting multi-level dynamic configuration. Background Art

[0002] Against the backdrop of advanced process evolution and the reconstruction of ultra-large-scale network architectures, programming protocol-independent packet processors (P4s) have become a core technology in software-defined networking (SDN) and SmartNICs due to their protocol independence and data plane programmability. However, P4s consist of a programmable parser, a programmable deparser, and a programmable match-action table (MAT) located between them.

[0003] MAT, a key core module, is primarily responsible for matching parsed data and executing different types of commands. However, in actual use, multiple matching and command execution operations are often required, which requires structural design and efficiency improvement. Verification of these structures is generally carried out using a verification platform built using the UVM verification methodology. However, conventional UVM verification platforms face significant challenges when faced with new structures. This also significantly impacts the efficiency of designers using the platform when carrying out their work.

[0004] An intelligent verification platform based on UVM (Universal Verification Methodology) plays a cornerstone role in ensuring the credibility of designs. A typical UVM platform environment is generally composed of an agent (including a driver, monitor, and sequencer), a scoreboard, and a reference model. For a reference model, data packets received by a monitor are typically transmitted to the reference model via a TLM interface, and then, after logical processing by the reference model, are sent to the scoreboard. Reference models generally implement the same functionality based on the design of the hardware architecture. Thus, for the same data stream, the same results should be obtained after processing by the reference model and by the design development code. Ultimately, the results can be compared to determine whether the design's logical processing is correct and meets expectations.

[0005] For traditional test platforms, in the process of verifying MAT, you first need to complete the writing of related structures such as i_agent, o_agent, reference model, scoreboard, etc., and then send sequence stimuli, drive the stimuli to the interface through the driver, and send the stimuli to the DUT (structure under test) through the interface. On the other hand, the monitor will sample the signal on the interface and send the signal to the reference model for processing. The processed data is sent to the scoreboard, waiting for the signal sent from the DUT, and after collection, it is sent to the scoreboard for comparison and verification.

[0006] Therefore, when verifying the multi-level structure of MAT, the general UVM test platform simulates the operation of MAT in the reference model, integrates the multi-level structure into the reference model one level at a time, and uniformly receives the configuration of each level in the reference model. Then, it is necessary to find the corresponding level and send the configuration to the correct level.

[0007] The existing UVM verification platform reference model implementation has the following technical defects:

[0008] 1. Generally, it is a single-level reference model. For some hardware designs with multi-level similar structures, directly integrating all of them will lead to low efficiency.

[0009] 2. The multi-instance model configuration needs to be manually modified, and each level of configuration needs to be found one by one, which can easily lead to a waste of hardware resources.

[0010] 3. Traditional architecture cannot support dynamic hierarchical expansion. If there are additions or deletions to hierarchies, the workload will increase. Summary of the Invention

[0011] This invention can construct a verification platform with a multi-level reference model for hardware designs with multi-level structures. This solves the code reusability and inefficiency issues of traditional platforms while improving scalability. By removing layers, the model can be dynamically modified. Finally, the configuration process is simplified, allowing for easy modification of the internal structure and related configurations of each layer, thus overcoming the problems mentioned in the background art.

[0012] Based on the above technical ideas, the technical solution adopted by the present invention is:

[0013] A UVM verification platform reference model hardware architecture supporting multi-level dynamic configuration includes the following steps:

[0014] S1 hierarchical reference model construction step, which includes model splitting and cascade connection;

[0015] S2 dynamic configuration mechanism implementation steps, which include configuration centralization, label distribution and real-time reconfiguration;

[0016] S3 level-independent processing step, which includes the general model template stage and the differential injection stage;

[0017] S4 verification process execution step, which includes data driving step, parallel processing step and result comparison step;

[0018] S5 dynamic expansion support step, which includes parameterized hierarchical control link and topology reconstruction link.

[0019] Further limitation of the above technical solution is the S1 hierarchical reference model construction step, in which the model splitting link includes analyzing the multi-level structure of the hardware design and creating an independent reference model for each level; the cascade connection link includes connecting the reference models in series according to the hardware data flow sequence, the first-level model receives the input data, and passes the result to the second-level model after processing, and the second-level model passes the result to the third level after processing to form a chain processing channel, and all models communicate through standardized interfaces to ensure the uniformity of the data packet format.

[0020] Further limitation of the above technical solution is the implementation step of the S2 dynamic configuration mechanism. In this step, the centralized configuration link includes establishing a central configuration manager at the top level of the verification platform to receive all configuration parameters of the test cases, and the configuration parameters carry hierarchical identification tags; the labeled distribution link includes the central configuration manager automatically routing the parameters to the reference model of the corresponding level according to the tag, and each level model updates the internal processing logic in real time after receiving the configuration.

[0021] To further limit the above technical solution, the real-time reconfiguration link includes modifying the level number parameter when the hardware level increases or decreases, triggering the model chain reconstruction, and the central manager automatically disconnecting the deleted level and redirecting the data flow to the remaining levels.

[0022] Further limitation of the above technical solution: the S3 level-independent processing step, in which the general model template link includes defining a general reference model template, including a basic processing unit, and the differentiated injection link includes dynamically customizing functions of each level model through the received configuration parameters. The same template can be instantiated into models with different functions.

[0023] To further limit the above technical solution, the S4 verification process execution step, in which the data-driven link includes the test data packet being simultaneously input into the hardware design (DUT) and the first-level reference model. Inside the hardware design: data is processed step by step according to a fixed hierarchy. Reference model chain: data flows through Model 1 → Model 2 → ... → Model N in sequence, and each level is processed according to the configuration.

[0024] To further limit the above technical solution, the parallel processing link includes the DUT hardware and the multi-level reference model synchronously processing data, and the result comparison link includes the final-level reference model output result and the hardware final output being synchronously sent to the verifier, and the verifier compares the differences between the two field by field, marks the mismatches and generates an error report.

[0025] A further limitation of the above technical solution is the S5 dynamic expansion support step, in which the parameterized hierarchical control link includes controlling the length of the reference model chain by modifying the global parameters. When the parameter value increases, the model instance of the newly added level is automatically generated and inserted into the chain. When the parameter value decreases, the terminal model is automatically removed and the data flow is redirected.

[0026] As a further limitation of the above technical solution, in the topology reconstruction link, when the number of levels changes, the system automatically rebuilds the connection relationship between models. The connection relationship is generated according to predefined topology rules without the need for human intervention.

[0027] Further limitations on the above technical solution include a configuration parameter dynamic modification model:

[0028]

[0029] The above program uses SystemVerilog programming language.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] 1. Multi-level reference models can improve verification efficiency. Only one reference model is maintained, but multiple copies are instantiated. If a problem occurs at a certain level, it is not necessary to find a specific location, but only a general location.

[0032] 2. Simple configuration, saving hardware resources. Through the top-level classified configuration, you can easily find the configuration of a certain level. As long as you target a certain level, you can quickly locate a certain configuration and modify it.

[0033] 3. Dynamic level expansion is possible. You can expand the level by simply modifying the parameters, and you can also quickly delete a level; BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0035] Figure 1 Verify the MAT schematic for the traditional test platform;

[0036] Figure 2 The present invention is a schematic diagram of a UVM verification platform reference model hardware architecture supporting multi-level dynamic configuration using the SV language-based UVM verification methodology. DETAILED DESCRIPTION

[0037] The following is combined with Figure 1-Figure 2 The present invention is described in further detail.

[0038] Embodiment 1: This embodiment provides a UVM verification platform reference model hardware architecture that supports multi-level dynamic configuration, such as Figure 1-Figure 2 As shown, the following steps are included:

[0039] S1 hierarchical reference model construction step, which includes model splitting and cascade connection;

[0040] S2 dynamic configuration mechanism implementation steps, which include configuration centralization, label distribution and real-time reconfiguration;

[0041] S3 level-independent processing step, which includes the general model template stage and the differential injection stage;

[0042] S4 verification process execution step, which includes data driving step, parallel processing step and result comparison step;

[0043] S5 dynamic expansion support step, which includes parameterized hierarchical control link and topology reconstruction link.

[0044] The S1 hierarchical reference model construction step, in which the model splitting link includes analyzing the multi-level structure of the hardware design and creating an independent reference model for each level; the cascade connection link includes connecting the reference models in series according to the hardware data flow sequence, the first-level model receives input data, and passes the result to the second-level model after processing. The second-level model passes the result to the third level after processing to form a chain processing channel. All models communicate through standardized interfaces to ensure the uniformity of data packet formats.

[0045] The S2 dynamic configuration mechanism implementation steps include the configuration centralization link in this step, which includes setting up a central configuration manager at the top level of the verification platform to receive all configuration parameters of the test cases, and the configuration parameters carry hierarchical identification tags; the label distribution link includes the central configuration manager automatically routing the parameters to the reference model of the corresponding level according to the tags, and each level model updates the internal processing logic in real time after receiving the configuration.

[0046] The real-time reconfiguration process includes modifying the number of layers parameters when hardware layers are added or removed, triggering model chain reconstruction, and the central manager automatically disconnecting the deleted layers and redirecting the data flow to the remaining layers.

[0047] The S3 level-independent processing step, in which the general model template link includes defining a general reference model template, including a basic processing unit, and the differentiated injection link includes dynamically customizing functions of each level model through received configuration parameters. The same template can be instantiated into models with different functions.

[0048] The S4 verification process execution step includes the data-driven link in which the test data packet is simultaneously input into the hardware design (DUT) and the first-level reference model. Inside the hardware design: data is processed step by step according to a fixed hierarchy. In the reference model chain: data flows through Model 1 → Model 2 → ... → Model N in sequence, and each level is processed according to the configuration.

[0049] The parallel processing link includes synchronous data processing of the DUT hardware and the multi-level reference model, and the result comparison link includes synchronously sending the output result of the final-level reference model and the final output of the hardware to the verifier. The verifier compares the differences between the two field by field, marks mismatches and generates an error report.

[0050] The S5 dynamic expansion support step includes the parameterized hierarchical control link in which the length of the reference model chain is controlled by modifying the global parameters. When the parameter value increases, the model instance of the newly added level is automatically generated and inserted into the chain. When the parameter value decreases, the terminal model is automatically removed and the data flow is redirected.

[0051] In the topology reconstruction phase, when the number of levels changes, the system automatically rebuilds the connection relationship between models. The connection relationship is generated according to predefined topology rules without manual intervention.

[0052] It also includes configuration parameters to dynamically modify the model:

[0053]

[0054]

[0055] The above program uses SystemVerilog programming language.

[0056] The specific working principle is:

[0057] Embodiment 2: This embodiment provides a UVM verification platform reference model hardware architecture that supports multi-level dynamic configuration, such as Figure 1-Figure 2 As shown, it also includes the use of UVM verification methodology and system-level hardware description language (SystemVerilog) to build a verification environment platform to implement multi-level functional verification and software problem reproduction for the MAT module.

[0058] SystemVerilog (SV) combines concepts from Verilog, VHDL, and C++, along with a testbench language and assertion language, enhancing design modeling capabilities at a higher level of abstraction. It is primarily targeted at chip implementation and verification processes. SV offers all the constructs required by chip designers and verification engineers, integrating features such as object-oriented programming, dynamic threading, and inter-thread communication.

[0059] The UVM verification methodology is a verification platform development framework based on the SV language, which is widely used in functional verification of digital designs. UVM provides a standardized methodology that can guide verification projects to start from the functional specifications of the DUT, formulate verification plans, decompose test points, create test cases, define acceptance methods and standards, automate processes and reports, etc. In addition, UVM can help verification engineers build a verification environment with standardized hierarchical structures and interfaces, and provide a reusable mechanism for verification environments and test cases in the form of SV class libraries, which greatly improves verification efficiency; such as Figure 1 It is the approximate relationship between the various components in the verification environment built based on UVM. In the UVM framework, various environmental components are independent of each other and perform their respective functions. Each simulation stage is clearly defined and executed in an orderly manner, which is equivalent to reflecting its universality in both "space" and "time" scales.

[0060] The MAT module is a crucial component of the P4 language, matching received messages and executing instructions. In this paper, it features a multi-layered structure, with some structural and configuration differences between the layers. However, each layer also shares similar logical processing units and structures.

[0061] The multi-level functional verification technique described here means that the correctness of each level can be verified by mapping the reference models of different levels to the actual hardware structures of each level. Furthermore, different configurations can be issued to each level through configuration, allowing each level to have its own unique characteristics. Specific implementation method:

[0063] The multi-level verification platform built by the present invention is completed using the UVM verification methodology based on the SV language. It mainly includes related structures such as i_agent, o_agent, reference model1, reference model2, reference modeln, scoreboard, etc. Finally, the physical signal connection between the DUT and the verification platform is established through the interface;

[0064] The test case mainly completes the definition of the MAT randomization sequence. Different test cases use different sequences to verify different functions.

[0065] As can be seen in the diagram above, the number of levels in each layer can be modified based on hierarchical requirements. Each reference model is interconnected, accepting data processed by a higher-level reference model and then further processing it based on its own configuration. This allows for the design of different reference model levels based on the actual hardware architecture, matching each level to the specific configuration, and personalizing each reference model. Finally, the processed data is sent to the scoreboard for comparison with the data collected by o_monitor to verify the accuracy of the DUT test results.

[0066] Beneficial effects of the present invention:

[0067] 1. Multi-level reference models can improve verification efficiency. Only one reference model is maintained, but multiple copies are instantiated. If a problem occurs at a certain level, it is not necessary to find a specific location, but only a general location.

[0068] 2. Simple configuration, saving hardware resources. Through the top-level classified configuration, you can easily find the configuration of a certain level. As long as you target a certain level, you can quickly locate a certain configuration and modify it.

[0069] 3. Dynamic level expansion is possible. You can expand the level by simply modifying the parameters, and you can also quickly delete a level.

[0070] The above contents are further detailed descriptions of the present invention in conjunction with specific preferred embodiments, so as to facilitate those skilled in the art to understand and apply the present invention. It should not be considered that the specific implementation of the present invention is limited to these descriptions.

Claims

1. A UVM verification platform reference model hardware architecture supporting multi-level dynamic configuration, characterized in that: The following steps are involved: S1 hierarchical reference model construction step, which includes model splitting and cascade connection; S2 dynamic configuration mechanism implementation steps, which include configuration centralization, label distribution and real-time reconfiguration; S3 level-independent processing step, which includes the general model template stage and the differential injection stage; S4 verification process execution step, which includes data driving step, parallel processing step and result comparison step; S5 dynamic expansion support step, which includes parameterized hierarchical control link and topology reconstruction link.

2. A UVM verification platform reference model hardware architecture supporting multi-level dynamic configuration according to claim 1, characterized in that, The S1 hierarchical reference model construction step, in which the model splitting link includes analyzing the multi-level structure of the hardware design and creating an independent reference model for each level; the cascade connection link includes connecting the reference models in series according to the hardware data flow sequence, the first-level model receives input data, and passes the result to the second-level model after processing. The second-level model passes the result to the third level after processing to form a chain processing channel. All models communicate through standardized interfaces to ensure the uniformity of data packet formats.

3. A UVM verification platform reference model hardware architecture supporting multi-level dynamic configuration according to claim 2, characterized in that, The S2 dynamic configuration mechanism implementation steps include the configuration centralization link in this step, which includes setting up a central configuration manager at the top level of the verification platform to receive all configuration parameters of the test cases, and the configuration parameters carry hierarchical identification tags; the label distribution link includes the central configuration manager automatically routing the parameters to the reference model of the corresponding level according to the tags, and each level model updates the internal processing logic in real time after receiving the configuration.

4. A UVM verification platform reference model hardware architecture supporting multi-level dynamic configuration according to claim 3, characterized in that, The real-time reconfiguration process includes modifying the number of layers parameters when hardware layers are added or removed, triggering model chain reconstruction, and the central manager automatically disconnecting the deleted layers and redirecting the data flow to the remaining layers.

5. A UVM verification platform reference model hardware architecture supporting multi-level dynamic configuration according to claim 4, characterized in that, The S3 level-independent processing step, in which the general model template link includes defining a general reference model template, including a basic processing unit, and the differentiated injection link includes dynamically customizing functions of each level model through received configuration parameters. The same template can be instantiated into models with different functions.

6. A UVM verification platform reference model hardware architecture supporting multi-level dynamic configuration according to claim 5, characterized in that, The S4 verification process execution step includes the data-driven link in which the test data packet is simultaneously input into the hardware design and the first-level reference model. Inside the hardware design: data is processed step by step according to a fixed hierarchy. In the reference model chain: data flows through Model 1 → Model 2 → ... → Model N in sequence, and each level is processed according to the configuration.

7. A UVM verification platform reference model hardware architecture supporting multi-level dynamic configuration according to claim 6, characterized in that, The parallel processing link includes synchronous data processing of the DUT hardware and the multi-level reference model, and the result comparison link includes synchronously sending the output result of the final-level reference model and the final output of the hardware to the verifier. The verifier compares the differences between the two field by field, marks mismatches and generates an error report.

8. A UVM verification platform reference model hardware architecture supporting multi-level dynamic configuration according to claim 7, characterized in that, The S5 dynamic expansion support step includes the parameterized hierarchical control link in which the length of the reference model chain is controlled by modifying the global parameters. When the parameter value increases, the model instance of the newly added level is automatically generated and inserted into the chain. When the parameter value decreases, the terminal model is automatically removed and the data flow is redirected.

9. A UVM verification platform reference model hardware architecture supporting multi-level dynamic configuration according to claim 8, characterized in that, In the topology reconstruction phase, when the number of levels changes, the system automatically rebuilds the connection relationship between models. The connection relationship is generated according to predefined topology rules without manual intervention.

10. A UVM verification platform reference model hardware architecture supporting multi-level dynamic configuration according to claim 9, characterized in that, It also includes configuration parameters to dynamically modify the model: The above program uses SystemVerilog programming language.

Images