A uvm verification platform reference model hardware architecture supporting multiple levels of dynamic configuration

Abstract

The application provides a UVM verification platform reference model hardware architecture supporting multistage dynamic configuration, belongs to the technical field of UVM verification platforms, and comprises the following steps: S1, a hierarchical reference model construction step, which comprises a model splitting link and a cascaded connection link; S2, a dynamic configuration mechanism implementation step, which comprises a centralized configuration link, a tag distribution link and a real-time reconfiguration link; and S3, a hierarchical independence processing step, which comprises a universal model template link and a differential injection link. The traditional verification platform is generally a single-stage reference model, and for some hardware designs with multistage similar structures, directly integrating all the structures leads to the problem of low efficiency. The application constructs a verification platform with multistage reference models through a multistage hardware design structure, and solves the problems of code reusability and low efficiency of the traditional platform.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of UVM verification platform, and particularly relates to a UVM verification platform reference model hardware architecture supporting multi-level dynamic configuration. BACKGROUND

[0002] Under the background of advanced process evolution and ultra-large network architecture reconstruction, programming protocol-independent packet processors (P4) has become the core technology in the field of software-defined network (SDN) and smart network interface card (SmartNIC) due to its protocol independence and data plane programmable capability; however, P4 is composed of a programmable parser, a programmable depacketizer and a programmable match table (MAT) located between them.

[0003] The MAT therein is a key core module, which is mainly responsible for matching the parsed data and executing different types of commands. However, in actual application, multiple matching and command execution operations are often required, which involves the design of the structure and the improvement of the efficiency. The verification of these structures is generally carried out by using a verification platform built by the UVM verification methodology, but the original structure of the general UVM verification platform faces great challenges when facing some new structures. At the same time, the efficiency of the platform used by the designers also has many influences when carrying out the work.

[0004] An intelligent verification platform based on UVM (Universal Verification Methodology) plays a cornerstone role in ensuring the credibility of the design. The environment of the general uvm platform is generally composed of an agent (including a driver, a monitor and a sequencer), a scoreboard and a reference model. For the reference model, the data packets accepted by the monitor are transmitted to the reference model through a tlm interface, and then sent to the scoreboard after logical processing of the reference model. The reference model generally implements the same function according to the design of the hardware architecture. In this way, the same results should be obtained after the processing of the reference model and the processing of the design and development code for the same data stream, and finally the results are compared, so as to judge whether the logical processing of the design is correct and meets the expectation.

[0005] For the traditional test platform, in the process of verifying MAT, first of all, i_agent, o_agent, reference model, scoreboard and other related structures need to be written, then the sequence excitation is sent, the excitation is driven to the interface through the driver, the excitation is sent to the DUT (structure under test) through the interface, on the other hand, the monitor samples the signal on the interface, and sends the signal to the reference model for processing, and the processed data is sent to the scoreboard, and waits for the signal sent from the DUT, and the signal is collected and sent to the scoreboard for comparison and verification.

[0006] Therefore, when verifying the multi-level structure of MAT, the general UVM test platform simulates the operation of MAT in the reference model, integrates the multi-level structure level by level into the reference model, and uniformly receives the configuration of each level in the reference model, and then needs to find the corresponding level and send the configuration to the correct level.

[0007] The existing uvm verification platform reference model implementation method has the following technical defects:

[0008] 1. Generally, the reference model is single-level, and for some hardware designs with multi-level similar structures, directly integrating all of them leads to low efficiency.

[0009] 2. The multi-instance model configuration needs to be manually modified, and each level configuration needs to be found one by one, which is easy to cause waste of hardware resources

[0010] 3. The traditional architecture cannot support dynamic level expansion, and if levels are added or deleted, it will increase the workload. SUMMARY

[0011] The present application can construct a verification platform with multi-level reference model for hardware design structure with multi-level structure, solve the problems of code reusability and low efficiency of traditional platform, and improve the expandability. If levels are added or deleted, the model can be dynamically modified. Finally, the configuration process is simplified, and the configuration can easily realize the modification of the internal form of each level and related configuration, thereby overcoming the problems in the above background art.

[0012] Based on the above technical idea, the technical scheme adopted by the present application is:

[0013] A UVM verification platform reference model hardware architecture supporting multi-level dynamic configuration, comprising the following steps:

[0014] S1 hierarchical reference model construction step, which includes model splitting link and cascading connection link;

[0015] S2 dynamic configuration mechanism implementation step, which includes a centralized link, a labeled distribution link and a real-time reconfiguration link;

[0016] S3 hierarchical independence processing step, which includes a general model template link and a differentiated injection link;

[0017] S4 verification process execution step, which includes a data-driven link, a parallel processing link and a result comparison link;

[0018] S5 dynamic expansion support step, which includes a parameterized hierarchical control link and a topology reconstruction link.

[0019] Further limitation of the above technical solution, the S1 hierarchical reference model construction step, the model splitting link in which includes analyzing the multi-level structure of the hardware design, and independently creating a reference model for each level; the cascading connection link includes connecting the reference models in the order of hardware data flow, the first level model receiving input data, and the result after processing being transmitted to the second level model, the second level model processing and then being transmitted to the third level to form a chain processing channel, all models communicating through standardized interfaces to ensure uniform data packet format.

[0020] Further limitation of the above technical solution, the S2 dynamic configuration mechanism implementation step, the centralized configuration link in which includes setting a central configuration manager at the top layer of the verification platform, receiving all configuration parameters of the test case, and the configuration parameters carrying level identification tags; the labeled distribution link includes the central configuration manager automatically routing the parameters to the corresponding level reference model according to the tags, and each level model updating the internal processing logic in real time after receiving the configuration.

[0021] Further limitation of the above technical solution, the real-time reconfiguration link includes modifying the level number parameter when the hardware level increases or decreases, triggering model chain reconstruction, the central manager automatically disconnecting the connection of the deleted level, and redirecting the data flow to the remaining levels.

[0022] Further limitation of the above technical solution, the S3 hierarchical independence processing step, the general model template link in which includes defining a general reference model template, including a basic processing unit, and the differentiated injection link includes each level model dynamically customizing functions through received configuration parameters, and the same template can be instantiated as models with different functions.

[0023] Further limit to the above technical solution, the S4 verification process performs steps, in which the data driving link includes test data packets input to hardware design (DUT) and the first level reference model at the same time, and in the hardware design: data is processed by fixed levels one by one, and the reference model chain: data flows through model 1→model 2→...→model N in turn, and each level is processed according to the configuration.

[0024] Further limit to the above technical solution, the parallel processing link includes DUT hardware and multi-level reference model synchronous data processing, and the result comparison link includes the final level reference model output result and the hardware final output being sent to the verifier at the same time, the verifier compares the differences between them field by field, marks the mismatched items and generates an error report.

[0025] Further limit to the above technical solution, the S5 dynamic expansion support step, in which the parameterized level control link includes controlling the length of the reference model chain by modifying global parameters, and when the parameter value increases, automatically generating a new level model instance and inserting it into the chain, and when the parameter value decreases, automatically removing the end model and redirecting the data flow.

[0026] Further limit to the above technical solution, the topology reconstruction link automatically reconstructs the connection relationship between models when the level number changes, and the connection relationship is generated through predefined topology rules without manual intervention.

[0027] Further limit to the above technical solution, it also includes dynamic modification of the model by configuration parameters.

[0028]

[0029] The above program uses the systemverilog programming language.

[0030] Compared with the prior art, the beneficial effects of the present application are:

[0031] 1. Multi-level reference model can improve verification efficiency. Only one reference model is maintained, but multiple copies are instantiated. If there is a problem at a certain level, it is not necessary to find a specific location, but only a general location.

[0032] 2. Simple configuration, saving hardware resources. Through the top-level classified configuration, the configuration of a certain level can be easily found, and only for a certain level, a certain configuration can be quickly located and modified.

[0033] 3. Dynamic level expansion can be performed. Only the parameter needs to be modified to expand the level, and a certain level can also be quickly deleted and reduced. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to make the technical solutions in the embodiments of the present application or the prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative effort based on these drawings.

[0035] Figure 1 Verification diagram of MAT for traditional test platform;

[0036] Figure 2 A schematic diagram completed by using a UVM verification methodology based on an SV language in a hardware architecture of a UVM verification platform reference model supporting multi-level dynamic configuration according to the present application. DETAILED DESCRIPTION

[0037] The present application will be further described below. Figures 1-2 The present application will be further described below.

[0038] Embodiment 1: The present embodiment provides a hardware architecture of a UVM verification platform reference model supporting multi-level dynamic configuration, as shown in the following figure, including the following steps: Figures 1-2

[0039] S1 hierarchical reference model construction step, including model splitting link and cascading connection link;

[0040] S2 dynamic configuration mechanism implementation step, including centralized configuration link, tag distribution link and real-time reconfiguration link;

[0041] S3 hierarchical independence processing step, including general model template link and differential injection link;

[0042] S4 verification flow execution step, including data driving link, parallel processing link and result comparison link;

[0043] S5 dynamic expansion support step, including parameterized hierarchical control link and topology reconstruction link.

[0044] The S1 hierarchical reference model construction step, in which the model splitting link includes analyzing the multi-level structure of the hardware design and independently creating a reference model for each level; the cascading connection link includes connecting the reference models in series according to the hardware data flow order, the first level model receiving input data, passing the results to the second level model after processing, and then passing the results to the third level to form a chain processing channel, all models communicating through standardized interfaces to ensure uniform data packet format.

[0045] ​The S2 dynamic configuration mechanism implementation step, wherein the centralized configuration link includes establishing a central configuration manager at the top layer of the verification platform, receiving all configuration parameters of the test case, and the configuration parameters carrying a hierarchical identification tag; the tag-based distribution link includes automatically routing the parameters to the corresponding hierarchical reference model by the central configuration manager according to the tag, and each hierarchical model updating the internal processing logic in real time after receiving the configuration.

[0046] The real-time reconfiguration link includes modifying the hierarchical quantity parameter when the hardware hierarchy increases or decreases, triggering the model chain reconstruction, automatically disconnecting the connection of the deleted hierarchy by the central manager, and redirecting the data flow to the remaining hierarchy.

[0047] The S3 hierarchical independence processing step, wherein the universal model template link includes defining a universal reference model template including a basic processing unit, and the differentiation injection link includes dynamically customizing the function of each hierarchical model through the received configuration parameters, and the same template can be instantiated as a model with different functions.

[0048] The S4 verification flow execution step, wherein the data driving link includes inputting the test data packet into the hardware design (DUT) and the first-level reference model at the same time, the hardware design internally: the data is processed level by level, and the reference model chain: the data flows through model 1→model 2→...→model N in turn, and each level is processed according to the configuration.

[0049] The parallel processing link includes synchronously processing data by the DUT hardware and the multi-level reference model, and the result comparison link includes synchronously sending the output result of the final-level reference model and the final output of the hardware to the verifier, comparing the two differences field by field by the verifier, marking the mismatched items and generating an error report.

[0050] The S5 dynamic expansion support step, wherein the parameterized hierarchical control link includes controlling the length of the reference model chain by modifying the global parameter, automatically generating a new hierarchical model instance and inserting it into the chain when the parameter value increases, and automatically removing the end model and redirecting the data flow when the parameter value decreases.

[0051] The topology reconstruction link automatically reconstructs the connection relationship between models when the number of hierarchies changes, and the connection relationship is generated through predefined topology rules without manual intervention.

[0052] It also includes dynamically modifying the model of the configuration parameter:

[0053]

[0054]

[0055] The above program uses the systemverilog programming language.

[0056] The specific working principle is as follows.

[0057] Embodiment 2: The embodiment provides a UVM verification platform reference model hardware architecture supporting multi-level dynamic configuration, as shown in the figure, and also comprises the following steps: adopting a UVM verification methodology and a system-level hardware description language (SystemVerilog), constructing a verification environment platform, and implementing multi-level functional verification and software problem reproduction on a MAT module. Figures 1-2

[0058] The SystemVerilog (SV language for short) combines concepts from Verilog, VHDL and C++, and verification platform language and assertion language, and improves the design modeling capability at a higher abstraction level, and is mainly positioned on the implementation and verification process of a chip. The SV language has all the structures required by chip design and verification engineers, and integrates object-oriented programming, dynamic threads and thread communication and other characteristics.

[0059] The UVM verification methodology is a verification platform development framework based on the SV language, and is widely applied to functional verification of digital design. The UVM provides a standardized methodology, which can guide verification engineers to start from the functional specification of a DUT, formulate a verification plan, decompose test points, create test cases, define acceptance methods and standards, and realize process automation and report automation. In addition, the UVM can help verification engineers to build a verification environment with a standardized hierarchical structure and interface, and provide a reusable mechanism for the verification environment and test cases in the form of an SV class library, thereby greatly improving the verification efficiency. Figure 1 The figure is a general relationship of various components in the verification environment based on the UVM. In the framework of the UVM, various environment components are independent of each other, each performs its own function, and each simulation stage is defined clearly and executed in an orderly manner, which is equivalent to embodying its universality in both the "space" and "time" dimensions.

[0060] The MAT module is an important component in the P4 language, and can match and execute instructions on the received packet. In the present application, the MAT module is composed of multiple levels, and the multiple levels are different in structure and configuration source, but each level has a certain similar logic processing unit and similar structure.

[0061] The multi-level functional verification refers to that the present application can verify the correctness of each level by one-to-one correspondence between the reference model of different levels and the actual hardware structure of different levels. Meanwhile, each level can be configured differently, and each level can have its own characteristics through configuration. DETAILED DESCRIPTION

[0063] ​The multi-level verification platform built by the application is completed by using the UVM verification methodology based on the SV language, and mainly comprises i_agent, o_agent, reference model 1, reference model 2, reference model n, scoreboard and related structures.

[0064] The test cases are mainly used for defining the MAT random sequence, different test cases use different sequences, and are used for verifying different functions.

[0065] As can be seen from the above figure, the number of each level can be modified according to the requirement of the level, meanwhile each reference model is connected with each other, can accept the data processed by the upper reference model, and then further processes the data according to the configuration of the reference model. This can design different reference model levels according to the actual hardware structure, match the levels one by one, and make each reference model have individuality according to the specific configuration. Finally, the processed data is compared with the data collected by the scoreboard and o_monitor, so as to check the correctness of the DUT test result.

[0066] The application has the following beneficial effects:

[0067] 1. The multi-level reference model can improve the verification efficiency. Only one reference model is maintained, but multiple copies are instantiated, if there is a problem in a certain level, it is not necessary to find a specific position, but only to find a general position.

[0068] 2. The configuration is simple, and the hardware resources are saved. Through the classified configuration of the top layer, the configuration of a certain level can be easily found, and only the configuration of a certain level can be quickly located and modified.

[0069] 3. The dynamic level expansion can be performed. The level expansion can be performed only by modifying the parameters, and meanwhile a certain level can be quickly deleted and reduced.

[0070] The above content is a further detailed description of the application combined with the specific preferred embodiment, so as to facilitate the understanding and application of the application by the person skilled in the art, and cannot be regarded as the limitation of the specific implementation of the application.

Claims

1. A reference model hardware architecture for a UVM verification platform supporting multi-level dynamic configuration, characterized in that, Includes the following steps: The S1 hierarchical reference model construction steps include model splitting and cascading connection steps. The S2 dynamic configuration mechanism implementation steps include a configuration centralization stage, a tag-based distribution stage, and a real-time reconfiguration stage. The S3 hierarchical independence process includes a general model template step and a differential injection step. The S4 verification process execution steps include a data-driven phase, a parallel processing phase, and a result comparison phase. S5 dynamic extension support steps, which include parameterized hierarchical control and topology reconstruction steps; The S1 hierarchical reference model construction step includes a model splitting step that involves analyzing the multi-level structure of the hardware design and creating an independent reference model for each level. The cascading connection step includes connecting the reference models in sequence according to the hardware data flow. The first-level model receives input data, processes it, and then passes the result to the second-level model. The second-level model processes the data and then passes it to the third level to form a chain processing channel. All models communicate through a standardized interface to ensure that the data packet format is uniform. The S2 dynamic configuration mechanism implementation steps include the following steps: the configuration centralization step includes establishing a central configuration manager at the top level of the verification platform to receive all configuration parameters of the test cases, and the configuration parameters carry hierarchical identification tags; the tag-based distribution step includes the central configuration manager automatically routing the parameters to the corresponding level reference model according to the tags, and each level model updating its internal processing logic in real time after receiving the configuration. The S3 level-independent processing step includes a general model template step that defines a general reference model template containing basic processing units, and a differential injection step that includes dynamic customization of functions for each level model through received configuration parameters. The same template can be instantiated into models with different functions. The S4 verification process execution steps include a data-driven step where test data packets are simultaneously input to the hardware design and the first-level reference model. Within the hardware design, data is processed step by step according to a fixed hierarchy. In the reference model chain, data flows sequentially through Model 1 → Model 2 → ... → Model N, with each level processed according to the configuration. The S5 dynamic expansion support step includes a parameterized hierarchical control step that controls the length of the reference model chain by modifying global parameters. When the parameter value increases, a new level of model instance is automatically generated and inserted into the chain. When the parameter value decreases, the end model is automatically removed and the data flow is redirected.

2. The hardware architecture of a UVM verification platform reference model supporting multi-level dynamic configuration according to claim 1, characterized in that, The real-time reconfiguration process includes modifying the number of levels when hardware levels are added or removed, triggering model chain reconstruction, automatically disconnecting the deleted level from the central manager, and redirecting the data stream to the remaining levels.

3. The hardware architecture of a UVM verification platform reference model supporting multi-level dynamic configuration according to claim 2, characterized in that, The parallel processing stage includes DUT hardware and multi-level reference models processing data synchronously. The result comparison stage includes the final reference model output and the final hardware output being sent to the verifier synchronously. The verifier compares the differences between the two field by field, marks mismatches and generates an error report.

4. The hardware architecture of a UVM verification platform reference model supporting multi-level dynamic configuration according to claim 3, characterized in that, When the number of levels changes during the topology reconstruction process, the system automatically rebuilds the connection relationships between models. These connection relationships are generated through predefined topology rules, requiring no manual intervention.

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