Method, device and storage medium for improving processor cache scheduling efficiency

Abstract

This invention relates to the field of processor technology, and particularly to a method, apparatus, and storage medium for improving processor cache scheduling efficiency. The method includes the following steps: starting the operating system kernel and obtaining the device source file of the computer device before the operating system kernel constructs the central processing unit topology; obtaining the cache configuration information of the L2 cache and L3 cache of the computer device's processor system according to the device source file; determining, based on the cache configuration information of the L2 cache and the L3 cache, whether the shared range of the L3 cache is greater than the shared range of the L2 cache; if so: adding a L2 cache scheduling domain at the same level as the L3 cache scheduling domain and corresponding to the L2 cache in the processor system, and pointing the processor system's scheduling domain pointer to the L2 cache scheduling domain. This invention can improve the data read / write efficiency of the processor system.

Description

Technical Field

[0001] This invention relates to the field of processor technology, and in particular to a method, apparatus and storage medium for improving processor cache scheduling efficiency. Background Technology

[0002] Modern servers typically use multi-core processors with Non-Uniform Memory Access (NUMA) architecture, and their caches employ a multi-level cache architecture. Based on the data access order and the tightness of integration with the Central Processing Unit (CPU), processor caches can be divided into Level 1 cache (L1 cache), Level 2 cache (L2 cache), and some high-end processors also have Level 3 cache (L3 cache). These caches are further subdivided according to the data type, such as instruction cache and data cache. All data stored in each level of cache is part of the data in the next lower level cache. The technical difficulty and manufacturing cost of these three types of caches decrease relatively, so their capacities increase relatively. When the CPU needs to read data, it first searches in the Level 1 cache; if not found, it searches in the Level 2 cache; if still not found, it searches in the Level 3 cache or main memory.

[0003] In existing multi-core processor architectures, multiple cores are designed with their own private L1 instruction cache and L1 data cache, a private L2 cache, and a shared L3 cache. There are also special cases where the L1 instruction cache and L1 data cache are private, the L2 cache is shared as a cluster, and multiple clusters share the L3 cache. Due to the scheduling domain design between processor cores, when processor cores in cluster A (sharing the L2 cache) and processor cores in another cluster B perform hot data exchange, although this improves L3 cache hit rate, the performance is significantly worse than data exchange performance between two processor cores belonging to the same cluster due to the loss of L2 cache sharing. In this situation, the processor system does not fully utilize the shared L2 cache, resulting in a performance penalty to some extent. Summary of the Invention

[0004] This invention provides a method, apparatus, and storage medium for improving processor cache scheduling efficiency, aiming to solve the technical problem that the secondary shared cache in existing processor systems is difficult to fully utilize.

[0005] To address the aforementioned technical problems, in a first aspect, the present invention provides a method for improving processor cache scheduling efficiency, the method comprising the following steps:

[0006] S101. Start the operating system kernel and obtain the device source file of the computer device before the operating system kernel builds the central processing unit topology;

[0007] S102. Obtain the cache configuration information of the L2 cache and L3 cache of the processor system of the computer device according to the device source file;

[0008] S103. Based on the cache configuration information of the second-level cache and the third-level cache respectively, determine whether the sharing range of the third-level cache is greater than the sharing range of the second-level cache. If so, proceed to step S104.

[0009] S104. Add a second-level cache scheduling domain in the processor system that is at the same level as the scheduling domain of the third-level cache and corresponds to the second-level cache, and point the scheduling domain pointer of the processor system to the second-level cache scheduling domain.

[0010] Furthermore, in step S103, the step of determining whether the shared range of the third-level cache is greater than the shared range of the second-level cache based on the cache configuration information of the second-level cache and the third-level cache is specifically as follows:

[0011] Based on the cache configuration information of the second-level cache and the third-level cache, determine the cache number of each of the second-level cache and the third-level cache;

[0012] Based on the cache number, determine the number of cores contained in the processor core cluster to which each of the L2 cache and the L3 cache belongs;

[0013] If the number of cores in the processor core cluster to which the L3 cache belongs is greater than the number of cores in the processor core cluster to which the L2 cache belongs, and the L2 cache is a shared cache, then the sharing range of the L3 cache is greater than the sharing range of the L2 cache.

[0014] Furthermore, in step S101, the device source file is an advanced configuration and power interface table or a device tree source file.

[0015] Furthermore, the method also includes the step of:

[0016] S105. Based on the processor system configured with the secondary cache scheduling domain, the operating system kernel completes the construction of the central processing unit topology.

[0017] In a second aspect, the present invention also provides an apparatus for improving processor cache scheduling efficiency, comprising:

[0018] The startup module is used to start the operating system kernel and obtain the device source file of the computer device before the operating system kernel builds the central processing unit topology.

[0019] The configuration information acquisition module is used to acquire the cache configuration information of the L2 cache and L3 cache of the processor system of the computer device according to the device source file;

[0020] The configuration judgment module is used to determine whether the sharing range of the third-level cache is greater than the sharing range of the second-level cache based on the cache configuration information of the second-level cache and the third-level cache respectively. If so, the setting module is executed.

[0021] The configuration module is used to add a second-level cache scheduling domain in the processor system that is at the same level as the scheduling domain of the third-level cache and corresponds to the second-level cache, and to point the scheduling domain pointer of the processor system to the second-level cache scheduling domain.

[0022] Furthermore, when the configuration determination module determines whether the sharing range of the third-level cache is greater than the sharing range of the second-level cache based on the respective cache configuration information of the second-level cache and the third-level cache, it is also used to:

[0023] Based on the cache configuration information of the second-level cache and the third-level cache, determine the cache number of each of the second-level cache and the third-level cache;

[0024] Based on the cache number, determine the number of cores contained in the processor core cluster to which each of the L2 cache and the L3 cache belongs;

[0025] If the number of cores in the processor core cluster to which the L3 cache belongs is greater than the number of cores in the processor core cluster to which the L2 cache belongs, and the L2 cache is a shared cache, then the sharing range of the L3 cache is greater than the sharing range of the L2 cache.

[0026] Furthermore, the device source file is an advanced configuration and power interface table or a device tree source file.

[0027] Furthermore, the startup module is also used for:

[0028] Based on the processor system configured with the secondary cache scheduling domain, the operating system kernel completes the construction of the central processing unit topology.

[0029] Thirdly, the present invention also provides an apparatus for improving processor cache scheduling efficiency, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the method for improving processor cache scheduling efficiency as described in any of the above embodiments.

[0030] Fourthly, the present invention also provides a storage medium storing a computer program, which, when executed by a processor, implements the steps of the method for improving processor cache scheduling efficiency as described in any of the above embodiments.

[0031] The beneficial effect achieved by this invention is that it proposes a method to improve the efficiency of processor cache scheduling. This method analyzes the sharing and scheduling of multi-level caches before the operating system kernel builds the processor topology, configures the scheduling domain of the shareable secondary cache and completes the topology modification, so that the operating system kernel can be aware of the higher-level shared cache structure, thereby enabling the processor core to make full use of the available secondary cache during program execution and improving the data read and write efficiency of the processor system. Attached Figure Description

[0032] Figure 1 This is a flowchart of the steps of a method for improving processor cache scheduling efficiency provided in an embodiment of the present invention;

[0033] Figure 2 This is a schematic diagram of the structure of the device for improving processor cache scheduling efficiency provided in an embodiment of the present invention;

[0034] Figure 3 This is a schematic diagram of another device for improving processor cache scheduling efficiency provided in an embodiment of the present invention. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0036] Please refer to Figure 1 , Figure 1 This is a flowchart illustrating the steps of a method for improving processor cache scheduling efficiency provided in an embodiment of the present invention. The method includes the following steps:

[0037] S101. Start the operating system kernel and obtain the device source file of the computer device before the operating system kernel builds the central processing unit topology.

[0038] The operating system kernel in this embodiment of the invention is a software with the highest privilege level that runs in the operating system of a computer device. It is responsible for managing and controlling the hardware resources of the computer device and providing basic services and interfaces for upper-level applications and users. When the operating system starts, the operating system kernel needs to design, plan and lay out the various components inside the central processing unit and their interconnections in order to achieve specific performance goals and functional requirements, such as the number, type and arrangement of cores, and the size, location and correlation of each level of cache (L1, L2, L3, etc.).

[0039] Specifically, in step S101, the device source file is either an Advanced Configuration and Power Interface (ACPI) table or a Device Tree Source (DTS) file. The ACPI table is a standard document used to regulate the power management and configuration information exchange between the operating system and computer hardware, clarifying the allocation of hardware resources in computer devices, such as memory address space, interrupt request lines (IRQs), and direct memory access (DMA) channels. The DTS file, on the other hand, is a data structure file describing hardware device information; it describes the connection relationships and hierarchical structure of various hardware devices within a computer system.

[0040] S102. Obtain the cache configuration information of the L2 cache and L3 cache of the processor system of the computer device according to the device source file.

[0041] Based on the specific entries in the advanced configuration and power interface table or the device tree source file, step S102 can easily obtain the cache configuration information for the L2 cache and L3 cache respectively. As described in the background art, in the prior art, the L1 cache is usually private to each processor core, and its sharing scope is limited to a single core. It is used to quickly store data and instructions that the core may frequently access in the near future, thereby improving the core's operating speed. The L3 cache, on the other hand, is usually shared by multiple processor cores, and its sharing scope covers multiple cores in the same processor. Multiple cores can access data in the L3 cache simultaneously, reducing the number of accesses to main memory and improving the overall performance of the processor. However, it is unclear whether the L2 cache is private to a processor core or shared between different cores. The main purpose of step S102 is to determine the configuration form and size relationship of the L2 cache and L3 cache by obtaining the corresponding cache configuration information.

[0042] S103. Based on the cache configuration information of the second-level cache and the third-level cache respectively, determine whether the sharing range of the third-level cache is greater than the sharing range of the second-level cache. If so, proceed to step S104.

[0043] Specifically, in step S103, the step of determining whether the shared range of the third-level cache is greater than the shared range of the second-level cache based on the cache configuration information of the second-level cache and the third-level cache is as follows:

[0044] Based on the cache configuration information of the second-level cache and the third-level cache, determine the cache number of each of the second-level cache and the third-level cache;

[0045] Based on the cache number, determine the number of cores contained in the processor core cluster to which each of the L2 cache and the L3 cache belongs;

[0046] If the number of cores in the processor core cluster to which the L3 cache belongs is greater than the number of cores in the processor core cluster to which the L2 cache belongs, and the L2 cache is a shared cache, then the sharing range of the L3 cache is greater than the sharing range of the L2 cache.

[0047] In this embodiment of the invention, the principle of determining that the secondary cache can be used to implement scheduling is that if the secondary cache itself is shared, but the size of the tertiary cache in the computer device hardware is relatively large, it is necessary to determine the hierarchical relationship through the core cluster to which different caches belong. When the core cluster of the tertiary cache is larger than that of the secondary cache, it means that the tertiary cache also belongs to the level after the secondary cache, and the two also have a sequential relationship when the processor core reads data.

[0048] S104. Add a second-level cache scheduling domain in the processor system that is at the same level as the scheduling domain of the third-level cache and corresponds to the second-level cache, and point the scheduling domain pointer of the processor system to the second-level cache scheduling domain.

[0049] By modifying the scheduling domain rules, a second-level cache scheduling was added to the original three-level cache scheduling, enabling the central processing unit core to utilize the second-level cache for process data interaction when performing program read and write operations, thereby improving data read and write efficiency.

[0050] The method further includes the following steps:

[0051] S105. Based on the processor system configured with the secondary cache scheduling domain, the operating system kernel completes the construction of the central processing unit topology.

[0052] It is understood that the method implemented in this embodiment of the invention is a method for replacing the topology logic of the central processing unit so that it can be executed by the operating system kernel. Its implementation is based on the fact that the secondary cache can be used for sharing. Therefore, in step S103, if the logic fails, the operating system kernel can simply load the original device source file to construct the central processing unit topology. The method implemented in this embodiment of the invention can also be directly added to the operating system kernel during implementation, and a switch can be set to enable or disable it on compliant computer devices.

[0053] The beneficial effect achieved by this invention is that it proposes a method to improve the efficiency of processor cache scheduling. This method analyzes the sharing and scheduling of multi-level caches before the operating system kernel builds the processor topology, configures the scheduling domain of the shareable secondary cache and completes the topology modification, so that the operating system kernel can be aware of the higher-level shared cache structure, thereby enabling the processor core to make full use of the available secondary cache during program execution and improving the data read and write efficiency of the processor system.

[0054] This invention also provides an apparatus 200 for improving processor cache scheduling efficiency. Please refer to... Figure 2 , Figure 2 This is a schematic diagram of the structure of an apparatus for improving processor cache scheduling efficiency provided in an embodiment of the present invention, which includes:

[0055] The startup module 201 is used to start the operating system kernel and obtain the device source file of the computer device before the operating system kernel builds the central processing unit topology;

[0056] Configuration information acquisition module 202 is used to acquire the cache configuration information of the L2 cache and L3 cache of the processor system of the computer device according to the device source file;

[0057] The configuration judgment module 203 is used to determine whether the sharing range of the third-level cache is greater than the sharing range of the second-level cache based on the cache configuration information of the second-level cache and the third-level cache respectively. If so, the setting module 204 is executed.

[0058] Setting module 204 is used to add a second-level cache scheduling domain in the processor system that is at the same level as the scheduling domain of the third-level cache and corresponds to the second-level cache, and to point the scheduling domain pointer of the processor system to the second-level cache scheduling domain.

[0059] Furthermore, when the configuration determination module 203 determines whether the sharing range of the third-level cache is greater than the sharing range of the second-level cache based on the respective cache configuration information of the second-level cache and the third-level cache, it is also used to:

[0060] Based on the cache configuration information of the second-level cache and the third-level cache, determine the cache number of each of the second-level cache and the third-level cache;

[0061] Based on the cache number, determine the number of cores contained in the processor core cluster to which each of the L2 cache and the L3 cache belongs;

[0062] If the number of cores in the processor core cluster to which the L3 cache belongs is greater than the number of cores in the processor core cluster to which the L2 cache belongs, and the L2 cache is a shared cache, then the sharing range of the L3 cache is greater than the sharing range of the L2 cache.

[0063] Furthermore, the device source file is an advanced configuration and power interface table or a device tree source file.

[0064] Furthermore, the startup module 201 is also used for:

[0065] Based on the processor system configured with the secondary cache scheduling domain, the operating system kernel completes the construction of the central processing unit topology.

[0066] The apparatus 200 for improving processor cache scheduling efficiency can implement the steps in the method for improving processor cache scheduling efficiency as described in the above embodiments, and can achieve the same technical effect. Refer to the description in the above embodiments, which will not be repeated here.

[0067] This invention also provides another device 300 for improving processor cache scheduling efficiency, please refer to... Figure 3 , Figure 3 This is a schematic diagram of the structure of an apparatus for improving processor cache scheduling efficiency provided in an embodiment of the present invention. The apparatus 300 for improving processor cache scheduling efficiency includes: a memory 302, a processor 301, and a computer program stored in the memory 302 and executable on the processor 301.

[0068] The processor 301 calls the computer program stored in the memory 302 to execute the steps in the method for improving processor cache scheduling efficiency provided in this embodiment of the invention. Please refer to... Figure 1 Specifically, it includes the following steps:

[0069] S101. Start the operating system kernel and obtain the device source file of the computer device before the operating system kernel builds the central processing unit topology.

[0070] In step S101, the device source file is an advanced configuration and power interface table or a device tree source file.

[0071] S102. Obtain the cache configuration information of the L2 cache and L3 cache of the processor system of the computer device according to the device source file.

[0072] S103. Based on the cache configuration information of the second-level cache and the third-level cache respectively, determine whether the sharing range of the third-level cache is greater than the sharing range of the second-level cache. If so, proceed to step S104.

[0073] In step S103, the step of determining whether the shared range of the third-level cache is greater than the shared range of the second-level cache based on the cache configuration information of the second-level cache and the third-level cache is as follows:

[0074] Based on the cache configuration information of the second-level cache and the third-level cache, determine the cache number of each of the second-level cache and the third-level cache;

[0075] Based on the cache number, determine the number of cores contained in the processor core cluster to which each of the L2 cache and the L3 cache belongs;

[0076] If the number of cores in the processor core cluster to which the L3 cache belongs is greater than the number of cores in the processor core cluster to which the L2 cache belongs, and the L2 cache is a shared cache, then the sharing range of the L3 cache is greater than the sharing range of the L2 cache.

[0077] S104. Add a second-level cache scheduling domain in the processor system that is at the same level as the scheduling domain of the third-level cache and corresponds to the second-level cache, and point the scheduling domain pointer of the processor system to the second-level cache scheduling domain.

[0078] The method further includes the following steps:

[0079] S105. Based on the processor system configured with the secondary cache scheduling domain, the operating system kernel completes the construction of the central processing unit topology.

[0080] The apparatus 300 for improving processor cache scheduling efficiency provided in this embodiment of the invention can implement the steps in the method for improving processor cache scheduling efficiency as described in the above embodiments, and can achieve the same technical effect. Refer to the description in the above embodiments, which will not be repeated here.

[0081] This invention also provides a storage medium storing a computer program. When the computer program is executed by a processor, it implements the various processes and steps in the method for improving processor cache scheduling efficiency provided in this invention, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0082] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware (such as a mobile phone, computer, server, air conditioner, or network device, etc.). The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0083] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0084] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form under the guidance of the present invention without departing from the spirit and scope of the claims. All such changes are within the protection scope of the present invention.

Claims

1. A method for improving processor cache scheduling efficiency, characterized in that, The method includes the following steps: S101. Start the operating system kernel and obtain the device source file of the computer device before the operating system kernel builds the central processing unit topology; S102. Obtain the cache configuration information of the L2 cache and L3 cache of the processor system of the computer device according to the device source file; S103. Based on the cache configuration information of the second-level cache and the third-level cache respectively, determine whether the sharing range of the third-level cache is greater than the sharing range of the second-level cache. If so, proceed to step S104. S104. Add a second-level cache scheduling domain in the processor system that is at the same level as the scheduling domain of the third-level cache and corresponds to the second-level cache, and point the scheduling domain pointer of the processor system to the second-level cache scheduling domain.

2. The method for improving processor cache scheduling efficiency according to claim 1, characterized in that, In step S103, the step of determining whether the shared range of the third-level cache is greater than the shared range of the second-level cache based on the cache configuration information of the second-level cache and the third-level cache is as follows: Based on the cache configuration information of the second-level cache and the third-level cache, determine the cache number of each of the second-level cache and the third-level cache; Based on the cache number, determine the number of cores contained in the processor core cluster to which each of the L2 cache and the L3 cache belongs; If the number of cores in the processor core cluster to which the L3 cache belongs is greater than the number of cores in the processor core cluster to which the L2 cache belongs, and the L2 cache is a shared cache, then the sharing range of the L3 cache is greater than the sharing range of the L2 cache.

3. The method for improving processor cache scheduling efficiency according to claim 1, characterized in that, In step S101, the device source file is an advanced configuration and power interface table or a device tree source file.

4. The method for improving processor cache scheduling efficiency according to claim 1, characterized in that, The method further includes the following steps: S105. Based on the processor system configured with the secondary cache scheduling domain, the operating system kernel completes the construction of the central processing unit topology.

5. An apparatus for improving processor cache scheduling efficiency, characterized in that, include: The startup module is used to start the operating system kernel and obtain the device source file of the computer device before the operating system kernel builds the central processing unit topology. The configuration information acquisition module is used to acquire the cache configuration information of the L2 cache and L3 cache of the processor system of the computer device according to the device source file; The configuration judgment module is used to determine whether the sharing range of the third-level cache is greater than the sharing range of the second-level cache based on the cache configuration information of the second-level cache and the third-level cache respectively. If so, the setting module is executed. The configuration module is used to add a second-level cache scheduling domain in the processor system that is at the same level as the scheduling domain of the third-level cache and corresponds to the second-level cache, and to point the scheduling domain pointer of the processor system to the second-level cache scheduling domain.

6. The apparatus for improving processor cache scheduling efficiency according to claim 5, characterized in that, When the configuration determination module determines whether the shared range of the third-level cache is greater than the shared range of the second-level cache based on the cache configuration information of the second-level cache and the third-level cache, it is further configured to: Based on the cache configuration information of the second-level cache and the third-level cache, determine the cache number of each of the second-level cache and the third-level cache; Based on the cache number, determine the number of cores contained in the processor core cluster to which each of the L2 cache and the L3 cache belongs; If the number of cores in the processor core cluster to which the L3 cache belongs is greater than the number of cores in the processor core cluster to which the L2 cache belongs, and the L2 cache is a shared cache, then the sharing range of the L3 cache is greater than the sharing range of the L2 cache.

7. The apparatus for improving processor cache scheduling efficiency according to claim 5, characterized in that, The device source file is either an advanced configuration and power interface table or a device tree source file.

8. The apparatus for improving processor cache scheduling efficiency according to claim 5, characterized in that, The startup module is also used for: Based on the processor system configured with the secondary cache scheduling domain, the operating system kernel completes the construction of the central processing unit topology.

9. An apparatus for improving processor cache scheduling efficiency, characterized in that, include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the steps of the method for improving processor cache scheduling efficiency as described in any one of claims 1-4.

10. A storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the steps of the method for improving processor cache scheduling efficiency as described in any one of claims 1-4.

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