SPI (Serial Peripheral Interface) communication system and method of slave without internal clock
By using the CS signal as the clock in the SPI communication system to generate the m_clk clock, the power consumption and rate limitation problems caused by the internal clock are solved, and low-power and high-efficiency SPI communication is achieved.
Patent Information
- Application Number
- CN202510852062.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-24
- Publication Date
- 2025-09-30
AI Technical Summary
Existing SPI slave modules require an internal clock when receiving and sending data, which results in unnecessary power consumption and limits the communication rate.
An SPI communication system without an internal clock is used in the slave. The CS signal is used as the clock. The m_clk clock is generated through the combination logic of CS and CLK to achieve data analysis and response, reducing the use of internal clocks.
The power consumption of the SPI slave module is reduced, the communication rate is increased, the circuit structure is simplified, and the transmission efficiency is increased.
Smart Images
Figure CN120723698A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of SPI communication, and in particular relates to an SPI communication system and method in which a slave machine has no internal clock. Background Art
[0002] SPI communication technology is a mature communication technology, on the basis of which various non-standard SPI communications have also been derived.
[0003] In the prior art, an SPI slave module receives data. After receiving a specific bit of data, the slave saves the corresponding bit-width data using an internal clock and parses the data. When an SPI slave module sends data, the slave module responds to the master module by reading the internal register using the internal clock and transmitting it via the SPI protocol.
[0004] It can be seen that the existing SPI slave module has an internal clock. After receiving the SPI command, the command data is transferred to the SPI internal clock domain for parsing. The parsed data is further processed. If data needs to be returned, the corresponding data is transferred from the SPI internal clock domain to the transmit shift register of the SPI communication clock domain.
[0005] When there is no command transmission on the SPI interface, the internal clock of the slave module cannot be turned off, and it is always waiting for the SPImaster module (host) to send commands to the internal clock of the slave module, which will generate unnecessary power consumption.
[0006] Since the slave needs to collect and parse SPI commands, its internal clock must be several times faster than the external clock. The faster the SPI communication rate, the higher the slave's internal clock frequency and the greater the power consumption. To reduce power consumption, you need to reduce the SPI communication rate. Summary of the Invention
[0007] The object of the present invention is to provide an SPI communication system with a slave having no internal clock, wherein the SPI slave module does not require an internal clock and can complete SPI parsing, processing and command response only through CS and CLK.
[0008] In order to achieve the above-mentioned purpose, the present invention adopts the following technical solutions:
[0009] An SPI communication system with a slave having no internal clock, comprising a master module and a slave module;
[0010] The slave module consists of the slave_inf module and the slave_reg module;
[0011] The slave_inf module is an interface module used to receive master data and convert the mosi serial data into shift_data parallel data; slave_reg is a register module;
[0012] Add a CS signal between the slave_inf module and the slave_reg module as the clock of the slave module, and use the rising edge of the CS signal as the clock for parsing shift_data after the SPI command is received.
[0013] The initial data initial value when the slave module is powered on and the response data response to the previous SPI command frame are assigned to shift_data through the m_clk clock generated by the combination logic of CS and CLK.
[0014] Preferably, the slave_reg module receives the shift_data data, uses CS as the clock, and parses the read, write, addr and data data contained in this SPI command from the shift_data parallel data at its rising edge.
[0015] If read is 1, the status data or register value of addr is assigned to rdata synchronously;
[0016] If write is 1, the wdata data is synchronously written to the register corresponding to addr.
[0017] Preferably, the slave_inf module is used to receive the initial data returned by the slave_reg module upon power-on and the response data frame for the last SPI command, and transmit them back to the master module via MISO;
[0018] The response data frame consists of read, write, addr and rdata.
[0019] Preferably, when the slave module performs the first SPI communication after being powered on, the slave module will send a fixed and unique data frame as the initial data frame. After receiving this data frame, the master will know that the slave is still in the initialization state.
[0020] In each subsequent SPI communication, the slave sends a response data frame to the last SPI command to the master through MISO.
[0021] In addition, based on the above-mentioned SPI communication system in which the slave has no internal clock, the present invention also proposes a corresponding SPI communication method in which the slave has no internal clock, which adopts the following scheme:
[0022] An SPI communication method without an internal clock of a slave device comprises the following steps:
[0023] When CS is low level, the master module sends mosi single bit data and the slave module sends miso single bit data at the rising edge of CLK. The master receives miso data and the slave receives mosi data at the falling edge of CLK.
[0024] Use CS and CLK to generate a clock m_clk. The clock m_clk is valid when CS is low and its level is opposite to that of CLK.
[0025] At the first rising edge of m_clk, the initial value or response to frame is assigned to shift_data, and the first falling edge of m_clk transfers the highest bit of shift_data to miso;
[0026] The second rising edge of m_clk shifts shift_data to the left, and receives mosi and assigns it to the lowest bit of shift_data; the second falling edge of m_clk transmits the highest bit of shift_data to miso;
[0027] Similarly, each subsequent rising edge of m_clk shifts shift_data to the left, receives mosi and assigns it to the lowest bit of shift_data, and each falling edge of m_clk transmits the highest bit of shift_data to miso;
[0028] The rising edge of CS parses shift_data, parses out read, write, addr, and data data, and executes the corresponding commands.
[0029] The present invention has the following advantages:
[0030] As described above, the present invention describes an SPI communication system and method for slave devices without an internal clock. In this system, the SPI slave module (slave) does not require an internal clock and can complete SPI parsing, processing, and command response using only CS and CLK. Specifically, the CS signal is used as the slave's clock, which has two functions: first, the rising edge of CS is used as the clock for parsing shift_data after SPI command reception is completed; second, the initial data (initial value) upon power-up of the slave module and the response data (response to frame) to the previous SPI command are assigned to shift_data using the m_clk clock generated by the CS and CLK combinational logic. During the active CS period, the bits transmitted by MOSI and MISO are all valid data. After power-on initialization, each bit transmitted by MISO is the response data for the previous SPI command. Since the slave module does not have an internal clock, its power consumption is reduced, and register reading and writing are controlled by CS as the clock. The SPI communication clock rate is not limited by the slave module's internal clock, but is determined by factors such as the chip manufacturing process, effectively improving the SPI communication rate. In addition, when the master sends a command, the slave module will transmit the response of the previous master command back to the master, increasing transmission efficiency. In addition, there is no cross-clock domain processing, the circuit is simple and has a wide range of applications. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 Schematic diagram of the structure of an SPI communication system in which the slave device has no internal clock according to an embodiment of the present invention;
[0032] Figure 2 This is a schematic diagram of the SPI communication method of the present invention;
[0033] Figure 3 Schematic diagram of SPI communication frame in an embodiment of the present invention;
[0034] Figure 4 Schematic diagram of the m_clk clock generated by the combination logic of CS and CLK in an embodiment of the present invention;
[0035] Figure 5 Schematic diagram of internal data processing of the slave module in an embodiment of the present invention. DETAILED DESCRIPTION
[0036] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
[0037] Example 1
[0038] like Figure 1As shown, this embodiment 1 describes an SPI communication system in which the slave has no internal clock, which includes a master module (i.e., a host) and a slave module (i.e., a slave). The SPI communication method of the present invention is as follows Figure 2 shown.
[0039] After CS is pulled low, the master sends mosi single-bit data and the slave sends miso single-bit data on the rising edge of CLK. The master receives miso data and the slave receives mosi data on the falling edge of CLK.
[0040] After CS rises, SPI communication ends and the slave module parses the SPI data.
[0041] In this embodiment, there is no clock inside the slave module, and the operation of the internal registers is completely changed by the master.
[0042] Specifically, the slave module consists of the slave_inf module and the slave_reg module.
[0043] The slave_inf module is an interface module that receives data from the master. It is not much different from the master-side interface and other spi_slave modules. The slave register interface has an additional CS signal that serves as the clock of slave_reg.
[0044] slave_reg is a register module. SPI communication uses the second level change of CS (i.e., the level change at the end of communication) as a storage register and transfers the response data to addr and rdata.
[0045] Unlike the slave, which has an internal clock and synchronizes the data shift_data received by the interface module and stores it in the register after the second level change of CS, the second level change edge of CS in the present invention is the clock for processing data. This clock edge triggers the storage register and prepares the read, write, addr and rdata actions.
[0046] The slave_inf module is used to receive SPI commands and convert the serial data of mosi into shift_data parallel data.
[0047] Add a CS signal between the slave_inf module and the slave_reg module as the clock of the slave module, such as Figure 1 As shown in the figure, the rising edge of the CS signal is used as the clock for parsing shift_data after the SPI command reception is completed.
[0048] The slave_reg module receives the shift_data data and uses CS as the clock. At its rising edge, it parses the read, write, addr, and data data contained in this SPI command from the shift_data parallel data.
[0049] In addition, the initial data initial value when the slave module is powered on and the response data response to the last SPI command response to frame are assigned to shift_data through the m_clk clock generated by the combination logic of CS and CLK.
[0050] The slave_inf module receives the read, write, addr, and rdata signals returned by the slave_reg module and transmits them back to the master device via the MISO port. During the first CS communication, read, write, addr, and rdata have initial values. The second and subsequent SPI communications are response frames to the previous SPI command and are transmitted back to the master module via MISO.
[0051] The response data frame consists of read, write, addr and rdata.
[0052] The slave_reg module receives the shift_data data and uses cs as the clock. On its rising edge (the second clock change indicates the end of SPI communication), it parses the read, write, addr, and data data of the current SPI command from the shift_data parallel data. If read is 1, the status data or register value of addr is synchronously assigned to rdata. If write is 1, the wdata data is synchronously written to the register corresponding to addr.
[0053] When the present invention receives and sends data through the slave module, it is not necessary to store or read register data through the internal clock.
[0054] When CS is low, the slave_inf module sends each bit of the data frame to the master in sequence on the rising edge of SPI CLK. On the falling edge, the slave_inf module receives each bit of the data sent by the master and assembles a complete frame.
[0055] A complete frame contains the following:
[0056] 1 bit is write enable, 1 bit is read enable, several bits are register address addr, and 8 bits are register data wdata.
[0057] Use the rising edge of CS as the storage data clock:
[0058] If the receive frame write enable bit is 1, write the corresponding address register data;
[0059] If the receive frame read enable is 1, the address and its corresponding register or status data are passed to the transmit data frame register and sent to the master through the rising edge of CLK during the next SPI communication;
[0060] If the read enable is 0, clear the send address addr and send data rdata of the slave_reg module.
[0061] At the falling edge of CS, the slave_inf module combines the read, write, and addr data parsed from the previous frame command and the rdata data required to be fed back from the previous frame command into a return frame and transmits it back to the master module through MISO.
[0062] like Figure 3 A schematic diagram of the SPI communication frame of the present invention is shown.
[0063] During the first SPI communication after the slave module is powered on, it sends a fixed and unique data frame as the initial data frame. After receiving this data frame, the master knows that the slave is still in the initialization state. If the data received by the master is not the initial data frame, the master can understand the working status or register data of the slave module by parsing the frame.
[0064] In each subsequent SPI communication, the slave sends a response data frame to the last SPI command to the master through MISO.
[0065] For example, the first SPI communication miso sends the initial data initial value when power is turned on, and the second SPI communication miso sends the response data frame response to frame 1 of the first command. Similarly, the third SPI communication miso sends the response data frame response to frame 2 of the second command, and so on. Figure 3 shown.
[0066] The SPI communication system in this embodiment in which the slave device has no internal clock is applicable to an intelligent power switch chip.
[0067] Example 2
[0068] like Figure 4 and Figure 5As shown, this embodiment describes an SPI communication method in which a slave has no internal clock. The method is implemented based on the SPI communication system in which a slave has no internal clock in the above-mentioned embodiment 1.
[0069] An SPI communication method without an internal clock of a slave device comprises the following steps:
[0070] When CS is active low, the master module sends mosi single-bit data at the rising edge of CLK, and the slave module sends miso single-bit data. At the falling edge of CLK, the master receives miso data, and the slave receives mosi data.
[0071] like Figure 4 As shown in the figure, in order to assign the initial data initial value when the slave module is powered on and the response data response to frame of the last SPI command to shift_data, CS and CLK are used to generate a clock m_clk (a clock that is generated only when CS is valid). The clock m_clk is valid when CS is low, and its level is opposite to that of CLK.
[0072] When m_clk first rises (ie, CS falls), assign the initial value or response to frame to shift_data (such as Figure 4 The first falling edge of m_clk (i.e. the first rising edge of CLK) will transfer the highest bit of shift_data to miso (as shown in the center line 0). Figure 4 midline 1).
[0073] like Figure 5 As shown, the second rising edge of m_clk (i.e. the first falling edge of CLK) shifts shift_data to the left (as shown in Figure 4 The second falling edge of m_clk (that is, the second rising edge of CLK) will transmit the highest bit of shift_data to miso.
[0074] Similarly, each subsequent rise of m_clk (i.e. Figure 5 The 3rd to 17th rising edges of m_clk (i.e. the 2nd to 16th falling edges of CLK) shift_data to the left, and receive mosi and assign it to the lowest bit of shift_data, and each falling edge of m_clk transmits the highest bit of shift_data to miso.
[0075] CS rising edge (such as Figure 4As shown in the center line 3, it is used as the clock for parsing shift_data after the SPI command is received. Analyze shift_data, parse out read, write, addr, and data data, and execute the corresponding command.
[0076] Among them, read, write, addr and the register data corresponding to addr serve as the corresponding data response to frame sent back by the slave module to the host master module during the next SPI communication.
[0077] The initial value is the initial data when the slave module is powered on. When the master receives the initial value, it knows that no operation has been performed on the module. The response frame is the response data frame of the last CS command.
[0078] exist Figure 5 The data_in data shown in represents the initial value or response to frame.
[0079] In this embodiment, CLK can be initially high or low. As long as the falling edge of CS is used to receive data_in (initial value or response to frame) and the rising edge of CS is used as the clock for parsing shift_data, it falls within the scope of the present invention.
[0080] Of course, the above description is only a preferred embodiment of the present invention, and the present invention is not limited to the above-mentioned embodiments. It should be noted that all equivalent substitutions and obvious deformation forms made by any technician familiar with this field under the guidance of this specification fall within the substantive scope of this specification and should be protected by the present invention.
Claims
1. An SPI communication system without an internal clock in a slave device, comprising a master module and a slave module; characterized in that: The slave module consists of the slave_inf module and the slave_reg module; the slave_inf module is an interface module that receives master data and converts the mosi serial data into shift_data parallel data; the slave_reg is a register module; Add a CS signal between the slave_inf module and the slave_reg module as the clock of the slave module, and use the rising edge of the CS signal as the clock for parsing shift_data after the SPI command is received. The initial data initial value when the slave module is powered on and the response data response to the previous SPI command response to frame are assigned to shift_data through the m_clk clock generated by the combination logic of CS and CLK.
2. The SPI communication system with no internal clock of the slave according to claim 1, characterized in that: The slave_reg module receives the shift_data data and uses CS as the clock. At its rising edge, it parses the read, write, addr and data data contained in this SPI command from the shift_data parallel data.
3. The SPI communication system with no internal clock of the slave according to claim 2, characterized in that: If read is 1, the status data or register value of addr is assigned to rdata synchronously; If write is 1, the wdata data is synchronously written to the register corresponding to addr.
4. The SPI communication system with no internal clock of the slave according to claim 1, wherein: The slave_inf module is used to receive the initial data returned by the slave_reg module at power-on and the response data frame for the last SPI command, and transmit it back to the master module via MISO; The response data frame consists of read, write, addr and rdata.
5. The SPI communication system with no internal clock of the slave according to claim 1, characterized in that: When the slave module is powered on and performs the first SPI communication, the slave module will send a fixed and unique data frame as the initial data frame. After receiving this data frame, the master will know that the slave is still in the initialization state. In each subsequent SPI communication, the slave sends a response data frame to the last SPI command to the master through MISO.
6. A SPI communication method with a slave having no internal clock, based on the SPI communication system with a slave having no internal clock according to any one of claims 1 to 5; characterized in that: The SPI communication method comprises the following steps: When CS is low level, the master module sends mosi single bit data and the slave module sends miso single bit data at the rising edge of CLK. The master receives miso data and the slave receives mosi data at the falling edge of CLK. Use CS and CLK to generate a clock m_clk. The clock m_clk is valid when CS is low and its level is opposite to that of CLK. At the first rising edge of m_clk, the initial value or response to frame is assigned to shift_data, and the first falling edge of m_clk transfers the highest bit of shift_data to miso; The second rising edge of m_clk shifts shift_data to the left, and receives mosi and assigns it to the lowest bit of shift_data; the second falling edge of m_clk transmits the highest bit of shift_data to miso; Similarly, each subsequent rising edge of m_clk shifts shift_data to the left, receives mosi and assigns it to the lowest bit of shift_data, and each falling edge of m_clk transmits the highest bit of shift_data to miso; The rising edge of CS parses shift_data, parses out read, write, addr, and data data, and executes the corresponding commands.