Pixelization matching circuit design and optimization method based on large language model

Abstract

The invention discloses a pixelated matching circuit design and optimization method based on a large language model, and relates to the technical field of radio frequency circuits, and the method comprises the steps: obtaining a target demand and a physical constraint of a matching circuit; generating an initial topological structure based on the target demand and the physical constraint, and performing parameter estimation on the initial topological structure to obtain an initial binary matrix constrained by the initial topological structure and the parameter; obtaining an optimization problem based on the initial binary matrix and the target demand; wherein the optimization problem comprises distribution of optimization parameters, optimization objectives and solution spaces; and obtaining a key performance index and an optimization algorithm according to the optimization problem, and carrying out iterative search in the optimization algorithm according to the key performance index to obtain an optimal solution for solving the optimization problem so as to generate an optimal pixelated topology. According to the method, the optimal pixelated topology can be generated, and efficient global optimization is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency circuit design, and in particular to a pixelated matching circuit design and optimization method based on a large language model. Background Art

[0002] With the increasing popularity of RF communications, the demand for multi-band and broadband wireless communication systems has placed unprecedented performance demands on power amplifiers (PAs). However, in CMOS processes, known for their low cost and high integration, PA design, particularly the core matching circuit design, faces severe challenges. Currently, PA design lacks innovation in topology. Designers tend to optimize within classic frameworks such as cascode. While reliable, this approach struggles to push the performance limits required for cutting-edge applications. Furthermore, matching circuit design is a complex multi-objective optimization problem. Achieving the optimal balance between output power, efficiency, linearity, gain, and stability typically requires a time-consuming and labor-intensive manual iterative process that relies heavily on the designer's personal experience and intuition.

[0003] The design of matching circuits primarily relies on the designer's personal experience and knowledge, but this experience is often implicit and difficult to quantify, making the design process less than a precisely replicable engineering science. Therefore, in order to seek more optimal matching circuit design and optimization methods, computational intelligence has been employed to achieve these designs. For example, the method proposed in the paper "Deep-Learning-Based Inverse-Designed Millimeter-Wave Passives and Power Amplifiers" treats the physical layout of the matching circuit as a pixelated grid. A machine learning algorithm determines whether each pixel should be filled with a conductor or left blank, thereby designing a new circuit topology. This algorithm optimizes a binary matrix representing the topology and uses expensive full electromagnetic simulation results as performance feedback, attempting to search for the optimal solution within a vast solution space. While this approach can optimize the matching circuit design process to a certain extent, it is costly, time-consuming, and inefficient, and does not achieve truly efficient global optimization.

[0004] In the process of implementing the present invention, the inventors discovered that the prior art has at least the following problems: Existing matching circuit design and optimization methods have not achieved true efficient global optimization. Summary of the Invention

[0005] The purpose of the present invention is to provide a pixelated matching circuit design and optimization method based on a large language model to solve the technical problem in the prior art that the matching circuit design and optimization method do not achieve true efficient global optimization.

[0006] The various technical effects that can be produced by the preferred technical solutions among the various technical solutions provided by the present invention are described in detail below.

[0007] To achieve the above objectives, the present invention provides the following technical solutions: In a first aspect, the present invention provides a pixelated matching circuit design and optimization method based on a large language model, comprising: Obtain target requirements and physical constraints for matching circuits; generating an initial topology structure based on the target requirements and the physical constraints, and performing parameter estimation on the initial topology structure to obtain an initial binary matrix constrained by the initial topology structure and the parameters; Obtaining an optimization problem based on the initial binary matrix and the target requirement; wherein the optimization problem includes optimization parameters, optimization targets, and distribution of solution space; A key performance indicator and an optimization algorithm are obtained according to the optimization problem, and an optimal solution to the optimization problem is obtained by iteratively searching in the optimization algorithm according to the key performance indicator, so as to generate an optimal pixelated topology.

[0008] Optionally, obtaining an optimization problem based on the initial binary matrix and the target requirement includes: Analyzing the initial binary matrix to identify unfixed pixels in the initial binary matrix, and obtaining the optimization parameters based on the unfixed pixels; Analyzing the target requirements to obtain the optimization target; The optimization parameters and optimization objectives are analyzed to confirm the distribution of the solution space.

[0009] Optionally, obtaining a key performance indicator and an optimization algorithm according to the optimization problem, and iteratively searching in the optimization algorithm according to the key performance indicator to obtain an optimal solution to the optimization problem to generate an optimal pixelated topology includes: Determining properties of the optimization problem and selecting an optimization algorithm based on the properties of the optimization problem; Based on the impedance matching circuit and electromagnetic topology structure generated in the optimization target and corresponding to the target requirement, confirming the physical size parameters required for the impedance matching circuit and the electromagnetic topology structure; Performing simulation analysis on the physical size parameters to obtain key performance indicators corresponding to the physical size parameters; An iterative search is performed in the optimization algorithm according to the key performance indicators to obtain an optimal solution to the optimization problem, so as to generate an optimal pixelated topology.

[0010] Optionally, confirming the properties of the optimization problem includes: Confirm whether the attribute of the optimization parameter is a high-dimensional discrete variable space; confirming the number of the optimization objectives; Determine whether the distribution of the solution space is a sparse space.

[0011] Optionally, generating an initial topology structure based on the target requirement and the physical constraint, and performing parameter estimation on the initial topology structure to obtain an initial binary matrix constrained by the initial topology structure and the parameters includes: The large language model generates an initial topology structure based on the target requirements and the physical constraints; Performing parameter estimation on the initial topological structure to obtain key physical parameters; An initial binary matrix based on the initial topological structure and the key physical parameter constraints.

[0012] Optionally, obtaining target requirements and physical constraints of the matching circuit includes: Performing simulation analysis on the matching circuit to obtain simulation results, and confirming target requirements of the matching circuit based on the simulation results; The area of ​​the matching circuit and the metal layer where the matching circuit is located are determined to obtain physical constraints of the matching circuit.

[0013] Optionally, in the simulation analysis of the matching circuit to obtain simulation results, and confirming the target requirements of the matching circuit based on the simulation results, the simulation analysis includes load pull simulation analysis and source pull simulation analysis, and the target requirements include input matching network targets, output matching network targets, key performance indicators and passive device constraints.

[0014] In a second aspect, the present invention further provides a pixelated matching circuit design and optimization processing device based on a large language model, comprising: Obtain modules to obtain target requirements and physical constraints of matching circuits; A generation module generates an initial topology structure based on the target requirements and the physical constraints, and performs parameter estimation on the initial topology structure to obtain an initial binary matrix constrained by the initial topology structure and the parameters; A confirmation module, which obtains an optimization problem based on the initial binary matrix and the target requirement; wherein the optimization problem includes optimization parameters, optimization objectives and distribution of solution space; An optimization module obtains a key performance indicator and an optimization algorithm according to the optimization problem, and iteratively searches in the optimization algorithm according to the key performance indicator to obtain an optimal solution to the optimization problem, so as to generate an optimal pixelated topology.

[0015] In a third aspect, the present invention further provides a terminal device, comprising: one or more processors and memory; In which, the memory is used to store one or more computer programs, and the one or more processors are used to execute one or more computer programs stored in the memory, so that the processor performs the steps of the pixelated matching circuit design and optimization method based on the large language model as described above.

[0016] In a fourth aspect, the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, the steps of the pixelated matching circuit design and optimization method based on the large language model as described above are implemented.

[0017] Implementing one of the above technical solutions of the present invention has the following advantages or beneficial effects: In this invention, the large language model first obtains the matching circuit's target requirements and physical constraints. Based on these requirements and physical constraints, it then generates an initial topology and performs parameter estimation on this initial topology, obtaining an initial binary matrix constrained by the initial topology and parameters. In subsequent optimization processes, this initial binary matrix serves as the starting point for the optimization algorithm, avoiding blind or random searches.

[0018] Then, an optimization problem is obtained based on the initial binary matrix and the target requirements, wherein the optimization problem includes the distribution of optimization parameters, optimization targets and solution space. Finally, key performance indicators and optimization algorithms are obtained according to the optimization problem, and an iterative search is performed in the optimization algorithm according to the key performance indicators to obtain the optimal solution to the optimization problem, so as to generate the optimal pixelated topology. The large language model in this embodiment generates an initial binary matrix according to the target requirements and physical constraints of the matching circuit, providing a high-quality initial starting point for the subsequent optimization design, saving operation time and improving efficiency. Subsequently, key performance indicators are determined according to the optimization problem, and a suitable optimization algorithm is selected. Finally, the optimization algorithm is continuously iterated according to the key performance indicators to obtain the optimal solution to the optimization problem, so as to generate the optimal pixelated topology and achieve efficient global optimization. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive work. In the drawings: Figure 1 1 is a flow chart of a method for designing and optimizing a pixelated matching circuit based on a large language model according to a first embodiment of the present invention; Figure 2 1 is a flow chart of step S20 in the method for designing and optimizing a pixelated matching circuit based on a large language model according to the first embodiment of the present invention; Figure 3 4 is a flow chart of step S40 in the method for designing and optimizing a pixelated matching circuit based on a large language model according to the first embodiment of the present invention; Figure 4 2 is a schematic structural diagram of a pixelated matching circuit design and optimization processing device based on a large language model according to a second embodiment of the present invention; Figure 5 It is a structural diagram of the terminal device of embodiment 3 of the present invention. DETAILED DESCRIPTION

[0020] In order to make the objects, technical solutions and advantages of the present invention clearer, the various exemplary embodiments to be described below will refer to the corresponding drawings, which constitute a part of the exemplary embodiments, in which various exemplary embodiments that may be used to implement the present invention are described. Unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation methods described in the following exemplary embodiments do not represent all implementation methods consistent with the present disclosure. It should be understood that they are only examples of processes, methods and devices that are consistent with some aspects of the present disclosure as detailed in the appended claims, and other embodiments may also be used, or structural and functional modifications may be made to the embodiments listed herein without departing from the scope and essence of the present invention.

[0021] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "transverse", etc. indicate the orientation or position relationship based on the drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the elements referred to must have a specific orientation, be constructed and operate in a specific orientation. The terms "first", "second", etc. are only used for descriptive purposes and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. The term "plurality" means two or more. The terms "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, an integral connection, a mechanical connection, an electrical connection, a communication connection, a direct connection, an indirect connection through an intermediate medium, and can be the internal connection of two elements or the interaction relationship between two elements. The term "and / or" includes any and all combinations of one or more related listed items. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0022] In order to illustrate the technical solution of the present invention, a specific embodiment is provided below, in which only the parts related to the embodiment of the present invention are shown.

[0023] Example 1: like Figure 1 As shown, the present invention provides a pixel matching circuit design and optimization method based on a large language model, including: S10, obtaining target requirements and physical constraints of the matching circuit; S20, generating an initial topology structure based on target requirements and physical constraints, performing parameter estimation on the initial topology structure, and obtaining an initial binary matrix constrained by the initial topology structure and the parameters; S30, obtaining an optimization problem based on the initial binary matrix and the target requirement; wherein the optimization problem includes the distribution of optimization parameters, optimization targets, and solution space; S40, obtaining a key performance indicator and an optimization algorithm according to the optimization problem, iteratively searching in the optimization algorithm according to the key performance indicator, obtaining an optimal solution to the optimization problem, and generating an optimal pixelated topology.

[0024] In this embodiment, the overall steps are implemented within a large language model (LLM). The LLM first obtains the matching circuit's target requirements and physical constraints. Based on these requirements and physical constraints, it then generates an initial topology and performs parameter estimation on this initial topology, obtaining an initial binary matrix constrained by the initial topology and parameters. In subsequent optimization processes, this initial binary matrix serves as the starting point for the optimization algorithm, avoiding blind or random searches.

[0025] Then, an optimization problem is obtained based on the initial binary matrix and the target requirements, wherein the optimization problem includes the distribution of optimization parameters, optimization targets and solution space. Finally, key performance indicators and optimization algorithms are obtained according to the optimization problem, and an iterative search is performed in the optimization algorithm according to the key performance indicators to obtain the optimal solution to the optimization problem, so as to generate the optimal pixelated topology. The large language model in this embodiment generates an initial binary matrix according to the target requirements and physical constraints of the matching circuit, providing a high-quality initial starting point for the subsequent optimization design, saving operation time and improving efficiency. Subsequently, key performance indicators are determined according to the optimization problem, and a suitable optimization algorithm is selected. Finally, the optimization algorithm is continuously iterated according to the key performance indicators to obtain the optimal solution to the optimization problem, so as to generate the optimal pixelated topology and achieve efficient global optimization.

[0026] Next, we will combine Figure 1 The pixel matching circuit design and optimization method based on the large language model of this embodiment are described in detail.

[0027] First, execute step S10 to obtain the target requirements and physical constraints of the matching circuit. Specifically, obtaining the target requirements and physical constraints of the matching circuit includes the following steps: performing simulation analysis on the matching circuit to obtain simulation results, and confirming the target requirements of the matching circuit based on the simulation results; determining the area of ​​the matching circuit and the metal layer on which the matching circuit is located, and obtaining the physical constraints of the matching circuit. In this embodiment, a CMOS PA operating in the 28-34 GHz range is used as an example.

[0028] The matching circuit's target requirements are determined by performing load-pull and source-pull simulations on the matching circuit to determine its optimal performance at the target operating frequency and power level. Specifically, load-pull simulations are used to determine the optimal load impedance, while source-pull simulations are used to determine the optimal source impedance. By combining these two simulations, the matching circuit can achieve optimal performance at the set frequency and power. Then, based on the simulation results, the target requirements that the matching circuit needs to achieve are confirmed.

[0029] In this embodiment, the target requirements specifically include input matching network targets, output matching network targets, key performance indicators, and passive device constraints.

[0030] For the input matching network target, in order to achieve maximum power transfer, the input impedance of the input matching network target should be Should be the PA die input impedance It follows the maximum power transfer theorem that when the load impedance and the signal source impedance are conjugate complex numbers of each other (i.e., the resistance parts are equal, the reactance parts are equal in value and opposite in sign), the signal source can transmit the maximum theoretical power to the load, thereby improving the energy conversion efficiency and output power performance of the power amplifier.

[0031] For the output matching network target, the output port impedance The system standard impedance (usually 50Ω) should be transformed into the optimal load impedance of the PA die at the maximum gain, power or efficiency point. Its essence is to achieve impedance matching, ensuring that signal energy is efficiently transmitted from the die to subsequent systems, while ensuring that the PA operates at the preset optimal performance point.

[0032] The key performance indicators include the maximum gain (MaxGain) within a specific frequency band, output power ( ), power added efficiency (PAE) and out-of-band rejection. When optimizing the matching circuit, it is necessary to clearly define the target performance to be optimized. The maximum gain (MaxGain) is the upper limit of the system's ability to amplify the input signal within a specific frequency band. Output power ( ) refers to the signal power that the system can provide at the output. Power-added efficiency (PAE) measures the system's ability to convert DC input power into RF output power. Out-of-band rejection refers to the ability to attenuate unwanted signals outside the target frequency band, ensuring that the system operates with minimal interference in other frequency bands.

[0033] Passive component constraints mean setting targets or constraints, such as inductor values ​​or quality factors, for designs that include specific inductor or capacitor structures (e.g., transformers). These constraints ensure that passive components match overall system performance, preventing circuit performance degradation due to substandard component parameters.

[0034] In addition, load-pull simulation is also required for the matching circuit. Load-pull simulation systematically changes the load impedance and measures key parameters such as the output power, efficiency, and gain of the circuit under different load conditions, so as to find the optimal load impedance point and guide the design and optimization of the matching circuit.

[0035] Based on the above simulation results, the target requirements of the matching circuit can be confirmed, providing specific design parameters for the subsequent matching circuit design.

[0036] Furthermore, step S10 requires obtaining the physical constraints of the matching circuit, determining the matching circuit area and the metal layer on which the matching circuit resides, and obtaining the physical constraints of the matching circuit. These physical constraints ensure that the matching circuit meets the required electrical performance and the manufacturability of the design. Subsequent layout and routing of the matching circuit can be more targeted to ensure the feasibility and reliability of the final design.

[0037] Then, step S20 is executed to generate an initial topology structure based on the target requirements and physical constraints, and to perform parameter estimation on the initial topology structure to obtain an initial binary matrix constrained by the initial topology structure and the parameters. Figure 2 As shown, the specific steps include: S21, the large language model generates an initial topology structure based on target requirements and physical constraints; S22, the parameters of the initial topology structure are estimated to obtain key physical parameters; S23, the initial binary matrix is ​​based on the initial topology structure and the key physical parameter constraints.

[0038] Specifically, the large language model uses its knowledge base to generate an initial topology based on target requirements and physical constraints. This initial topology is a classic one (such as a transformer or LC matching network), which describes the connection method and layout framework of each component.

[0039] The large language model then infers key physical parameters of the recommended initial topology, such as the transformer's line width W, number of turns N, and spacing D. Line width W defines the unit size of the pixelated grid. The number of turns N and the topology can be configured by presetting a portion of pixels fixed to 1 in a binary matrix to form a topological skeleton (e.g., an overpass structure). Spacing D can be configured by presetting a portion of pixels fixed to 0 in the binary matrix to form isolation zones between windings.

[0040] Finally, the initial binary matrix is ​​constructed based on the initial topology and key physical parameters. The initial topology and key physical parameters are used as constraints to construct the initial binary matrix. It should be noted that the initial binary matrix is ​​a grid of pixels consisting of 0s and 1s.

[0041] It should be noted that step S20 combines the corresponding parameters of the target requirements and physical constraints to generate an initial binary matrix that conforms to engineering experience through a large language model. The generated initial binary matrix will serve as the starting point of the subsequent optimization algorithm. It is not a blind or random search, and provides a reliable foundation for subsequent optimization.

[0042] Then, step S30 is executed to obtain an optimization problem based on the initial binary matrix and the target requirement; wherein the optimization problem includes optimization parameters, optimization objectives, and the distribution of the solution space. In this embodiment, obtaining the optimization problem based on the initial binary matrix and the target requirement includes: analyzing the initial binary matrix, identifying unfixed pixels in the initial binary matrix, and obtaining optimization parameters based on the unfixed pixels; analyzing the target requirement to obtain the optimization objective; and analyzing the optimization parameters and optimization objective to confirm the distribution of the solution space.

[0043] Specifically, the optimization parameters are obtained by analyzing the initial binary matrix. Since the initial binary matrix is ​​a grid of pixels consisting of 0s and 1s, the unfixed pixels represent areas that can be adjusted in the matching circuit design. By analyzing the unfixed pixels, we can understand their potential role and impact on the entire circuit design. For example, some unfixed pixels may be located on critical signal transmission paths, and their adjustment may directly affect the performance of the circuit. Other unfixed pixels may be located in more marginal or non-critical areas, and their impact on circuit performance is relatively small.

[0044] The optimization goal is obtained by analyzing the target requirements. The target requirements include input matching network targets, output matching network targets, key performance indicators and passive device constraints. Among them, the input matching network target involves the impedance matching of the signal source, ensuring that the signal source can effectively transfer power to the matching circuit and reduce reflection and loss. The output matching network target focuses on the impedance matching at the load end to maximize the power transmission efficiency and signal quality at the load end. Key performance indicators include the maximum gain (MaxGain) within a specific frequency band, output power ( ), power added efficiency (PAE), and out-of-band rejection, which directly reflect the performance of the matching circuit. Passive component constraints refer to the actual physical limitations that need to be considered during the design process, such as the size, capacitance, and inductance range of passive components such as capacitors and inductors, as well as their layout and interconnection requirements. By analyzing the target requirements, the optimization goal can be determined.

[0045] More specifically, the optimization goal is to minimize multiple , refers to the difference between the actual performance index and the true performance index. For the optimization goal, the optimization goal is the core of the optimization problem and guides the subsequent optimization process.

[0046] In this embodiment, it is also necessary to analyze the optimization parameters and optimization objectives to confirm the distribution of the solution space. Specifically, confirming the distribution of the solution space is based on the analysis of the designer's experience. Confirming the distribution of the solution space is to understand all possible parameter combinations and their corresponding performance, and the set of all possible solutions to a specific problem. Here, it is necessary to confirm whether the solution space is a sparse space. Sparse space means that effective or feasible solutions account for a low proportion in the entire solution space, and most solutions are not feasible or of poor quality. Therefore, designers need to use professional knowledge and experience to narrow the search scope and improve design efficiency. It should be noted that confirming the distribution of the solution space is a more important part of obtaining the optimization problem, which directly affects the accuracy and efficiency of subsequent design.

[0047] Finally, step S40 is executed to obtain the key performance indicators and optimization algorithm according to the optimization problem, and iteratively search in the optimization algorithm according to the key performance indicators to obtain the optimal solution to the optimization problem, so as to generate the optimal pixelated topology. Figure 3As shown, it specifically includes the following steps: S41, confirming the properties of the optimization problem, and selecting an optimization algorithm based on the properties of the optimization problem; S42, generating an impedance matching circuit and an electromagnetic topology structure corresponding to the target requirements based on the optimization target, and confirming the physical size parameters required for the impedance matching circuit and the electromagnetic topology structure; S43, performing simulation analysis on the physical size parameters to obtain the key performance indicators corresponding to the physical size parameters; S44, performing iterative search in the optimization algorithm based on the key performance indicators to obtain the optimal solution to the optimization problem, so as to generate the optimal pixelated topology.

[0048] Specifically, when executing step S40, the properties of the optimization problem must first be determined. For the optimization parameters, it is necessary to determine whether they are high-dimensional. For the optimization objectives, it is necessary to determine how many optimization objectives there are and whether they are multi-objective. For the distribution of the solution space, it is necessary to confirm whether it is sparse. After confirming the properties of the optimization problem, the large language model will select the appropriate optimization algorithm based on the properties of the optimization problem.

[0049] The large language model then generates the impedance matching circuit and electromagnetic topology corresponding to the target requirements based on the optimization goal, and determines the physical size parameters required for the impedance matching circuit and electromagnetic topology. The large language model uses its internal knowledge base on microwave electrical design to generate the physical size parameters for the impedance matching circuit and electromagnetic topology corresponding to the target requirements.

[0050] Subsequently, the physical dimension parameters are simulated and analyzed to derive the key performance indicators corresponding to them. Prior to this, the physical dimension parameters must be passed into a script template, where a new simulation-capable script is generated. The generated new script is then transferred to a simulation automation packager, which launches the simulation software, executes the script, and automatically parses the simulation log or output file to extract key performance indicators. In this embodiment, the simulation software includes ADS and Cadence Virtuoso, and key performance indicators include S-parameters, gain, efficiency, and so on.

[0051] Finally, an iterative search is performed in the optimization algorithm based on the key performance indicators to obtain the optimal solution to the optimization problem and generate the optimal pixelated topology.

[0052] Specifically, this embodiment establishes an interactive interface between an automated process and a large language model. The automated process converts the knowledge and experience described in natural language provided by the large language model into a machine-readable scripting language. The automated process includes a simulator and a compiler.

[0053] In this embodiment, the automated process receives the key performance indicators and the selected optimization algorithm from the large language model, and then the simulator executes the simulation task corresponding to the key performance indicators. The compiler compares the key performance indicators with the optimization goals to determine whether the design parameters need to be adjusted. If adjustment is required, the compiler will generate new design parameters and pass them to the large language model through the interactive interface. The large language model generates a new design scheme again based on these new parameters, and loops this process until the optimal solution that meets the optimization goals is found. In this process, the close collaboration between the automated process and the large language model realizes the rapid iteration and optimization of the design parameters, greatly improving the efficiency and accuracy of the pixelated matching circuit design and optimization. Ultimately, the optimal pixelated topology obtained not only meets the performance indicator requirements, but also has advantages in terms of cost, volume, etc., providing strong support for practical applications.

[0054] Below, a COMS PA operating at 28-34 GHz is used as an example.

[0055] First, execute step S10 to perform a load-pull simulation on the CMOS PA to determine that the input and output impedance values ​​of the input matching circuit at the target output power are: (45 + j*9) Ω, (6 + j*60) Ω, respectively; the input and output impedance values ​​of the inter-stage matching circuit are: (11 + j*19) Ω, (30 + j*13) Ω, respectively; and the input and output impedance values ​​of the output matching circuit are: (6.2 + j*35) Ω, (45 + j*9) Ω, respectively. Therefore, the core goal determined in step S10 is to design three passive networks at the 28-34 GHz frequency point to meet the target impedance requirements of the circuit for the six ports.

[0056] Then, step S20 is executed, where the large language model generates an initial topology structure based on target requirements and physical constraints, and performs parameter estimation on the initial topology structure to obtain an initial binary matrix constrained by the initial topology structure and the parameters.

[0057] Here, the specific instructions for the large language model are: Design an output matching network for a 28-34 GHz PA. The input and output impedance values ​​of the input matching circuit are (45 + j * 9) Ω and (6 + j * 60) Ω, respectively. The matching circuit is based on a 65nm CMOS process and distributed across the M8 and M9 layers. Please fully utilize the internal microwave circuit design knowledge base to recommend one or more classic starting topologies, such as transformers and LC networks, and estimate the key physical parameters of the recommended topologies.

[0058] After analyzing the large language model, a differential transformer structure was recommended. Key initial parameters were estimated: line width W = 12μm for the M8 layer, number of turns N = 1 for the M8 layer, line width W = 10μm for the M9 layer, and number of turns N = 2 for the M9 layer. Based on these parameters, the pixelated grid cell size for the M8 layer was defined as 12μm x 12μm, and the pixelated grid cell size for the M9 layer was defined as 10μm x 10μm. On an area of ​​120μm x 150μm, an initial binary matrix of 10x6 was formed for the M8 layer, and a 12x8 matrix was formed for the M9 layer. Based on the basic form of a two-turn transformer, an overpass structure was pre-defined between the primary and secondary coils in the M9 matrix, connected vias. The pixel count between the coils was fixed to 0 to ensure spacing. Ultimately, a rough transformer topology was formed as a starting point for optimization.

[0059] Design an output matching network for a 28-34 GHz PA. The input and output impedances of the inter-stage matching circuit are (11 + j * 19) Ω and (30 + j * 13) Ω, respectively. This matching circuit is based on a 65nm CMOS process and is distributed across the M8 and M9 layers. Please fully utilize the internal microwave circuit design knowledge base to recommend one or more classic starting topologies, such as transformers and LC networks, and estimate the key physical parameters of the recommended topologies.

[0060] After analyzing the large language model, a transformer structure was recommended, and initial parameters were estimated: line width W = 10μm for the M8 layer, number of turns N = 2 for the M8 layer, line width W = 8μm for the M9 layer, and number of turns N = 1 for the M9 layer. Based on this, the pixelated grid cell size for the M8 layer was defined as 10μm x 10μm, and the pixelated grid cell size for the M9 layer was defined as 8μm x 8μm. On an area of ​​120μm x 150μm, the M8 layer formed an initial 12x8 binary matrix, and the M9 layer formed an initial 15x9 binary matrix. Based on the basic form of a two-turn transformer, an overpass structure was pre-defined between the primary and secondary coils in the M8 matrix, connected by vias. The pixel points between the coils were fixed to 0 to ensure spacing. Ultimately, a rough transformer topology was formed as a starting point for optimization.

[0061] Design an output matching network for a 28-34 GHz PA. The input and output impedances of the output matching circuit are (6.2 + j*35) Ω and (45 + j*9) Ω, respectively. This matching circuit is based on a 65nm CMOS process and is distributed across the M8 and M9 layers. Please fully utilize the internal microwave circuit design knowledge base to recommend one or more classic starting topologies, such as a transformer or LC network, and estimate the key physical parameters of the recommended topology.

[0062] After large language model analysis, it is recommended to adopt a transformer structure, and the initial parameters are estimated: M8 layer line width W = 10μm, M8 layer turns N = 1, M9 layer line width W = 8μm, M9 layer turns N = 1.

[0063] Based on this, the pixelated grid cell size for the M8 layer is defined as 10μm x 10μm, and the pixelated grid cell size for the M9 layer is defined as 8μm x 8μm. Over an area of ​​120μm x 150μm, the M8 layer forms a 12x8 initial binary matrix, and the M9 layer forms a 15x9 initial binary matrix. Based on the basic form of a single-turn transformer, no electromagnetic topology constraints are imposed.

[0064] Then, steps S30 and S40 are executed to obtain an optimization problem based on the initial binary matrix and the target requirements; key performance indicators and an optimization algorithm are obtained based on the optimization problem, and an iterative search is performed in the optimization algorithm based on the key performance indicators to obtain the optimal solution to the optimization problem, thereby generating an optimal pixelated topology. According to the specific steps described in Example 1, the initial binary matrix, etc., is further processed to generate an optimal pixelated topology. The optimal pixelated topology generated based on the above example is shown below.

[0065] Input matching: M8: , M9: Inter-level matching: M8: , M9: Output matches: M8: , M9: .

[0066] The embodiment is only a special example and does not represent only one way of implementing the present invention.

[0067] Example 2: like Figure 4 As shown, the present invention also provides a pixel matching circuit design and optimization processing device based on a large language model, comprising: An acquisition module S100 acquires target requirements and physical constraints of a matching circuit; A generating module S200 generates an initial topology structure based on the target requirement and the physical constraint, and performs parameter estimation on the initial topology structure to obtain an initial binary matrix constrained by the initial topology structure and the parameters; Confirmation module S300, obtaining an optimization problem based on the initial binary matrix and the target requirement; wherein the optimization problem includes optimization parameters, optimization objectives, and distribution of solution space; The optimization module S400 obtains a key performance indicator and an optimization algorithm according to the optimization problem, and iteratively searches the optimization algorithm according to the key performance indicator to obtain an optimal solution to the optimization problem, so as to generate an optimal pixelated topology.

[0068] Since the pixelated matching circuit design and optimization processing device based on a large language model introduced in this embodiment is the device used to implement the pixelated matching circuit design and optimization method based on a large language model in Example 1 of this application, based on the pixelated matching circuit design and optimization method based on a large language model introduced in Example 1 of this application, those skilled in the art can understand the specific implementation and various variations of the pixelated matching circuit design and optimization processing device based on a large language model in this embodiment, so how the pixelated matching circuit design and optimization processing device based on a large language model implements the method in Example 1 of this application will not be introduced in detail here. As long as those skilled in the art implement the device used by the pixelated matching circuit design and optimization method based on a large language model in Example 1 of this application, they all fall within the scope of protection to be protected by this application.

[0069] Example 3: Based on the same inventive concept, the third embodiment of the present invention further provides a terminal device, such as Figure 5 As shown, it includes one or more processors 301 and a memory 302; wherein, the memory is used to store one or more computer programs, and the one or more processors are used to execute the one or more computer programs stored in the memory, so that the processor performs the features / steps of the embodiment of the pixelated matching circuit design and optimization method based on the large language model as described in Example 1.

[0070] Those skilled in the art will appreciate that all or part of the features / steps of the aforementioned method embodiments may be implemented via methods, data processing systems, or computer programs. These features may be implemented entirely in software, without hardware, or through a combination of hardware and software. The aforementioned computer programs may be stored in one or more computer-readable storage media. The storage media stores the computer programs, and when executed (e.g., by a processor), the computer programs perform the steps of the aforementioned large language model-based pixelated matching circuit design and optimization method embodiments.

[0071] Example 4: Based on the same inventive concept, the fourth embodiment of the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, the steps of any method of the pixelated matching circuit design and optimization method based on a large language model described in the first embodiment above are implemented.

[0072] The foregoing is merely a preferred embodiment of the present invention. Those skilled in the art will appreciate that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. Furthermore, under the guidance of the present invention, these features and embodiments may be modified to suit specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are intended to be within the scope of the present invention.

Claims

1. A pixel matching circuit design and optimization method based on a large language model, characterized in that: include: Obtain target requirements and physical constraints for matching circuits; generating an initial topology structure based on the target requirements and the physical constraints, and performing parameter estimation on the initial topology structure to obtain an initial binary matrix constrained by the initial topology structure and the parameters; Obtaining an optimization problem based on the initial binary matrix and the target requirement; wherein the optimization problem includes optimization parameters, optimization targets, and distribution of solution space; A key performance indicator and an optimization algorithm are obtained according to the optimization problem, and an optimal solution to the optimization problem is obtained by iteratively searching in the optimization algorithm according to the key performance indicator, so as to generate an optimal pixelated topology.

2. The pixel matching circuit design and optimization method based on a large language model according to claim 1, characterized in that: The optimization problem obtained based on the initial binary matrix and the target requirement includes: Analyzing the initial binary matrix to identify unfixed pixels in the initial binary matrix, and obtaining the optimization parameters based on the unfixed pixels; Analyzing the target requirements to obtain the optimization target; The optimization parameters and optimization objectives are analyzed to confirm the distribution of the solution space.

3. The pixelated matching circuit design and optimization method based on a large language model according to claim 1, characterized in that: The step of obtaining a key performance indicator and an optimization algorithm according to the optimization problem, and iteratively searching in the optimization algorithm according to the key performance indicator to obtain an optimal solution to the optimization problem to generate an optimal pixelated topology includes: Determining properties of the optimization problem and selecting an optimization algorithm based on the properties of the optimization problem; Based on the impedance matching circuit and electromagnetic topology structure generated in the optimization target and corresponding to the target requirement, confirming the physical size parameters required for the impedance matching circuit and the electromagnetic topology structure; Performing simulation analysis on the physical size parameters to obtain key performance indicators corresponding to the physical size parameters; An iterative search is performed in the optimization algorithm according to the key performance indicators to obtain an optimal solution to the optimization problem, so as to generate an optimal pixelated topology.

4. The pixel matching circuit design and optimization method based on a large language model according to claim 3, characterized in that: The determining of the properties of the optimization problem includes: Confirm whether the attribute of the optimization parameter is a high-dimensional discrete variable space; confirming the number of the optimization objectives; Determine whether the distribution of the solution space is a sparse space.

5. The pixelated matching circuit design and optimization method based on a large language model according to claim 1, characterized in that: The generating of an initial topology structure based on the target requirements and the physical constraints, and performing parameter estimation on the initial topology structure to obtain an initial binary matrix constrained by the initial topology structure and the parameters, includes: The large language model generates an initial topology structure based on the target requirements and the physical constraints; Performing parameter estimation on the initial topological structure to obtain key physical parameters; An initial binary matrix based on the initial topological structure and the key physical parameter constraints.

6. The pixelated matching circuit design and optimization method based on a large language model according to claim 1, characterized in that: The obtaining of target requirements and physical constraints of the matching circuit includes: Performing simulation analysis on the matching circuit to obtain simulation results, and confirming target requirements of the matching circuit based on the simulation results; The area of ​​the matching circuit and the metal layer where the matching circuit is located are determined to obtain physical constraints of the matching circuit.

7. The pixelated matching circuit design and optimization method based on a large language model according to claim 6, characterized in that: In the performing simulation analysis on the matching circuit to obtain simulation results, and confirming target requirements of the matching circuit based on the simulation results, the simulation analysis includes load pull simulation analysis and source pull simulation analysis, and the target requirements include input matching network targets, output matching network targets, key performance indicators, and passive device constraints.

8. A pixel matching circuit design and optimization processing device based on a large language model, characterized in that: include: Obtain modules to obtain target requirements and physical constraints of matching circuits; A generation module generates an initial topology structure based on the target requirements and the physical constraints, and performs parameter estimation on the initial topology structure to obtain an initial binary matrix constrained by the initial topology structure and the parameters; A confirmation module, which obtains an optimization problem based on the initial binary matrix and the target requirement; wherein the optimization problem includes optimization parameters, optimization objectives and distribution of solution space; An optimization module obtains a key performance indicator and an optimization algorithm according to the optimization problem, and iteratively searches in the optimization algorithm according to the key performance indicator to obtain an optimal solution to the optimization problem, so as to generate an optimal pixelated topology.

9. A terminal device, characterized in that: include: one or more processors and memory; The memory is used to store one or more computer programs, and the one or more processors are used to execute one or more computer programs stored in the memory, so that the processor performs the steps of the pixelated matching circuit design and optimization method based on a large language model as described in any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of the pixelated matching circuit design and optimization method based on a large language model as described in any one of claims 1 to 7 are implemented.

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