A method for generating integrated circuit test stimuli and related apparatus

Abstract

The application discloses a method for generating integrated circuit test excitation and related equipment, which comprises the following steps: analyzing a coverage point code file and an RTL file, obtaining an input signal combination for triggering each coverage point according to a coverage point in the coverage point code file and a logical relationship in the RTL file, and generating a test excitation according to the input signal. The method greatly reduces manual participation and improves overall test efficiency. Moreover, the method accurately deduces the input signal combination according to the coverage point and the logical relationship in the RTL file, generates a test excitation matched with the input signal combination, improves the accuracy and comprehensiveness of the test excitation generation, and thus comprehensively detects the function of the integrated circuit and improves the accuracy of the test.

Description

Technical Field

[0001] This application relates to the field of integrated circuit testing technology, and in particular to a method for generating integrated circuit test stimuli and related equipment. Background Technology

[0002] In integrated circuit (IC) verification, cover points are an important criterion for measuring the comprehensiveness of IC verification. Cover points define the key signal states and logic conditions that need to be tested in the IC chip design.

[0003] Typically, testing integrated circuits requires verification engineers to manually complete the entire process, such as extracting coverage points and designing test stimuli.

[0004] Verification engineers need to spend a lot of time and effort extracting coverage points and designing test stimuli, resulting in low efficiency in integrated circuit verification. Moreover, manual operation is prone to errors and omissions in the verification plan due to the complexity of the logic, which cannot meet the verification requirements and affect the verification cycle. Summary of the Invention

[0005] To address the aforementioned issues, this application provides a method and related equipment for generating integrated circuit test stimuli.

[0006] In a first aspect, embodiments of this application provide a method for generating integrated circuit test stimuli, the method comprising:

[0007] Obtain the overlay code file of the integrated circuit and the corresponding register transfer level (RTL) file of the overlay code file; the overlay code file includes at least one overlay; the RTL file is used to record the logical relationships of signals inside the integrated circuit;

[0008] A combination of input signals that triggers each of the coverage points is obtained based on at least one of the coverage points and the logical relationship;

[0009] A corresponding test stimulus is generated based on each of the input signal combinations; the test stimulus is used to drive the integrated circuit to trigger the coverage point.

[0010] In one possible implementation, obtaining the combination of input signals that trigger each of the coverage points based on at least one of the coverage points and the logical relationship includes:

[0011] The cover point code file is parsed to identify the target signal corresponding to each cover point and the target value of the target signal.

[0012] Based on the RTL file, the type of each target signal is determined;

[0013] The input signal combination for each coverage point is determined based on the type of each target signal and the logical relationship recorded in the RTL file.

[0014] In one possible implementation, the target signal type includes an input signal, an intermediate signal, or an output signal;

[0015] Determining the input signal combination for the coverage point based on the type of the target signal and the logical relationship recorded in the RTL file includes:

[0016] When the target signal is an input signal, the target signal and the target value corresponding to the target signal are combined as input signals.

[0017] When the target signal is an intermediate signal or an output signal, the target signal is deduced in reverse according to the logical relationship recorded in the RTL file to obtain the input signal combination that makes the target signal satisfy the target value.

[0018] In one possible implementation, the reverse derivation of the target signal based on the logical relationship recorded in the RTL file includes:

[0019] Locate the assignment logic of the target signal in the RTL file, and extract the upstream signal combination in the assignment logic;

[0020] Based on the assignment logic, a mapping relationship is established between the target value of the target signal and the value of the upstream signal combination;

[0021] The value of the upstream signal combination that makes the target signal satisfy the target value is determined according to the mapping relationship, and the input signal combination is obtained according to the value of the upstream signal combination.

[0022] In one possible implementation, establishing the mapping relationship between the target value of the target signal and the value of the upstream signal combination based on the assignment logic includes:

[0023] When the assignment logic represents that multiple combinations of upstream signals can make the target signal satisfy the target value, a mapping relationship is established between the target value of the target signal and the values ​​of each combination of upstream signals.

[0024] In one possible implementation, the method further includes:

[0025] The input signals corresponding to the test stimuli are combined and converted into signal-driven code that conforms to the syntax specifications of the test platform;

[0026] The signal-driven code is embedded in the test platform; the signal-driven code includes signal assignment statements and timing control statements; the signal assignment statements are used to define the specific values ​​of the input signals, and the timing control statements are used to define the time nodes when the signals are applied.

[0027] In one possible implementation, the method further includes:

[0028] The test stimulus is simulated and verified to determine whether the test stimulus triggers the corresponding coverage point;

[0029] If the coverage point is not triggered, determine the failure type of the test stimulus not triggering the corresponding coverage point;

[0030] Adjustments are made based on the failure type, and the test stimulus corresponding to the coverage point is regenerated until the coverage point is triggered.

[0031] Secondly, embodiments of this application provide an apparatus for generating integrated circuit test stimuli, the apparatus comprising:

[0032] An acquisition module is used to acquire the overlay code file of the integrated circuit and the register transfer level (RTL) file corresponding to the overlay code file; the overlay code file includes at least one overlay; the RTL file is used to record the logical relationships of signals inside the integrated circuit.

[0033] The parsing module is used to obtain the combination of input signals that trigger each of the coverage points based on at least one of the coverage points and the logical relationship;

[0034] The generation module is used to generate corresponding test stimuli based on the combination of the input signals; the test stimuli are used to generate signal driving code for the test platform, and the signal driving code is used to drive the integrated circuit to trigger the coverage of the coverage point.

[0035] In one possible implementation, the parsing module is specifically used to parse the coverage point code file, identify the target signal corresponding to each coverage point and the target value of the target signal; determine the type of each target signal based on the RTL file; and determine the input signal combination of each coverage point according to the type of each target signal and the logical relationship recorded in the RTL file.

[0036] In one possible implementation, the target signal type includes an input signal, an intermediate signal, or an output signal;

[0037] The parsing module is specifically used to, when the target signal is an input signal, take the target signal and the target value corresponding to the target signal as a combination of input signals; when the target signal is an intermediate signal or an output signal, perform reverse derivation on the target signal according to the logical relationship recorded in the RTL file to obtain a combination of input signals that makes the target signal satisfy the target value.

[0038] In one possible implementation, the parsing module is specifically used to locate the assignment logic of the target signal in the RTL file, extract the upstream signal combination involved in the assignment logic; establish a mapping relationship between the target value of the target signal and the value of the upstream signal combination based on the assignment logic; determine the value of the upstream signal combination that makes the target signal satisfy the target value according to the mapping relationship, and obtain the input signal combination according to the value of the upstream signal combination.

[0039] In one possible implementation, the parsing module is specifically used to establish a mapping relationship between the target value of the target signal and the values ​​of each group of upstream signal combinations, when the assignment logic characterizes that multiple combinations of upstream signals can make the target signal satisfy the target value.

[0040] In one possible implementation, the generation module is further configured to convert the combination of input signals corresponding to the test stimulus into signal-driven code that conforms to the syntax specifications of the test platform; embed the signal-driven code into the test platform; the signal-driven code includes signal assignment statements and timing control statements; the signal assignment statements are used to define the specific values ​​of the input signals, and the timing control statements are used to define the time nodes when the signals are applied.

[0041] In one possible implementation, the device further includes a verification module;

[0042] The verification module is used to perform simulation verification on the test stimulus, determine whether the test stimulus triggers the corresponding coverage point; if the coverage point is not triggered, determine the failure type of the test stimulus not triggering the corresponding coverage point; adjust according to the failure type, and regenerate the test stimulus corresponding to the coverage point until the coverage point is triggered.

[0043] Thirdly, embodiments of this application provide a control device, including a processor and a memory, wherein the memory is used to store programs, instructions or code, and the processor is used to execute the programs, instructions or code in the memory to complete the method for generating integrated circuit test stimuli as described in any of the first aspects.

[0044] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program, which is loaded by a processor to execute the method for generating integrated circuit test stimuli as described in the first aspect.

[0045] This application provides a method and related equipment for generating integrated circuit test stimuli. The method parses a coverage point code file and an RTL file, and obtains the input signal combination that triggers each coverage point based on the logical relationships between the coverage points in the code file and the RTL file. Then, test stimuli are generated based on these input signals. This significantly reduces manual intervention and improves overall testing efficiency. Furthermore, this method accurately derives the input signal combination based on the logical relationships between the coverage points and the RTL file, generating matching test stimuli, thus improving the accuracy and comprehensiveness of test stimulus generation. This allows for comprehensive testing of the integrated circuit's functionality and enhances testing accuracy. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 A flowchart illustrating a method for generating integrated circuit test stimuli according to an embodiment of this application;

[0048] Figure 2 A flowchart illustrating another method for generating integrated circuit test stimuli provided in an embodiment of this application;

[0049] Figure 3 A flowchart for determining a combination of input signals is provided in an embodiment of this application;

[0050] Figure 4 This is a schematic diagram of a software module of a controller provided in an embodiment of this application. Detailed Implementation

[0051] Typically, integrated circuit verification engineers need to manually extract coverage points to design verification plans, and then develop test stimuli based on the verification plans. Verification engineers not only need to spend a lot of time and effort developing test stimuli, but also need to spend time debugging the test stimuli to compensate for the poor accuracy of manual development.

[0052] To address this technical problem, this application provides a method and related equipment for generating integrated circuit test stimuli. This method parses the coverage point code file and the Register Transfer Level (RTL) design file, and obtains the input signal combinations that trigger each coverage point based on the logical relationships between the coverage points in the code file and the RTL file. Test stimuli are then generated based on these input signals. This significantly reduces manual intervention and improves overall testing efficiency. Furthermore, this method accurately derives the input signal combinations based on the logical relationships between the coverage points and the RTL file, generating matching test stimuli, thus improving the accuracy and comprehensiveness of test stimulus generation. This allows for comprehensive testing of the integrated circuit's functionality and enhances testing accuracy.

[0053] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0054] See Figure 1 This figure is a flowchart illustrating a method for generating integrated circuit test stimuli according to an embodiment of this application. This method can be executed by a controller in an electronic device or by other devices with computing capabilities; the following description uses a controller as the executing entity. The method includes:

[0055] S101: The controller obtains the coverage point code file of the integrated circuit and the corresponding RTL file of the coverage point code file.

[0056] Coverage code files are code files used to define the verification targets of integrated circuits, typically using hardware description languages ​​such as SystemVerilog (SV). Coverage points are critical checkpoints for measuring the completeness of integrated circuit verification; they can also be understood as describing the key scenarios that need to be tested on the integrated circuit. During integrated circuit testing and verification, test stimuli can be used to bring the integrated circuit to the required test scenarios, i.e., triggering coverage points.

[0057] In this embodiment, the coverage point code file includes at least one coverage point. The coverage point defines a corresponding target signal and its target value. It is understood that the target signal and its target value defined by the coverage point correspond to the test scenario described by the coverage point. Based on the target signal and its target value, a corresponding input signal combination can be derived, which drives the integrated circuit to implement the test scenario described by the coverage point.

[0058] The target signal defined by a coverage point can be one or more, that is, a group of target signals. Correspondingly, the target value of the target signal defined by the coverage point refers to the target value of each target signal defined by the coverage point.

[0059] RTL files are the core design files for integrated circuits, and are typically written in Verilog or VHDL. RTL files are used to record the logical relationships between signals within the integrated circuit.

[0060] The logical relationship between signals within an integrated circuit can also be understood as the operational rules between signals, such as the signal transformation relationship implemented through modules like logic gates, adders, or state machines.

[0061] The internal signals of an integrated circuit include input signals, intermediate signals, and output signals. Input signals are control or data signals transmitted from external devices to the integrated circuit; intermediate signals are signals output from the internal logic units of the integrated circuit; and output signals are signals output by the integrated circuit to the outside world.

[0062] It is important to note that the type of enable signal (en) must be determined according to its definition in integrated circuit design. An enable signal can be an input signal or an intermediate signal.

[0063] If the enable signal is input from outside the integrated circuit, such as by an external controller, host computer, or other device, to control the start-up or shutdown of internal modules, the enable signal is an input signal. If the enable signal is generated by internal logic of the integrated circuit, such as by the output of an internal state machine, counter, or other module, to control other internal modules, the enable signal is an intermediate signal.

[0064] S102: The controller parses the coverage point code file and RTL file, and obtains the combination of input signals to trigger each coverage point based on at least one coverage point and logical relationship.

[0065] The controller can perform structured analysis on the coverage point code file using automated tools (such as a compiler or parser) to extract each coverage point. Furthermore, the controller extracts the logical relationships of the internal signals of the integrated circuit from the RTL file.

[0066] For each coverage point, the controller obtains the corresponding input signal combination based on the logical relationship of the signals within the integrated circuit. The input signal combination includes at least one input signal and the values ​​of each input signal. Driving the integrated circuit according to the input signal combination can trigger the coverage point.

[0067] As an example, if the coverage point is "data_out=8'hFF", and "data_out=in1+in2" is defined in the RTL file, and "data_out=8'hFF" can be made when "in1=8'hAA,in2=8'h55", then the input signal combination that triggers the coverage point can be "in1=8'hAA,in2=8'h55".

[0068] The controller parses the coverage point code file and RTL file to deduce what signals need to be input to the integrated circuit to trigger the coverage point, thus determining the corresponding input signal combination. Step S102 transforms the abstract coverage point into a specific, operable combination of input signals, providing a direct basis for subsequent test stimulus generation. This replaces the manual derivation of input signals and avoids derivation errors or omissions caused by the complexity of the RTL file logic.

[0069] S103: The controller generates corresponding test stimuli based on the combination of each input signal.

[0070] Test stimuli are signal sequences used to drive the operation of integrated circuits. Essentially, test stimuli are the timing-based and coded representation of combinations of input signals. As an example, a test stimulus could be in1 = 0xAA and in2 = 0x55 at the rising edge of the clock. Each combination of input signals corresponds one-to-one with a test stimulus.

[0071] The signal-driven code of the test platform is the specific implementation of the test stimulus, and it can be directly integrated into the integrated circuit test platform. The test platform can drive the integrated circuit to trigger coverage points by running the signal-driven code.

[0072] In related technologies, verification engineers need to manually derive input signal combinations based on coverage points, write test stimuli, and repeatedly debug them. However, the method provided in this application combines the logical relationships of RTL files to derive input signal combinations based on coverage points, thereby obtaining the test stimuli corresponding to each coverage point. This method replaces the repetitive work of verification engineers, significantly reducing the time cost of test stimulus development and shortening the integrated circuit verification cycle.

[0073] Furthermore, when manually deriving input signal combinations, key signals are easily overlooked due to the complexity of RTL file logic and the cumbersome coverage points, resulting in test stimuli failing to cover the corresponding coverage points. This method, through structured analysis of the coverage point code file and RTL file, reverse-engineers the input signal combinations based on logical relationships, ensuring that the generated test stimuli meet the coverage requirements of the coverage points recorded in the coverage point code file, thereby improving the accuracy and comprehensiveness of integrated circuit verification.

[0074] To test integrated circuits using test stimuli, the controller generates test stimuli based on the combination of input signals, and then generates signal drive code for the test platform based on the test stimuli.

[0075] In one possible implementation, such as Figure 2 As shown, after step S103, the method further includes:

[0076] S104: The controller generates corresponding signal drive code based on the test stimulus and embeds the signal drive code into the test platform.

[0077] Test stimuli are essentially logical descriptions of combinations of input signals and the values ​​of each input signal, while signal-driven code is the specific code implementation of the test stimuli. The controller needs to convert the test stimuli into a code format supported by the test platform, that is, convert the test stimuli into the corresponding signal-driven code.

[0078] Signal-driven code is used to apply input signals to the input terminals of integrated circuits in a test platform. The signal-driven code must conform to the syntax specifications of the test platform. Signal-driven code can include signal assignment statements and timing control statements. Signal assignment statements define the specific values ​​of the input signals, while timing control statements define the timing points at which the signals are applied. By designing timing control statements, signals can be applied at the correct times, meeting the timing requirements of integrated circuits and avoiding test failures caused by signal timing errors.

[0079] A test platform is a virtual environment used to verify the functionality of integrated circuits, typically constructed from code. As an example, a test platform may include a stimulus generation module, a chip under test (DUT), and a signal monitoring module. The test platform can simulate the actual operating environment of the integrated circuit, applying input signals and acquiring output signals to determine whether the integrated circuit meets design requirements.

[0080] After the controller converts the test stimulus into signal-driven code that conforms to the syntax specification, the controller can embed the signal-driven code into the test platform through a preset interface or template, so that the signal-driven code runs automatically when the test starts.

[0081] This application embodiment transforms abstract test stimuli into executable signal-driven code, enabling the test stimuli to be recognized and run by the test platform, thereby realizing the test verification of integrated circuits.

[0082] The method provided in this application embodiment can obtain the input signal combination corresponding to each coverage point based on the coverage point code file and RTL file, which reduces the dependence on the professional skills of verification engineers and simplifies the verification process.

[0083] To facilitate understanding, the specific implementation of step S102 will be further described below.

[0084] In one possible implementation, such as Figure 3 As shown, step S102 includes:

[0085] S1021: The controller parses the coverage point code file and identifies the target signal corresponding to each coverage point and the target value of the target signal.

[0086] Coverage points are used to define target signals and their target values. The controller can determine the coverage points recorded in the coverage point code file by parsing the coverage point code file, and then determine the target signal and target value defined by the coverage point based on the coverage point.

[0087] Coverage points are used to define at least one target signal and the target value of the target signal. For ease of understanding, this application embodiment uses the definition of a target signal and the target value of the target signal by a coverage point as an example.

[0088] S1022: The controller determines the type of each target signal based on the RTL file.

[0089] After identifying the target signal and its value corresponding to the coverage point, the controller needs to determine the type of the target signal. The type of the target signal characterizes its position within the signal logic relationships of the integrated circuit. The RTL file records these relationships, allowing the determination of the target signal type based on the RTL file.

[0090] The controller determines the type of the target signal, providing a basis for the logical deduction of subsequent steps, so as to adopt an appropriate processing method for different types of target signals.

[0091] S1023: The controller determines the input signal combination for each coverage point based on the type of each target signal and the logical relationship recorded in the RTL file.

[0092] The controller combines the type of the target signal and the logical relationship recorded in the RTL file to transform the target signal and target value defined by the coverage point into a combination of input signals that can be directly applied to the input terminal of the integrated circuit, thus establishing the relationship between the coverage point and the test stimulus.

[0093] The controller determines the combination of input signals differently depending on the type of the target signal. In this embodiment, the target signal types include input signals, intermediate signals, and output signals.

[0094] Input signals are signals input from outside the integrated circuit and are declared as input in the module port list of the RTL file.

[0095] Intermediate signals are signals generated by the internal logic of the integrated circuit. They are only declared within the RTL file, and the values ​​of intermediate signals are determined by the internal logic of the integrated circuit.

[0096] Output signals are signals that are output from the integrated circuit to the outside. They are declared as "output" in the module port list of the RTL file, and the values ​​of the output signals are also determined by the internal logic of the integrated circuit.

[0097] It is easy to see that the input signal is directly input from outside the integrated circuit and does not undergo internal logic operations. The intermediate signal and the output signal are both results obtained by performing internal logic operations on the input signal. The intermediate signal is an intermediate result, and the output signal is the final output of the integrated circuit.

[0098] When the target signal is the input signal, there is no need to derive the target signal; the value of the target signal defined by the coverage point can be directly used as the input signal combination.

[0099] When the target signal is an intermediate or output signal, to obtain the input signal combination, it is necessary to reverse-engineer the target signal based on the logical relationships of the signals inside the integrated circuit as recorded in the RTL file, and then obtain the input signal combination. This input signal combination, after undergoing logical operations within the integrated circuit, can make the target signal take the target value.

[0100] In one possible implementation, the target signal is deduced in reverse based on the logical relationships recorded in the RTL file, including:

[0101] Locate the assignment logic of the target signal in the RTL file and extract the upstream signal combination involved in the assignment logic;

[0102] The mapping relationship between the target value of the target signal and the combined value of the upstream signals is established based on the assignment logic.

[0103] Based on the mapping relationship, the values ​​of the upstream signal combination that make the target signal satisfy the target value are derived, and the input signal combination is obtained by tracing back based on the values ​​of the upstream signal combination.

[0104] Assignment logic is the logic for assigning values ​​to the target signal as recorded in the RTL file. It relates the target signal's value to the values ​​of other signals. In an RTL file, assignment logic can be represented by code statements that assign values ​​to the target signal. Examples include continuous assignment statements, procedural assignment statements, or conditional assignment statements.

[0105] The upstream signal combination refers to the set of signals that directly participate in the calculation of the target signal value in the assignment logic. For example, in data_out = in1 + in2, the upstream signal combination is {in1, in2}, and the target signal is data_out.

[0106] Mapping relationships refer to the correspondence between the target value of the target signal and the combined value of the upstream signals. Mapping relationships can also be understood as the inverse operation rules of assignment logic. For example, if the assignment logic is data_out = in1 + in2, and the target value is data_out = 5, then the mapping relationship is in1 + in2 = 5.

[0107] The controller identifies all upstream signals that determine the value of the target signal through the positioning and assignment logic. Then, it establishes a mapping relationship between the target value of the target signal and the combined values ​​of the upstream signals, transforming the forward calculation rules of the assignment logic into reverse lookup rules to clearly define the values ​​of the upstream signals that make the target signal meet the target value. Finally, starting from the mapping relationship, the controller works backward to deduce the values ​​of the upstream signals, ultimately locating the directly controllable input signal, completing the conversion from the target value of the target signal to the combination of input signals.

[0108] In one possible scenario, the value of the output signal or intermediate signal may be influenced by multiple signals, and there may be multiple combinations of input signals that result in the same output signal or intermediate signal. In this case, the assignment logic may characterize multiple combinations of upstream signals that can make the target signal meet the target value.

[0109] In the embodiments of this application, when the assignment logic characterizes multiple upstream signal combinations that can make the target signal meet the target value, multiple upstream signal combinations that can make the target signal meet the target value are determined, and a mapping relationship is established between the target value of the target signal and the value of each upstream signal combination.

[0110] When the assignment logic of the target signal allows for multiple combinations of signal values ​​that can satisfy the target value of the coverage point, such a combination of signal values ​​constitutes a set of upstream signal combinations. As an example, if the assignment logic of the target signal `out` is `out=a|b` (OR operation), and the target value is `out=1`, then the upstream signal combinations could be {a=1,b=0}, {a=0,b=1}, and {a=1,b=1}. All three of these upstream signal combinations can satisfy the target value, meaning that multiple upstream signal combinations can ensure the target signal meets the target value.

[0111] When multiple combinations of upstream signals can make the target signal meet the target value, the mapping relationship is no longer one-to-one, but one-to-many. That is, the target value of the target signal corresponds to the value of multiple combinations of upstream signals (e.g., out=1 corresponds to [{a=1,b=0},{a=0,b=1},{a=1,b=1}]).

[0112] By identifying all possible combinations of upstream signals, incomplete subsequent input signal combinations are avoided due to the omission of any combination. This provides sufficient evidence for subsequent traceability and improves the comprehensiveness of verification.

[0113] Furthermore, in the process of generating input signal combinations based on upstream signal combinations, if there are multiple upstream signal combinations corresponding to the target signal, it is necessary to reverse derive the corresponding input signal combination for each upstream signal combination, and then generate the corresponding test stimulus based on each input signal combination. Finally, multiple test stimuli corresponding to the same coverage point are obtained.

[0114] When multiple coverage points are recorded in the coverage point code file, at least one test stimulus is generated for each coverage point, thereby improving the accuracy and comprehensiveness of integrated circuit testing.

[0115] As an example, the assignment logic might look like this:

[0116] Input b, d; / / Define input

[0117] Output a; / / Define the output

[0118] Logic c; / / Intermediate variable

[0119] assign a=b&c:

[0120] always_ff @(posedge clk) begin

[0121] c=!rst_n ? 1'b0 : d;

[0122] …

[0123] end

[0124] …

[0125] As an example, let's assume the output signal a=0. In the reverse derivation analysis, when we reach the statement `assign a=b&c`, we find that the value of the output signal a depends on this statement. This statement indicates that when a=0, either b=0 or c=0 is required.

[0126] As an input signal, b can be used to directly record a feasible combination of input signals: %a_0=("b"≥0).

[0127] c is an intermediate signal, requiring further reverse derivation. When analyzing the statement c=!rst_n ? 1'b0 : d, the value of the intermediate signal c depends on this statement; that is, when c=0, rst_n needs to be 0, or rst_n=1 and d=0. In this case, the code statement a=0 can be represented as %a_0=("b"≥0,"rst_n"≥0,"comb1"≥{"rst_n"≥1,"d"≥0}).

[0128] Since a=0 only requires either b=0 or c=0 to be true, the code statement for a=0 can be represented as %a_0=("comb1"≥{"b"≥0,"rst_n"≥"?","d"≥"?"},"comb2"≥{"rst_n"≥"0","b"≥"?","d"≥"?"},"comb3"≥{"rst_n"≥"1","b"≥"?","d"≥"1"}). The "?" in the code statement indicates that the value of this signal can be random. Thus, all possible combinations of input signals corresponding to the output signal a=0 are obtained.

[0129] As another example, if the output signal is set to a=1, then in the reverse derivation analysis to the statement assign a=b&c, the value of the output signal a depends on this statement. This statement indicates that when a=0, b=1 and c=1 are required.

[0130] 'b' is the input signal, directly recorded as a necessary signal: %a_1=("comb1"≥{"b"≥1}), and it also needs to satisfy c=1. 'c' is an intermediate signal; we continue to deduce the value of 'c' in reverse, determining the value of 'c' using the statement c=!rst_n ? 1'b0:d. Furthermore, this statement is contained within the always_ff block, meaning the value of 'b' must remain for one cycle after 'd' is 1. That is, when c=1, rst_n=1 and d=1, 'b' must remain for one cycle.

[0131] Here, the requirement for a=1 is that b=1 and c=1 are both 1. The code statement for a=0 can be represented as %a_1=("comb1"≥{"b"≥1,"rsn_n"≥"1","d"≥"1","cycle1"≥"1"}). Thus, all the input signal combinations corresponding to the output signal a=1 are obtained.

[0132] To further improve the accuracy and reliability of test stimuli, the method also includes:

[0133] The test stimulus is simulated and verified to determine whether the test stimulus triggers the corresponding coverage point;

[0134] If the coverage point is not triggered, determine the failure type of the test stimulus not triggering the corresponding coverage point;

[0135] Adjustments are made based on the failure type, and the test stimulus corresponding to the coverage point is regenerated until the coverage point is triggered.

[0136] The controller can input the signal drive code corresponding to the test stimulus into the Electronic Design Automation (EDA) simulation tool. The EDA simulation tool will then virtually run the generated test stimulus, simulate the working state of the integrated circuit under the test stimulus, and collect and analyze the signal changes of the integrated circuit.

[0137] EDA simulation tools automatically compare the value of the target signal output from the integrated circuit simulation with the target value of the coverage point to determine the coverage status of the coverage point. If the value of the target signal output from the simulation is the same as the target value defined for the coverage point, it indicates that the coverage point has been triggered. If the value of the target signal output from the simulation is different from the target value defined for the coverage point, it indicates that the coverage point has not been triggered.

[0138] There are two possible reasons why a coverage point might not be triggered: First,

[0139] When the coverage point is not covered, step S102 can be re-executed to correct the input signal combination derived in step S102 so that it can trigger the target value of the target signal during re-simulation.

[0140] The method for generating integrated circuit test stimuli provided in this application embodiment can also be executed by a software module within the controller, specifically, as shown in... Figure 4 As shown, the software modules in the controller used to implement this method may include a parser, a backpropagator, and an excitation generator.

[0141] The parser is used to perform structured parsing of the cover point code file and RTL file, extracting the cover points in the cover point code file and the logical relationships of the internal signals of the integrated circuit recorded in the RTL file.

[0142] The reverse engineer is used to transform the target requirements of the coverage point into a directly controllable combination of input signals based on the results obtained from the parser. The reverse engineer determines the type of the target signal in the coverage point according to the logical relationships recorded in the RTL file. If the target signal is an input signal, its target value is directly used as the input signal combination; if the target signal is an intermediate or output signal, the reverse engineer traces back based on the logical relationships recorded in the RTL file, starting from the target value of the target signal, deriving the value of the upstream signal through assignment logic, tracing back layer by layer to the input signal, and finally obtaining the input signal combination that can trigger the target value.

[0143] The stimulus generator is used to combine the input signals obtained from the backpropagator into executable test code and complete the integration with the test platform.

[0144] The stimulus generator can convert input signal combinations into signal-driven code that conforms to the test platform's syntax specifications, and integrate the generated signal-driven code into the test platform so that the signal-driven code can be called during simulation.

[0145] It should be noted that if the test stimulus still fails to trigger the corresponding coverage point coverage after repeatedly executing step S102, the parser, reverse engineer, and stimulus generator may need to be updated or repaired to ensure the accuracy of test stimulus generation.

[0146] The method provided in this application is applicable to all types of integrated circuits. Furthermore, when the integrated circuit design changes, only the coverage code file and RTL file need to be updated; this method can then regenerate the corresponding test stimuli without requiring extensive manual design and debugging. It offers rapid response to design changes and strong adaptability. Moreover, this method uses a unified parsing and test stimulus generation based on the coverage code file and RTL file, providing a standardized process for integrated circuit testing. Different testers and projects can follow the same method to generate test stimuli, reducing test discrepancies caused by human error, facilitating the establishment of a standardized testing system, and improving the reliability and repeatability of testing.

[0147] Based on the above method embodiments, this application further provides an integrated circuit test stimulus generation apparatus, the apparatus comprising:

[0148] An acquisition module is used to acquire the overlay code file of the integrated circuit and the register transfer level (RTL) file corresponding to the overlay code file; the overlay code file includes at least one overlay; the RTL file is used to record the logical relationships of signals inside the integrated circuit.

[0149] The parsing module is used to obtain the combination of input signals that trigger each of the coverage points based on at least one of the coverage points and the logical relationship;

[0150] The generation module is used to generate corresponding test stimuli based on the combination of the input signals; the test stimuli are used to generate signal driving code for the test platform, and the signal driving code is used to drive the integrated circuit to trigger the coverage of the coverage point.

[0151] In one possible implementation, the parsing module is specifically used to parse the coverage point code file, identify the target signal corresponding to each coverage point and the target value of the target signal; determine the type of each target signal based on the RTL file; and determine the input signal combination of each coverage point according to the type of each target signal and the logical relationship recorded in the RTL file.

[0152] In one possible implementation, the target signal type includes an input signal, an intermediate signal, or an output signal;

[0153] The parsing module is specifically used to, when the target signal is an input signal, take the target signal and the target value corresponding to the target signal as a combination of input signals; when the target signal is an intermediate signal or an output signal, perform reverse derivation on the target signal according to the logical relationship recorded in the RTL file to obtain a combination of input signals that makes the target signal satisfy the target value.

[0154] In one possible implementation, the parsing module is specifically used to locate the assignment logic of the target signal in the RTL file, extract the upstream signal combination involved in the assignment logic; establish a mapping relationship between the target value of the target signal and the value of the upstream signal combination based on the assignment logic; determine the value of the upstream signal combination that makes the target signal satisfy the target value according to the mapping relationship, and obtain the input signal combination according to the value of the upstream signal combination.

[0155] In one possible implementation, the parsing module is specifically used to establish a mapping relationship between the target value of the target signal and the values ​​of each group of upstream signal combinations, when the assignment logic characterizes that multiple combinations of upstream signals can make the target signal satisfy the target value.

[0156] In one possible implementation, the generation module is further configured to convert the combination of input signals corresponding to the test stimulus into signal-driven code that conforms to the syntax specification of the test platform; embed the signal-driven code into the test platform; the signal-driven code includes signal assignment statements and timing control statements; the signal assignment statements are used to define the specific values ​​of the input signals, and the timing control statements are used to define the time nodes when the signals are applied.

[0157] In one possible implementation, the device further includes a verification module;

[0158] The verification module is used to perform simulation verification on the test stimulus, determine whether the test stimulus triggers the corresponding coverage point; if the coverage point is not triggered, determine the reason why the test stimulus does not trigger the corresponding coverage point, and make adjustments according to the reason until the coverage point is triggered.

[0159] In one possible implementation, this application also provides a control device.

[0160] The control device may include memory and a processor. The memory may be random access memory (RAM), flash memory, read-only memory (ROM), EPROM, non-volatile read-only memory (Electronic Programmable ROM), registers, hard disk, removable disk, etc.

[0161] Memory can store computer instructions. When these instructions are executed by a processor, the processor can use them to perform methods for generating test stimuli for integrated circuits. Memory can also store data.

[0162] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape) or a semiconductor medium (e.g., solid-state disk (SSD)).

[0163] This application also provides a readable storage medium for storing the methods provided in the above embodiments. Examples include random access memory (RAM), flash memory, read-only memory (ROM), EPROM, non-volatile read-only memory (Electronic Programmable ROM), registers, hard disks, removable disks, or any other form of storage medium in the art.

[0164] In the embodiments of this application, the terms "first" and "second" (if they exist) are used only as name identifiers and do not represent the order of first and second.

[0165] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. Regarding the methods disclosed in the embodiments, since they correspond to the product embodiments disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the description of the product embodiments.

[0166] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for generating test stimuli for integrated circuits, characterized in that, The method includes: Obtain the overlay code file of the integrated circuit and the corresponding register transfer level (RTL) file of the overlay code file; the overlay code file includes at least one overlay; the RTL file is used to record the logical relationships of signals inside the integrated circuit; The cover point code file is parsed to identify the target signal corresponding to each cover point and the target value of the target signal. Based on the RTL file, the type of each target signal is determined; the signal type of the target signal includes input signal, intermediate signal, or output signal. The input signal combination for each coverage point is determined based on the type of each target signal and the logical relationship recorded in the RTL file; A corresponding test stimulus is generated based on each of the input signal combinations; the test stimulus is used to drive the integrated circuit to trigger the coverage point.

2. The method according to claim 1, characterized in that, Determining the input signal combination for the coverage point based on the type of the target signal and the logical relationship recorded in the RTL file includes: When the target signal is an input signal, the target signal and the target value corresponding to the target signal are combined as input signals. When the target signal is an intermediate signal or an output signal, the target signal is deduced in reverse according to the logical relationship recorded in the RTL file to obtain the input signal combination that makes the target signal satisfy the target value.

3. The method according to claim 2, characterized in that, The step of reverse derivation of the target signal based on the logical relationship recorded in the RTL file includes: Locate the assignment logic of the target signal in the RTL file, and extract the upstream signal combination in the assignment logic; Based on the assignment logic, a mapping relationship is established between the target value of the target signal and the value of the upstream signal combination; The value of the upstream signal combination that makes the target signal satisfy the target value is determined according to the mapping relationship, and the input signal combination is obtained according to the value of the upstream signal combination.

4. The method according to claim 3, characterized in that, The process of establishing a mapping relationship between the target value of the target signal and the value of the upstream signal combination based on the assignment logic includes: When the assignment logic represents that multiple combinations of upstream signals can make the target signal satisfy the target value, a mapping relationship is established between the target value of the target signal and the values ​​of each combination of upstream signals.

5. The method according to claim 1, characterized in that, The method further includes: The input signals corresponding to the test stimuli are combined and converted into signal-driven code that conforms to the syntax specifications of the test platform; The signal-driven code is embedded in the test platform; the signal-driven code includes signal assignment statements and timing control statements; the signal assignment statements are used to define the specific values ​​of the input signals, and the timing control statements are used to define the time nodes when the signals are applied.

6. The method according to claim 1, characterized in that, The method further includes: The test stimulus is simulated and verified to determine whether the test stimulus triggers the corresponding coverage point; If the coverage point is not triggered, determine the failure type of the test stimulus not triggering the corresponding coverage point; Adjustments are made based on the failure type, and the test stimulus corresponding to the coverage point is regenerated until the coverage point is triggered.

7. An apparatus for generating test stimuli for integrated circuits, characterized in that, The device includes: An acquisition module is used to acquire the overlay code file of the integrated circuit and the register transfer level (RTL) file corresponding to the overlay code file; the overlay code file includes at least one overlay; the RTL file is used to record the logical relationships of signals inside the integrated circuit. The parsing module is used to parse the coverage point code file and the RTL file, identify the target signal corresponding to each coverage point and the target value of the target signal; determine the type of each target signal based on the RTL file; the signal type of the target signal includes input signal, intermediate signal or output signal; and determine the input signal combination of each coverage point according to the type of each target signal and the logical relationship recorded in the RTL file. The generation module is used to generate corresponding test stimuli based on the combination of the input signals; the test stimuli are used to generate signal driving code for the test platform, and the signal driving code is used to drive the integrated circuit to trigger the coverage of the coverage point.

8. A control device, characterized in that, It includes a processor and a memory, the memory being used to store programs, instructions, or code, and the processor being used to execute the programs, instructions, or code in the memory to complete the method for generating integrated circuit test stimuli as described in any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The device contains a computer program that is loaded by a processor to execute the method for generating integrated circuit test stimuli as described in any one of claims 1-6.

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