Chip verification method and device, medium and program product

Abstract

The invention discloses a chip verification method and device, a medium and a program product, and relates to the field of chip verification, and the method comprises the steps: constructing an initial directed graph based on each component module of a to-be-tested chip and the multi-level function division of each component module; setting weights for directed edges in the initial directed graph to obtain a target directed graph; the weight of the first directed edge in the target directed graph is zero, and the sum of the weights of the second directed edges corresponding to the same parent vertex is a preset numerical value; the first directed edge comprises directed edges used for connecting different composition modules; the second directed edges are other directed edges except the first directed edge in the target directed graph; and searching a corresponding path from the target directed graph based on a preset verification demand to construct a verification target set so as to realize verification of the to-be-tested chip. According to the method, the weight directed graph is constructed for the to-be-tested chip, so that the chip is purposefully and selectively verified, the chip verification efficiency and flexibility are improved, and the process of mass production and market application of the chip is accelerated.

Description

Technical Field

[0001] The present invention relates to the field of chip verification, and in particular to a chip verification method, device, medium and program product. Background Art

[0002] In IC (Integrated Circuit) design, Bring Up (BU) is the process of powering up a chip for the first time after production is complete, performing functional verification and debugging. This process is a crucial transition from theoretical design to practical application, primarily ensuring that the chip functions according to design specifications. Bring Up is a critical step in chip development, not only verifying the correctness of the hardware design but also ensuring seamless integration between hardware and software. A successful Bring Up is a prerequisite for the chip to smoothly enter mass production and market deployment. Currently, the Bring Up stage typically involves comprehensive testing of all chip functions, which is extremely time-consuming and resource-intensive, and may hinder the chip's progress in mass production and market deployment.

[0003] It can be seen that in the Bring Up stage, how to achieve purposeful and selective verification of the chip without the need for full coverage testing of all functions of the chip is a technical problem that technical personnel in this field need to solve. Summary of the Invention

[0004] The purpose of the embodiments of the present invention is to provide a chip verification method, device, medium, and program product. By constructing a weighted directed graph for the chips under test, this method enables targeted and selective chip verification, improving the efficiency and flexibility of chip verification and thereby accelerating the process of mass production and market application of chips. The specific implementation is as follows.

[0005] In a first aspect, the present invention provides a chip verification method, comprising: Construct an initial directed graph based on the components of the chip under test and the multi-level functional division of each component module; Setting weights for directed edges in the initial directed graph to obtain a target directed graph; the weight of the first directed edge in the target directed graph is zero, and the sum of the weights of the second directed edges corresponding to the same parent vertex is a preset value; the first directed edges include directed edges for connecting different component modules; the second directed edges are directed edges other than the first directed edges in the target directed graph; Based on the preset verification requirements, the corresponding path is searched from the target directed graph, and a verification target set is constructed according to the corresponding path to verify the chip under test.

[0006] Optionally, based on the components of the chip under test and the multi-level functional division of each component module, an initial directed graph is constructed, including: According to the multi-level functional division of the component modules, the component modules are multi-level classified to obtain a multi-level classification result; Based on the multi-level classification results of each component module, determine the vertices used to construct the initial directed graph; Using a preset connection rule, sequentially connect the vertices used to construct the initial directed graph to obtain the initial directed graph; The preset connection rules are rules constructed based on the usage order of each component module and the hierarchical relationship of each vertex.

[0007] Optionally, the component module includes an input channel; the multi-level classification result of the input channel includes a first-level classification result and other-level classification results of the input channel; The first-level classification result of the input channel includes at least one input interface, and different input interfaces are used to receive input information from different sources; The classification results of other levels of the input channel include a number of input interfaces obtained by classifying the classification results of the previous level of the input channel according to the first classification reference information; The first classification reference information includes any one or a combination of the transmission line type, information type and sender of the input information.

[0008] Optionally, the component module includes an output channel; the multi-level classification result of the output channel includes the first-level classification result of the output channel and the classification results of other levels; The first-level classification result of the output channel includes at least one output interface, and different output interfaces are used to output different types of output information; The classification results of other levels of the output channel include a number of output interfaces obtained by classifying the classification results of the previous level of the output channel according to the second classification reference information; The second classification reference information includes any one or a combination of the transmission line type, information type and receiver of the output information.

[0009] Optionally, the component module includes a configuration module, and the multi-level classification result of the configuration module includes a first-level classification result and other-level classification results of the configuration module; The first-level classification result of the configuration module is the result of classifying the configuration functions of the configuration module according to the parameter type of the configuration parameters. The first-level classification result of the configuration module includes a first configuration function regarding data parameters, a second configuration function regarding selection parameters, and a third configuration function regarding state machine parameters. The selection parameters are used to specify the direction of control branches in the chip. The classification results of other levels of the configuration module are obtained by classifying the classification results of the previous level of the configuration module according to the third classification reference information; The third category reference information includes parameter types and / or usage functions of configuration parameters.

[0010] Optionally, using a preset connection rule, sequentially connecting the vertices used to construct the initial directed graph to obtain the initial directed graph includes: Using the first vertex determined based on the multi-level classification result of the configuration module, a subgraph is constructed for each configuration function; each configuration function includes a first configuration function, a second configuration function, and a third configuration function; By using the preset connection rules and the order of use of each configuration function, each subgraph and the second vertex determined based on the multi-level classification results of the input channel and the output channel are sequentially connected to obtain an initial directed graph.

[0011] Optionally, a subgraph is constructed for each configuration function using the first vertex determined based on the multi-level classification result of the configuration module, including: Determine the vertex corresponding to any configuration function among the first vertices as the starting vertex; any configuration function is any function among the configuration functions; According to the hierarchical relationship of each vertex, the starting vertex, the intermediate vertex and the newly added return vertex are sequentially connected to construct a subgraph corresponding to any configuration function; Among them, the intermediate vertex is the vertex in the first vertex corresponding to the multi-level classification result of any configuration function; the multi-level classification result of any configuration function is the result obtained after multi-level classification of any configuration function; the return vertex represents the path returning to the starting vertex in the subgraph when it reaches the return vertex in the subgraph.

[0012] Optionally, the first directed edge further includes a directed edge in the target directed graph connected to the return vertex.

[0013] Optionally, the process of setting the weight of the second directed edge corresponding to the same parent vertex includes: Based on the importance of each child vertex corresponding to the same parent vertex, weights are set for the second directed edges between the same parent vertex and each child vertex, so that the sum of the weights of the second directed edges corresponding to the same parent vertex is a preset value.

[0014] Optionally, search for a corresponding path from the target directed graph based on preset verification requirements, including: Search the target directed graph for a corresponding path with the first preset vertex as the path starting point, the second preset vertex as the path ending point, and the path weight meeting the preset weight condition.

[0015] Optionally, the process of determining the path weight includes: The path weight of the corresponding path is determined based on the sum of the weights of the directed edges in the corresponding path.

[0016] Optionally, the preset weight condition includes any one or a combination of the following: the path weight is greater than a first preset weight threshold, the path weight is less than a second preset weight threshold, and the path weight is within a preset weight range.

[0017] In a second aspect, the present invention provides an electronic device, comprising: memory for storing computer programs; The processor is used to execute the computer program to implement the steps of the aforementioned chip verification method.

[0018] In a third aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the aforementioned chip verification method when executed by a processor.

[0019] In a fourth aspect, the present invention provides a computer program product, comprising a computer program / instruction, which implements the steps of the aforementioned chip verification method when executed by a processor.

[0020] In the present invention, an initial directed graph is constructed based on the component modules of the chip to be tested and the multi-level functional division of each component module; weights are set for the directed edges in the initial directed graph to obtain a target directed graph; the weight of the first directed edge in the target directed graph is zero, and the sum of the weights of the second directed edges corresponding to the same parent vertex is a preset value; the first directed edge includes directed edges for connecting different component modules; the second directed edge is other directed edges in the target directed graph except the first directed edge; based on the preset verification requirements, a corresponding path is searched from the target directed graph, and a verification target set is constructed according to the corresponding path to verify the chip to be tested.

[0021] Beneficial effects: The present invention constructs an initial directed graph based on the various component modules of the chip to be tested and the multi-level functional division of each component module, and sets weights for the directed edges in the initial directed graph according to the zero weight setting of the directed edges and the rule that the sum of the weights of the directed edges corresponding to the same parent vertex is equal to the preset value, so as to obtain a target directed graph, and then searches for the corresponding path from the target directed graph according to the preset verification requirements, and constructs a verification target set that meets the user's needs based on the corresponding path, so as to purposefully and selectively select verification targets for the chip to be tested, and realize verification of the chip to be tested. It can be seen that compared with the full coverage test of all functions of the chip in the Bring Up stage, the present invention can realize purposeful and selective verification of the chip, improve the efficiency and flexibility of chip verification, and thus accelerate the process of the chip entering mass production and market application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0023] Figure 1 A flow chart of a chip verification method provided by an embodiment of the present invention; Figure 2 A schematic diagram of a multi-level classification result of an input channel provided by an embodiment of the present invention; Figure 3 A schematic diagram of a multi-level classification result of an output channel provided by an embodiment of the present invention; Figure 4 A schematic diagram of a multi-level classification result of a configuration module provided by an embodiment of the present invention; Figure 5 A schematic diagram of a directed edge weight relationship provided by an embodiment of the present invention; Figure 6 A schematic diagram of a weighted directed graph of a chip to be tested provided by an embodiment of the present invention; Figure 7 A structural diagram of an electronic device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0025] The terms "including" and "having," as used in the present description and accompanying drawings, and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements and may include steps or elements that are not listed.

[0026] In order to enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0027] Bring Up is a very critical step in chip development. It not only verifies the correctness of the hardware design, but also ensures the seamless integration of hardware and software. A successful Bring Up is a prerequisite for the chip to smoothly enter mass production and market application. At present, in the Bring Up stage, all functions of the chip are usually fully tested, which is very time-consuming and resource-consuming, and may affect the process of the chip entering mass production and market application. To this end, the present invention provides a chip verification method. By constructing a weighted directed graph for the chip to be tested, it is possible to achieve purposeful and selective verification of the chip, improve the efficiency and flexibility of chip verification, and thus accelerate the process of the chip entering mass production and market application.

[0028] See also Figure 1 As shown, an embodiment of the present invention provides a chip verification method, including: Step S11: construct an initial directed graph based on the component modules of the chip to be tested and the multi-level functional division of each component module.

[0029] An embodiment of the present invention divides the component structure of a chip IP (Intellectual Property, a hardware description language program with specific circuit functions, which is independent of the integrated circuit process and can be ported to different semiconductor processes to produce integrated circuit chips) from the perspective of application development to obtain the component modules of the chip under test. The multi-level functional division of the component modules of the chip under test is determined from a category perspective according to the BU requirements. Then, the chip functional flow is utilized and based on the component modules of the chip under test and the multi-level functional division of each component module, an initial directed graph is constructed for the chip under test.

[0030] Specifically, the embodiment of the present invention performs multi-level classification on the component modules according to the multi-level functional division of the component modules of the chip to be tested to obtain a multi-level classification result; based on the multi-level classification results of each component module, the vertices used to construct the initial directed graph are determined; and using preset connection rules, the vertices used to construct the initial directed graph are sequentially connected to obtain the initial directed graph.

[0031] The preset connection rule is a connection rule constructed based on the usage order of each component module and the hierarchical relationship of each vertex. It should be noted that the hierarchical relationship of each vertex corresponds to the multi-level classification result of the component modules.

[0032] According to one specific example, the component module of the chip to be tested includes an input channel, and the multi-level classification results of the input channel include the first-level classification results of the input channel and other-level classification results; specifically, the first-level classification results of the input channel include at least one input interface, and different input interfaces are used to receive input information from different sources; the other-level classification results of the input channel include several input interfaces obtained after classifying the previous-level classification results of the input channel according to the first classification reference information.

[0033] That is, the second-level classification results of the input channel include several input interfaces obtained after classifying the first-level classification results of the input channel according to the first classification reference information, and the third-level classification results of the input channel include several input interfaces obtained after classifying the second-level classification results of the input channel according to the first classification reference information. And so on, multi-level classification results of the input channel can be obtained.

[0034] The first classification reference information includes any one or a combination of the transmission line type, information type and sender of the input information, and may also include other reference information of the input information, which is not specifically limited here.

[0035] For example, the transmission line types for input information include, but are not limited to, the AMBA (Advanced Microcontroller Bus Architecture) bus, the I2C (Inter-Integrated Circuit) bus, and the SPI (Serial Peripheral Interface) bus. The AMBA bus further includes four different bus types: AHB (Advanced High-Performance Bus), ASB (Advanced System Bus), APB (Advanced Peripheral Bus), and AXI (Advanced eXtensible Interface). Input information types include, but are not limited to, reset information, clock information, debug information, and bus information. The senders of input information include, but are not limited to, clock sources, bus devices, debug devices, and reset devices.

[0036] by Figure 2For example, for the first-level classification results of the input channel, the input channel can be divided into the following four types of interfaces according to the different sources of the input information: bus input interface, debug input interface, global reset input interface and clock input interface, that is, these four types of interfaces are used to receive input information from different sources. Among them, the bus input interface is the most important input source of the chip IP and the core foundation for the realization of IP functions. In the current chip design, the AMBA bus is the mainstream solution; the debug input interface is used for the debug access input of the chip IP and can be used as a direct configuration and test interface for the internal registers and memories of the IP; the global reset input interface is used to globally reset the IP; the clock input interface is used to provide a clock signal for the chip IP, mainly to provide a stable timing reference for the internal operations of the chip IP. It should be noted that the embodiment of the present invention can also continue to divide the input channel to a deeper level based on the first classification reference information.

[0037] According to another specific example, the constituent module of the chip to be tested includes an output channel, and the multi-level classification results of the output channel include the first-level classification results and other-level classification results of the output channel; specifically, the first-level classification results of the output channel include at least one output interface, and different output interfaces are used to output different types of output information; other-level classification results of the output channel include several output interfaces obtained after classifying the previous-level classification results of the output channel according to the second classification reference information.

[0038] That is, the second-level classification results of the output channel include several output interfaces obtained after classifying the first-level classification results of the output channel according to the second classification reference information, and the third-level classification results of the output channel include several output interfaces obtained after classifying the second-level classification results of the output channel according to the second classification reference information. And so on, multi-level classification results of the output channel can be obtained.

[0039] The second category reference information includes any one or a combination of the transmission line type, information type and receiver of the output information, and may also include other reference information of the output information, which is not specifically limited here.

[0040] For example, the transmission line types for output information include, but are not limited to, the AMBA bus, PCIe (Peripheral Component Interconnect express, a high-speed serial computer expansion bus standard), and USB (Universal Serial Bus). Output information types include, but are not limited to, normal output information and abnormal output information. Normal output information includes debug output information, interrupt output information, and status output information, while abnormal output information includes fatal exception output information, correctable exception output information, and uncorrectable exception output information. Recipients of output information include, but are not limited to, other IP addresses within the chip, devices external to the chip, the interrupt controller of the chip's internal processor, internal chip registers, and external chip registers.

[0041] by Figure 3 For example, for the first-level classification results of the output channel, the output channel can be specifically divided into the following two types of interfaces according to the information type of the output information: normal output interface and abnormal output interface. For the second-level classification results of the output channel, the normal output interface can be specifically divided into the following five types of interfaces according to the second classification reference information: bus output interface, protocol output interface, debug output interface, interrupt output interface, normal state output interface, and the abnormal output interface can be divided into the following three types of interfaces: fatal abnormal output interface, correctable abnormal output interface, and uncorrectable abnormal output interface. It should be noted that the embodiment of the present invention can also continue to divide the output channel to a deeper level according to the second classification reference information.

[0042] The bus output interface refers to the chip IP's internal output interface, used to output IP data processing results to other chip IPs. It typically uses an AMBA bus interface, such as a DMA (Direct Memory Access) controller to write data to RAM (Random Access Memory). The protocol output interface refers to the chip IP's external output interface, used to encode the IP's data processing results according to the implemented communication protocol and output them externally through chip pins, such as PCIe bus output or USB bus output. The debug output interface refers to the output interface for debug trace data within the chip IP. This can be implemented in various ways, such as using a bus output interface to output debug trace data to a dedicated debug trace unit or directly to chip pins via GPIO (General-Purpose Input / Output). The interrupt output interface allows the chip IP to output important status information to the interrupt controller of the internal chip processor in the form of an interrupt. The normal status output interface allows the chip IP to output important status information to internal registers or registers in external global units for access by other chip IPs.

[0043] Among them, the fatal exception output interface is used to output fatal exception information. Fatal exception information refers to error information that directly causes the functional state machine to stop abnormally, such as AXI access exceptions. The correctable exception output interface is used to output correctable exception information. Correctable exception information refers to information that only prompts the occurrence of an exception but does not affect the execution of the functional state machine. For example, the register value boundary configuration exceeds the boundary, but after the IP detects the error, it will be used according to the error correction boundary and will only prompt a configuration error. The uncorrectable exception output interface is used to output uncorrectable exception information. Uncorrectable exception information refers to information that not only prompts the occurrence of an exception, but also the IP itself cannot correct it. It does not affect the execution of the functional state machine, but the execution result will have data abnormal information. For example, when DMA writes data, a checksum exception is prompted, but the data can still be written, but the written data is different from the expectation.

[0044] According to another specific example, the constituent modules of the chip to be tested include a configuration module, and the multi-level classification results of the configuration module include the first-level classification results and other-level classification results of the configuration module; specifically, the first-level classification results of the configuration module are the results obtained after classifying the configuration functions of the configuration module according to the parameter types of the configuration parameters; the first-level classification results of the configuration module include a first configuration function regarding data parameters, a second configuration function regarding selection parameters, and a third configuration function regarding state machine parameters; the selection parameters are used to specify the direction of control branches in the chip; other-level classification results of the configuration module are the results obtained after classifying the previous-level classification results of the configuration module according to the third classification reference information.

[0045] That is, the second-level classification result of the configuration module is the result obtained by classifying the first-level classification result of the configuration module according to the third classification reference information, and the third-level classification result of the configuration module is the result obtained by classifying the second-level classification result of the configuration module according to the third classification reference information. By analogy, multi-level classification results of the configuration module can be obtained.

[0046] The third category reference information includes the parameter type and / or usage function of the configuration parameter, and of course may also include other reference information of the configuration parameter, which is not specifically limited here.

[0047] by Figure 4For example, from the perspective that configuration parameters include data parameters and control parameters, and control parameters include selection parameters and state machine parameters, for the first-level classification results of the configuration module, the configuration functions of the configuration module can be divided into the following three categories according to the parameter type of the configuration parameters: the first configuration function regarding data parameters, the second configuration function regarding selection parameters, and the third configuration function regarding state machine parameters. For the second-level classification results of the configuration module, the first configuration function regarding data parameters can be divided into the following three categories according to the third classification reference information: the configuration function regarding parameter intervals, the configuration function regarding buffer parameters, and the configuration function regarding clock source parameters, and the second configuration function regarding selection parameters can be divided into the following five categories: the configuration function regarding priority selection, the configuration module regarding read and write direction selection, the configuration function regarding channel selection, the configuration function regarding mode selection, and the configuration function regarding explicit selection, and the third configuration function regarding state machine parameters can be divided into the following four categories: the configuration function regarding start / enable, the configuration function regarding pause, the configuration function regarding reset, and the configuration function regarding completion / idle. Regarding the third-level classification results of the configuration module, the configuration functions regarding parameter intervals can be specifically divided into the following three categories based on the third classification reference information: configuration functions regarding random parameters, configuration functions regarding boundary parameters, and configuration functions regarding branch parameters; the configuration functions regarding buffer parameters can be divided into the following three categories: configuration functions regarding position parameters, configuration functions regarding size parameters, and configuration functions regarding full and empty parameters; and the configuration functions regarding clock source parameters can be divided into the following two categories: configuration functions regarding source parameters and configuration functions regarding frequency division parameters. It should be noted that the embodiment of the present invention can further divide the configuration module into deeper levels based on the third classification reference information.

[0048] Among them, data parameters are used to configure the data processing functions in the data processing module of the chip under test; selection parameters are used to specify the direction of the control branch in the chip under test; state machine parameters are used to configure the functional state machine of the chip under test. The functional state machine is an abstraction of the overall operation control of the chip IP, and does not specifically refer to the specific state machine in the implementation of the IP hardware code. The overall operation control here mainly refers to the core external output function of the chip IP, such as the read and write data output functions of the DMA controller, and the IO (Input / Output) read and write output of the SSD (Solid State Disk).

[0049] Data parameters include parameter intervals, buffer parameters, and clock source parameters. Parameter intervals abstractly represent data processing function configurations with interval-sized characteristics, such as the number of IP channels and queue depth. Based on their characteristics, parameter intervals can be further categorized into three types: random parameters, boundary parameters, and branch parameters. Random parameters and boundary parameters refer to the selection of random and boundary values ​​within the parameter interval, respectively. Branch parameters are key parameters that change the branching behavior of the IP data processing module.

[0050] Buffer parameters abstract the configuration of memory areas used within chip IP, such as FIFOs (First Input First Output), buffers, and queues. Buffer parameters can be further categorized into three categories based on their characteristics: location parameters, size parameters, and full / empty parameters. Location parameters configure whether the memory area is located inside or outside the IP; size parameters configure the size of the memory area; and full / empty parameters configure the memory area's characteristics, such as empty, half-full, full, or watermark.

[0051] Clock source parameters abstract clock input configurations. Based on their characteristics, they can be simplified into two categories: source parameters and frequency division parameters. Source parameters configure the internal clock tree the clock originates from, while frequency division parameters configure the chip IP's operating frequency division.

[0052] Selection parameters abstract functional configurations that specify the direction of control branches. Based on their characteristics, selection parameters can be simplified into the following five categories: priority selection, read / write direction selection, channel selection, mode selection, and explicit selection. Priority selection specifies the priority or arbitration mode of a control branch; read / write direction selection specifies the destination direction of the IP's data flow, such as the read and write directions of DMA; channel selection specifies the working channel number for multi-channel or multi-engine IP; mode selection specifies the relevant transmission mode within the data flow; and explicit mode specifies the masking characteristics of indicative parameters such as status and interrupts.

[0053] In addition, state machine parameters can be simplified into the following four categories: start / enable, pause, reset, and complete / idle. Among them, start / enable is used to control the start / enable of the functional state machine; pause is used to control the pause of the functional state machine; reset is used to control the reset of the functional state machine; complete / idle is used to control the end of the functional state machine to put the functional state machine in the complete / idle state.

[0054] After determining the vertices used to construct the initial directed graph based on the multi-level classification results of the component modules of the chip to be tested, the first vertex determined based on the multi-level classification results of the configuration module can be used to construct a subgraph for each configuration function; wherein each configuration function includes a first configuration function, a second configuration function and a third configuration function; then, using the preset connection rules and the order in which each configuration function is used, each subgraph and the second vertex determined based on the multi-level classification results of the input channel and the output channel are sequentially connected to obtain the initial directed graph.

[0055] Among them, the multi-level classification results of the configuration module include the first-level classification results and other-level classification results of the configuration module, and the first-level classification results of the configuration module include the first configuration function about the data parameters, the second configuration function about the selection parameters and the third configuration function about the state machine parameters, and the other-level classification results of the configuration module are the results obtained after classifying the previous-level classification results of the configuration module according to the third classification reference information. It can also be understood that the other-level classification results of the configuration module include the multi-level classification results of the first configuration function about the data parameters, the multi-level classification results of the second configuration function about the selection parameters and the multi-level classification results of the third configuration function about the state machine parameters.

[0056] Based on this, for any configuration function among the first configuration function, the second configuration function and the third configuration function, the corresponding subgraph construction process can specifically include: determining the vertex in the first vertex corresponding to any configuration function as the starting vertex; according to the hierarchical relationship of each vertex, sequentially connecting the starting vertex, the intermediate vertex and the newly added return vertex to construct a subgraph corresponding to any configuration function; wherein the intermediate vertex is the vertex in the first vertex corresponding to the multi-level classification result of any configuration function; the multi-level classification result of any configuration function is the result obtained after multi-level classification of any configuration function; the return vertex represents that the path returns to the starting vertex in the subgraph when it reaches the return vertex in the subgraph.

[0057] After constructing the subgraphs corresponding to the first configuration function, the second configuration function, and the third configuration function respectively, based on the usage order of input channel->configuration module->output channel, the usage order of second configuration function->first configuration function->third configuration function, and the hierarchical relationship of each vertex, the second vertex determined based on the multi-level classification result of the input channel, the second vertex determined based on the multi-level classification result of the output channel, and each subgraph are sequentially connected to construct an initial directed graph for the chip to be tested.

[0058] Step S12, setting weights for the directed edges in the initial directed graph to obtain a target directed graph; the weight of the first directed edge in the target directed graph is zero, and the sum of the weights of the second directed edges corresponding to the same parent vertex is a preset value; the first directed edge includes a directed edge for connecting different component modules; the second directed edge is the other directed edges in the target directed graph except the first directed edge.

[0059] In an embodiment of the present invention, after constructing an initial directed graph for the chip to be tested, it is necessary to further set weights for each directed edge in the initial directed graph to convert the initial directed graph into a weighted directed graph, thereby obtaining a target directed graph.

[0060] The step of setting a weight for each directed edge in the initial directed graph specifically includes setting the weights of the directed edges in the initial directed graph that connect different modules and the directed edges connected to the return vertex to zero. That is, the weight of the first directed edge in the target directed graph is zero, and the first directed edge includes not only the directed edges that connect different modules but also the directed edge connected to the return vertex.

[0061] In this way, the embodiment of the present invention proposes a zero weight setting rule. On the one hand, the connecting directed edges of the component modules on the necessary path when the chip starts running are set to zero weight. On the other hand, the directed edges connected to the return vertex are set to zero weight. By setting the directed edges to zero weight, it only plays the role of path connection in the forward reasoning of the weighted directed graph.

[0062] The step of setting a weight for each directed edge in the initial directed graph specifically includes setting weights for directed edges corresponding to the same parent vertex in the initial directed graph, except for directed edges with zero weight, so that the sum of the weights of the directed edges corresponding to the same parent vertex equals a preset value. That is, for directed edges in the target directed graph except for the first directed edge, which are denoted as second directed edges, the sum of the weights of the second directed edges corresponding to the same parent vertex in the target directed graph equals the preset value.

[0063] According to one example, the process of setting the weight of the second directed edge corresponding to the same parent vertex in the target directed graph can specifically include: based on the importance of each child vertex corresponding to the same parent vertex, setting the weight of the second directed edge between the same parent vertex and each child vertex, so that the sum of the weights of the second directed edges corresponding to the same parent vertex is a preset value.

[0064] Specifically, the importance of each child vertex is determined based on the chip composition or function, its importance to chip operation, frequency of use, and the impact of a failure on the chip, as reflected by each child vertex corresponding to the same parent vertex. The sum of the importance of each child vertex is then determined. The degree ratio of each child vertex is then determined based on the ratio of the importance of each child vertex to the sum. The degree ratio of each child vertex is then multiplied by 10 to obtain the weight of the second directed edge between the same parent vertex and each child vertex. For example, suppose that the importance of the two child vertices S1 and S2 corresponding to parent vertex F is 4 and 8, respectively. In this case, the sum of the importance of these two child vertices is 12. Then, based on the ratio of S1's importance to the sum, the degree ratio of S1 is determined to be 0.33, and based on the ratio of S2's importance to the sum, the degree ratio of S2 is determined to be 0.67. The degree ratios of each child vertex are then multiplied by 10 to obtain the weights of the second directed edges between parent vertex F and its two child vertices S1 and S2, respectively, as 3.3 and 6.7.

[0065] Take the preset value equal to 10 as an example, Figure 5 As shown, vertex F is the parent vertex of vertex S1 and vertex S2, and accordingly, vertex S1 and vertex S2 are the child vertices of vertex F. is the weight of the directed edge between vertex F and vertex S1, is the weight of the directed edge between vertex F and vertex S2, which needs to be satisfied at this time Vertex S1 is the parent vertex of vertex S1W1 and vertex S1W2. Correspondingly, vertex S1W1 and vertex S1W2 are the child vertices of vertex S1. is the weight of the directed edge between vertex S1 and vertex S1W1, is the weight of the directed edge between vertex S1 and vertex S1W2, which needs to be satisfied at this time Vertex S2 is the parent vertex of vertex S2W1, vertex S2W2, and vertex S2W3. Correspondingly, vertex S2W1, vertex S2W2, and vertex S2W3 are the child vertices of vertex S2. is the weight of the directed edge between vertex S2 and vertex S2W1, is the weight of the directed edge between vertex S2 and vertex S2W2, is the weight of the directed edge between vertex S2 and vertex S2W3, which needs to be satisfied at this time .

[0066] Taking the preset value equal to 10, and the components of the chip under test including input channels, configuration modules and output channels as an example, the weighted directed graph of the chip under test is constructed according to the above steps. The final weighted directed graph is as follows: Figure 6 It should be noted that Figure 6This is only a specific example of an embodiment of the present invention, not the only example, and there are certainly other situations.

[0067] Step S13: searching for corresponding paths from the target directed graph based on preset verification requirements, and constructing a verification target set according to the corresponding paths to verify the chip to be tested.

[0068] In an embodiment of the present invention, after constructing a target directed graph for the chip to be tested, a preset verification requirement input by a user terminal or a pre-configured preset verification requirement is obtained, and then a corresponding path is searched from the target directed graph based on the preset verification requirement, and a verification target set is constructed according to the corresponding path to verify the chip to be tested using the verification target set.

[0069] The preset verification requirement is a verification requirement constructed based on preset vertices and preset weight conditions. Specifically, searching for a corresponding path from the target directed graph based on the preset verification requirement may include searching for a corresponding path from the target directed graph with a first preset vertex as the path starting point, a second preset vertex as the path ending point, and a path weight that satisfies the preset weight condition.

[0070] The process of determining a path weight may specifically include determining the path weight of a path based on the sum of the weights of all directed edges in the path. For example, if a path is A->B->C, where the weight of the directed edge between A->B is 5 and the weight of the directed edge between B->C is 3, the path weight of the path is 8.

[0071] In an embodiment of the present invention, the preset weight condition includes any one or a combination of the following: the path weight is greater than a first preset weight threshold, the path weight is less than a second preset weight threshold, and the path weight is within a preset weight range. The first preset weight threshold, the second preset weight threshold, and the preset weight range can be set based on actual chip verification requirements.

[0072] For example, the preset weight conditions may include a path weight greater than 8, a path weight less than 12, a path weight between 8-12, a path weight less than 8, or a path weight greater than 12, etc., and no further examples are given here.

[0073] Beneficial effects: The present invention constructs an initial directed graph based on the various component modules of the chip to be tested and the multi-level functional division of each component module, and sets weights for the directed edges in the initial directed graph according to the zero weight setting of the directed edges and the rule that the sum of the weights of the directed edges corresponding to the same parent vertex is equal to the preset value, so as to obtain a target directed graph, and then searches for the corresponding path from the target directed graph according to the preset verification requirements, and constructs a verification target set that meets the user's needs based on the corresponding path, so as to purposefully and selectively select verification targets for the chip to be tested, and realize verification of the chip to be tested. It can be seen that compared with the full coverage test of all functions of the chip in the Bring Up stage, the present invention can realize purposeful and selective verification of the chip, improve the efficiency and flexibility of chip verification, and thus accelerate the process of the chip entering mass production and market application.

[0074] Furthermore, the embodiment of the present application also discloses an electronic device, Figure 7 This is a block diagram of an electronic device according to an exemplary embodiment. The content in the diagram should not be considered as limiting the scope of use of this application. The electronic device may specifically include: at least one processor 11, at least one memory 12, a power supply 13, a communication interface 14, an input / output interface 15, and a communication bus 16. The memory 12 is used to store a computer program, which is loaded and executed by the processor 11 to implement the relevant steps in the chip verification method disclosed in any of the aforementioned embodiments. In addition, the electronic device in this embodiment may specifically be an electronic computer.

[0075] In this embodiment, the power supply 13 is used to provide operating voltage for various hardware devices on the electronic device; the communication interface 14 can create a data transmission channel between the electronic device and external devices. The communication protocol it follows is any communication protocol that can be applied to the technical solution of this application and is not specifically limited here; the input and output interface 15 is used to obtain external input data or output data to the outside world. Its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0076] In addition, the memory 12, as a carrier for resource storage, can be a read-only memory, random access memory, disk or CD, etc. The resources stored thereon can include an operating system 121, a computer program 122, etc., and the storage method can be temporary storage or permanent storage.

[0077] The operating system 121 is used to manage and control the hardware devices on the electronic device and the computer program 122, and can be Windows Server, NetWare, Unix, Linux, etc. In addition to including a computer program capable of performing the chip verification method performed by the electronic device disclosed in any of the aforementioned embodiments, the computer program 122 can further include a computer program capable of performing other specific tasks.

[0078] Furthermore, this application also discloses a computer-readable storage medium for storing a computer program; wherein, when executed by a processor, the computer program implements the aforementioned chip verification method. The specific steps of this method can be referred to the corresponding contents disclosed in the aforementioned embodiments and will not be repeated here.

[0079] Furthermore, this application also discloses a computer program product, including a computer program / instructions, wherein when executed by a processor, the computer program / instructions implement the aforementioned chip verification method. The specific steps of this method can be referred to the corresponding contents disclosed in the aforementioned embodiments and will not be repeated here.

[0080] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Reference can be made to the descriptions of the identical or similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the methods.

[0081] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0082] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0083] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0084] The above is a detailed introduction to the technical solution provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only applicable to help understand the method of the present application and its core ideas. At the same time, for those skilled in the art, according to the ideas of the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A chip verification method, characterized in that: include: Constructing an initial directed graph based on the components of the chip to be tested and the multi-level functional division of the components; Setting weights for directed edges in the initial directed graph to obtain a target directed graph; the weight of a first directed edge in the target directed graph is zero, and the sum of the weights of second directed edges corresponding to the same parent vertex is a preset value; the first directed edges include directed edges for connecting different component modules; the second directed edges are directed edges in the target directed graph other than the first directed edges; Based on preset verification requirements, corresponding paths are searched from the target directed graph, and a verification target set is constructed according to the corresponding paths to verify the chip to be tested.

2. The chip verification method according to claim 1, characterized in that: The initial directed graph is constructed based on the component modules of the chip to be tested and the multi-level functional division of each component module, including: According to the multi-level functional division of the component modules, the component modules are subjected to multi-level classification to obtain a multi-level classification result; Determining vertices for constructing the initial directed graph based on the multi-level classification results of each of the component modules; Using a preset connection rule, sequentially connecting the vertices used to construct the initial directed graph to obtain the initial directed graph; The preset connection rule is a rule constructed based on the usage order of each component module and the hierarchical relationship of each vertex.

3. The chip verification method according to claim 2, characterized in that: The component module includes an input channel; the multi-level classification result of the input channel includes the first-level classification result and other-level classification results of the input channel; The first-level classification result of the input channel includes at least one input interface, and different input interfaces are used to receive input information from different sources; The other level classification results of the input channel include a number of input interfaces obtained by classifying the previous level classification results of the input channel according to the first classification reference information; The first classification reference information includes any one or a combination of the transmission line type, information type and sender of the input information.

4. The chip verification method according to claim 3, characterized in that: The component module includes an output channel; the multi-level classification result of the output channel includes the first-level classification result and other-level classification results of the output channel; The first-level classification result of the output channel includes at least one output interface, and different output interfaces are used to output different types of output information; The other level classification results of the output channel include a plurality of output interfaces obtained by classifying the previous level classification results of the output channel according to the second classification reference information; The second classification reference information includes any one or a combination of the transmission line type of the output information, the information type and the receiver.

5. The chip verification method according to claim 4, characterized in that: The composition module includes a configuration module, and the multi-level classification results of the configuration module include the first-level classification results and other-level classification results of the configuration module; The first-level classification result of the configuration module is a result obtained by classifying the configuration functions of the configuration module according to the parameter type of the configuration parameters; the first-level classification result of the configuration module includes a first configuration function regarding data parameters, a second configuration function regarding selection parameters, and a third configuration function regarding state machine parameters; the selection parameters are used to specify the direction of control branches in the chip; The classification results of the other levels of the configuration module are obtained by classifying the classification results of the previous level of the configuration module according to the third classification reference information; The third classification reference information includes parameter types and / or usage functions of configuration parameters.

6. The chip verification method according to claim 5, characterized in that: The method of sequentially connecting the vertices used to construct the initial directed graph using a preset connection rule to obtain the initial directed graph includes: Using the first vertex determined based on the multi-level classification result of the configuration module, constructing a subgraph for each configuration function; the configuration functions include the first configuration function, the second configuration function and the third configuration function; Using a preset connection rule and the order of use of the configuration functions, the subgraphs and the second vertices determined based on the multi-level classification results of the input channels and the output channels are sequentially connected to obtain the initial directed graph.

7. The chip verification method according to claim 6, characterized in that: The method of constructing a subgraph for each configuration function using the first vertex determined based on the multi-level classification result of the configuration module includes: Determine a vertex corresponding to any configuration function among the first vertices as a starting vertex; the any configuration function is any one of the configuration functions; According to the hierarchical relationship of each vertex, the starting vertex, the intermediate vertices and the newly added return vertex are sequentially connected to construct a subgraph corresponding to any one of the configuration functions; Among them, the intermediate vertex is the vertex in the first vertex corresponding to the multi-level classification result of any configuration function; the multi-level classification result of any configuration function is the result obtained after multi-level classification of any configuration function; the return vertex represents the path returning to the starting vertex in the subgraph when it reaches the return vertex in the subgraph.

8. The chip verification method according to claim 7, characterized in that: The first directed edge further includes a directed edge in the target directed graph connected to the return vertex.

9. The chip verification method according to claim 1, characterized in that: The process of setting the weight of the second directed edge corresponding to the same parent vertex includes: Based on the importance of each child vertex corresponding to the same parent vertex, weights are set for the second directed edges between the same parent vertex and the child vertices, so that the sum of the weights of the second directed edges corresponding to the same parent vertex is a preset value.

10. The chip verification method according to any one of claims 1 to 9, characterized in that: The searching for a corresponding path from the target directed graph based on a preset verification requirement includes: Search the target directed graph for a corresponding path having a first preset vertex as a path starting point, a second preset vertex as a path end point, and a path weight that satisfies a preset weight condition.

11. The chip verification method according to claim 10, characterized in that: The process of determining path weights includes: A path weight of the corresponding path is determined based on the sum of the weights of the directed edges in the corresponding path.

12. The chip verification method according to claim 11, characterized in that: The preset weight conditions include any one or a combination of the following: the path weight is greater than a first preset weight threshold, the path weight is less than a second preset weight threshold, and the path weight is within a preset weight range.

13. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the chip verification method according to any one of claims 1 to 12.

14. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the chip verification method according to any one of claims 1 to 12 are implemented.

15. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the steps of the chip verification method according to any one of claims 1 to 12 are implemented.

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