Chip layout correction method, medium, product and device

Abstract

The application provides a chip layout correction method, medium, product and equipment. The method comprises the following steps: grouping target layout patterns in a chip layout based on pattern characteristics to obtain target pattern groups to be optimized; using optimization agents corresponding to the target pattern groups to optimize the target layout patterns to obtain optimized layout patterns, each optimization agent being set corresponding to a target pattern group; collecting the optimized layout patterns meeting an expected specification to obtain a result set; adjusting the layout patterns in the result set through a mask generation model to obtain mask data corresponding to each layout pattern, the mask generation model being used for mapping design target patterns corresponding to the chip layout into mask data. This method can use different optimization agents to make the corresponding layout patterns obtain targeted optimization, and convert the optimized layout patterns into mask data through the mask generation model, so that the layout patterns adapt to the photolithography process requirements.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a chip layout correction method, medium, product and device. BACKGROUND

[0002] In the current technical field of semiconductor technology, due to the complexity of the layout, the OPC (Optical Proximity Correction) software cannot solve the optimization problem of all patterns with a general parameter. In the practical process of developing and optimizing the OPC Recipe (a technical scheme for correcting the corresponding lithographic image under a given OPC tool software), engineers mainly do two things. The first is to define complex rules using script commands to select corresponding patterns and try to maintain universality to cope with possible new chip design layouts; the second is to try to find better Recipe parameters such as cut edge division, evaluation point placement, etc. for corresponding patterns and make special processing. The reason why OPC Recipe development and optimization are difficult and require a long time is that both of them need to be iterated repeatedly and require considerable experience of engineers.

[0003] And with the continuous improvement of the current domestic chip factory (Fabrication Plant, referred to as FAB) capacity and the migration to advanced nodes, it is difficult for FAB to maintain a strong OPC team to face the challenges of expanding OPC Recipe development and optimization. How to use less manpower to give a solution more quickly and effectively, and to effectively deposit experience in the FAB during the iteration process instead of losing past experience with possible personnel flow is a difficult problem currently faced by FAB. SUMMARY

[0004] In view of the above problems, the present application provides a chip layout correction method, medium, product and device which can overcome the above problems or at least partially solve the above problems.

[0005] An object of the present application is to improve the correction efficiency of the chip layout.

[0006] Another further object of the present application is to reduce the manpower required in the chip layout correction process and the complexity of each optimization agent.

[0007] In particular, the present application provides a chip layout correction method, comprising:

[0008] grouping the to-be-optimized layout patterns in the chip layout based on pattern features, thereby obtaining a target pattern grouping to be optimized;

[0009] optimizing the to-be-optimized layout graph by using the optimization agent corresponding to the target graph group to obtain an optimized layout graph, each optimization agent being set up in correspondence with a group of target graph groups and being configured to optimize the to-be-optimized layout graph in the corresponding target graph group based on the graph features of the target graph group;

[0010] collecting the optimized layout graphs that meet the expected specification to obtain a result set;

[0011] adjusting the layout graphs in the result set by using a mask generation model to obtain mask data corresponding to each layout graph, the mask generation model being used to map the design target graph corresponding to the chip layout into the mask data.

[0012] Optionally, the step of optimizing the to-be-optimized layout graph by using the optimization agent corresponding to the target graph group to obtain an optimized layout graph is followed by:

[0013] grouping the optimized layout graphs that do not meet the expected specification again by using a precise graph grouping algorithm to obtain precise graph groups;

[0014] optimizing the optimized layout graphs again by using a precise graph optimization agent corresponding to the precise graph group to obtain a second optimized layout graph, each precise graph optimization agent being set up in correspondence with a group of precise graph groups and being configured to optimize the optimized layout graph in the corresponding precise graph group based on a specific graph in the precise graph group;

[0015] collecting the second optimized layout graphs that meet the expected specification into the result set.

[0016] Optionally, the step of optimizing the optimized layout graphs again by using a precise graph optimization agent corresponding to the precise graph group to obtain a second optimized layout graph is followed by:

[0017] in the case where there are second optimized layout graphs that do not meet the expected specification, collecting the second optimized layout graphs that do not meet the expected specification into a target graph set;

[0018] adjusting the design target graph corresponding to the second optimized layout graph in the target graph set so that it meets the condition of optical proximity correction convergence;

[0019] re-executing the step of grouping the to-be-optimized layout graph in the chip layout based on the graph features according to the second optimized layout graph in the adjusted target graph set.

[0020] Optionally, the step of grouping the to-be-optimized layout patterns in the chip layout based on the layout pattern features comprises:

[0021] determining design target patterns and expected specifications corresponding to the entire chip layout;

[0022] performing preliminary general optimization on the entire chip layout to obtain preliminary general optimization results;

[0023] in a case where there are layout patterns in the preliminary general optimization results that do not meet the expected specifications, obtaining the layout patterns that do not meet the expected specifications as the to-be-optimized layout patterns.

[0024] Optionally, the step of grouping the to-be-optimized layout patterns in the chip layout based on the layout pattern features comprises:

[0025] obtaining a grouping agent, the grouping agent being configured to group the to-be-optimized layout patterns according to the layout pattern features;

[0026] grouping the to-be-optimized layout patterns by using the grouping agent, thereby obtaining the target pattern groups to be optimized.

[0027] Optionally, the step of grouping the to-be-optimized layout patterns in the chip layout based on the layout pattern features comprises:

[0028] grouping the to-be-optimized layout patterns that do not meet the expected specifications by using a preset algorithm, thereby obtaining the target pattern groups to be optimized, the preset algorithm being a fuzzy pattern grouping algorithm or an accurate pattern grouping algorithm, the fuzzy pattern grouping algorithm being configured to classify the layout patterns according to the layout pattern features, and the accurate pattern grouping algorithm being configured to group the to-be-optimized layout patterns according to preset target patterns.

[0029] Optionally, the step of adjusting the result set by using the mask production model to obtain mask data corresponding to each of the to-be-optimized layout patterns further comprises:

[0030] determining whether the adjusted mask data meets preset convergence requirements;

[0031] if not, further modifying the adjusted mask data by using preset general optical proximity correction parameters to obtain mask data that meets the preset convergence requirements.

[0032] According to another aspect of the present application, there is also provided a computer readable storage medium having a computer program stored thereon, the computer program being configured to implement the steps of the chip layout modification method of any of the above when executed by a processor.

[0033] According to still another aspect of the present application, there is also provided a computer program product comprising a computer program which, when executed by a processor, implements the steps of any of the above chip layout modification methods.

[0034] According to still another aspect of the present application, there is also provided a computer device comprising a memory, a processor, and a machine executable program stored on the memory and running on the processor, and the processor implements the steps of any of the above chip layout modification methods when executing the machine executable program.

[0035] The chip layout modification method of the present application first groups the layout patterns to be optimized in the chip layout based on the pattern features, thereby obtaining target pattern groups to be optimized; then uses the optimization agents corresponding to the target pattern groups to optimize the layout patterns to be optimized, thereby obtaining optimized layout patterns, each optimization agent being set up in correspondence with a target pattern group and being configured to optimize the layout patterns to be optimized in the target pattern group based on the pattern features of the target pattern group; next, the optimized layout patterns meeting the expected specifications are summarized to obtain a result set; finally, the layout patterns in the result set are adjusted by a mask generation model to obtain mask data corresponding to each layout pattern, the mask generation model being used to map the design target patterns corresponding to the chip layout into mask data. By this method, the layout patterns to be optimized in the corresponding groups can be optimized using different optimization agents based on the grouping of the pattern features, so that the layout patterns of different features can all be optimized in a targeted manner, avoiding the inefficiency of uniform processing, greatly reducing the amount of calculation and the complexity of the corresponding optimization agents, and in addition, the optimized layout patterns are converted into mask data by the mask generation model, thereby directly adapting to the requirements of the photolithography process and ensuring the consistency of wafer imaging and design targets.

[0036] The above and other objects, advantages and features of the present application will become more apparent from the following detailed description of some embodiments thereof, when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0037] Some embodiments of the present application will now be described in detail in the following text, with reference to the accompanying drawings, in an exemplary and non-limiting manner. The same reference numerals in the drawings denote the same or similar components or parts. It should be understood by those skilled in the art that the drawings are not necessarily drawn to scale. In the drawings:

[0038] Figure 1 is a flowchart of a chip layout modification method according to an embodiment of the present application;

[0039] Figure 2 is a flowchart of a chip layout modification method according to another embodiment of the present application;

[0040] Figure 3 is a flowchart of a method for modifying a chip layout according to yet another embodiment of the present application;

[0041] Figure 4 is a schematic diagram of a computer program product according to an embodiment of the present application;

[0042] Figure 5 is a schematic diagram of a computer readable storage medium according to an embodiment of the present application; and

[0043] Figure 6 is a schematic diagram of a computer device according to an embodiment of the present application. DETAILED DESCRIPTION

[0044] Those skilled in the art will understand that the embodiments described below are merely a part of the embodiments of the present application, but not all the embodiments of the present application, and are intended to explain the technical principles of the present application, and not intended to limit the protection scope of the present application. Based on the embodiments provided by the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort shall fall within the protection scope of the present application.

[0045] It should be noted that the logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as an ordered listing of executable instructions for implementing logical functions, and can be specifically embodied in any computer readable medium for use by an instruction execution system, apparatus or device, such as a computer-based system, a system including a processor or other system that can fetch the instructions from the instruction execution system, apparatus or device and execute the instructions, or in conjunction with these instruction execution systems, apparatus or devices.

[0046] In the current field of semiconductor technology, OPC (Optical Proximity Correction) is a key EDA technology in the semiconductor lithography process, which is used to compensate for the pattern distortion caused by the diffraction of light in the lithography process. OPC is a core technology for chip manufacturing at advanced process nodes, which optimizes the original layout in the mask design stage through pre-distortion, so that the actual printed pattern on the wafer is as close as possible to the design target. The chip factory will obtain the mask data (Mask) from the original design pattern through the OPC tool software, and then take the mask data to the foundry.

[0047] In actual operation, the OPC tool software inputs the original design pattern to the OPC Recipe (optical proximity correction process recipe) for processing. The OPC recipe is a technical solution for correcting the lithography image corresponding to the OPC tool software, and is essentially a series of optimization strategies and parameter settings. The general process is to implement OPC optimization on the design layout, and then perform lithography simulation detection. If the detection finds a bad point, the OPC Recipe is iteratively improved.

[0048] Generally, the OPC Recipe of a certain process layer under a given technology node is generated by engineers in a chip factory based on the layout pattern characteristics of the process layer on the OPC software tool through repeated iteration and tuning. Due to the complexity of the layout, the OPC software cannot solve the optimization problem of all patterns with a general parameter. The main things engineers do in the practice of developing and tuning the OPC Recipe are two. The first is to use script commands to define complex rules to select corresponding patterns and try to maintain universality to cope with possible new chip design layouts; the second is to try to find more optimal Recipe parameters such as cut edge division, evaluation point placement, etc. for corresponding patterns and make special processing. The difficulty and long time required for OPC recipe development and tuning is because both of these aspects require repeated iteration and considerable experience of engineers.

[0049] However, with the continuous expansion of domestic FAB capacity and the migration to advanced nodes, it is difficult for FAB to maintain a strong OPC team to face the challenges of expanding OPC Recipe development and tuning. How to use less manpower to give a faster and more effective solution and effectively deposit experience in the FAB during the iteration process instead of losing past experience with possible personnel flow is a difficult problem currently faced by FAB.

[0050] To solve the above problems, the present application provides a chip layout correction method, and the specific process is as follows Figure 1 As shown, Figure 1 is a flowchart of a chip layout correction method according to an embodiment of the present application. The chip layout correction method at least includes the following steps S101 to S104.

[0051] In step S101, the to-be-optimized layout patterns in the chip layout are grouped based on the pattern features, so as to obtain the target pattern groups to be optimized. In some optional embodiments, step S101 can generally include grouping the to-be-optimized layout patterns that do not meet the expected specification by using a preset algorithm, so as to obtain the target pattern groups to be optimized. The pattern features generally refer to the geometric features in the layout patterns, such as the line width, the pitch, the density, the corner shape and the like in the layout patterns. The preset algorithm can generally include a fuzzy pattern grouping algorithm, which is usually used for classification according to the pattern features of the layout patterns. The fuzzy pattern grouping algorithm divides the patterns into a plurality of "feature clusters" based on the geometric features (such as the line width, the pitch, the curvature, the density and the like) of the layout patterns by similarity calculation (such as the Euclidean distance, the cosine similarity), and the patterns in the same cluster have similar OPC correction requirements. Therefore, when processing the patterns that do not meet the specification (Specification, referred to as Spec), the patterns can be quickly classified into representative groups, so as to avoid defining complex screening rules manually.

[0052] In addition, the preset algorithm can also include an accurate pattern grouping algorithm, which is used for grouping the to-be-optimized layout patterns according to the preset target patterns. That is, if the to-be-optimized layout patterns all contain a specific preset target pattern, the layout patterns are divided into a group, so as to facilitate subsequent targeted optimization.

[0053] It should be noted that the preset algorithm used in the grouping processing stage of the to-be-optimized layout patterns in the scheme of the present application can be any one of the fuzzy pattern grouping algorithm or the accurate pattern grouping algorithm, or the fuzzy pattern grouping algorithm and the accurate pattern grouping algorithm can be used in sequence in special cases, for example, the fuzzy pattern grouping algorithm is used for fuzzy grouping processing first, and then the accurate pattern grouping algorithm is used for accurate processing. The corresponding grouping algorithm can be selected by the person skilled in the art according to the actual needs.

[0054] In step S102, the to-be-optimized layout patterns are optimized by using the optimization agent corresponding to the target pattern group, so as to obtain the optimized layout patterns. Each optimization agent is set corresponding to a group of target pattern groups, and is configured to optimize the to-be-optimized layout patterns in the corresponding target pattern group by reinforcement learning based on the pattern features of the corresponding target pattern group. In this step, an AI agent (AI Agent) corresponding to each target pattern group is configured, that is, the aforementioned optimization agent. Therefore, each optimization agent can automatically optimize the OPC parameters (such as the line segment offset, the auxiliary pattern size) according to the grouping features of the corresponding group, so as to generate the optimized layout patterns. Each agent only processes the patterns in a specific group, so as to avoid the optimization inefficiency caused by the general parameters.

[0055] It should be noted that the generation manner of each agent in the present application can be based on machine learning generation, for example, reinforcement learning, or based on neural network generation. A person skilled in the art can determine the generation manner of the agent according to the actual situation. A preferred embodiment is to obtain the optimization agent corresponding to each group through reinforcement learning, specifically: for each specific special category, the AI reinforcement learning technology can be used to automatically optimize the better OPC parameter, thereby replacing a large amount of manual work, obtaining the mask optimization result and the OPC Recipe setting faster and better, and assisting in improving the process window. Because there is no need to do complex special processing in each category, the optimization problem becomes simple and can be more effectively solved by the AI reinforcement learning algorithm. Finally, many categories of patterns correspond to many reinforcement learning AI agents. After the training of the reinforcement learning agent is completed, the optimal parameter setting can be given to the pattern (pattern) in the corresponding group, and even under the current optimal parameter configuration of the group, there can still be part of the pattern that does not meet the expected specification (Spec).

[0056] In step S103, the optimized layout patterns meeting the expected specification are summarized to obtain a result set. In the OPC (Optical Proximity Correction) scene, the Spec is a key basis for judging whether the layout pattern optimization meets the standard, and specifically includes: pattern size specification: the deviation of the etching line width and aperture size from the design target pattern (ADI Target) needs to be within the allowed range; lithography simulation specification: the number and position of bad points need to meet the process requirements when the lithography simulation detection (LRC) is performed; process window specification: the imaging stability of the optimized pattern under different exposure energy and focal length conditions needs to meet the standard, etc.

[0057] Step S104, adjusting the layout patterns in the result set through a mask generation model to obtain mask data corresponding to each layout pattern. The mask generation model is used to map the design target pattern corresponding to the chip layout to mask data. Since the plurality of AI Agents have previously optimized the patterns in their respective groups and obtained the optimal parameter settings and optimal results, the final result set is formed by combining these results. This result set contains a large number of different types of patterns and also includes the pre-determined ADI Target (design target pattern) and the mapping pair of the optimal Mask (mask data). Based on this result set, an AI mapping model from the ADI Target to the final Mask, i.e., the mask generation model, can be trained. The mask data corresponding to each layout pattern in the result set is obtained by adjusting the layout pattern through the mask generation model. The mask is equivalent to a "template" for chip manufacturing, which records the specific information of the chip pattern. In the subsequent photolithography process, light will pass through the mask and shine on the wafer coated with photoresist, thereby transferring the pattern on the mask to the wafer surface. Finally, the chip factory will take the mask data to the wafer foundry after obtaining the mask data (Mask). Wafer foundry refers to the operation of making a mask according to the mask data, and then using photolithography, etching, deposition, and other semiconductor manufacturing processes to gradually build the actual circuit structure of the chip on the wafer, and finally complete the production and manufacturing of the chip.

[0058] Through this method, the to-be-optimized layout patterns can be grouped based on pattern characteristics, and then optimized by different optimization agents corresponding to the groups, so that the layout patterns of different characteristics can be optimized specifically, avoiding the inefficiency of unified processing, greatly reducing the amount of calculation and the complexity of the corresponding optimization agent. In addition, the optimized layout patterns are converted into mask data through a mask generation model, thereby directly adapting to the needs of the photolithography process and ensuring the consistency of wafer imaging and design targets.

[0059] In general, the step of grouping the to-be-optimized layout patterns in the chip layout based on pattern characteristics can generally include the following steps: determining the design target pattern and the expected specification corresponding to the entire chip layout; performing preliminary general optimization on the entire chip layout to obtain a preliminary general optimization result; in the case that there are layout patterns in the preliminary general optimization result that do not meet the expected specification, obtaining the layout patterns that do not meet the expected specification as the to-be-optimized layout patterns. The design target pattern (ADI Target) generally refers to the ideal pattern form expected to be achieved after photolithography and etching, while the expected specification (Spec) generally refers to the allowed error range, such as critical dimension deviation ≤ 3 nm, edge position error ≤ 2 nm, etc. This can provide a clear reference standard for subsequent optimization, for example, the ADI Target determines the target contour of the OPC correction, and the Spec defines the allowed error range.

[0060] And the preliminary general optimization generally refers to using general OPC parameters to perform the first optimization on the full-chip layout to generate the "preliminary general optimization result". The general parameters are usually set based on historical process experience, for example: the default offset of line segment end point is 5 nm, the default pitch of auxiliary pattern (SRAF) is 20 nm, etc. In this way, the full-chip layout can be quickly processed, and more than 80% of the conventional patterns (such as regular line arrays and large-size patterns) can be covered. However, due to the high efficiency of general optimization but insufficient targeting, it is difficult to solve the distortion problem of complex patterns (such as dense corners and extremely small line widths), so there will be some complex patterns that still do not meet the expected specifications. Therefore, the patterns that do not meet the Spec are selected as "to-be-optimized layout patterns" for subsequent grouping optimization.

[0061] In some optional embodiments, even if the current group of optimal parameters is configured, there can still be some patterns that do not meet the expected Spec, so the step of optimizing the to-be-optimized layout patterns by using the optimization agent corresponding to the target pattern grouping to obtain the optimized layout patterns can generally further include: grouping the optimized layout patterns that do not meet the expected specifications again by using an accurate pattern grouping algorithm to obtain accurate pattern groupings; optimizing the optimized layout patterns again by using accurate pattern optimization agents corresponding to the accurate pattern groupings to obtain secondary optimized layout patterns, each accurate pattern optimization agent is set corresponding to a group of accurate pattern groupings, and is configured to optimize the optimized layout patterns in the group based on specific patterns in the corresponding accurate pattern grouping; and collecting the secondary optimized layout patterns that meet the expected specifications into a result set. Still taking reinforcement learning as an example, for the patterns in each group that do not meet the expected specifications, the application selects to use an accurate pattern grouping algorithm to list all these specific patterns, and then more specifically optimizes the layout patterns in each group by reinforcement learning. At this time, the accurate pattern optimization agent is not targeted at a certain type of pattern, but at a specific pattern, and the problem is very clear, so more accurate optimization operations will be performed to finally obtain the secondary optimized layout patterns.

[0062] Optionally, after the step of optimizing the optimized layout pattern by the agent corresponding to the accurate pattern of the accurate pattern group, the method can further include: in the case that the twice-optimized layout pattern does not meet the expected specification, collecting the twice-optimized layout pattern that does not meet the expected specification into a target pattern set; adjusting the design target pattern corresponding to the twice-optimized layout pattern in the target pattern set to meet the condition of optical proximity effect correction convergence; and re-executing the step of grouping the layout patterns to be optimized in the chip layout based on the pattern features according to the twice-optimized layout pattern in the adjusted target pattern set. When there are still layout patterns that do not meet the expected specification (Spec) in the twice-optimized layout pattern (such as CD deviation > 5 nm, and the bad point of photolithography cannot be eliminated), it means that the pattern is not friendly to OPC. Such patterns are collected into a target pattern set that is difficult to converge. On the premise of not affecting the function of the chip, the corresponding design target pattern (ADI Target) is modified to adapt to the lithography-etching process capability. For example, for an extremely narrow line pattern: the line width target is appropriately relaxed (such as from 14 nm to 14.5 nm), but the circuit delay change is ensured to be less than 5%; or for a sharp corner pattern: a round corner (such as a radius of 0.5 nm) is added to avoid corner loss during etching. Subsequently, the pattern is re-participated in the operation of grouping and optimization as a layout pattern to be optimized. In this way, for extreme patterns that cannot be solved by traditional methods, the design end is adjusted to ensure the optimization of the chip layout, and the failure of tape-out caused by unmanufacturable design can also be reduced.

[0063] In still some optional embodiments, since the AI model cannot achieve 100% recovery of the mapping relationship from the ADI Target to the final Mask, it can only give a basic convergent full-chip Mask, and some slight errors need to be fine-tuned by using a general parameter in actual use to ensure that the contour given by the final mask completely meets the design requirements of the lithography target pattern (ADI Target). Therefore, after the step of adjusting the result set by the mask generation model to obtain the mask data corresponding to each layout pattern to be optimized, the method can further include: judging whether the adjusted mask data meets the preset convergence requirement; and if not, further modifying the adjusted mask data by using a preset general optical proximity effect correction parameter to obtain mask data that meets the preset convergence requirement.

[0064] Since the method of the present application adopts a multi-layer AI modeling mode to automatically complete the OPC Recipe optimization and application process, in order to further realize automation, the concept of grouping agent can also be introduced. Specifically, the step of grouping the to-be-optimized layout graphics in the chip layout based on the graphic features can further include: obtaining a grouping agent, the grouping agent being used for grouping according to the graphic features of the to-be-optimized layout graphics; and grouping the to-be-optimized layout graphics through the grouping agent, thereby obtaining the target graphic grouping to be optimized. Through the introduction of the grouping agent (Grouping Agent), the traditional graphic grouping algorithm is upgraded to a dynamic learning type intelligent classification system, which is specially used for identifying the geometric features of the chip layout graphics and completing automatic grouping, thereby replacing the traditional fuzzy grouping algorithm and the precise grouping algorithm. The grouping agent can automatically extract the multi-dimensional features of the graphics, such as line width, spacing, curvature, proximity effect factor, etc., then based on the feature similarity matrix, the graphics are classified into corresponding groups (such as "high-density line group" and "isolated hole group") or new groups are generated, and the grouping accuracy can also be iteratively improved (such as reducing the cross-group misclassification rate) through the feedback of historical grouping data and optimization results.

[0065] In addition, it should be noted that different combinations of the steps involved in the present application, or replacement or simplification of certain steps, constitute a workflow. For example, the process starts with precise graphic grouping instead of default fuzzy graphic grouping, or in the automatic optimization process of the AI Agent of each group, the fuzzy graphic grouping with different similarity parameters is iteratively used to form a pyramid-shaped multi-layer AI Agent structure instead of directly using precise graphic grouping to form a two-layer AI Agent structure. Those skilled in the art can adjust it according to actual needs.

[0066] Figure 2 is a chip layout modification method flowchart according to another embodiment of the present application, as shown in Figure 2 The chip layout modification method includes at least the following steps S201 to S213.

[0067] Step S201, determine the design target graphics and expected specifications corresponding to the entire chip layout. The design target graphics generally refer to the ideal form (ADI Target) of the chip layout, such as line width, spacing, and other geometric parameters. The expected specifications generally refer to the quantification standards (Spec) of each layout graphic, such as critical dimension (CD) deviation ≤3nm, edge placement error (EPE) ≤2nm, etc.

[0068] Step S202, a preliminary general optimization is performed on the entire chip layout to obtain a preliminary general optimization result. The general optimization parameters are used to perform a first OPC processing on the full chip layout, to quickly correct regular patterns (such as regular line arrays), and then output a “preliminary optimization result”, but complex patterns (such as dense corners, minimum line width) may still not meet the expected specifications.

[0069] Step S203, the layout patterns that do not meet the expected specifications are obtained as the to-be-optimized layout patterns.

[0070] Step S204, the to-be-optimized layout patterns in the chip layout are grouped based on the pattern features, to obtain a target pattern grouping to be optimized. The pattern features generally refer to the line width, density, curvature and other geometric features of the pattern, and the grouping operation can be performed by a fuzzy pattern grouping algorithm or an accurate pattern grouping algorithm, or by a grouping agent obtained by reinforcement learning.

[0071] Step S205, the to-be-optimized layout patterns are optimized by using the optimization agent corresponding to the target pattern grouping to obtain optimized layout patterns. Each grouping is configured with a corresponding reinforcement learning agent, which is used to automatically optimize the OPC parameters (such as auxiliary pattern size, line segment offset, etc.) according to the pattern features in the grouping, to generate a first optimized layout. In this way, each optimization agent only needs to optimize the pattern features in the current target pattern grouping, without considering other complex situations.

[0072] Step S206, the optimized layout patterns that do not meet the expected specifications are grouped again by using an accurate pattern grouping algorithm to obtain accurate pattern groupings. The patterns that still do not meet the specifications after the first optimization are further subdivided, and the optimization of the subdivided patterns is more targeted. Each accurate pattern grouping is not a pattern of a certain category, but a specific pattern, and the problem of the pattern is very clear.

[0073] Step S207, the optimized layout patterns are optimized again by using the accurate pattern optimization agent corresponding to the accurate pattern grouping to obtain second optimized layout patterns. The accurate pattern optimization agent is used to intelligently optimize the more accurate specific patterns, to obtain the second optimized layout patterns.

[0074] Step S208, in the case that there are second optimized layout patterns that do not meet the expected specifications, the second optimized layout patterns that do not meet the expected specifications are summarized into the target pattern set. This step filters out extreme patterns that cannot meet the specifications even after the second optimization, to avoid falling into invalid iterations. These patterns are usually caused by the mismatch between the design and the process capability, and need to be intervened from the design end. In this way, the optimization resources can be released from the “unsolvable problem”, focused on the solvable patterns, the overall process efficiency is improved, and the manpower is not wasted on the patterns at the edge of the process limit.

[0075] Step S209, adjust the design target pattern corresponding to the secondary optimization layout pattern in the target pattern set to meet the condition of optical proximity effect correction convergence. After the adjustment in step S209 is completed, continue to execute step S204 to re-group and optimize the adjusted pattern as the layout pattern to be optimized. In this way, when the manufacturing end cannot meet the design requirements, manufacturability is achieved by compromising the design end (such as relaxing the line width target). For example, the line width target of an extremely narrow line is relaxed from 14 nm to 14.5 nm to ensure that it meets the standard after lithography-etching. This step breaks the opposition between "design-manufacturing" and cooperatively adjusts the pattern that cannot be manufactured to become feasible.

[0076] Step S210, the layout patterns meeting the expected specifications are summarized to obtain a result set. After the above-mentioned multiple optimization steps are completed, the layout patterns meeting the expected specifications need to be summarized to the result set

[0077] Step S211, adjust the layout patterns in the result set through a mask generation model to obtain mask data corresponding to each layout pattern. Convert the qualified patterns into mask data (Mask) to prepare for tape-out. The mask generation model automatically generates mask patterns adapted to the lithography process by learning the "ADI Target-Optimal Mask" mapping relationship. The mask generation model can greatly improve the conversion efficiency of layout patterns to mask data.

[0078] Step S212, determine whether the adjusted mask data meets the preset convergence requirement.

[0079] Step S213, in the case where the determination in step S212 is no, further correct the adjusted mask data through the preset general optical proximity effect correction parameters to obtain mask data meeting the preset convergence requirement. Since the AI model may have local errors, the general parameters need to be fine-tuned to ensure that there is no mistake. For example, the mask generated by the model may be narrowed overall due to the "density effect" in the dense line area, and needs to be expanded globally by 0.3 nm. Finally, through fine-tuning, the process window stability of the mask data can be improved, and the failure of tape-out caused by model errors can be avoided.

[0080] Finally, the method of the present application realizes significant optimization in efficiency, accuracy, yield, and cost through multi-layer AI modeling and automatic process design. The specific effects include: the OPC Recipe development cycle is greatly shortened, the full-process automation reduces the dependence on manpower, and the pattern correction accuracy is significantly improved. In addition, since the AI agent will continuously iterate and update, the optimization results and tuning strategies are continuously updated to the training set of the AI agent, and the optimization convergence speed of new patterns is improved generation by generation.

[0081] In order to further clearly illustrate the operation flow of the present application, a specific tuning flow is provided and the data flow is described, Figure 3 is a flowchart of a chip layout modification method according to another embodiment of the present application, which comprises at least the following steps S301 to S312.

[0082] Step S301, determine the design target pattern corresponding to the whole chip and the expected specification.

[0083] Step S302, perform preliminary general optimization using general optimization parameters. After preliminary general optimization, some complex patterns may still not meet the expected specification, so that the layout 310 meeting the expected specification and the layout 311 not meeting the expected specification are obtained.

[0084] Step S303, perform fuzzy grouping on the layout 311 not meeting the expected specification, to obtain a plurality of target pattern groups, including target pattern group 320 and target pattern group 321, etc.

[0085] Then, the layout patterns to be optimized in each target pattern group are optimized, taking the target pattern group 320 as an example:

[0086] Step S304, select a representative pattern in the target pattern group 320.

[0087] Step S305, obtain the optimization agent corresponding to the target pattern group 320 through AI reinforcement learning iteration tuning.

[0088] Step S306, apply the optimization agent in the target pattern group 320.

[0089] After the optimization agent optimization, there may still be layout patterns not meeting the expected specification in the target pattern group 320, so that the layout pattern 330 meeting the expected specification and the layout pattern 331 not meeting the expected specification are obtained.

[0090] Step S307, accurate grouping. Since the layout patterns not meeting the expected specification in the layout pattern 331 are generally complex patterns, it is difficult to optimize them by using simple pattern features, so accurate grouping is selected. The accurate pattern grouping algorithm is used to accurately group the layout patterns to be optimized according to the preset target pattern, that is, if the layout patterns to be optimized all contain a certain specific preset target pattern, then these layout patterns are divided into a group, so as to facilitate subsequent targeted optimization.

[0091] After the final accurate grouping, a plurality of accurate pattern groups can be obtained, such as accurate pattern group 340 and accurate pattern group 341, and each pattern in the accurate pattern group is subjected to secondary targeted optimization.

[0092] The specific optimization operation is described by taking the accurate pattern group 340 as an example.

[0093] In step S308, the accurate pattern optimization agent corresponding to the accurate pattern group 340 is obtained by AI reinforcement learning iteration optimization in the accurate pattern group 340.

[0094] In step S309, the accurate pattern optimization agent is applied in the present group.

[0095] After the optimization agent optimization of the to-be-optimized layout pattern in the accurate pattern group 340, there can still be layout patterns that do not meet the expected specifications, so the layout pattern 350 that meets the expected specifications and the layout pattern 351 that does not meet the expected specifications are obtained.

[0096] The pattern in the layout pattern 351 that does not meet the expected specifications is not satisfied after multiple optimizations, which means that the pattern is very unfriendly to OPC. Such patterns are summarized into a difficult-to-converge pattern set 360 (i.e., a target pattern set) for special processing.

[0097] In step S310, the design target pattern corresponding to the secondary optimization layout pattern in the target pattern set is adjusted.

[0098] The adjusted layout pattern is added to the layout 311 that does not meet the expected specifications as a to-be-optimized layout pattern again, and participates in the next round of optimization operation.

[0099] Finally, all AI agents obtain the optimal parameter settings for the patterns in their corresponding groups, and generate optimal results. These results are summarized together to form a final result set. That is, all patterns in the layout 310 that meet the expected specifications, the layout pattern 330 that meets the expected specifications, and the layout pattern 350 that meets the expected specifications are summarized into the result set 370.

[0100] The result set 370 stores a large number of different types of patterns, and also includes a predetermined ADI Target (design target pattern) and a mapping pair of the optimal Mask (expected specifications). Based on such a result set, an AI mapping model (i.e., a mask generation model) from the ADI Target to the final Mask can be trained.

[0101] In step S311, the mask data corresponding to each layout pattern is obtained by adjusting the layout pattern in the result set through the mask generation model.

[0102] Step S312, the adjusted mask data is further corrected by a preset general optical proximity effect correction parameter. Since the AI model cannot achieve 100% recovery of the mapping relationship from the ADI Target to the final mask, it can only give a basically convergent full-chip mask, and the final slight error needs to be fine-tuned by actually using a general parameter to ensure that the contour given by the final mask completely meets the design requirements of the ADI Target.

[0103] In summary, the present application adopts a multi-layer AI modeling method to automatically complete the OPC Recipe optimization and application process. The method of the present application first introduces fuzzy pattern grouping, divides the layout that cannot be optimized by a general parameter into a plurality of representative groups according to the characteristics of the patterns, then uses reinforcement learning to automatically optimize the patterns in each group, thereby optimizing the corresponding AI Agent for each group to give the best optimization parameters and obtain the optimal result.

[0104] In the process of automatic optimization of each group, two-layer AI Agent mechanism is introduced to cope with the case that the specific AI Agent of each group cannot obtain the final convergent Spec; then the optimization results of all AI Agents are summarized in a result set, and the ADI Target and the corresponding optimal mask of the optimization result set are used as input and output pairs to construct an AI model from the ADI Target to the final mask; finally, the mask obtained based on AI is fine-tuned by using a general parameter to make up for the possible precision loss of the AI model, and the final mask after OPC is obtained.

[0105] Among them, by grouping the complex layout patterns, a plurality of different representative groups are obtained, and for each specific and special category, the AI reinforcement learning technology can be used to automatically optimize the better OPC parameters, thereby replacing a large amount of manual work, obtaining the mask optimization result and the OPC Recipe setting faster and better, and assisting in improving the process window. Within each category, there is no need to do complex special processing, and the relative problem becomes simple and can be more effectively solved by the AI reinforcement learning algorithm. Finally, many categories of patterns correspond to many reinforcement learning AI Agents

[0106] The optimal solutions of each category given by a large number of AI Agents are collected to form an optimal result set. Based on the result set, an AI mapping model from the ADI Target to the final Mask is constructed, which can be applied to the new ADI Target to quickly obtain the corresponding Mask. The optimization results and experience of the previous reinforcement learning AI Agent are solidified in the AI mapping model. The double-layer AI architecture of the AI Agent + AI mapping model can better obtain the mask with better performance and deposit the experience of continuously optimizing the new layout.

[0107] In addition, it should be noted that different combinations of the steps involved in the present application, or replacement or simplification of certain steps, constitute a workflow. For example, the initial process uses precise pattern grouping instead of default fuzzy pattern grouping, or in the automatic tuning process of the AI Agent of each group, the fuzzy pattern grouping with different similarity parameters is iteratively used to form a pyramid-shaped multi-layer AI Agent structure instead of directly using precise pattern grouping to form a two-layer AI Agent structure. Those skilled in the art can adjust it according to actual needs.

[0108] The flowchart provided in the present embodiment is not intended to indicate that the operations of the method are performed in any particular order, or that all the operations of the method are included in all cases. In addition, the method can include additional operations. Within the scope of the technical idea provided by the method of the present embodiment, additional changes can be made to the above method.

[0109] It should be understood that in some embodiments, parts can be realized by hardware, software, firmware or a combination thereof. In the above implementation, a plurality of steps or methods can be realized by software or firmware stored in a memory and executed by a suitable instruction execution system.

[0110] The present embodiment also provides a computer program product 10, a computer readable storage medium 20, and a computer device 30. Figure 4 is a schematic diagram of a computer program product 10 according to an embodiment of the present application, Figure 5 is a schematic diagram of a computer readable storage medium 20 according to an embodiment of the present application, Figure 6is a schematic diagram of a computer device 30 according to an embodiment of the present application. The computer program product 10 comprises a computer program 11 which, when executed by the processor 32, implements the steps of any of the methods of modifying a chip layout described above. The computer readable storage medium 20 has stored thereon the computer program 11 which, when executed by the processor 32, implements the steps of any of the methods of modifying a chip layout described above. The computer device 30 can comprise a memory 31, a processor 32 and the computer program 11 stored on the memory 31 and running on the processor 32.

[0111] The computer program 11 for carrying out operations of the present application can be assembly instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state setting data, configuration data for integrated circuits, or source code or object code written in any combination of one or more programming languages and process programming languages. The computer program 11 can be executed entirely on a user's computer, partially on a user's computer, as a standalone software package, partially on a user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or can be connected to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, in order to execute aspects of the present application, electronic circuits including, for example, programmable logic circuits, Field-Programmable Gate Arrays (FPGA) or Programmable Logic Arrays (PLA) can execute computer readable program instructions by utilizing state information of the computer readable program instructions to individualize the electronic circuits.

[0112] For the purposes of the description of the present embodiment, the computer program product 10 is a tangible computer program product comprising the computer program 11. For the purposes of the description of the present embodiment, the computer-readable storage medium 20 is a tangible device that is capable of retaining and storing the computer program 11, which can be any device that can contain, store, communicate, propagate or transport the program 11 for use by or in connection with the instruction execution system, apparatus or device. More specific examples (a non-exhaustive list) of the computer-readable storage medium 20 include the following: portable computer diskette, hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, a floppy disk, a mechanical encoder device, and any suitable combination of the foregoing.

[0113] The computer device 30 can be, for example, a server, a desktop computer, a notebook computer, a tablet computer, or a smartphone. In some examples, the computer device 30 can be a cloud computing node. The computer device 30 can be described in the general context of computer system-executable instructions, such as program modules, being executed by a computer system. Generally, program modules can include routines, programs, objects, components, logic, data structures, and the like, that perform particular tasks or implement particular abstract data types. The computer device 30 can be practiced in distributed cloud computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed cloud computing environment, program modules can be located in local or remote computer system storage media including memory storage devices.

[0114] The computer device 30 can include a processor 32 adapted to execute instructions stored in memory 31, which provides temporary storage for operations of the instructions during execution. The processor 32 can be a single core processor, a multi-core processor, a computing cluster, or any number of other configurations. The memory 31 can include random access memory (RAM), read only memory, flash memory, or any other suitable memory systems.

[0115] The computer device 30 can also include a network adapter / interface and an input / output (I / O) interface. The I / O interface allows input and output of data with external devices that can be connected to the computer device. The network adapter / interface can provide for communication between the computer device and a network, generally illustrated as communication network.

[0116] At this point, those skilled in the art will appreciate that although specific exemplary embodiments of the application have been described herein, the present application also encompasses many other variations or modifications in accordance with the principles of the application as set forth above. Accordingly, the scope of the present application should be understood to include all such variations and modifications.

Claims

1. A method for modifying a chip layout, comprising: determining design target patterns and expected specifications corresponding to an entire chip layout; performing a preliminary global optimization on the entire chip layout to obtain a preliminary global optimization result; in a case where there are layout patterns in the preliminary global optimization result that do not meet the expected specifications, obtaining the layout patterns that do not meet the expected specifications as to-be-optimized layout patterns; grouping the to-be-optimized layout patterns in the chip layout based on pattern features, thereby obtaining target pattern groups to be optimized; optimizing the to-be-optimized layout patterns using optimization agents corresponding to the target pattern groups to obtain optimized layout patterns, each of the optimization agents being set up corresponding to a group of the target pattern groups and being configured to optimize the to-be-optimized layout patterns in the corresponding group of target pattern groups based on the pattern features of the corresponding group of target pattern groups; collecting the optimized layout patterns that meet the expected specifications to obtain a result set; and adjusting layout patterns in the result set using a mask generation model to obtain mask data corresponding to each of the layout patterns, the mask generation model being used to map the design target patterns corresponding to the chip layout to the mask data. 2.The method of claim 1, wherein, after the step of optimizing the to-be-optimized layout patterns using optimization agents corresponding to the target pattern groups to obtain optimized layout patterns, the method further comprises: grouping the optimized layout patterns that do not meet the expected specifications again using an accurate pattern grouping algorithm to obtain accurate pattern groups; optimizing the optimized layout patterns again using accurate pattern optimization agents corresponding to the accurate pattern groups to obtain second-optimized layout patterns, each of the accurate pattern optimization agents being set up corresponding to a group of the accurate pattern groups and being configured to optimize the optimized layout patterns in the corresponding group of accurate pattern groups based on a specific pattern in the corresponding group of accurate pattern groups; and collecting the second-optimized layout patterns that meet the expected specifications into the result set. 3.The method of claim 2, wherein, after the step of optimizing the optimized layout patterns again using accurate pattern optimization agents corresponding to the accurate pattern groups to obtain second-optimized layout patterns, the method further comprises: in a case where there are second-optimized layout patterns that do not meet the expected specifications, collecting the second-optimized layout patterns that do not meet the expected specifications into a target pattern set; adjusting the design target patterns corresponding to the second-optimized layout patterns in the target pattern set to meet a condition of optical proximity effect correction convergence; and re-executing the step of grouping the to-be-optimized layout patterns in the chip layout based on pattern features according to the second-optimized layout patterns in the adjusted target pattern set. 4.The method of claim 1, wherein, the step of grouping the to-be-optimized layout patterns in the chip layout based on pattern features comprises: ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ An acquisition grouping agent is configured to group the layout patterns to be optimized according to the pattern features of the layout patterns to be optimized. The layout patterns to be optimized are grouped by the grouping agent, so as to obtain the target pattern groups to be optimized.

5. The chip layout correction method of claim 1, wherein the grouping of the layout patterns to be optimized in the chip layout according to the pattern features comprises: The layout patterns to be optimized that do not meet the expected specifications are grouped by a preset algorithm, so as to obtain the target pattern groups to be optimized, the preset algorithm being a fuzzy pattern grouping algorithm or an accurate pattern grouping algorithm, the fuzzy pattern grouping algorithm being configured to group the layout patterns according to the pattern features of the layout patterns, and the accurate pattern grouping algorithm being configured to group the layout patterns to be optimized according to preset target patterns.

6. The chip layout correction method of claim 1, wherein the adjustment of the result set by the mask generation model to obtain the mask data corresponding to each of the layout patterns to be optimized further comprises: determining whether the adjusted mask data meets preset convergence requirements; if not, further correcting the adjusted mask data by using preset general optical proximity correction parameters to obtain mask data meeting the preset convergence requirements.

7. A computer readable storage medium having a computer program stored thereon, the computer program being executed by a processor to implement the steps of the chip layout correction method according to any one of claims 1 to 6.

8. A computer program product comprising a computer program, the computer program being executed by a processor to implement the steps of the chip layout correction method according to any one of claims 1 to 6.

9. A computer device comprising a memory, a processor, and a machine executable program stored on the memory and running on the processor, and the processor executes the machine executable program to implement the steps of the chip layout correction method according to any one of claims 1 to 6. ​ ​

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