Method, device and medium for generating neural network architecture of memristor

Abstract

The application provides a method and device for generating a neural network architecture of a memristor, and a medium, which comprises the following steps: step one, obtaining an input signal and performing event-driven coding to convert the input signal into a pulse sequence, and performing neural computing using pulse time information in a time coding manner. The application performs structural pruning and non-structural pruning in the pruning optimization stage, and dynamically adjusts the pruning proportion according to the task computing load in the inference stage, thereby solving the problems of not using pruning technology and lacking a dynamic pruning adjustment strategy in the prior art, reducing computing redundancy and power consumption; the application uses a pruned organic memristor array in the inference stage, and dynamically adjusts the pruning proportion in combination with the task load, thereby optimizing the inference process, solving the problems of large computing redundancy in the inference stage, not combining pruning technology and being difficult to adapt to different tasks in the prior art, reducing energy consumption and improving the adaptability of the network to different tasks.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices and neuromorphic computing technology, and particularly relates to a neural network architecture generation method and device of a memristor, equipment and a medium. BACKGROUND

[0002] With the development of artificial intelligence and neural network technology, the traditional computing architecture faces the bottleneck of energy consumption and computing efficiency. Spiking neural networks (SNNs) have become a research hotspot for low-power information processing due to their event-driven computing method and sparse activation characteristics. Organic electronic materials have attracted widespread attention in the field of new brain-like computing due to their low power consumption, strong adjustability, flexibility and other advantages. Organic brain-like devices such as organic thin film transistors (OTFTs), memristors and organic electrochemical synapses (OECTs) can simulate the weight adjustment and plasticity of biological synapses, providing the possibility for building high-efficiency artificial intelligence hardware. However, there are still some problems:

[0003] I. In the prior art, the publication number CN117830801A discloses a spiking neural network model based on a photoelectric memristor and a dynamic object detection method. Although the neural network calculation is performed using the memristor, the pruning technology is not used, resulting in large calculation redundancy, high power consumption, and lack of dynamic pruning adjustment strategy.

[0004] II. In the prior art, the publication number CN115374928A discloses a method and device for training convolution kernels in a spiking convolutional neural network. Although the training of convolution kernels is optimized, the inference stage is not optimized, there is a lot of calculation redundancy in the inference process, and the pruning technology is not combined, resulting in high energy consumption and difficulty in dynamically adjusting the network structure to adapt to different tasks.

[0005] Therefore, a neural network architecture generation method, device, equipment and medium of a memristor are proposed. SUMMARY

[0006] Therefore, the embodiments of the present application hope to provide a neural network architecture generation method, device, equipment and medium of a memristor to solve or alleviate the technical problems existing in the prior art, and at least provide a beneficial choice.

[0007] To solve the above technical problems, one technical solution adopted by the present application is: a neural network architecture generation method of a memristor, comprising the following steps:

[0008] Step one, obtain the input signal and perform event-driven encoding, convert the input signal into a pulse sequence, and use the pulse time information to perform neural computation in a time coding manner;

[0009] Step two, build a cooperative computing architecture, deploy an organic memristor array to store weights, integrate a low-energy pruning module, a LIF neuron computing core, and a memory-computing integrated control unit, and use the synaptic plasticity of the organic memristor to lay a hardware foundation for weight learning and pruning optimization;

[0010] Step three, store synaptic weights through an organic memristor array, dynamically adjust the organic memristor conductance based on the STDP rule, and learn and update synaptic weights online;

[0011] Step four, in the pruning optimization phase, calculate the L1 / L2 norm or gradient contribution of the synaptic weight, set a threshold, perform structural pruning or non-structural pruning on redundant weights below the threshold, and update the organic memristor state;

[0012] Step five, after pruning, re-adjust the weights through short-term Fine-Tuning training using the plasticity of the organic memristor;

[0013] Step six, in the inference phase, use the pruned organic memristor array for pulse transmission calculation, trigger pulses through LIF neuron accumulation, and dynamically adjust the pruning ratio according to the task computation load to prune more redundant neurons in low-load scenarios;

[0014] Step seven, after pulse neural network calculation, output classification or recognition results in an event-driven manner.

[0015] Provided as a further preferred embodiment of the present technical solution, in step two, the organic memristor array is a copper phthalocyanine-based organic memristor array, and the power consumption of a single device is less than 1 nW. The storage and update of synaptic weights are performed through the conductance-adjustable characteristics.

[0016] Provided as a further preferred embodiment of the present technical solution, in step three, the STDP rule is:

[0017] When the pre-synaptic pulse precedes the post-synaptic pulse, the organic memristor conductance increases by ΔG=0.01G0;

[0018] When the post-synaptic pulse precedes the pre-synaptic pulse, the conductance decreases by ΔG=0.005G0;

[0019] Where G0 is the initial conductance value.

[0020] Provided as a further preferred embodiment of the present technical solution, in step four, the structural pruning includes deleting unimportant neurons or channels in the neural network, the non-structural pruning sets low-contribution weights to zero, and the pruning threshold is dynamically adjusted according to the validation set accuracy with an adjustment step of 0.05.

[0021] Provided as a further preferred embodiment of the present technical solution, in step six, the pruning ratio is dynamically adjusted according to the task computation load, specifically:

[0022] The pruning threshold of simple tasks is raised to 0.3, and 40% redundant weights are cut off;

[0023] The pruning threshold of complex tasks is reduced to 0.05, and more weights are retained.

[0024] Further preferably, in step one, when the input signal is an image signal, the event-driven encoding converts the pixel gray value into a pulse frequency, and 255 gray values correspond to a 100Hz pulse frequency, and time coding is performed through pulse intervals.

[0025] Further preferably, in step five, the number of iterations of the short-term Fine-Tuning training is 5-10 times, and the network accuracy is restored to more than 85% of the accuracy before pruning by adjusting the effective weights.

[0026] To solve the above technical problems, another technical solution adopted by the present application is: a neural network architecture generation device of a memristor, comprising: a signal acquisition and encoding module, a computing architecture construction module, a synaptic weight learning module, a pruning optimization module, a network fine-tuning module, an inference calculation module, and a result output module;

[0027] The signal acquisition and encoding module is configured to acquire an input signal and perform event-driven encoding, convert the input signal into a pulse sequence, and perform neural computation using pulse time information in a time coding manner;

[0028] The computing architecture construction module is configured to construct a collaborative computing architecture, deploy an organic memristor array to store weights, integrate a low-energy pruning module, a LIF neuron calculation core, and a storage-computing integrated control unit, and use the synaptic plasticity of the organic memristor to lay a hardware foundation for weight learning and pruning optimization;

[0029] The synaptic weight learning module is configured to store synaptic weights through an organic memristor array, dynamically adjust the conductance of the organic memristor based on the STDP rule, and learn and update synaptic weights online;

[0030] The pruning optimization module is configured to calculate the L1 / L2 norm or gradient contribution of synaptic weights in the pruning optimization stage, execute structural pruning or non-structural pruning on redundant weights below the threshold after setting the threshold, and update the state of the organic memristor;

[0031] The network fine-tuning module is configured to perform short-term Fine-Tuning training after pruning, and use the plasticity of the organic memristor to adjust the weights again;

[0032] The inference calculation module is configured to perform pulse transmission calculation in an inference stage by using the pruned organic memristor array, trigger pulses by LIF neurons, and dynamically adjust a pruning ratio according to a task calculation load to prune more redundant neurons in a low load scenario.

[0033] The result output module is configured to output a classification or recognition result in an event-driven manner after pulse neural network calculation.

[0034] To solve the above technical problems, another technical solution adopted by the present application is an electronic device, which comprises a processor and a memory coupled with the processor, and the memory stores program instructions, which, when executed by the processor, cause the processor to perform the steps of the neural network architecture generation method of the organic memristor as described above.

[0035] To solve the above technical problems, another technical solution adopted by the present application is a computer-readable storage medium storing program instructions capable of implementing the neural network architecture generation method of the organic memristor as described above.

[0036] The embodiments of the present application have the following advantages due to the adoption of the above technical solutions.

[0037] 1. The present application solves the problems of not using pruning technology and lacking dynamic pruning adjustment strategy in the prior art by performing structural pruning and non-structural pruning in the pruning optimization stage and dynamically adjusting the pruning ratio in the inference stage according to the task calculation load, thereby reducing calculation redundancy and power consumption.

[0038] 2. The present application optimizes the inference process by using the pruned organic memristor array in the inference stage and dynamically adjusting the pruning ratio according to the task load, thereby solving the problems of large calculation redundancy in the inference stage, not combining pruning technology and being difficult to adapt to different tasks in the prior art, reducing energy consumption and improving the adaptability of the network to different tasks.

[0039] The above summary is only for the purpose of the description and is not intended to limit in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present application will be apparent from the drawings and the following detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without any creative effort.

[0041] Figure 1 A flowchart of a method for generating a neural network architecture of a memristor according to the present application;

[0042] Figure 2 A functional module diagram of a device for generating a neural network architecture of a memristor according to the present application;

[0043] Figure 3 A structural diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0044] The embodiments of the present disclosure will be described in detail below with reference to the drawings.

[0045] It should be apparent that the following describes the embodiments of the present disclosure through specific concrete examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, not all. The present disclosure can also be implemented or applied by other different specific embodiments, and the details in the specification can be modified or changed based on different views and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present disclosure.

[0046] It should be noted that the various aspects of the embodiments described below are within the scope of the appended claims. It should be apparent that the aspects described herein can be embodied in a wide variety of forms and that any specific structure and / or function described herein is merely illustrative. Based on the disclosure provided, one skilled in the art should appreciate that an aspect described herein can be implemented independently of any other aspects and that two or more of these aspects can be combined in various ways. For example, an apparatus can be implemented or a method can be practiced using any number of the aspects set forth herein. In addition, such an apparatus can be implemented or such a method can be practiced using other structure and / or functionality in addition to or other than one or more of the aspects set forth herein.

[0047] It should also be noted that the drawings provided in the following embodiments are only schematic - actual dimensions and shapes of the components can be different from those shown in the drawings, and the layout of the components can be more complex. It should be noted that the drawings provided in the following embodiments are only schematic - actual dimensions and shapes of the components can be different from those shown in the drawings, and the layout of the components can be more complex.

[0048] Also in the following description, specific details are given to provide thorough understanding of examples. However, one skilled in the relevant art will understand that the aspects described can be practiced without

[0049] Figure 1 is a flowchart of a method for generating a neural network architecture of a memristor according to an embodiment of the present application. It should be noted that the method of the present application is not limited to the order of the flowchart shown Figure 1 As shown in the flowchart: the method for generating a neural network architecture of a memristor, comprising the following steps: Figure 1

[0050] Step one, get the input signal and perform event-driven encoding, convert the input signal to a pulse sequence, use pulse time information to perform neural computation in a time coding manner;

[0051] Specifically, first, get the input signal and perform preprocessing, if the input signal is an image signal, collect the pixel gray value through a CMOS image sensor or an organic photodetector, the resolution supports 128x128 to 1024x1024 pixels, the sampling frequency is dynamically adjusted according to the scene (such as dynamic object detection set to 100fps), and the original gray value range [0, 255] is mapped to the [0, 1] interval for normalization by the formula:

[0052] ;

[0053] ;

[0054] Then, generate a pulse sequence based on a threshold event triggering mechanism, set a dynamic threshold:

[0055] ;

[0056] Wherein, is a basic threshold of 0.1, is a sensitivity coefficient adjustable between 0.5-2.0;

[0057] When the signal change amount , a pulse event is generated, and the normalized gray value is mapped to the pulse frequency according to (e.g. gray value 255 corresponds to 100Hz);

[0058] Next, use relative time interval coding (RIT) or absolute time coding (ATC) for time coding, RIT calculates the time interval between adjacent pulses and maps it to the weight, and ATC encodes the subsequent pulse time with the first pulse time as a reference; ​​

[0059] The pulse sequence is further thinned, isolated pulses with a time interval greater than 100 ms are deleted, an asynchronous event-driven bus (such as the AER protocol of the DAVIS chip) is used for parallel transmission, the transmission rate is dynamically adjusted according to the pulse density, and the average power consumption is less than 10μW;

[0060] Finally, the pulse amplitude is set to 0.5-1.5V to match the 1V switching threshold voltage of the copper phthalocyanine-based memristor, and the timing is synchronized by combining a 1kHz global clock with a local event trigger, and distributed to the corresponding memristor synapse by the memory-computing integrated control unit, and the interface adaptation with the organic memristor array is completed.

[0061] Step two, build a collaborative computing architecture, deploy an organic memristor array to store weights, integrate a low-energy pruning module, a LIF neuron computing core, and a memory-computing integrated control unit, and use the plasticity of organic memristor synapses to lay a hardware foundation for weight learning and pruning optimization;

[0062] Specifically, first, the copper phthalocyanine-based organic memristor array is prepared; a vacuum evaporation process is used to carefully deposit a 50nm-thick copper phthalocyanine (CuPc) active layer on a flexible PET substrate, and to ensure good conductivity and compatibility, the upper and lower electrodes are made of ITO (indium tin oxide) and Pt (platinum), respectively; the size of a single device is strictly set to 10μm×10μm, and after preparation, its performance is tested; the test results show that the power consumption of a single device is significantly lower than 1nW, and by applying a voltage of ±1V, the memristor conductance can be flexibly adjusted in a relatively wide range of 0.1μS to 10μS, and this conductance adjustment range characteristic plays a crucial role in the subsequent physical storage of synaptic weights;

[0063] Then, the design of the low-energy pruning module hardware circuit is entered; in this link, the FPGA (field programmable gate array) architecture is selected to build the entire circuit system; specifically, a special L1 norm calculation unit is designed, which can quickly and accurately calculate the L1 norm of the weight data in the neural network; at the same time, a dynamic threshold comparator is configured, which dynamically adjusts the comparison threshold according to the actual calculation requirements and network running state to adapt to different pruning scenarios; in terms of structural pruning module, the logic circuit for deleting unimportant neurons or channels in the neural network is integrated, which can reasonably simplify the structure of the neural network according to the pre-set pruning standard; the non-structural pruning module needs to configure the weight zero mask register, which can zero the weights that contribute less to the network performance, thereby optimizing the network weights; in addition, in order to accurately control the adjustment range of the pruning threshold, an 8-bit DAC (digital-to-analog converter) is used to achieve high-precision control of the pruning threshold adjustment step size of 0.05, ensuring that the network performance and complexity can be more finely balanced when pruning.

[0064] Next, the LIF (Leaky Integrate and Fire) neuron calculation core circuit is built; in the circuit construction process, a transconductance operational amplifier is used to realize the key membrane potential accumulation capacitor and leakage resistance functions; among them, the membrane potential accumulation capacitor is set to 1nF, which can more ideally accumulate the charge of the input electrical signal to simulate the membrane potential change process of biological neurons when receiving signals; the leakage resistance is set to 10MΩ, which slowly releases the accumulated charge when the neuron does not receive external signal input, simulating the natural decay phenomenon of biological neuron membrane potential; at the same time, the trigger voltage of the threshold comparator is set to 0.8V, when the membrane potential accumulation exceeds this threshold, the neuron will fire a pulse signal, and the output pulse width is set to 200ns, which can effectively ensure the accuracy and stability of signal transmission between neurons, so that the entire LIF neuron calculation core circuit can efficiently support the event-driven sparse computing mode, improving the computing efficiency of the neural network when processing actual data;

[0065] After that, an integrated storage and calculation control unit is integrated; in this unit, an ARM Cortex-M4 processor is selected as the main control core, which has strong computing and control capabilities and can effectively manage and schedule the entire collaborative computing architecture; in order to realize accurate monitoring and management of the state of the memristor, a memristor state register group is configured, which can store the conductance value and pruning mark of the memristor and other key information in real time; a weight update controller is set up, which is specially used to perform conductance adjustment operation under STDP (Spike-Timing-Dependent Plasticity, Spike-Timing-Dependent Plasticity) rule, dynamically adjusts the conductance of the memristor according to the order and time interval of the neuron pulse, and realizes adaptive learning and update of the neural network weight; a data routing matrix is constructed, which dynamically optimizes the flow direction of the pulse signal in the entire collaborative computing architecture according to the real-time data flow and computing task demand during network operation, ensures that data can be efficiently transmitted to each processing unit, and improves the overall operation efficiency of the system; and through the AXI (Advanced eXtensible Interface, Advanced eXtensible Interface) bus, high-speed communication between the storage and calculation control unit and the memristor array and other functional modules is realized, ensuring the stability and efficiency of data transmission;

[0066] Finally, a hybrid bonding process is used to heterogeneously integrate the prepared organic memristor array and the silicon-based integrated circuit (which has integrated the low-energy pruning module, LIF neuron calculation core and storage and calculation control unit designed in the previous step) ; during the integration process, a 3D stacked architecture is selected to be constructed on the PET substrate, which can effectively improve the integration degree of the system and reduce the occupied space of the chip; the electrical connection between different functional layers is realized through copper pillar interconnection, and the good conductivity of copper ensures stable signal transmission between functional modules; during this integration process, the reversible conductance change characteristics of the memristor under ±1V voltage are fully utilized, providing a solid and reliable hardware foundation for subsequent weight learning and pruning optimization operations based on the STDP rule, so that the entire collaborative computing architecture can run efficiently and stably, and lay a good hardware platform for realizing the neural network architecture generation of the memristor;

[0067] Taking the image recognition special architecture as an example, a phthalocyanine copper memristor array with a preparation scale of 4096x4096 is prepared; in actual operation, the power consumption of a single device is only 0.8nW under 100Hz pulse driving, showing extremely low energy consumption characteristics; the low-energy pruning module adopts a parallel pipeline structure, which can efficiently process the L1 norm calculation of 1024 weights in each clock cycle, greatly improving the efficiency of the pruning operation; the LIF neuron core supports a pulse frequency of up to 1MHz, which can quickly process input signals and meet the requirements of real-time application scenarios; the memory and calculation integrated control unit can control the delay within 50ns when updating the weight, ensuring the timeliness and accuracy of weight update; through such a collaborative computing architecture, a recognition accuracy of 95% is achieved on the MNIST dataset, and the power consumption is only 1.2mW, which is 80% lower than the traditional GPU scheme, fully demonstrating the significant advantages of the collaborative computing architecture in energy consumption and performance.

[0068] Step three, store the synaptic weight through the organic memristor array, and make the organic memristor conductance dynamically adjust based on the STDP rule to learn and update the synaptic weight online;

[0069] Specifically, first, a mapping system of synaptic weight and memristor conductance is constructed in the organic memristor array; the weight matrix generated by neural network training is converted into the conductance value of the memristor according to the linear relationship , The specific mapping formula is:

[0070] ;

[0071] Among them, the conductance range of the phthalocyanine copper-based memristor is set to , , and are the extreme values of the weight matrix;

[0072] By applying a 0.5V write voltage, the calculated conductance value is accurately stored in the corresponding memristor unit, and the power consumption of a single device during the storage operation is controlled within 0.8nW;

[0073] Then, the hardware execution circuit of the STDP rule is designed; a time stamp comparator is used to record the time difference between the pre-synaptic pulse and the post-synaptic pulse in real time :

[0074] When (the pre-synaptic pulse precedes the post-synaptic pulse), a +1V voltage pulse (width 10μS) is triggered to increase the memristor conductance ( is the initial conductance);

[0075] When -1V voltage pulse is applied, the conductance decreases ; The integrated transconductance amplifier in the circuit realizes the accurate control of the micro-current of conductance change through a 10 nF coupling capacitor, and the current fluctuation range does not exceed ±2%;

[0076] Then, a closed-loop feedback system for online learning is built, and the specific process is as follows:

[0077] Pulse signal processing: the input pulse sequence is completed by the weighted summation of the memristor array, the membrane potential is calculated by the 1 nF membrane potential accumulation capacitor and the 10 MΩ leakage resistor in the LIF neuron core, and the pulse is output when the threshold of 0.8 V is exceeded;

[0078] Timing difference recording: the comparator captures the timestamps of the pre- and post-synaptic pulses in real time, and generates signal;

[0079] Conductance update control: the STDP controller generates a voltage regulation signal according to , addresses the target memristor unit through the row and column selection circuit, and synchronously updates the conductance value in the weight register through the storage and calculation integrated control unit;

[0080] Dynamic calibration: every 100 training cycles, a full 1 pulse sequence is input to the memristor array, and the output current I=V×G (V=1V bias voltage) is measured. When the actual conductance is more than 5% different from the target conductance , fine-tune it through a ±0.1V incremental voltage pulse;

[0081] Subsequently, a conductance-weight consistency calibration mechanism is built; during the calibration process, the ARM Cortex-M4 processor is used as the main control unit, the current data of the memristor array is read through the AXI bus, the conductance-weight mapping curve is fitted by the least squares method, and the error caused by the device discreteness is corrected in real time; for example, when the target conductance of a certain memristor unit is 5μS and the actual measurement is 5.3μS, the controller automatically sends a-0.1V calibration pulse to make the conductance return to the target value, and the conductance consistency error between devices can be reduced to ±3% after calibration;

[0082] Finally, online learning verification is carried out on the CIFAR-10 dataset; a three-layer SNN architecture (input layer of 1024 neurons, hidden layer of 512 neurons, and output layer of 10 neurons) is used, and the size of the copper phthalocyanine memristor array is 1024×512:

[0083] After 500 rounds of training, the accuracy of the memristor conductance update reaches 92%, and the STDP rule makes the network maintain an identification accuracy of 85.6% at a pruning rate of 30%, which is 7.3% higher than the fixed weight architecture;

[0084] The energy consumption of each training round is only 0.2 mW, of which the power consumption of the memristor array accounts for 65% (about 0.13 mW), and the energy consumption of the storage-computation integrated control unit is 0.07 mW;

[0085] Further verification on the MNIST dataset shows that when the recognition accuracy reaches 95%, the system power consumption is only 1.2 mW, which is 80% lower than the traditional GPU scheme, meeting the low-power demand of Internet of Things edge devices.

[0086] Step four, in the pruning optimization stage, the L1 / L2 norm or gradient contribution of the synaptic weight is calculated, the threshold is set, the redundant weight below the threshold is executed structural pruning or non-structural pruning, and the organic memristor state is updated;

[0087] Specifically, first, the weight importance evaluation mechanism is started in the pruning optimization stage, and the L1 norm or gradient contribution value of the synaptic weight is calculated in parallel through the hardware acceleration unit; for L1 norm calculation, a pipeline structure FPGA is adopted , wherein, is the synaptic weight matrix element; the gradient contribution calculation obtains the gradient value of the weight to the loss function through the back propagation algorithm , and takes the absolute value as the importance index; the evaluation process is triggered after every 100 training rounds, and the time consumption of a single calculation is controlled within 50 μS;

[0088] Then, the pruning threshold is dynamically set based on the evaluation results; the initial threshold is determined by the accuracy-threshold curve of the verification set , for example, the initial threshold is set to 0.05 on the CIFAR-10 dataset, and then the threshold is adjusted by 0.05 steps according to the accuracy change of the verification set: if the accuracy decreases by more than 3%, the threshold is reduced by 0.05; if the accuracy is stable, the threshold is increased by 0.05, until the accuracy-pruning rate balance point is found; the storage-computation integrated control unit records the threshold adjustment history in real time, and optimizes the adjustment step through the PID algorithm, so that the convergence speed of the threshold is improved by 40%;

[0089] Then, the structural pruning and non-structural pruning operations are executed:

[0090] Structural pruning: important neurons or channels in the neural network are deleted through hardware logic circuit; for fully connected layers, the output variance of each neuron is calculated, and neurons with a variance lower than 20% of the threshold are deleted; for convolutional layers, the channel importance sorting algorithm is adopted, and the 10% channels with the smallest L1 norm are deleted, and the row and column selection logic of the memristor array is updated, and the memristor units corresponding to the deleted neurons / channels are marked as "invalid";

[0091] Non-structure pruning: generate weight zero mask matrix, perform zero operation on weights below threshold; through FPGA configuration special mask register, output low level signal to control the write circuit of the memristor array, when the weight needs to be zero, apply-1V voltage to the corresponding memristor unit to make its conductance zero (<0.1μS), and mark the position as "0" in the weight register at the same time;

[0092] Then, the organic memristor state is updated, specifically including:

[0093] Conductance value calibration: for the memristor units that are not pruned, the conductance is fine-tuned by 0.5V voltage pulse according to the new weight value, and the adjustment accuracy is ±0.5%;

[0094] Invalid unit marking: through the storage and calculation integrated control unit, write invalid address table to the address decoder of the memristor array, and skip the marked units during subsequent calculation to reduce invalid power consumption;

[0095] Array reconstruction: when the pruning rate exceeds 30%, start the dynamic reconstruction algorithm of the memristor array, remap the effective weights to continuous physical units, shorten the data addressing path, and improve the calculation efficiency by 15-20%;

[0096] Finally, verify the pruning effect on the CIFAR-10 dataset: use a 3-layer SNN architecture, the initial weight matrix size is 512x256, after 5 rounds of pruning optimization, the pruning rate reaches 50%, at this time:

[0097] L1 norm pruning retains high contribution weights (top 30%), and the validation set accuracy is stable at 87.2%;

[0098] Gradient contribution pruning has significant advantages in complex tasks, and when dealing with dynamic object detection tasks, the accuracy is improved by 2.3% compared with L1 norm pruning;

[0099] The power consumption of the memristor array is reduced by 45%, the average working current of a single device is reduced from 1.2nA to 0.65nA after pruning, and the calculation delay is reduced by 18ns through dynamic reconstruction.

[0100] Step five, after pruning, through short-term Fine-Tuning training, the weight is adjusted again by the plasticity of organic memristor;

[0101] Specifically, first, after the pruning operation is completed, start the short-term Fine-Tuning training process, select 10%-20% representative samples (such as 500 images of each class in CIFAR-10) from the training data set, convert them into pulse sequences through event-driven coding, and input them into the pruned memristor neural network; The selection of training data follows the gradient sensitivity principle, and samples with high weight update contribution are preferred to accelerate the accuracy recovery;

[0102] Then, the training parameters of Fine-Tuning are set: the number of iterations is fixed at 5-10 times (dynamically adjusted according to the pruning rate, and 10 times are taken when the pruning rate is >40%), the learning rate is set to 1 / 10 of the initial training stage (such as 0.001), the mini-batch gradient descent method is adopted, and the batchsize is set to 32; the in-memory computing control unit monitors the gradient change in the training process in real time, and when the accuracy improvement of 2 consecutive iterations is <0.5%, the training is automatically terminated in advance to avoid overfitting;

[0103] Then, the synaptic plasticity of the organic memristor is used to perform weight adjustment:

[0104] Forward propagation: the pulse sequence passes through the pruned memristor array, and the LIF neuron calculates the membrane potential and outputs the pulse, at this time only the memristor units that are not pruned (conductance >0.1 μS) are activated;

[0105] Error backpropagation: according to the output error, the gradient of each layer weight is calculated, and for the weights that are not pruned, the conductance adjustment signal is generated through the STDP rule: when the presynaptic pulse precedes the postsynaptic pulse, a +0.5V voltage pulse (width 5 μS) is applied to increase the conductance by ΔG=0.005G0; otherwise, a -0.5V pulse is applied to decrease the conductance by ΔG=0.0025G0 (G0=1 μS);

[0106] Weight update: after completing one batch of training, the conductance of the target memristor unit is fine-tuned through the row and column selection circuit, and the adjustment accuracy is controlled within ±0.3%, and the single update power consumption is <0.5nW;

[0107] Subsequently, dynamic calibration of the memristor state is implemented: after each round of training, the conductance of the memristor unit updated in Fine-Tuning is measured, and if the error between the measured value and the target value is >3%, secondary calibration is performed through incremental voltage pulses (±0.1V); for example, if the target conductance of a memristor unit is 3 μS and the measured value is 2.9 μS, a +0.1V pulse (width 2 μS) is applied to increase the conductance to 3.02 μS, ensuring the weight storage accuracy;

[0108] Finally, the Fine-Tuning effect is verified on the MNIST dataset: when the pruning rate is 50%, after 5 iterations of training:

[0109] The network recognition accuracy is restored from 82% after pruning to 87.5% (more than the target of 85% before pruning);

[0110] The conductance adjustment amplitude of the effective weights in the memristor array is 15%-20% on average, and the adjustment amplitude of the high contribution weights (top 20%) is up to 30%;

[0111] The energy consumption of the entire Fine-Tuning process is 0.8 mW, which is reduced by 75% compared to the traditional GPU solution, and the average number of updates of a single memristor device is 120 times, which is within its 10^5 endurance range.

[0112] Step six, the inference stage uses the pruned organic memristor array for pulse transmission calculation, accumulates the trigger pulse through the LIF neuron, and dynamically adjusts the pruning ratio according to the task calculation load to prune more redundant neurons in low load scenarios;

[0113] Specifically, first, in the inference stage, the pruned organic memristor array is connected to the pulse transmission calculation link, the pulse sequence generated by the event-driven encoding of the input signal enters the memristor array through the row and column gating circuit, and each pulse signal corresponds to a 0.5V bias voltage applied to the memristor conductance to produce a transient change, completing the weighted summation operation; At this time, the memristor units that are not pruned (conductance > 0.1 μS) participate in the calculation, and the redundant units marked are skipped through the address mask to reduce invalid power consumption;

[0114] Then, the pulse accumulation trigger is realized through the LIF neuron calculation core; the core uses a transconductance operational amplifier to build a membrane potential accumulation circuit, where the membrane potential capacitor is 1nF and the leakage resistance is 10MΩ. When the accumulated potential exceeds the 0.8V threshold, a 200ns wide output pulse is triggered; To meet the dynamic pruning requirements, the threshold voltage of the LIF neuron can be dynamically adjusted by an 8-bit DAC (adjustment step 0.05V), and the threshold can be appropriately lowered in low load scenarios to speed up pulse triggering and improve calculation efficiency;

[0115] Next, real-time evaluation of the task calculation load is implemented; the following indicators are monitored through the storage and calculation integrated control unit:

[0116] Pulse input frequency per unit time (such as the number of input pulses / ms);

[0117] Effective use rate of the memristor array (proportion of memristor units participating in calculation);

[0118] Discharge frequency of LIF neurons. When the input pulse frequency is <10Hz and the effective use rate is <30%, it is determined to be a low load scenario; when the input pulse frequency is >50Hz and the effective use rate is >70%, it is determined to be a high load scenario;

[0119] Subsequently, the pruning ratio is dynamically adjusted according to the task load:

[0120] Low-load scenario: raise the pruning threshold from the default 0.1 to 0.3, recalculate the L1 norm of the weights through the hardware pruning module, perform secondary pruning on weights below 0.3, and additionally prune 20% redundant neurons; for example, in the MNIST handwritten digit recognition task, the fully connected layer neurons can be pruned from 512 to 307 in low-load, and the invalid cell marker table of the memristor array is updated at the same time;

[0121] High-load scenario: reduce the pruning threshold to 0.05, restore some previously pruned neurons (about 10%), restore the corresponding memristor conductance to 80% of the pruning threshold by applying a +1V voltage pulse, and ensure the calculation accuracy of complex tasks;

[0122] Then, the pulse transmission path is optimized to adapt to dynamic pruning; when the pruning ratio is adjusted, the data routing reconstruction algorithm is started by the compute-in-memory control unit:

[0123] Analyze the spatial distribution of the currently active memristor cells;

[0124] Generate the optimal pulse transmission path through a greedy algorithm to shorten the signal transmission delay;

[0125] Update the row and column gating logic to make the pulse preferentially flow through high-conductance (high-contribution) memristor cells, improving the calculation efficiency by 15-20%;

[0126] Finally, the load adaptive pruning effect is verified in the dynamic object detection scenario:

[0127] When detecting static background (low load), the pruning ratio is raised to 60%, the memristor array power consumption is reduced from 1.2mW to 0.5mW, and the detection accuracy is maintained at 85%;

[0128] When detecting fast-moving objects (high load), 15% of the neurons are restored, the power consumption rises to 0.8mW, and the detection accuracy improves to 89.3%;

[0129] During the entire inference process, the average firing frequency of LIF neurons is dynamically adjusted according to the load, from 20Hz in low-load to 60Hz in high-load, and through dynamic pruning, the system energy efficiency ratio (accuracy / power consumption) is improved by 35%, which is significantly better than the fixed pruning strategy.

[0130] Step seven, after the pulse neural network calculation, output the classification or recognition result in an event-driven manner;

[0131] Specifically, first, after the pulse neural network completes the calculation, the event-driven result aggregation mechanism is started; through the mapping relationship between the discharge frequency of the LIF neuron and the category label, the pulse sequence of the output layer neuron is converted into a classification result; for example, in a 10-class task, the 10 neurons of the output layer correspond to the digital categories 0-9 respectively, and if a neuron discharges the most number of times (such as 30 times) within 100 ms, it is determined that the input image belongs to the category corresponding to the neuron;

[0132] Then, an event-driven output encoding circuit is constructed; the address event representation (AER) protocol is adopted, when the output layer neuron discharges, an event package containing the neuron address (such as category encoding) and time stamp is generated, and is transmitted to the output interface through an asynchronous bus; the event package format is: [category ID (4 bits)] [time stamp (16 bits)], the data amount of a single event package is only 2 bytes, which is 90% less than the traditional frame output, and the transmission power consumption is controlled within 1 μW;

[0133] Next, the reliability enhancement processing of the output result is implemented:

[0134] Time window voting: a 200 ms time window is set, the discharge times of each output neuron in the window are counted, and a weighted voting mechanism (near-time pulse weight = 1, far-time pulse weight = 0.5) is adopted to avoid misjudgment caused by a single noise pulse;

[0135] Confidence calculation: the confidence is calculated according to the difference between the discharge times and the second highest discharge times, when the difference > 10 times, the confidence > 90%, and the result is directly output; when the difference ≤ 10 times, a secondary verification (such as re-inputting the signal to calculate once) is started;

[0136] Subsequently, the adaptation optimization of the output interface is carried out:

[0137] Hardware interface: the output bus supports low-power protocols such as SPI and I2C, and dynamically adjusts the transmission rate (10 kbps-1 Mbps) according to the requirements of external devices, and automatically switches to the I2C protocol (power consumption < 0.5 μW) in low-power mode;

[0138] Software protocol: the output event stream follows the CEF (Compliant Event Format) standard, is compatible with mainstream neuromorphic processors (such as Intel Loihi and IBM TrueNorth), and is convenient for subsequent system integration;

[0139] Next, the precision calibration mechanism of the output result is established; after completing 100 recognition tasks, 10% of the samples are automatically selected for backtracking verification:

[0140] The sample signal is re-inputted, and the deviation of the output result and the true label is recorded;

[0141] If the error rate is greater than 5%, trigger network fine-tuning (invoke the Fine-Tuning process of step five), fine-tune the output layer memristor conductance by ± 5%;

[0142] After calibration, the error rate can be reduced to within 2%, ensuring long-term stability;

[0143] Finally, the event-driven output effect is verified on the MNIST dataset:

[0144] The recognition delay of a single image is 1.2ms (including pulse transmission and result aggregation), which is 85% lower than traditional frame output;

[0145] The output stage power consumption is only 0.8μW, accounting for 0.67% of the entire inference process power consumption;

[0146] The classification accuracy of event-driven output is 95.3%, which is comparable to the traditional synchronous output method, but the data transmission volume is reduced by 92%, suitable for bandwidth-limited Internet of Things scenarios.

[0147] In one embodiment, specifically, in step one, when the input signal is an image signal, the event-driven encoding converts the pixel gray value into pulse frequency, and 255 gray value corresponds to 100Hz pulse frequency, which is time encoded by pulse interval;

[0148] Specifically, when the input signal is an image signal, the event-driven encoding converts the pixel gray value into pulse frequency, wherein 255 gray value corresponds to 100Hz pulse frequency, and the gray value is proportionally mapped to the corresponding pulse frequency, and the time interval between adjacent pulses is used to calculate the weight, so as to realize low-power conversion and brain-like feature extraction of image signals, and provide efficient input for subsequent organic memristor array neural computing;

[0149] Taking the MNIST handwritten digital image (28x28 pixels) as an example, after collecting and normalizing the gray image, set:

[0150] ;

[0151] The gray value 200 corresponds to about 78Hz pulse frequency, and the interval between adjacent pulses when using RIT encoding is converted to weight:

[0152] ;

[0153] After sparsification, about 2000 valid pulses are generated for a single image, which reduces the data volume by 90% compared to traditional frame transmission, and the transmission power consumption is reduced to 5μW.

[0154] In one embodiment, specifically, in step two, the organic memristor array is a copper phthalocyanine-based organic memristor array, and the power consumption of a single device is less than 1 nW, and the storage and update of synaptic weights are realized through the adjustable conductance characteristic;

[0155] Specifically, the copper phthalocyanine-based organic memristor array adopted is a device array with a “ITO / CuPc / Pt” sandwich structure, in which copper phthalocyanine (CuPc) is used as the active material. A 50 nm thick CuPc layer is deposited on a flexible PET substrate by vacuum evaporation process. The upper and lower electrodes are ITO transparent electrode and Pt metal electrode, respectively. The size of a single device is 10 μm × 10 μm. The power consumption of a single device is less than 1 nW. The conductance adjustment range is 0.1 μS to 10 μS when a ±1 V voltage is applied. The weight matrix obtained by neural network training is mapped to the conductance value of the memristor to realize the physical storage and update of synaptic weights. Meanwhile, the array is integrated with a low-energy pruning module, a LIF neuron calculation core, and a storage and calculation integrated control unit to form a collaborative computing architecture, which lays a hardware foundation for weight learning and pruning optimization.

[0156] For example, in the implementation scenario of MNIST handwritten digit recognition, a copper phthalocyanine-based organic memristor array with a scale of 28 × 28 is prepared, the device size is 10 μm × 10 μm, the CuPc active layer is deposited on the PET substrate by vacuum evaporation, and the “ITO / CuPc / Pt” structure is constructed. The power consumption of a single device is 0.8 nW under 100 Hz pulse driving, the conductance can be adjusted between 0.1 μS and 10 μS by ±1 V voltage, and the synaptic weight range is [-1, 1]. The array is integrated with a pruning module based on FPGA (supporting L1 norm calculation, threshold adjustment step 0.05), a LIF neuron core constructed by a transconductance operational amplifier (membrane potential capacitance 1 nF, leakage resistance 10 MΩ, trigger threshold 0.8 V), and an ARM Cortex-M4 control unit to form a collaborative computing architecture. The architecture achieves a recognition accuracy of 95% on the MNIST dataset, and the overall power consumption is only 1.2 mW, of which the power consumption of the copper phthalocyanine memristor array accounts for 65%. Compared with the traditional silicon-based neural network scheme, the energy consumption is reduced by 80%, which verifies the effectiveness of the copper phthalocyanine-based memristor array in realizing low-power synaptic weight storage and update through the adjustable conductance characteristic.

[0157] In one embodiment, specifically, in step three, the STDP rule is:

[0158] When the pre-synaptic pulse precedes the post-synaptic pulse, the conductance of the organic memristor increases by ΔG = 0.01G0;

[0159] When the post-synaptic pulse precedes the pre-synaptic pulse, the conductance decreases by ΔG = 0.005G0;

[0160] wherein G0 is an initial conductance value;

[0161] Specifically, the STDP (spike-timing-dependent plasticity) rule simulates the timing-dependent weight adjustment mechanism of biological synapses, and realizes online learning of synaptic weights by using the conductance-adjustable characteristics of organic memristors. The core of the STDP rule is to dynamically adjust the conductance of the memristor according to the time difference between the pre-synaptic pulse and the post-synaptic pulse: when the pre-synaptic pulse precedes the post-synaptic pulse, a voltage pulse is applied to increase the conductance of the memristor by ΔG = 0.01G0 (G0 is the initial conductance of 1 μS), thereby strengthening the synaptic connection; when the post-synaptic pulse precedes the pre-synaptic pulse, the conductance is reduced by ΔG = 0.005G0, thereby weakening the synaptic connection, so as to realize adaptive updating of the weights of the neural network.

[0162] For example, in a three-layer pulse neural network based on a copper phthalocyanine-based memristor (input layer of 28x28 neurons, hidden layer of 128 neurons, and output layer of 10 neurons), the STDP rule is implemented for the MNIST handwritten digit recognition task.

[0163] The memristor array adopts an "ITO / CuPc / Pt" structure, and the initial conductance of a single device is G0 = 1 μS. The conductance is adjusted by ±1V voltage pulses (width of 10 μs), and the voltage pulses are generated by the STDP controller according to the time difference Δt between the pre-synaptic pulse and the post-synaptic pulse.

[0164] When an input image (such as the number "3") is event-driven encoded to generate a pulse sequence, the hidden layer neurons receive the pre-synaptic pulse (discharge of the input layer) and the post-synaptic pulse (discharge of the hidden layer itself), and the time stamp comparator records Δt. If the pre-synaptic pulse is 15 ms earlier than the post-synaptic pulse (Δt = 15 ms > 0), a +1V pulse is triggered to increase the conductance of the corresponding memristor by 0.01x1 μS = 0.01 μS, and the updated conductance is 1.01 μS. If the post-synaptic pulse is 10 ms earlier than the pre-synaptic pulse (Δt = -10 ms < 0), a -1V pulse is applied to reduce the conductance by 0.005x1 μS = 0.005 μS, and the updated conductance is 0.995 μS.

[0165] After 500 rounds of training, the STDP rule enables the network to maintain an identification accuracy of 92.3% at a pruning rate of 30%, which is 8.1% higher than that of the fixed weight network. The average conductance update times of a single memristor device in the training is 180, which is within the range of 10 5 times of durability, and the energy consumption of each round of training is only 0.2 mW, which verifies the low-power learning capability of the STDP rule combined with the copper phthalocyanine memristor.

[0166] In one embodiment, specifically, in step four, the structural pruning includes deleting unimportant neurons or channels in the neural network, the non-structural pruning is to set low-contribution weights to zero, and the pruning threshold is dynamically adjusted according to the validation set accuracy, and the adjustment step is 0.05;

[0167] Specifically, the structural pruning and the non-structural pruning achieve precise pruning of redundant connections in the neural network by quantifying the importance of weights and dynamically adjusting the threshold, as follows:

[0168] The structural pruning directly reduces the network size by deleting unimportant neurons or channels in the neural network (such as neurons with output variance less than 20% of the threshold in the fully connected layer, and the 10% channels with the smallest L1 norm in the convolutional layer);

[0169] The non-structural pruning sets low-contribution weights below the threshold to zero, retains the network topology but reduces invalid calculations, and the pruning threshold is dynamically adjusted according to the validation set accuracy with a step of 0.05 (such as reducing the threshold when the accuracy decreases by more than 3%, and increasing the threshold when it is stable), to balance the accuracy and computational efficiency.

[0170] In one embodiment, specifically, in step five, the number of iterations of short-term Fine-Tuning training is 5-10, and the network accuracy is restored to more than 85% of that before pruning by adjusting the effective weights;

[0171] Specifically, the short-term Fine-Tuning training optimizes the network weights after pruning through limited iterations, and uses the plasticity of organic memristors to restore the calculation accuracy: after the pruning operation, 10%-20% of representative training samples (such as 500 images of each class in CIFAR-10) are selected, 5-10 iterations (10 times when the pruning rate is greater than 40%) and a learning rate of 0.001 (1 / 10 of the initial training) are used to perform gradient descent, and the conductance of the memristor is adjusted through the STDP rule: if the presynaptic pulse arrives first, a +0.5V pulse is applied to increase the conductance by 0.005G0, otherwise a -0.5V pulse is applied to decrease the conductance by 0.0025G0 (G0=1μS), and after each round of training, the memristor units with an error in conductance greater than 3% are calibrated, finally the network accuracy is restored to more than 85% of that before pruning;

[0172] For example: on the MNIST dataset, a three-layer SNN (input layer 784, hidden layer 256, output layer 10) with a pruning rate of 50% is executed Fine-Tuning:

[0173] Select 1000 representative images, event-driven encoding as pulse sequence, iteration number set to 5 times, batchsize=32;

[0174] In forward propagation, the pruned memristor array (devices with conductance >0.1 μS are reserved) performs weighted summation, and the LIF neuron triggers a pulse when the accumulated membrane potential reaches a threshold;

[0175] During back propagation, the memristor units corresponding to effective weights are applied with ±0.5V voltage pulses (5 μs wide) to adjust the conductance value. For example, if the initial conductance of a memristor corresponding to a certain weight is 2 μS, it is increased to 2.1 μS after optimization;

[0176] After each round of training, the conductance is measured, and a +0.1V calibration pulse is applied to units with an error >3% (e.g., the target is 3 μS, but the measured value is 2.9 μS) to ensure the accuracy of the weights;

[0177] After pruning, the initial accuracy is 82%, and after Fine-Tuning, it is increased to 87.6% (exceeding the target of 85%), with an energy consumption of 0.8 mW, which is 75% lower than the GPU solution. A single memristor is updated 120 times (within the 10 5 times of endurance), verifying the accuracy recovery capability of short-term Fine-Tuning combined with the plasticity of memristors.

[0178] In one embodiment, specifically in step six, the pruning ratio is dynamically adjusted according to the task computing load, specifically:

[0179] The pruning threshold for simple tasks is increased to 0.3, and 40% of redundant weights are pruned;

[0180] The pruning threshold for complex tasks is reduced to 0.05, retaining more weights;

[0181] Specifically, in the dual-task switching scenario of intelligent terminals, when the system detects that the user switches from a complex scenario (such as real-time video analysis) to a simple scenario (such as handwritten digit input):

[0182] The input pulse frequency is reduced from 50 Hz to 10 Hz, and the effective usage rate of the memristor array is reduced from 75% to 25%, indicating a simple task;

[0183] The pruning threshold is increased from 0.05 to 0.3, and the structural pruning module is started to delete 40% of redundant neurons in the fully connected layer (e.g., from 512 to 307). Non-structural pruning sets weights with L1 norm <0.3 to zero, and the corresponding memristor units are reset to zero conductance by a -1V voltage pulse;

[0184] After switching to the MNIST recognition task, the network recognition accuracy remains 95.3% when the pruning rate is 40%, the memristor array power consumption is reduced from 1.2 mW to 0.5 mW, and the calculation delay is shortened from 2.1 ms to 1.3 ms; when switching to the CIFAR-10 detection again, the threshold is reduced to 0.05, the accuracy is restored to 87.2% by restoring part of the neurons (about 15%), and the power consumption is increased to 0.8 mW, realizing energy efficiency adaptive optimization under different task loads.

[0185] In summary, the neural network architecture generation method of the memristor provided by the embodiment of the present application encodes the input signal in an event-driven manner and converts it into a pulse sequence, constructs a cooperative computing architecture of a copper phthalocyanine-based organic memristor array to store weights, dynamically adjusts the conductance of the memristor based on the STDP rule to learn and update the synaptic weights online, calculates the weight norm or gradient contribution in the pruning optimization stage, performs structural and non-structural pruning and updates the state of the memristor, re-adjusts the weights by using the plasticity of the memristor through short-term Fine-Tuning training after pruning, dynamically adjusts the pruning ratio according to the task load in the inference stage, and finally outputs the result in an event-driven manner, realizing low-power and efficient neural network architecture generation.

[0186] Figure 2 Figure 1 is a schematic diagram of the functional modules of the neural network architecture generation device of the memristor according to the embodiment of the present application, as shown in the figure, the neural network architecture generation device of the memristor comprises a signal acquisition and encoding module, a computing architecture construction module, a synaptic weight learning module, a pruning optimization module, a network fine-tuning module, an inference calculation module and a result output module. Figure 2

[0187] The signal acquisition and encoding module is configured to acquire an input signal and perform event-driven encoding, convert the input signal into a pulse sequence, and perform neural computation using pulse time information in a time coding manner.

[0188] The computing architecture construction module is configured to construct a cooperative computing architecture, deploy an organic memristor array to store weights, integrate a low-energy pruning module, a LIF neuron calculation core and a memory-computing integrated control unit, and use the synaptic plasticity of the organic memristor to lay a hardware foundation for weight learning and pruning optimization.

[0189] The synaptic weight learning module is configured to store synaptic weights through the organic memristor array, dynamically adjust the conductance of the organic memristor based on the STDP rule to learn and update the synaptic weights online.

[0190] The pruning optimization module is configured to calculate the L1 / L2 norm or gradient contribution of the synaptic weights in the pruning optimization stage, perform structural pruning or non-structural pruning on redundant weights below the threshold after setting the threshold, and update the state of the organic memristor. ​

[0191] a network fine-tuning module configured to adjust the weights through short-term Fine-Tuning training after pruning;

[0192] a reasoning calculation module configured to perform pulse transmission calculation using the pruned organic memristor array in the reasoning stage, accumulate trigger pulses through LIF neurons, and dynamically adjust the pruning ratio according to the task calculation load to prune more redundant neurons in a low-load scenario;

[0193] a result output module configured to output the classification or recognition result in an event-driven manner after pulse neural network calculation.

[0194] To sum up, the neural network architecture generation device of the memristor provided by the embodiment of the present application acquires input signals through the signal acquisition and coding module and performs event-driven coding to convert the input signals into pulse sequences, uses the calculation architecture construction module to construct a collaborative calculation architecture of the organic memristor array to store the weights, uses the synaptic weight learning module to make the memristor conductance dynamically adjusted to learn and update the weights online based on the STDP rule, uses the pruning optimization module to calculate the weight norm or gradient contribution, performs structural and non-structural pruning and updates the memristor state, uses the network fine-tuning module to adjust the weights through short-term Fine-Tuning training after pruning, uses the reasoning calculation module to dynamically adjust the pruning ratio according to the task load in the reasoning stage, and finally uses the result output module to output the result in an event-driven manner, thereby realizing low-power generation and optimization of the neural network architecture.

[0195] For other details of the implementation of each module in the neural network architecture generation device of the memristor in the above embodiment, refer to the description in the neural network architecture generation method of the memristor in the above embodiment, which will not be repeated here.

[0196] It should be noted that each embodiment in the present specification adopts a progressive description manner, and each embodiment focuses on the difference from other embodiments, and the same and similar parts between embodiments can be referred to each other. For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant part can refer to the part of the method embodiment.

[0197] As Figure 3 A structural schematic diagram of an electronic device is provided in the embodiment of the present disclosure. It shows a structural schematic diagram suitable for realizing the electronic device in the embodiment of the present disclosure. Figure 3 The electronic device shown is only an example, and should not bring any limitation to the function and use range of the embodiment of the present disclosure.

[0198] As Figure 3As shown, the electronic device can include a processor (e.g., a central processing unit, a graphics processing unit, etc.) that can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) or a program loaded into a random access memory (RAM) from a storage device. In the RAM, various programs and data required for the operation of the electronic device are also stored. The processor, the ROM, and the RAM are connected to each other through a bus. An input / output (I / O) interface is also connected to the bus.

[0199] Generally, the following devices can be connected to the I / O interface: input devices including, for example, a sensor or a visual information collection device; output devices including, for example, a display screen; storage devices including, for example, a magnetic tape, a hard disk, etc.; and communication devices. The communication devices can allow the electronic device to communicate wirelessly or wired with other devices (such as edge computing devices) to exchange data. Although Figure 3 The electronic device is shown with various devices, but it is understood that not all of the shown devices are required to be implemented or present. More or fewer devices can alternatively be implemented or present.

[0200] In particular, according to embodiments of the present disclosure, the processes described above with reference to the flowcharts can be implemented as a computer software program. For example, embodiments of the present disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network through the communication devices, or installed from the storage devices, or installed from the ROM. When the computer program is executed by the processor, all or part of the steps of the neural network architecture generation method of the memristor of the embodiments of the present disclosure are performed.

[0201] Detailed descriptions of the present embodiments can refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0202] According to the computer-readable storage medium of the embodiments of the present disclosure, the non-transitory computer-readable instructions are stored thereon. When the non-transitory computer-readable instructions are run by the processor, all or part of the steps of the neural network architecture generation method of the memristor of the embodiments of the present disclosure are performed.

[0203] The above computer-readable storage medium includes, but is not limited to, optical storage media (e.g., CD-ROM and DVD), magneto-optical storage media (e.g., MO), magnetic storage media (e.g., magnetic tape or a mobile hard disk), media with built-in rewritable non-volatile memory (e.g., a memory card), and media with built-in ROM (e.g., a ROM cartridge).

[0204] For details of the present embodiment, reference can be made to the corresponding description in the foregoing embodiments, which will not be repeated here.

[0205] The above has described the basic principles of the present disclosure in combination with specific embodiments, but it needs to be pointed out that the advantages, benefits, effects and the like mentioned in the present disclosure are only examples and not limitations, and these advantages, benefits, effects and the like cannot be considered as necessary for each embodiment of the present disclosure. In addition, the above specific details of the disclosure are only for the purpose of example and for the purpose of understanding, and not for limitation, and the above details do not limit the present disclosure to be necessarily implemented with the above specific details.

[0206] In the present disclosure, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations, and the block diagrams of the devices, apparatuses, equipment, systems involved in the present disclosure are only illustrative examples and are not intended to require or imply the connection, arrangement, configuration as shown in the block diagram. As those skilled in the art will recognize, these devices, apparatuses, equipment, systems can be connected, arranged, configured in any manner. Words such as "include", "contain", "have" and the like are open-ended words, which mean "including but not limited to", and can be used interchangeably. The words "or" and "and" used herein mean the word "and / or", and can be used interchangeably unless the context clearly indicates otherwise. The word "such as" used herein means the phrase "such as but not limited to", and can be used interchangeably.

[0207] In addition, as used herein, "or" used in a list of items, starting with "at least one of", indicates a disjunctive list such that, for example, "at least one of A, B, or C" means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, the phrase "exemplary" does not mean that a described example is preferred or better than other examples.

[0208] It also needs to be pointed out that in the systems and methods of the present disclosure, each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions of the present disclosure.

[0209] Various changes, modifications, and alterations to the techniques described herein can be made without departing from the teachings of the attached claims. Moreover, the scope of the claims of the present disclosure is not limited to the particular aspects described herein. Rather, the scope of the claims of the present disclosure includes all alternatives, modifications, and equivalents falling within the scope of the claims of the present disclosure. Accordingly, the attached claims are incorporated into this Detailed Description by reference.

[0210] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other aspects without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0211] The above description has been presented for the purpose of illustration and description. Furthermore, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although various example aspects and embodiments have been discussed above, those of ordinary skill in the art will appreciate a variety of modifications, alternatives, permutations, and equivalents thereof. Accordingly, the disclosure is intended to embrace all such alterations, modifications, and permutations of the aspects described herein, including other aspects falling within the scope of the appended claims.

Claims

1. A method for generating a neural network architecture for memristors, characterized in that, Includes the following steps: The input signal is acquired and event-driven encoded, and then converted into a pulse sequence. The pulse time information is used for neural computation using a time encoding method. A collaborative computing architecture is constructed, an organic memristor array is deployed to store weights, and a low-power pruning module, a LIF neuron computing core, and an in-memory computing control unit are integrated. The synaptic plasticity of organic memristors lays the hardware foundation for weight learning and pruning optimization. Synaptic weights are stored using an organic memristor array, and the conductance of the organic memristor is dynamically adjusted during training based on the STDP rule, enabling online learning and updating of synaptic weights. During the pruning optimization phase, the L1 / L2 norm or gradient contribution of synaptic weights is calculated. After setting a threshold, structural or unstructured pruning is performed on redundant weights below the threshold, and the organic memristor state is updated. After pruning, the weights are readjusted using the plasticity of organic memristors through short-term fine-tuning training. During the inference phase, a pruned organic memristor array is used for pulse transmission computation. The trigger pulses are accumulated through LIF neurons, and the pruning ratio is dynamically adjusted according to the task computation load to prune more redundant neurons in low-load scenarios. After being processed by a spiking neural network, the classification or recognition results are output in an event-driven manner.

2. The method for generating a neural network architecture for a memristor according to claim 1, characterized in that: The organic memristor array is a copper phthalocyanine-based organic memristor array, with a single device power consumption of less than 1nW, and synaptic weights are stored and updated through adjustable conductivity.

3. The method for generating a neural network architecture for a memristor according to claim 1, characterized in that: The STDP rule is as follows: When the presynaptic pulse precedes the postsynaptic pulse, the conductance of the organic memristor increases by ΔG = 0.01G0; When the postsynaptic pulse precedes the presynaptic pulse, the conductance decreases by ΔG = 0.005G0; Where G0 is the initial conductivity value.

4. The method for generating a neural network architecture for a memristor according to claim 1, characterized in that: The structural pruning includes deleting unimportant neurons or channels in the neural network, while the unstructured pruning involves resetting low contribution weights to zero, and the pruning threshold is dynamically adjusted based on the accuracy of the validation set, with an adjustment step size of 0.

05.

5. The method for generating a neural network architecture for a memristor according to claim 1, characterized in that: The specific steps for dynamically adjusting the pruning ratio based on the task calculation load are as follows: The pruning threshold for simple tasks is increased to 0.3, and 40% of redundant weights are removed. The pruning threshold for complex tasks is reduced to 0.05, retaining more weights.

6. The method for generating a neural network architecture for a memristor according to claim 1, characterized in that: When the input signal is an image signal, the event-driven encoding converts the pixel grayscale value into a pulse frequency. A grayscale value of 255 corresponds to a pulse frequency of 100Hz, and time encoding is performed through the pulse interval.

7. The method for generating a neural network architecture for a memristor according to claim 1, characterized in that: In step five, the number of iterations of the short-term fine-tuning training is 5-10 times, and the network accuracy is restored to more than 85% of that before pruning by adjusting the effective weights.

8. A memristor neural network architecture generation apparatus, applied to the memristor neural network architecture generation method according to any one of claims 1-7, characterized in that, include: The system includes a signal acquisition and encoding module, a computational architecture construction module, a synaptic weight learning module, a pruning and optimization module, a network fine-tuning module, an inference computation module, and a result output module. The signal acquisition and encoding module is configured to acquire input signals and perform event-driven encoding, convert the input signals into pulse sequences, and use time encoding to perform neural computation using pulse time information. The computing architecture building module is configured to build a collaborative computing architecture, deploy an organic memristor array to store weights, integrate a low-power pruning module, a LIF neuron computing core, and an in-memory computing control unit, and utilize the synaptic plasticity of organic memristors to lay the hardware foundation for weight learning and pruning optimization. The synaptic weight learning module is configured to store synaptic weights through an organic memristor array, and dynamically adjust the conductance of the organic memristor based on the STDP rule to learn and update synaptic weights online. The pruning optimization module is configured to calculate the L1 / L2 norm or gradient contribution of synaptic weights during the pruning optimization stage, set a threshold, perform structural or unstructured pruning on redundant weights below the threshold, and update the organic memristor state. The network fine-tuning module is configured to readjust the weights using the plasticity of organic memristors after pruning and short-term fine-tuning training. The inference computing module is configured to use a pruned organic memristor array for pulse transmission computing during the inference phase, accumulate trigger pulses through LIF neurons, and dynamically adjust the pruning ratio according to the task computing load to prune more redundant neurons in low-load scenarios. The result output module is configured to output classification or recognition results in an event-driven manner after calculation by a spiking neural network.

9. An electronic device, characterized in that, The electronic device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the neural network architecture generation method for the memristor according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing a computer to perform the method for generating a neural network architecture for a memristor as described in any one of claims 1-7.

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