Gate driving unit, gate driving circuit, display panel and display device

Abstract

The application relates to a gate driving unit, a gate driving circuit, a display panel and a display device. The gate driving unit comprises a sampling module, an output module and a rollback module. The sampling module is connected with the output module through a first connection node, and the sampling module is connected with the rollback module through a second connection node. The sampling module is used for sampling an input previous-stage scanning signal, and the first connection node and the second connection node are determined according to a sampling result. The output module is used for determining the potential of the current-stage scanning signal according to the potential of the first connection node in a display scanning mode, so as to control the display state of the current-stage pixel row by using the current-stage scanning signal. The rollback module is used for outputting a reset signal according to the potential of the second connection node in an intra-frame scanning mode, so as to rollback the state of a target pixel row by using the reset signal, and the target pixel row is a pixel row located in front of the current-stage pixel row by a preset row. Thus, the horizontal pit and groove appearing in the intra-frame scanning can be effectively solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a gate driving unit, a gate driving circuit, a display panel and a display device. BACKGROUND

[0002] With the continuous maturity of liquid crystal display technology, liquid crystal display (LCD) has many advantages such as thin body, power saving, no radiation, etc., and thus is widely applied. For example, it is widely applied in liquid crystal televisions, mobile phones, personal digital assistants, digital cameras, computers or notebook computers and other devices.

[0003] At present, intra-frame scanning is one of the common touch scanning schemes of LCD, which needs to scan multiple times in the display scanning process of the same frame to obtain the capacitance value generated by touch. Therefore, during the intra-frame scanning, in order to avoid the interference to the digital signal (i.e. data signal) caused by the jump coupling of the common electrode voltage (i.e. VCOM signal), the gate driving on array (GOA) unit and the data signal need to be closed during the intra-frame scanning, and the data signal is written again after the intra-frame scanning is completed. Due to the GOA closing and restarting, and the existence of the rising and falling edges of the GOA pre-charge row, the same driving data signal may be incorrectly written before the scanning cutoff row is cut off, and the horizontal pit phenomenon may occur, as shown in FIG. 1. Figure 1 Therefore, how to avoid the horizontal pit phenomenon caused by intra-frame scanning has become a technical problem to be solved. SUMMARY

[0004] The present application provides a gate driving unit, a gate driving circuit, a display panel and a display device to solve the problem that the existing intra-frame scanning is prone to the horizontal pit phenomenon.

[0005] In a first aspect, an embodiment of the present application provides a gate driving unit, which comprises a sampling module, an output module and a rollback module.

[0006] The sampling module is connected with the output module through a first connection node, and is connected with the rollback module through a second connection node. The sampling module is configured to sample an input previous stage scanning signal, and determine the potentials of the first connection node and the second connection node according to the sampling result.

[0007] The output module is configured to determine the potential of a current stage scanning signal according to the potential of the first connection node in a display scanning mode, so as to control the display state of a current stage pixel row by using the current stage scanning signal.

[0008] The reset module is configured to output a reset signal according to the potential of the second connection node in the intra-frame scanning mode, so as to reset the state of a target pixel row, which is a pixel row located in front of the current pixel row by a preset number of rows.

[0009] Optionally, the reset module comprises a first switch tube, a second switch tube, a third switch tube and a fourth switch tube.

[0010] The source of the first switch tube is connected with a first voltage source, the source of the second switch tube is connected with a second voltage source, the drain of the first switch tube and the drain of the second switch tube are both connected with the output end of the reset signal and are connected with the sampling module of the gate driving unit corresponding to the target pixel row.

[0011] The gate of the first switch tube and the gate of the second switch tube are both connected with the drain of the third switch tube, the gate of the third switch tube is connected with a first clock signal, the source of the third switch tube is connected with the drain of the fourth switch tube, the gate of the fourth switch tube is connected with a second clock signal, and the source of the fourth switch tube is connected with the second connection node.

[0012] In the display scanning mode, the first clock signal and the second clock signal are two clock signals with opposite phases; in the intra-frame scanning mode, the first clock signal and the second clock signal are both low potential signals, and the voltage value of the first voltage source is lower than the voltage value of the second voltage source.

[0013] Optionally, in the case of a scanning stop row of the current pixel row, the potential of the second connection node is high potential, and the reset module outputs a high potential signal as the reset signal.

[0014] In the case of a non-scanning stop row of the current pixel row, the potential of the second connection node is low potential, and the reset module outputs a low potential signal as the reset signal.

[0015] Optionally, the sampling module comprises a fifth switch tube, a sixth switch tube, a seventh switch tube, a first capacitor and a second capacitor.

[0016] The drain of the fifth switch tube and the drain of the seventh switch tube are both connected with the output end of the previous stage scanning signal, the gate of the fifth switch tube is connected with the first clock signal, and the source of the fifth switch tube is connected with the first end of the first capacitor and the drain of the sixth switch tube, respectively.

[0017] A gate of the sixth switch tube is connected with the second clock signal, and a source of the sixth switch tube is connected with the first connection node; a gate of the seventh switch tube is connected with the first clock signal, a source of the seventh switch tube is connected with a source of the fourth switch tube and a first end of the second capacitor through the second connection node, and a second end of the first capacitor and a second end of the second capacitor are both connected with the first voltage source.

[0018] Optionally, the output module comprises a pull-down resistor, an eighth switch tube, a ninth switch tube and a tenth switch tube.

[0019] The first end of the pull-down resistor is connected with the first voltage source, the second end of the pull-down resistor is connected with the first connection node, a gate of the eighth switch tube and a gate of the ninth switch tube respectively, a drain of the eighth switch tube is connected with the second clock signal, a source of the eighth switch tube and a drain of the tenth switch tube are both used as an output end of a scanning signal of a current stage and connected with a pixel row of the current stage.

[0020] A drain of the ninth switch tube is connected with a gate of the tenth switch tube, a source of the ninth switch tube is connected with the second voltage source, and a source of the tenth switch tube is connected with the first voltage source.

[0021] Optionally, in a case that the scanning signal is effective in a high potential, the first switch tube, the third switch tube, the fourth switch tube and the ninth switch tube are P-type field effect tubes, and the second switch tube, the fifth switch tube, the sixth switch tube, the seventh switch tube, the eighth switch tube and the tenth switch tube are N-type field effect tubes.

[0022] Optionally, in a case that the scanning signal is effective in a low potential, the first switch tube, the third switch tube, the fourth switch tube and the ninth switch tube are N-type field effect tubes, and the second switch tube, the fifth switch tube, the sixth switch tube, the seventh switch tube, the eighth switch tube and the tenth switch tube are P-type field effect tubes.

[0023] In a second aspect, the embodiments of the present application further provide a gate driving circuit, comprising: a plurality of gate driving units as described in the first aspect, the plurality of gate driving units are cascaded in sequence, and each of the gate driving units corresponds to a pixel row.

[0024] In a third aspect, the embodiments of the present application further provide a display panel, comprising an array substrate and a gate driving circuit as described in the second aspect, wherein the gate driving circuit is arranged on the array substrate.

[0025] In a fourth aspect, the embodiments of the present application further provide a display device, which comprises a housing and the display panel as described in the third aspect, and the display panel is arranged on the housing.

[0026] Compared with the prior art, the technical solution provided by the embodiments of the present application has the following advantages: the gate drive unit comprises a sampling module, an output module and a rollback module; the sampling module is connected with the output module through a first connection node, and is connected with the rollback module through a second connection node; the sampling module is configured to sample an input previous-stage scanning signal, and determine the potentials of the first connection node and the second connection node according to a sampling result; the output module is configured to determine the potential of a current-stage scanning signal according to the potential of the first connection node in a display scanning mode, so as to control the display state of a current-stage pixel row by using the current-stage scanning signal; and the rollback module is configured to output a reset signal according to the potential of the second connection node in an intra-frame scanning mode, so as to rollback the state of a target pixel row by using the reset signal, the target pixel row being a pixel row located in front of the current-stage pixel row by a preset number of rows. In this way, the gate drive unit can determine the potential of the current-stage scanning signal according to the potential of the first connection node in the display scanning mode by using the output module, so as to control the display state of the current-stage pixel row by using the current-stage scanning signal, and can output the reset signal according to the potential of the second connection node in the intra-frame scanning mode by using the rollback module, so as to rollback the state of the target pixel row by using the reset signal, thereby effectively avoiding the horizontal pit lines caused by the intra-frame scanning, and achieving the purpose of improving the display effect of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0027] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles of the application.

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, those skilled in the art can obtain other drawings from these drawings without any creative effort.

[0029] One or more embodiments are illustrated by way of example with reference to the drawings, which are not construed as limiting the embodiments, and elements having the same reference numerals in the drawings represent the same elements, unless otherwise specified. The drawings in the drawings do not constitute a proportional limitation.

[0030] Figure 1 Principle diagram of existing intra-frame scanning horizontal pit lines;

[0031] Figure 2 A structure schematic diagram of a gate driving unit provided for an embodiment of the present application is shown in FIG. 1;

[0032] Figure 3 A structure schematic diagram of a gate driving unit provided for another embodiment of the present application is shown in FIG. 2;

[0033] Figure 4 A state schematic diagram of a gate driving unit in a sampling stage of a display scanning mode provided for an embodiment of the present application is shown in FIG. 3;

[0034] Figure 5 A state schematic diagram of a gate driving unit in an output stage of a display scanning mode provided for an embodiment of the present application is shown in FIG. 4;

[0035] Figure 6 A state schematic diagram of a gate driving unit in a reset stage of a display scanning mode provided for an embodiment of the present application is shown in FIG. 5;

[0036] Figure 7 A state schematic diagram of a gate driving unit in a subsequent cycle of a display scanning mode provided for an embodiment of the present application is shown in FIG. 6;

[0037] Figure 8 A state schematic diagram of a gate driving unit in an intra-frame scanning mode provided for an embodiment of the present application is shown in FIG. 7;

[0038] Figure 9 A state schematic diagram of a gate driving unit in another intra-frame scanning mode provided for an embodiment of the present application is shown in FIG. 8;

[0039] Figure 10 A flyback effect schematic diagram provided for an embodiment of the present application is shown in FIG. 9;

[0040] Figure 11 A structure schematic diagram of a gate driving circuit provided for an embodiment of the present application is shown in FIG. 10;

[0041] Figure 12 A structure schematic diagram of a display panel provided for an embodiment of the present application is shown in FIG. 11;

[0042] Figure 13 A structure schematic diagram of a display device provided for an embodiment of the present application is shown in FIG. 12.

[0043] Wherein, 100, gate drive unit; 110, sampling module; 120, output module; 130, rollback module; A, first connection node; B, second connection node; T1, first switch tube; T2, second switch tube; T3, third switch tube; T4, fourth switch tube; T5, fifth switch tube; T6, sixth switch tube; T7, seventh switch tube; C1, first capacitor; C2, second capacitor; R1, pull-down resistor; T8, eighth switch tube; T9, ninth switch tube; T10, tenth switch tube. DETAILED DESCRIPTION

[0044] To make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work belong to the scope of protection of the present application.

[0045] The following disclosure provides many different embodiments, or examples, for implementing different structures of the present application. For the purpose of simplicity, the components and arrangements of the examples, which are depicted in the following disclosure are shown as being in electrical communication or positional relationship to one another. It will be recognized by those skilled in the art that other implementations and arrangements can be made without departing from the scope of the present application. It should be noted that many of the materials described herein are by way of example and thus specific details are not required as aspects of the application can be practiced with a wide and varied variety of systems, apparatuses, and materials. Moreover, descriptions of any example embodiments are intended to include all possible combinations of the described elements. It is intended that each element described herein can be replaced by any suitable element that produces the same or similar results.

[0046] Reference will now be made to Figure 2 , Figure 2 A structural schematic diagram of a gate drive unit provided by the embodiments of the present application is shown in FIG. 1. As shown in FIG. 1, the gate drive unit 100 includes a sampling module 110, an output module 120 and a rollback module 130. Figure 2

[0047] The sampling module 110 is connected with the output module 120 through a first connection node A, and the sampling module 110 is connected with the rollback module 130 through a second connection node B. The sampling module 110 is configured to sample an input previous-stage scanning signal, and determine the potentials of the first connection node A and the second connection node B according to the sampling result.

[0048] The output module 120 is configured to determine the potential of a current-stage scanning signal according to the potential of the first connection node A in a display scanning mode, so as to control the display state of a current-stage pixel row by using the current-stage scanning signal.

[0049] ​The reset module 130 is configured to output a reset signal according to the potential of the second connection node B in the intra-frame scanning mode, so as to reset the state of a target pixel row, which is a pixel row located in front of the current pixel row by a preset number of rows.

[0050] Specifically, each gate drive unit 100 can correspond to one pixel row. Assuming that a display panel has N pixel rows, N gate drive units 100 are needed to drive and control the pixel rows corresponding thereto, where N is any integer greater than 0. For the convenience of understanding, the gate drive unit 100 at the nth stage can be taken as an example for illustration, where n is any value in the range of 1 to N.

[0051] The sampling module 110 can sample the input previous-stage scanning signal Scan(n-1) and determine the potentials of the first connection node A and the second connection node B according to the sampling result. Here, the previous-stage scanning signal Scan(n-1) refers to the scanning signal output by the previous-stage gate drive unit 100.

[0052] The output module 120 can determine the potential of the current-stage scanning signal Scan(n) according to the potential of the first connection node A in the display scanning mode, so as to control the display state of the current-stage pixel row by using the current-stage scanning signal Scan(n). Here, the current-stage scanning signal Scan(n) refers to the scanning signal output by the current-stage gate drive unit 100.

[0053] The reset module 130 can output a reset signal RST(n-x) according to the potential of the second connection node B in the intra-frame scanning mode, so as to reset the state of a target pixel row (i.e., the n-x pixel row) by using the reset signal RST(n-x). Here, x refers to the number of pixel rows to be reset, and the value of x can be set according to actual needs, such as 2, 3, 4, etc.

[0054] In this way, the gate drive unit 100 can determine the potential of the current-stage scanning signal Scan(n) according to the potential of the first connection node A in the display scanning mode by using the output module 120, so as to control the display state of the current-stage pixel row by using the current-stage scanning signal Scan(n), and can output a reset signal RST(n-x) according to the potential of the second connection node B in the intra-frame scanning mode by using the reset module 130, so as to reset the state of a target pixel row by using the reset signal RST(n-x). In this way, the horizontal scratches caused by intra-frame scanning can be effectively avoided, and the display effect of the display panel can be improved.

[0055] In an optional embodiment, please refer to Figure 3The rollback module 130 comprises a first switch tube T1, a second switch tube T2, a third switch tube T3 and a fourth switch tube T4.

[0056] The source of the first switch tube T1 is connected with a first voltage source VGL, the source of the second switch tube T2 is connected with a second voltage source VGH, the drain of the first switch tube T1 and the drain of the second switch tube T2 are both output terminals of a reset signal RST(n-x) and are connected with the sampling module 110 of the gate driving unit 100 corresponding to the target pixel row.

[0057] The gate of the first switch tube T1 and the gate of the second switch tube T2 are both connected with the drain of the third switch tube T3, the gate of the third switch tube T3 is connected with a first clock signal XCK, the source of the third switch tube T3 is connected with the drain of the fourth switch tube T4, the gate of the fourth switch tube T4 is connected with a second clock signal CK, and the source of the fourth switch tube T4 is connected with the second connection node B.

[0058] In the case of the display scanning mode, the first clock signal XCK and the second clock signal CK are two clock signals with opposite phases; in the case of the intra-frame scanning mode, the first clock signal XCK and the second clock signal CK are both low potential signals, and the voltage value of the first voltage source VGL is lower than the voltage value of the second voltage source VGH.

[0059] Specifically, since the first clock signal XCK and the second clock signal CK are two clock signals with opposite phases in the display scanning mode, if the third switch tube T3 is in the conducting state, the fourth switch tube T4 is in the cut-off state; if the third switch tube T3 is in the cut-off state, the fourth switch tube T4 is in the conducting state, so that the first switch tube T1 and the second switch tube T2 cannot output the reset signal RST(n-x) according to the potential of the second connection node B. Since the first clock signal XCK and the second clock signal CK are both low potential signals in the intra-frame scanning mode, the third switch tube T3 and the fourth switch tube T4 can be in the conducting state at the same time, at this time, the first switch tube T1 and the second switch tube T2 can output the corresponding reset signal RST(n-x) according to the potential of the second connection node B, so as to realize the rollback of the state of the target pixel row.

[0060] In an optional embodiment, in the case of the scanning cut-off row of the current level of pixel behavior, the potential of the second connection node B is a high potential, and the rollback module 130 outputs a high potential signal as the reset signal RST(n-x);

[0061] In the case of the non-scanning cut-off row of the current level of pixel behavior, the potential of the second connection node B is a low potential, and the rollback module 130 outputs a low potential signal as the reset signal RST(n-x).

[0062] Specifically, if the current pixel is a scan-off row, the potential of the second connection node B is high, at this time, the second switch tube T2 is in the on state, the first switch tube T1 is in the off state, and the high potential of the second voltage source VGH can be output to the target pixel row through the second switch tube T2 as a reset signal RST(n-x), so that the target pixel row can re-enter the display scanning state and re-write the corresponding data signal.

[0063] If the current pixel is not a scan-off row, the potential of the second connection node B is low, at this time, the first switch tube T1 is in the on state, and the second switch tube T2 is in the off state, and the low potential of the first voltage source VGL can be output to the target pixel row through the first switch tube T1 as a reset signal RST(n-x), so that the target pixel row is covered by the low potential.

[0064] For example, assuming that the scan-off row is the 10th pixel row, and x is 2, for the gate drive unit 100 corresponding to the 10th pixel row, the rollback module 130 outputs a high potential reset signal RST(n-x) to the 8th pixel row, so that the new round of display scanning starts from the 8th pixel row; and for the gate drive unit 100 corresponding to the 12th pixel row, the rollback module 130 outputs a low potential reset signal RST(n-x) to the 10th pixel row, so that the 10th pixel row is covered by the low potential, avoiding the conflict between the original high potential of the 10th pixel row and the high potential of the 8th pixel row.

[0065] In an optional embodiment, please continue to refer to Figure 3 The sampling module 110 includes a fifth switch tube T5, a sixth switch tube T6, a seventh switch tube T7, a first capacitor C1, and a second capacitor C2.

[0066] The drain of the fifth switch tube T5 and the drain of the seventh switch tube T7 are connected to the output end of the previous scan signal Scan(n-1), the gate of the fifth switch tube T5 is connected to the first clock signal XCK, and the source of the fifth switch tube T5 is connected to the first end of the first capacitor C1 and the drain of the sixth switch tube T6.

[0067] The gate of the sixth switch tube T6 is connected to the second clock signal CK, and the source of the sixth switch tube T6 is connected to the first connection node A; the gate of the seventh switch tube T7 is connected to the first clock signal XCK, and the source of the seventh switch tube T7 is connected to the source of the fourth switch tube T4 and the first end of the second capacitor C2 through the second connection node B; the second end of the first capacitor C1 and the second end of the second capacitor C2 are connected to the first voltage source VGL.

[0068] Specifically, in the sampling stage of the display scanning mode, the previous stage scanning signal Scan(n-1) is at high level, the first clock signal XCK is at high level, and the second clock signal CK is at low level. At this time, the fifth switch tube T5 and the seventh switch tube T7 are in the conductive state, and the sixth switch tube T6 is in the cut-off state. The high level of the previous stage scanning signal Scan(n-1) can be written into the first capacitor C1 and the second capacitor C2, so as to pull up the potentials of the first capacitor C1 and the second capacitor C2.

[0069] In the output stage of the display scanning mode, the previous stage scanning signal Scan(n-1) is at low level, the first clock signal XCK is at low level, and the second clock signal CK is at high level. At this time, the sixth switch tube T6 is in the conductive state, and the fifth switch tube T5 and the seventh switch tube T7 are in the cut-off state. The first capacitor C1 and the second capacitor C2 are continuously maintained at high level.

[0070] In the reset stage of the display scanning mode, the previous stage scanning signal Scan(n-1) is at low level, the first clock signal XCK is at high level, and the second clock signal CK is at low level. At this time, the fifth switch tube T5 and the seventh switch tube T7 are in the conductive state, and the sixth switch tube T6 is in the cut-off state. The low level of the previous stage scanning signal Scan(n-1) can be written into the first capacitor C1 and the second capacitor C2, so as to pull down the potentials of the first capacitor C1 and the second capacitor C2.

[0071] In this way, the sampling module 110 can sample the input previous stage scanning signal Scan(n-1), and adjust the potentials of the first capacitor C1 and the second capacitor C2 according to the sampling result, and then adjust the potentials of the first connection node A and the second connection node B.

[0072] In an optional embodiment, please continue to refer to Figure 3 The output module 120 includes a pull-down resistor R1, an eighth switch tube T8, a ninth switch tube T9, and a tenth switch tube T10.

[0073] The first end of the pull-down resistor R1 is connected with the first voltage source VGL, the second end of the pull-down resistor R1 is connected with the first connection node A, the gate of the eighth switch tube T8, and the gate of the ninth switch tube T9 respectively, the drain of the eighth switch tube T8 is connected with the second clock signal CK, and the source of the eighth switch tube T8 and the drain of the tenth switch tube T10 are both used as the output end of the current stage scanning signal Scan(n) and connected with the current stage pixel row.

[0074] The drain of the ninth switch tube T9 is connected with the gate of the tenth switch tube T10, the source of the ninth switch tube T9 is connected with the second voltage source VGH, and the source of the tenth switch tube T10 is connected with the first voltage source VGL.

[0075] Specifically, in the sampling phase of the display scanning mode, the eighth switch transistor T8 and the ninth switch transistor T9 can obtain a low potential from the pull-down resistor R1, at this time, the eighth switch transistor T8 is in the off state, the ninth switch transistor T9 is in the on state, the second voltage source VGH is connected to the gate of the tenth switch transistor T10 through the ninth switch transistor T9, the tenth switch transistor T10 is in the on state, and the first voltage source VGL outputs the low potential of the current stage scanning signal Scan(n) through the tenth switch transistor T10.

[0076] In the output phase of the display scanning mode, the high potential of the first capacitor C1 is output to the gates of the eighth switch transistor T8 and the ninth switch transistor T9, at this time, the eighth switch transistor T8 is in the on state, the ninth switch transistor T9 and the tenth switch transistor T10 are in the off state, and the second clock signal CK outputs the high potential of the current stage scanning signal Scan(n) through the eighth switch transistor T8.

[0077] In the reset phase of the display scanning mode, since the sixth switch transistor T6 is in the off state, the eighth switch transistor T8 and the ninth switch transistor T9 can obtain a low potential from the pull-down resistor R1, at this time, the eighth switch transistor T8 is in the off state, the ninth switch transistor T9 is in the on state, the second voltage source VGH is connected to the gate of the tenth switch transistor T10 through the ninth switch transistor T9, the tenth switch transistor T10 is in the on state, and the first voltage source VGL outputs the low potential of the current stage scanning signal Scan(n) through the tenth switch transistor T10.

[0078] In this way, the output module 120 can determine the potential of the current stage scanning signal Scan(n) according to the potential of the first connection node A in the display scanning mode, so as to control the display state of the current stage pixel row by using the current stage scanning signal Scan(n).

[0079] In an optional embodiment, please continue to refer to Figure 3 In the case that the scanning signal is high potential effective, the first switch transistor T1, the third switch transistor T3, the fourth switch transistor T4 and the ninth switch transistor T9 are P-type field effect transistors, and the second switch transistor T2, the fifth switch transistor T5, the sixth switch transistor T6, the seventh switch transistor T7, the eighth switch transistor T8 and the tenth switch transistor T10 are N-type field effect transistors.

[0080] Specifically, the scanning signal is high potential effective means that the scanning signal is low potential in the normal state and is high potential in the driving display. That is, when the scanning signal is high potential, the pixel row is driven and displayed, and when the scanning signal is low potential, the pixel row is not driven and displayed.

[0081] In Figure 3The gate drive unit 100 shown, the first switch tube T1, the third switch tube T3, the fourth switch tube T4 and the ninth switch tube T9 are P-type field effect tubes, the second switch tube T2, the fifth switch tube T5, the sixth switch tube T6, the seventh switch tube T7, the eighth switch tube T8 and the tenth switch tube T10 are N-type field effect tubes, so that the display state of the pixel row of the level can be controlled in the display scanning mode, and the state of the target pixel row is rolled back in the frame scanning mode, as follows:

[0082] In the sampling stage of the display scanning mode, the previous stage scanning signal Scan(n-1) is high, the first clock signal XCK is high, and the second clock signal CK is low. At this time, the fifth switch tube T5 and the seventh switch tube T7 are in the on state, and the sixth switch tube T6 is in the off state. The high potential of the previous stage scanning signal Scan(n-1) can be written into the first capacitor C1 and the second capacitor C2, and the potential of the first capacitor C1 and the second capacitor C2 is pulled up. The eighth switch tube T8 and the ninth switch tube T9 can obtain low potential from the pull-down resistor R1. At this time, the eighth switch tube T8 is in the off state, and the ninth switch tube T9 is in the on state. The second voltage source VGH is connected to the gate of the tenth switch tube T10 through the ninth switch tube T9, and the tenth switch tube T10 is in the on state. The first voltage source VGL outputs the low potential of the current stage scanning signal Scan(n) through the tenth switch tube T10, as shown in Figure 4 .

[0083] In the output stage of the display scanning mode, the previous stage scanning signal Scan(n-1) is low, the first clock signal XCK is low, and the second clock signal CK is high. At this time, the sixth switch tube T6 is in the on state, and the fifth switch tube T5 and the seventh switch tube T7 are in the off state, so that the first capacitor C1 and the second capacitor C2 are continuously maintained at high potential. The high potential of the first capacitor C1 is output to the gate of the eighth switch tube T8 and the ninth switch tube T9. At this time, the eighth switch tube T8 is in the on state, and the ninth switch tube T9 and the tenth switch tube T10 are in the off state. The second clock signal CK outputs the high potential of the current stage scanning signal Scan(n) through the eighth switch tube T8, as shown in Figure 5 .

[0084] In the reset stage of the display scanning mode, the previous stage scanning signal Scan(n-1) is at low potential, the first clock signal XCK is at high potential, and the second clock signal CK is at low potential. At this time, the fifth switch tube T5 and the seventh switch tube T7 are in the on state, and the sixth switch tube T6 is in the off state. The low potential of the previous stage scanning signal Scan(n-1) can be written into the first capacitor C1 and the second capacitor C2, so as to pull down the potential of the first capacitor C1 and the second capacitor C2. Since the sixth switch tube T6 is in the off state, the eighth switch tube T8 and the ninth switch tube T9 can obtain low potential from the pull-down resistor R1 at this time. At this time, the eighth switch tube T8 is in the off state, the ninth switch tube T9 is in the on state, the second voltage source VGH is connected to the gate of the tenth switch tube T10 through the ninth switch tube T9, the tenth switch tube T10 is in the on state, and the first voltage source VGL outputs the low potential of the current stage scanning signal Scan(n) through the tenth switch tube T10, as shown in Figure 6 .

[0085] In the subsequent period of the display scanning mode, even if the first clock signal XCK becomes low potential and the second clock signal CK becomes high potential, since the first capacitor C1 stores low potential, the eighth switch tube T8 will remain in the off state, the ninth switch tube T9 will remain in the on state, and the tenth switch tube T10 will remain in the on state. The first voltage source VGL continuously outputs the low potential of the current stage scanning signal Scan(n) through the tenth switch tube T10, as shown in Figure 7 .

[0086] In the frame scanning mode, the first clock signal XCK and the second clock signal CK are both pulled down. At this time, the fifth switch tube T5, the sixth switch tube T6, and the seventh switch tube T7 are all in the off state, and the third switch tube T3 and the fourth switch tube T4 are both in the on state. If the current stage pixel is a non-scanning off row (i.e., the current stage pixel row does not belong to the scanning row), the potential stored in the second capacitor C2 is low potential, which will cause the first switch tube T1 to be on and the second switch tube T2 to be off. The first voltage source VGL outputs the low potential of the reset signal RST(n-x) through the first switch tube T1. In this way, the first capacitor C1 corresponding to the pixel row in front of the current stage pixel row by x rows is covered by low potential, and the first capacitor C1 corresponding to the current stage pixel row is covered by the state of the pixel row behind the current stage pixel row by x rows, as shown in Figure 8 .

[0087] If the current pixel row is a scan cutoff row (i.e., the current pixel row belongs to the scan row), the potential stored in the second capacitor C2 is high, which will cause the second switch T2 to turn on and the first switch T1 to turn off. The second voltage source VGH outputs a high-potential reset signal RST(nx) through the second switch T2. In this way, the first capacitor C1 corresponding to the pixel row x rows before the current pixel row is pulled high, while the first capacitor C1 corresponding to the current pixel row will be pulled low by the reset signal RST(nx) of the pixel row x rows after the current pixel row. Figure 9 As shown. In this way, by performing a backscan after the pit stops, the scan cutoff line (let's say line n) can be moved back to several lines before the pit stop line (line nx), and the data signal can be rewritten, overwriting the line containing the potentially mischarged co-drive data signal, ensuring complete charging and resolving the issue of lateral pitting. The backscan effect is as follows: Figure 10 As shown. Here, "padding" refers to the forced interruption of normal data writing due to intra-frame scanning touch sampling. Through the above method, in display scanning mode, the gate driving unit 100 can have the output module 120 determine the potential of the current-level scan signal Scan(n) based on the potential of the first connection node A, thereby controlling the display state of the current-level pixel row using the current-level scan signal Scan(n). Furthermore, in intra-frame scanning mode, the back-off module 130 can output a reset signal RST(nx) based on the potential of the second connection node B, thereby using the reset signal RST(nx) to back-off the state of the target pixel row. This effectively avoids horizontal pits caused by intra-frame scanning, achieving the goal of improving the display effect of the display panel.

[0088] In an optional embodiment, when the scanning signal is active at a low potential, the first switch T1, the third switch T3, the fourth switch T4 and the ninth switch T9 are N-type field-effect transistors, and the second switch T2, the fifth switch T5, the sixth switch T6, the seventh switch T7, the eighth switch T8 and the tenth switch T10 are P-type field-effect transistors.

[0089] Specifically, "scan signal low-level active" means that the scan signal is high under normal conditions but low when driving the display. That is, when the scan signal is low, the display of that pixel row is driven; when the scan signal is high, the display of that pixel row is not driven.

[0090] When the first switch tube T1, the third switch tube T3, the fourth switch tube T4 and the ninth switch tube T9 are N-type field effect tubes, and the second switch tube T2, the fifth switch tube T5, the sixth switch tube T6, the seventh switch tube T7, the eighth switch tube T8 and the tenth switch tube T10 are P-type field effect tubes, in this way, the gate drive unit 100 can also control the display state of the pixel row at the current level in the display scanning mode, and can perform rollback on the state of the target pixel row in the frame scanning mode, and the principle is similar to the previous embodiment, and will not be described here.

[0091] Referring to Figure 11 The embodiment of the present application further provides a gate drive circuit, which comprises: a plurality of the gate drive units 100 in the foregoing embodiment, and the plurality of gate drive units 100 are cascaded in sequence, and each gate drive unit 100 corresponds to a pixel row.

[0092] Referring to Figure 12 The embodiment of the present application further provides a display panel, which comprises an array substrate 210 and the gate drive circuit 200 in the foregoing embodiment, and the gate drive circuit 200 is arranged on the array substrate 210.

[0093] Referring to Figure 13 The embodiment of the present application further provides a display device, which comprises a housing 310 and the display panel 300 in the foregoing embodiment, and the display panel 300 is arranged on the housing 310.

[0094] It should be noted that the display device can be a display screen, or a mobile phone, a computer, a television and a wearable device provided with a display screen, and the like, and the present application is not limited thereto.

[0095] The device embodiments described above are only schematic, and the units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, that is, they can be located in one place, or distributed on multiple network units. According to actual needs, part or all of the modules can be selected to achieve the purpose of the embodiment of the present application.

[0096] Those skilled in the art can clearly understand the implementation of the embodiments by the description of the above embodiments. The embodiments can be implemented by means of software plus a general hardware platform, and of course, can also be implemented by hardware. Based on such understanding, the above technical solutions can be embodied in the form of a software product, and the computer software product can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, and the like, and includes a plurality of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in each embodiment or some parts of the embodiments.

[0097] It is to be understood that the terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises", "comprising", "includes", "including" and "has", "having" are inclusive and therefore specify the presence of stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order in which they are described unless specifically indicated as such. It is also to be understood that additional or alternative steps can be employed.

[0098] The above description is merely that of specific embodiments of the present application, and thus is not intended to limit the present application. From the above description, one skilled in the art can clearly understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the generic principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the application. Accordingly, the present application is not to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A gate drive unit characterized by, The gate driving unit comprises a sampling module, an output module and a rollback module; The sampling module is connected with the output module through a first connection node, and is connected with the rollback module through a second connection node; The sampling module is configured to sample an input previous-stage scanning signal, and determine potentials of the first connection node and the second connection node according to a sampling result; The output module is configured to determine a potential of a current-stage scanning signal according to the potential of the first connection node in a display scanning mode, so as to control a display state of a current-stage pixel row by using the current-stage scanning signal; The rollback module is configured to output a reset signal according to the potential of the second connection node in an intra-frame scanning mode, so as to rollback a state of a target pixel row by using the reset signal, the target pixel row being a pixel row located in front of the current-stage pixel row by a preset number of rows, and the intra-frame scanning mode being a working mode in which multiple touch scanning is performed in a display scanning process of a same frame to obtain a capacitance value generated by touch.

2. The gate drive unit of claim 1, wherein, The rollback module comprises a first switch tube, a second switch tube, a third switch tube and a fourth switch tube; The source of the first switch tube is connected with a first voltage source, the source of the second switch tube is connected with a second voltage source, the drain of the first switch tube and the drain of the second switch tube are both used as an output end of the reset signal and are connected with the sampling module of a gate driving unit corresponding to the target pixel row; The gate of the first switch tube and the gate of the second switch tube are both connected with the drain of the third switch tube, the gate of the third switch tube is connected with a first clock signal, the source of the third switch tube is connected with the drain of the fourth switch tube, the gate of the fourth switch tube is connected with a second clock signal, and the source of the fourth switch tube is connected with the second connection node; In the display scanning mode, the first clock signal and the second clock signal are two clock signals with opposite phases; in the intra-frame scanning mode, the first clock signal and the second clock signal are both low potential signals, and the voltage value of the first voltage source is lower than the voltage value of the second voltage source.

3. The gate drive unit of claim 2, wherein, In the case that the current-stage pixel row is a scanning stop row, the potential of the second connection node is a high potential, and the rollback module outputs a high potential signal as the reset signal; In the case that the current-stage pixel row is a non-scanning stop row, the potential of the second connection node is a low potential, and the rollback module outputs a low potential signal as the reset signal.

4. The gate drive unit of claim 2, wherein, The sampling module comprises a fifth switch tube, a sixth switch tube, a seventh switch tube, a first capacitor and a second capacitor; The drain of the fifth switch tube and the drain of the seventh switch tube are both connected with an output end of a previous-stage scanning signal, the gate of the fifth switch tube is connected with the first clock signal, and the source of the fifth switch tube is connected with a first end of the first capacitor and the drain of the sixth switch tube respectively; A gate of the sixth switch tube is connected with the second clock signal, and a source of the sixth switch tube is connected with the first connection node; a gate of the seventh switch tube is connected with the first clock signal, a source of the seventh switch tube is connected with a source of the fourth switch tube and a first end of the second capacitor through the second connection node, and a second end of the first capacitor and a second end of the second capacitor are both connected with the first voltage source.

5. The gate drive unit of claim 4, wherein, The output module comprises a pull-down resistor, an eighth switch tube, a ninth switch tube and a tenth switch tube. The first end of the pull-down resistor is connected with the first voltage source, the second end of the pull-down resistor is connected with the first connection node, a gate of the eighth switch tube and a gate of the ninth switch tube respectively, a drain of the eighth switch tube is connected with the second clock signal, and a source of the eighth switch tube and a drain of the tenth switch tube are both used as an output end of a scanning signal of the present stage and connected with a pixel row of the present stage. A drain of the ninth switch tube is connected with a gate of the tenth switch tube, a source of the ninth switch tube is connected with the second voltage source, and a source of the tenth switch tube is connected with the first voltage source.

6. The gate drive unit of claim 5, wherein, In the case that the scanning signal is high potential effective, the first switch tube, the third switch tube, the fourth switch tube and the ninth switch tube are P-type field effect tubes, and the second switch tube, the fifth switch tube, the sixth switch tube, the seventh switch tube, the eighth switch tube and the tenth switch tube are N-type field effect tubes.

7. The gate drive unit of claim 5, wherein, In the case that the scanning signal is low potential effective, the first switch tube, the third switch tube, the fourth switch tube and the ninth switch tube are N-type field effect tubes, and the second switch tube, the fifth switch tube, the sixth switch tube, the seventh switch tube, the eighth switch tube and the tenth switch tube are P-type field effect tubes.

8. A gate drive circuit, characterized by comprising: The gate driving circuit comprises: a plurality of gate driving units as claimed in any one of claims 1-7, the plurality of gate driving units are cascaded in sequence, and each of the gate driving units corresponds to a pixel row.

9. A display panel, characterized by, The display panel comprises an array substrate and the gate driving circuit as claimed in claim 8, wherein the gate driving circuit is arranged on the array substrate.

10. A display device, characterized by comprising: The display device comprises a housing and the display panel as claimed in claim 9, wherein the display panel is arranged on the housing.

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