Semiconductor device structure including vertical fuse structure

Abstract

The invention provides a semiconductor element structure and a preparation method thereof. The semiconductor device structure includes a semiconductor substrate, a fuse structure and a circuit region. The semiconductor substrate has a first surface and a second surface opposite to the first surface. The fuse structure is at least partially disposed within the semiconductor substrate. The circuit region is electrically connected to the fuse structure. The fuse structure includes a first fuse element, a second fuse element, and a fuse medium connecting the first fuse element and the second fuse element. The first fuse element, the second fuse element, and the fuse medium are disposed along a first direction from the first surface toward the second surface of the semiconductor substrate.

Description

Technical Field

[0001] This application claims priority to U.S. patent application No. 18 / 619,520 (i.e., the priority date is "March 28, 2024"), the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a semiconductor device structure, and more particularly to a semiconductor device structure having a vertical fuse structure. Background Art

[0003] Fuses and electronic fuses are commonly used in memory devices to convert redundant memory cells into normal memory cells. A test circuit is used to determine the fuse's status (i.e., whether it is blown) to determine whether the corresponding memory cell is a normal memory cell or a redundant memory cell. As technology advances, the size of memory cells in semiconductor device structures will decrease. Since the size of each component in a semiconductor device structure cannot be reduced indefinitely, finding other methods to reduce the size of the semiconductor device structure is crucial.

[0004] The above description of “prior art” only provides background technology, does not admit that the above description of “prior art” reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the Invention

[0005] One embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a semiconductor substrate, a fuse structure, and a circuit area. The semiconductor substrate has a first surface and a second surface opposite the first surface. The fuse structure is at least partially disposed within the semiconductor substrate. The circuit area is electrically connected to the fuse structure. The fuse structure includes a first fuse element, a second fuse element, and a fuse medium connecting the first and second fuse elements. The first fuse element, the second fuse element, and the fuse medium are disposed along a first direction from the first surface of the semiconductor substrate toward the second surface.

[0006] Another embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a semiconductor substrate, a fuse structure, and a circuit region. The semiconductor substrate has a first surface and a second surface opposite the first surface. The fuse structure extends through the semiconductor substrate from the first surface to the second surface. The circuit region is electrically connected to the fuse structure.

[0007] Another embodiment of the present disclosure provides a method for fabricating a semiconductor device structure. The method includes providing a semiconductor substrate having a first surface and a second surface opposite the first surface; forming a fuse structure within the semiconductor substrate; and forming a circuit region within the semiconductor substrate, wherein the circuit region is electrically connected to the fuse structure.

[0008] The semiconductor device structure includes a vertical fuse structure that penetrates the semiconductor substrate. The process for producing the fuse structure can be integrated with the process for defining wiring paths (e.g., vias and metal layers) above the semiconductor substrate. This improves the device's power consumption without additional cost.

[0009] The above has outlined the technical features and advantages of the present disclosure in a fairly broad manner, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those skilled in the art to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used quite easily to modify or design other structures or processes to achieve the same purposes as those of the present disclosure. It should also be understood by those skilled in the art to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] A more complete understanding of the present disclosure can be obtained by referring to the detailed description and claims.The present disclosure should also be understood to be associated with the reference numerals of the drawings, which represent similar elements throughout the description.

[0011] Figure 1A is a schematic cross-sectional view illustrating the semiconductor device structure according to some embodiments of the present disclosure.

[0012] Figure 1B It is an enlarged schematic diagram illustrating some embodiments of the present disclosure. Figure 1A The semiconductor device structure shown.

[0013] Figure 2 is a schematic cross-sectional view illustrating the semiconductor device structure according to some embodiments of the present disclosure.

[0014] Figure 3 is a schematic cross-sectional view illustrating the semiconductor device structure according to some embodiments of the present disclosure.

[0015] Figure 4 is a schematic cross-sectional view illustrating the semiconductor device structure according to some embodiments of the present disclosure.

[0016] Figure 5 is a schematic cross-sectional view illustrating the semiconductor device structure according to some embodiments of the present disclosure.

[0017] Figure 6A is a schematic cross-sectional view illustrating the semiconductor device structure according to some embodiments of the present disclosure.

[0018] Figure 6B It is an enlarged schematic diagram illustrating some embodiments of the present disclosure. Figure 6A The semiconductor device structure shown.

[0019] Figure 7 is a schematic cross-sectional view illustrating the semiconductor device structure according to some embodiments of the present disclosure.

[0020] Figure 8A is a schematic cross-sectional view illustrating one or more stages of an exemplary method for fabricating a semiconductor device structure according to some embodiments of the present disclosure.

[0021] Figure 8B is a schematic cross-sectional view illustrating one or more stages of an exemplary method for fabricating a semiconductor device structure according to some embodiments of the present disclosure.

[0022] Figure 8C is a schematic cross-sectional view illustrating one or more stages of an exemplary method for fabricating a semiconductor device structure according to some embodiments of the present disclosure.

[0023] Figure 8D is a schematic cross-sectional view illustrating one or more stages of an exemplary method for fabricating a semiconductor device structure according to some embodiments of the present disclosure.

[0024] Figure 8E is a schematic cross-sectional view illustrating one or more stages of an exemplary method for fabricating a semiconductor device structure according to some embodiments of the present disclosure.

[0025] Figure 8F is a schematic cross-sectional view illustrating one or more stages of an exemplary method for fabricating a semiconductor device structure according to some embodiments of the present disclosure.

[0026] Figure 8G is a schematic cross-sectional view illustrating one or more stages of an exemplary method for fabricating a semiconductor device structure according to some embodiments of the present disclosure.

[0027] Figure 8H is a schematic cross-sectional view illustrating one or more stages of an exemplary method for fabricating a semiconductor device structure according to some embodiments of the present disclosure.

[0028] Figure 8I is a schematic cross-sectional view illustrating one or more stages of an exemplary method for fabricating a semiconductor device structure according to some embodiments of the present disclosure.

[0029] Figure 9A is a schematic cross-sectional view illustrating one or more stages of an exemplary method for fabricating a semiconductor device structure according to some embodiments of the present disclosure.

[0030] Figure 9B is a schematic cross-sectional view illustrating one or more stages of an exemplary method for fabricating a semiconductor device structure according to some embodiments of the present disclosure.

[0031] Figure 9C is a schematic cross-sectional view illustrating one or more stages of an exemplary method for fabricating a semiconductor device structure according to some embodiments of the present disclosure.

[0032] Figure 10 FIG2 is a structural diagram illustrating a system for testing semiconductor device structures according to some embodiments of the present disclosure.

[0033] Figure 11 Schematic diagram illustrating the semiconductor device structure of some embodiments of the present disclosure.

[0034] Figure 12 Schematic diagram illustrating the semiconductor device structure of some embodiments of the present disclosure.

[0035] Figure 13 Schematic diagram illustrating the semiconductor device structure of some embodiments of the present disclosure.

[0036] Figure 14 is an equivalent circuit diagram illustrating some embodiments of the present disclosure. Figure 13 An equivalent circuit of a portion of a semiconductor element is shown.

[0037] Figure 15 1 is a flow chart illustrating a method for preparing a semiconductor device structure according to some embodiments of the present disclosure.

[0038] The description of the accompanying drawings is as follows:

[0039] 1a: Semiconductor device structure

[0040] 1b: Semiconductor device structure

[0041] 1c: Semiconductor device structure

[0042] 1d: Semiconductor device structure

[0043] 1e: Semiconductor device structure

[0044] 1f: Semiconductor device structure

[0045] 1g: Semiconductor device structure

[0046] 3: Circuit

[0047] 4: Equivalent circuit

[0048] 10: Electronic components

[0049] 10': Electronic components

[0050] 10's1: Surface

[0051] 10's2: Surface

[0052] 11: Base

[0053] 11s1: Surface

[0054] 11s2: Surface

[0055] 12: Circuit area

[0056] 13: Fuse structure

[0057] 13': Fuse structure

[0058] 13”: Fuse structure

[0059] 14: Buffer layer

[0060] 14s1: Surface

[0061] 14s2: Surface

[0062] 14s3: Surface

[0063] 15: Dielectric structure

[0064] 18: Conductive pad

[0065] 20: Circuit board

[0066] 30: Electrical connector

[0067] 31: Electrical connector

[0068] 32: Electrical connector

[0069] 40: Electronic components

[0070] 50: Circuit board

[0071] 60: Dielectric layer

[0072] 61: Groove

[0073] 62: Dielectric layer

[0074] 63: Opening

[0075] 70: System

[0076] 71: Component

[0077] 72: Signal Generator

[0078] 73: Monitor

[0079] 74: Coupler

[0080] 75: Probe

[0081] 131: Fuse element

[0082] 131': Fuse element

[0083] 131s1: Surface

[0084] 131's1: Surface

[0085] 131s2: Surface

[0086] 131's2: Surface

[0087] 131s3: Surface

[0088] 132: Fuse medium

[0089] 132': Fuse medium

[0090] 133: Fuse element

[0091] 133': Fuse element

[0092] 133s1: Surface

[0093] 133s2: Surface

[0094] 133s3: Surface

[0095] 141: Part

[0096] 142: Part

[0097] 143: Part

[0098] 161a: Conductive via

[0099] 161b: Conductive via

[0100] 161c: Conductive vias

[0101] 161d: Conductive via

[0102] 162: Conductive vias

[0103] 171: Conductive layer

[0104] 172: Conductive layer

[0105] 173: Conductive layer

[0106] 500: Preparation method

[0107] 502: Steps

[0108] 504: Steps

[0109] 506: Steps

[0110] 508: Steps

[0111] 510: Steps

[0112] 512: Steps

[0113] 701: Fuse

[0114] 705: Reference resistor unit

[0115] 705-1: Terminal

[0116] 705-2: Terminal

[0117] 710: Evaluation Unit

[0118] 711A: Conductive Path

[0119] 711B: Conductive Path

[0120] 720: Status setting unit

[0121] 722: Conductive terminal

[0122] 730: Latch circuit

[0123] 731: Inverter

[0124] 732: Inverter

[0125] H1: Plane

[0126] H2: Planes

[0127] IN_1: input terminal

[0128] IN_2: Input terminal

[0129] L1: Size

[0130] L2: Dimensions

[0131] L3: Dimensions

[0132] OUT_1: output terminal

[0133] OUT_2: output terminal

[0134] RF: Resistor

[0135] RR: Resistor

[0136] TA: Switching Circuit

[0137] TB: Switching circuit

[0138] TC: Switching Circuit

[0139] TD: Switching Circuit

[0140] TE: Switching Circuit

[0141] VB: Status setting signal

[0142] VDD: Power supply terminal (power signal)

[0143] VE: conductive terminal

[0144] VSS: Ground terminal

[0145] W: Node

[0146] W1: Dimensions

[0147] W2: Dimensions

[0148] W3: Dimensions

[0149] X: Direction

[0150] Y: direction

[0151] X1: Signal

[0152] Y1: signal DETAILED DESCRIPTION

[0153] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, the description of a first component formed on a second component may include embodiments in which the first and second components are in direct contact, and may also include embodiments in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is for simplicity and clarity, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or configurations discussed.

[0154] It will be understood that when an element is referred to as being “connected to” or “coupled to” another element, the initial element can be directly connected or coupled to the other element or other intervening elements may be present.

[0155] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the progressive concept of the present disclosure, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0156] The terminology used herein is for the purpose of describing specific embodiments only and is not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, these terms specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0157] It should be understood that the use of the term "about" in the description of the present disclosure refers to variations in the amounts of ingredients, compositions, or reactants of the present disclosure, such as variations in amounts that may occur due to typical measurements and liquid handling procedures used to prepare concentrates or solutions. Furthermore, variations may result from inadvertent errors in measurement procedures, differences in the manufacture, source, or purity of ingredients used to make compositions or implement methods, and the like. In one aspect, the term "about" refers to within 10% of the reported value. In another aspect, the term "about" refers to within 5% of the reported value. Furthermore, in another aspect, the term "about" refers to within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

[0158] Figure 1A is a schematic cross-sectional view illustrating a semiconductor device structure 1 a according to some embodiments of the present disclosure.

[0159] Figure 1A FIG2 is a schematic cross-sectional view illustrating a semiconductor device structure 1a according to some embodiments of the present disclosure. In some embodiments, the semiconductor device structure 1a may include an electronic device 10. The electronic device 10 may include a semiconductor die or a wafer. The electronic device 10 may include a substrate 11, a circuit region 12, a fuse structure 13, and a buffer layer 14.

[0160] Substrate 11 may include a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. Substrate 11 may include an elemental semiconductor including silicon or germanium in single crystal, polycrystalline, or amorphous form; a compound semiconductor material including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor material including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or a combination thereof. In some embodiments, the alloy semiconductor substrate may include a SiGe alloy having gradient Ge features, wherein the Si and Ge compositions change from one ratio at one location to another ratio depending on the location of the feature. In another embodiment, the SiGe alloy is formed on a silicon substrate. In some embodiments, the SiGe alloy may be mechanically strained by another material in contact with the SiGe alloy. In some embodiments, substrate 11 may have a multilayer structure. It should be understood that some doped regions, isolation structures, and / or other components may be formed within the semiconductor carrier. The substrate 11 may have a surface 11 s 1 (or a lower surface) and a surface 11 s 2 (or an upper surface) opposite to the surface 11 s 1 .

[0161] Circuit area 12 may include one or more integrated circuits. Circuit area 12 may be formed within substrate 11. In some embodiments, circuit area 12 may be electrically connected to fuse structure 13. Circuit area 12 may be configured to control the short circuit and / or open circuit state of fuse structure 13. In addition, circuit area 12 may include circuits for an application processor (AP), a central processing unit (CPU), a graphics processing unit (GPU), dynamic random access memory (DRAM), static random access memory (SRAM), power management, or other purposes.

[0162] In some embodiments, the fuse structure 13 may be at least partially disposed within the substrate 11. The fuse structure 13 may include a fuse or an antifuse. The fuse structure 13 may include a first terminal and a second terminal to which different voltages (or powers) are applied. The first terminal and the second terminal may be connected via a fuse dielectric (or a fuse link). Applying a programming current to the fuse structure 13 destroys the fuse dielectric, thereby changing the resistivity of the fuse structure 13. A sensing circuit may be used to read the fuse state (i.e., whether it has been programmed). The fuse structure 13 may include a fuse element 131 (or a first terminal), a fuse dielectric 132 (or a fuse link), and a fuse element 133 (or a second terminal). In some embodiments, each of the fuse element 131, the fuse dielectric 132, and the fuse element 133 may include copper, tungsten, ruthenium, iridium, nickel, osmium, rhodium, aluminum, molybdenum, cobalt, tantalum, alloys thereof, polysilicon, or combinations thereof.

[0163] Please refer to Figure 1B , which illustrates an enlarged view of the semiconductor device structure shown in 1A. In some embodiments, the fuse element 131 can be disposed within the substrate 11. The fuse element 131 can be electrically connected to a power supply having a relatively low voltage. The fuse element 131 can have a surface 131s1 (or a lower surface) and a surface 131s2 (or an upper surface) opposite to the surface 131s1. In some embodiments, the surface 131s1 of the fuse element 131 can be substantially aligned with the surface 11s1 of the substrate 11. In some embodiments, the surface 131s1 of the fuse element 131 can be exposed through the substrate 11.

[0164] The fuse medium 132 may be disposed on or above the fuse element 131. In some embodiments, the fuse medium 132 may be disposed within the substrate 11. The fuse medium 132 may be disposed between the fuse elements 131 and 133 along the Y direction.

[0165] In some embodiments, the fuse element 133 may be disposed within the substrate 11. The fuse element 133 may be disposed on or above the fuse medium 132. In some embodiments, the fuse element 131, the fuse medium 132, and the fuse element 133 may be disposed along the Y direction. The fuse element 133 may be electrically connected to a power supply having a relatively high voltage. The fuse element 133 may have a surface 133s1 (or a lower surface) connected to the fuse medium 132 and a surface 133s2 (or an upper surface) opposite to the surface 133s1. In some embodiments, the surface 133s2 of the fuse element 133 may be substantially aligned with the surface 11s2 of the substrate 11. In some embodiments, the surface 133s2 of the fuse element 133 may be exposed through the substrate 11.

[0166] The fuse element 131 may have a dimension (e.g., width) W1 along the X direction. The fuse medium 132 may have a dimension (e.g., width) W2 along the X direction. The fuse element 133 may have a dimension (e.g., width) W3 along the X direction. In some embodiments, dimension W1 may be substantially equal to dimension W3. In some embodiments, dimension W1 may be greater than dimension W2. The fuse element 131 may have a dimension (e.g., length) L1 along the Y direction. The fuse element 133 may have a dimension (e.g., length) L2 along the Y direction. In some embodiments, dimension L1 may be substantially equal to dimension L2.

[0167] In some embodiments, a buffer layer 14 may be embedded within the substrate 11. The buffer layer 14 may be disposed between the substrate 11 and the fuse structure 13. The fuse structure 13 may be separated from the substrate 11 by the buffer layer 14. The buffer layer 14 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or combinations thereof. The buffer layer 14 may include a portion 141 adjacent to the fuse element 131, a portion 142 adjacent to the fuse medium 132, and a portion 143 adjacent to the fuse element 133. Portions 141, 142, and 143 may define a T-shaped profile in a cross-sectional view. The buffer layer 14 may have a surface 14s1 (or a lower surface) and a surface 14s2 (or an upper surface) opposite to the surface 14s1. In some embodiments, the surface 14s1 of the buffer layer 14 may be substantially aligned with the surface 131s1 of the fuse element 131. In some embodiments, the surface 14s1 of the buffer layer 14 may be substantially aligned with the surface 11s1 of the substrate 11. In some embodiments, a surface 14s2 of the buffer layer 14 can be substantially aligned with a surface 133s2 of the fuse element 131. In some embodiments, a surface 14s2 of the buffer layer 14 can be substantially aligned with a surface 11s2 of the substrate 11.

[0168] Please refer back Figure 1A , the electronic component 10 may include a dielectric structure 15. The dielectric structure 15 may be disposed on or above the surface 11s2 of the substrate 11. The dielectric structure 15 may include a silicon oxide-based material, such as tetraethyl orthosilicate (TEOS) oxide, plasma-enhanced CVD (PECVD) oxide (SiO2), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or other suitable materials. The dielectric structure 15 may also be referred to as an interlayer dielectric. The dielectric structure 15 may include a multilayer structure.

[0169] Electronic component 10 may include conductive vias 161a, 161b, and 162 and conductive layers 171 and 172 within dielectric structure 15. Each of conductive vias 161a, 161b, and 162 and conductive layers 171 and 172 may include copper, tungsten, ruthenium, iridium, nickel, osmium, rhodium, aluminum, molybdenum, cobalt, tantalum, alloys thereof, and combinations thereof.

[0170] The conductive via 161 a may be disposed between the circuit region 12 and the conductive layer 171 and electrically connect the circuit region 12 and the conductive layer 171 .

[0171] The conductive via 161b may be disposed between the fuse structure 13 and the conductive layer 171 and electrically connect the fuse structure 13 and the conductive layer 171. The conductive via 161b may be located at a plane that is substantially the same as the conductive via 161a.

[0172] Conductive layer 171 may be disposed on or over conductive vias 161 a and 161 b .

[0173] The conductive via 162 may be disposed between the conductive layer 171 and the conductive layer 172 and electrically connect the conductive layer 171 and the conductive layer 172 .

[0174] Conductive layer 172 may be disposed on or above conductive vias 162. It should be understood that electronic component 10 may include other conductive traces and / or vias for routing. For example, electronic component 10 may include conductive traces and / or vias above conductive layer 172 that may connect to pads adjacent to the upper surface of dielectric structure 15.

[0175] The semiconductor device structure 1a includes a vertical fuse structure (eg, fuse structure 13) penetrating the substrate 11. The fuse structure 13 can be fabricated at a higher density without requiring additional volume, which can enhance the performance of the semiconductor device structure 1a.

[0176] Figure 2 is a cross-sectional view illustrating a semiconductor device structure 1b according to some embodiments of the present disclosure. The semiconductor device structure 1b can be Figure 1A The semiconductor device structure 1a shown is similar, and the differences between the two are described below.

[0177] In some embodiments, fuse element 131 may have a dimension (eg, length) L3 along the Y direction. In some embodiments, dimension L3 of fuse element 131 may be different from dimension L2 of fuse element 133. In some embodiments, dimension L3 of fuse element 131 may be smaller than dimension L2 of fuse element 133.

[0178] Figure 3 is a cross-sectional view illustrating a semiconductor device structure 1c according to some embodiments of the present disclosure. The semiconductor device structure 1c can be Figure 1A The semiconductor device structure 1a shown is similar, and the differences between the two are described below.

[0179] The buffer layer 14 may have a surface 14s3 (or a side surface) extending between the surfaces 14s1 and 14s2. In some embodiments, the surface 14s3 may be tilted relative to the surface 11s1. The fuse element 131 may have a surface 131s3 (or a side surface) extending between the surfaces 131s1 and 131s2. In some embodiments, the surface 131s3 may be tilted relative to the surface 11s1. The fuse element 133 may have a surface 133s3 (or a side surface) extending between the surfaces 133s1 and 133s2. In some embodiments, the surface 133s3 may be tilted relative to the surface 11s2.

[0180] In some embodiments, the fuse element 131 may gradually taper toward the surface 11s1 of the substrate 11. In some embodiments, the fuse element 133 may gradually taper toward the surface 11s1 of the substrate 11. In some embodiments, the dimension (e.g., width) of the surface 131s2 of the fuse element 131 along the X direction may be greater than the dimension (e.g., width) of the surface 131s1 of the fuse element 131 along the X direction. In some embodiments, the dimension (e.g., width) of the surface 133s2 of the fuse element 133 along the X direction may be greater than the dimension (e.g., width) of the surface 133s1 of the fuse element 133 along the X direction may be greater than the dimension (e.g., width) of the surface 131s2 of the fuse element 131 along the X direction.

[0181] Figure 4 is a cross-sectional view illustrating a semiconductor device structure 1d according to some embodiments of the present disclosure. The semiconductor device structure 1d can be Figure 1A The semiconductor device structure 1a shown is similar, and the differences between the two are described below.

[0182] In some embodiments, the fuse element 131 may taper toward the surface 11s2 of the substrate 11, and the fuse element 133 may taper toward the surface 11s1 of the substrate 11. In some embodiments, the dimension (e.g., width) of the surface 131s2 of the fuse element 131 may be smaller than the dimension of the surface 131s1 of the fuse element 131 along the X-direction. In some embodiments, the portion 141 may taper toward the surface 11s1 of the substrate 11. In some embodiments, the portion 143 may taper toward the surface 11s2 of the substrate 11.

[0183] Figure 5 is a cross-sectional view illustrating a semiconductor device structure 1e according to some embodiments of the present disclosure. The semiconductor device structure 1e can be Figure 1A The semiconductor device structure 1a shown is similar, and the differences between the two are described below.

[0184] In some embodiments, the semiconductor device structure 1 e may include a circuit board 20 and an electrical connector 30 .

[0185] The circuit board 20 can be disposed on or below the surface 11s1 of the substrate 11. In some embodiments, the circuit board 20 can be configured to apply a relatively low voltage to the fuse element 131. The circuit board 20 can include a printed circuit board (PCB) comprising a plurality of metal layers separated from each other by multiple layers of dielectric material and interconnected by conductive vias. In some embodiments, the fuse element 131 can be electrically connected to ground via the circuit board 20.

[0186] The electrical connector 30 may be disposed between the circuit board 20 and the fuse element 131 and electrically connect the circuit board 20 and the fuse element 131. The electrical connector 30 may include a solder ball, a conductive bump, or the like. The electrical connector 30 may include an alloy of gold and tin solder, an alloy of silver and tin solder, or other suitable materials.

[0187] Figure 6A and Figure 6B The semiconductor device structure 1f according to some embodiments of the present disclosure is illustrated. The semiconductor device structure 1f can be Figure 1A The semiconductor device structure 1a is similar to the semiconductor device structure 1a shown in FIG. 1 , and the differences between the two are described below. In some embodiments, the semiconductor device structure 1f may include a fuse structure 13 ′ and a conductive pad 18 .

[0188] In some embodiments, the fuse structure 13' may include a fuse element 131', a fuse medium 132', and a fuse element 133'. In some embodiments, the fuse element 131' may completely penetrate the substrate 11. The fuse element 131' may have a surface 131's1 and a surface 131's2 opposite to the surface 131's1. In some embodiments, the surface 131's1 of the fuse element 131' may be substantially aligned with the surface 11s1 of the substrate 11. In some embodiments, the surface 131's1 of the fuse element 131' may be exposed through the surface 11s1 of the substrate 11. In some embodiments, the surface 131's2 of the fuse element 131' may be substantially aligned with the surface 11s2 of the substrate 11. In some embodiments, the surface 131's2 of the fuse element 131' may be exposed through the surface 11s2 of the substrate 11.

[0189] The fuse dielectric 132' may be disposed on or above the fuse element 131'. The fuse dielectric 132' may be embedded within the dielectric structure 15. In some embodiments, the fuse dielectric 132' may be disposed on or above the surface 11s2 of the substrate 11. In some embodiments, the fuse dielectric 132' may be located at a plane (or height) H1 that is substantially the same as a plane of the conductive via 161a.

[0190] In some embodiments, fuse element 133' can be disposed on or above fuse dielectric 132'. In some embodiments, fuse element 133' can be embedded within dielectric structure 15. In some embodiments, fuse dielectric 132' can be located at a plane (or height) H2 that is substantially the same as the plane of conductive layer 171. In some embodiments, fuse dielectric 132' and conductive layer 171 can be connected and define a monolithic structure, with no or indistinct boundary between them.

[0191] The semiconductor device structure 1f may include a conductive via 161c, a conductive via 161d, and a conductive layer 173. The conductive via 161c may be disposed between the fuse element 131′ and the conductive layer 173 and electrically connect the fuse element 131′ and the conductive layer 173. The conductive via 161d may be disposed between the conductive pad 18 and the conductive layer 173 and electrically connect the conductive pad 18 and the conductive layer 173.

[0192] Conductive pads 18 may be disposed within substrate 11. In some embodiments, conductive pads 18 may be electrically connected to fuse structure 13'. In some embodiments, conductive pads 18 may be configured to apply a relatively low voltage to fuse element 131'. In some embodiments, conductive pads 18 may be electrically connected to ground. Although not shown, it should be understood that semiconductor device structure 1f may include other conductive traces or vias electrically connecting conductive pads 18 to external power supply components.

[0193] In other embodiments, the conductive pad 18 and the conductive through hole 161c may be omitted. Figure 5 The circuit board 20 and the electrical connector 30 shown may be disposed below the fuse element 131 ′, thereby applying a relatively low voltage to the fuse element 131 ′.

[0194] In this embodiment, a portion of the fuse structure 13' can be located within the dielectric structure 15. Furthermore, the process for forming the fuse medium 132' and the fuse element 133' can be integrated with the process for forming the conductive via 161a and the conductive layer 171. Therefore, power consumption can be reduced without any additional cost.

[0195] Figure 7 is a cross-sectional view illustrating a semiconductor device structure 1g according to some embodiments of the present disclosure. The semiconductor device structure 1g can be Figure 1A The semiconductor device structure 1a shown is similar, and the differences between the two are described below.

[0196] In some embodiments, the semiconductor device structure 1g may include an electronic device 10', an electronic device 40, and a circuit board 50. The electronic device 10' may include a substrate 11 and a fuse structure 13". In some embodiments, the fuse structure 13" may include: Figures 1A to 6A The fuse structure 13 or fuse structure 13' is shown. The electronic component 10' may have a surface 10's1 and a surface 10's2 opposite to the surface 10's1. The surface 11s1 of the substrate 11 may be defined as the surface 10's1 of the electronic component 10'.

[0197] The electronic component 40 may be disposed on or below the surface 10 ′s1 of the electronic component 10 ′. The electronic component 40 may include a semiconductor die or chip, such as a logic die (e.g., an application processor (AP), a system-on-chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), a microcontroller, etc.), a memory chip (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), or other active components. The electronic component 40 may be electrically connected to the electronic component 10 ′ via an electrical connector 31 .

[0198] The circuit board 50 can be disposed on or above the surface 10's2 of the electronic component 10'. The circuit board 50 can include a PCB or other suitable interposer. The circuit board 50 can serve as a power supply configured to provide higher and / or lower voltages to the electronic component 10'. The circuit board 50 can be electrically connected to the electronic component 10' via the electrical connector 32.

[0199] Figures 8A to 8I is a schematic cross-sectional view illustrating one or more stages of an exemplary method for fabricating a semiconductor device structure according to some embodiments of the present disclosure.

[0200] Please refer to Figure 8A , a substrate 11 may be provided. A dielectric layer 60 may be formed within the substrate 11 and exposed through the surface 11s2 of the substrate 11. In some embodiments, an opening may be formed by performing an etching technique on the surface 11s2 of the substrate 11. Next, a dielectric material is deposited and filled into the opening to form the dielectric layer 60. The dielectric layer 60 may include silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials. The dielectric material may be deposited by atomic layer deposition (ALD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), physical vapor deposition (PVD), or other suitable processes.

[0201] Please refer to Figure 8B , a portion of the dielectric layer 60 may be removed. A trench 61 may be formed. The trench 61 may be recessed from the surface 11s2 of the substrate 11. The bottom of the dielectric layer 60 may remain and be exposed.

[0202] Please refer to Figure 8C, the fuse element 131 can be formed in the trench 61. The manufacturing technology of the fuse element 131 can include PVD, CVD, ALD or other appropriate processes. In some embodiments, a conductive material is deposited to cover the surface 11s2 and fill the trench 61. Next, an etching technique can be performed to pattern the conductive material, thereby defining the fuse element 131. However, this disclosure is not intended to be limiting.

[0203] Please refer to Figure 8D A dielectric layer 62 may be formed in the trench 61. The dielectric layer 62 may cover the fuse element 131. The dielectric layer 62 may be formed and / or patterned by one or more etching techniques and deposition techniques. The dielectric layer 62 may include silicon oxide, silicon nitride, silicon oxynitride, or other suitable materials.

[0204] Please refer to Figure 8E A portion of dielectric layer 62 may be removed to expose a portion of the upper surface of fuse element 131. Dielectric layer 60 and dielectric layer 62 may together define buffer layer 14. Dielectric layer 62 may define an opening 63, and opening 63 defines the location and pattern of a fuse medium.

[0205] Please refer to Figure 8F , a fuse medium 132 can be formed in the opening 63. A fuse element 133 can be formed to fill the trench 61. The fuse structure 13 can be fabricated. The fuse medium 132 and the fuse element 133 can be formed and / or patterned by one or more etching techniques and deposition techniques.

[0206] Please refer to Figure 8G , the circuit region 12 may be formed to be adjacent to the surface 11s2 of the substrate 11. Figures 8A to 8G The fuse structure 13 is illustrated as being formed before the circuit region 12 , but it should be understood that the stages for producing each detailed element of the circuit region 12 and the stages for producing the fuse structure 13 may be performed in a suitable manner.

[0207] Please refer to Figure 8H Conductive vias 161a and 161b may be formed over surface 11s2 of substrate 11. Conductive layer 171 may be formed over conductive vias 161a and 161b. Conductive via 162 may be formed over conductive layer 171. Conductive layer 172 may be formed over conductive via 162. Dielectric structure 15 may be formed over surface 11s2 of substrate 11.

[0208] Please refer to Figure 8I , the surface 11s1 of the substrate 11 may be removed by polishing or grinding techniques. The buffer layer 14 and the fuse element 131 may be exposed through the surface 11s1 of the substrate 11. As a result, a semiconductor element structure (e.g., Figure 1AThe semiconductor device structure 1a is shown.

[0209] Figures 9A to 9C is a schematic cross-sectional view illustrating one or more stages of an exemplary method for manufacturing a semiconductor device structure according to some embodiments of the present disclosure. FIG8A to FIG8B The stages shown are the same or similar. Figure 9A depiction Figure 8B The stage following the one depicted.

[0210] Please refer to Figure 9A , the fuse element 131' may be formed within the buffer layer 14. The circuit region 12 may be formed to be adjacent to the surface 11s2 of the substrate 11.

[0211] Please refer to Figure 9B , a conductive pad 18 may be formed. Conductive vias 161a, 161c, and 161d and a fuse medium 132' may be formed. A conductive layer 171 and a conductive layer 173, which may serve as a fuse element 133', may be formed to cover the conductive vias 161a, 161c, and 161d and the fuse medium 132'. Conductive via 162 may be formed over conductive layer 171. Conductive layer 172 may be formed over conductive via 162. A dielectric structure 15 may be formed over surface 11s2 of substrate 11. Fuse element 131', fuse medium 132', and fuse element 133' may collectively define or represent a fuse structure 13'.

[0212] Please refer to Figure 9C , the surface 11s1 of the substrate 11 may be removed by polishing or grinding techniques. The buffer layer 14 and the fuse element 131' may be exposed through the surface 11s1 of the substrate 11. As a result, a semiconductor element structure (e.g., Figure 6A The semiconductor device structure 1f is shown.

[0213] Figure 10 FIG. 1 is a schematic diagram illustrating a system 70 for testing semiconductor device structures according to some embodiments of the present disclosure. Semiconductor device structures 1 a to 1 g can be used to operate the system 70 .

[0214] according to Figure 10 , system 70 is configured to monitor a component 71. In some embodiments, system 70 is configured to test component 71. Component 71 may include a memory, a memory element, a memory die, or a memory wafer. In some embodiments, component 71 may include one or more memory cells. Component 71 may be tested after manufacturing and then shipped.

[0215] In some embodiments, system 70 may constitute a test device. System 70 may include hardware and software components that provide a suitable operating and functional environment for testing. In some embodiments, system 70 may include a signal generator 72, a monitor 73, and a coupler 74.

[0216] The signal generator 72 is configured to generate a test signal. In some embodiments, the signal generator 72 can provide a power signal. It should be understood that other electronic signals, such as data signals and power signals, can also be provided to the component 71.

[0217] Monitor 73 is configured to determine a state of element 71. Monitor 73 may be configured to determine a state of a component of element 71. The response signal may be identified by monitor 73 to determine whether a component (eg, a memory cell) of element 71 is a normal component or a redundant component.

[0218] The coupler 74 is configured to couple the signal generator 72 to the element 71. In some embodiments, the coupler 74 can be coupled to the element 71 via one or more probes 75. The probes 75 can be part of a probe head or a probe package (not shown). The probes 75 can be electrically coupled to a plurality of test conductive terminals (pads) and / or bonding pads provided on the element 71. The test conductive pads and / or bonding pads provide electrical connections to the interconnect structures (e.g., wiring) of the element 71. For example, some probes can be coupled to pads associated with power terminals (e.g., VDD) and ground terminals (e.g., VSS) of the element 71. Other probes can be coupled to pads associated with input / output (I / O) terminals (e.g., data signals) of the element 71. In this way, the system 70 is operable to apply electronic signals to the element 71 and obtain response signals from the element 71 during testing.

[0219] Figure 11 FIG3 is a schematic diagram of a circuit 3 according to some embodiments of the present disclosure. The circuit 3 may include a semiconductor device, a memory, a memory element, a memory die, a memory chip, or other components including a fuse structure.

[0220] The circuit 3 may include a fuse 701, an evaluation unit 710, and a state setting unit 720. In some embodiments, Figures 1A to 7 The fuse structures 13, 13', and 13" shown may be applicable to the fuse 701. In some embodiments, the evaluation unit 710 may include a reference resistor unit 705, a plurality of switch circuits TD and TE, and a latch circuit 730. In some embodiments, the fuse 701 and the switch circuits TA and TB may serve as part of the evaluation unit 710. In some embodiments, the state setting unit 720 may include the fuse 701, a conductive terminal 722, and two switch circuits TB and TC.

[0221] Please refer to Figure 11 Reference resistor unit 705 has a terminal 705-1 configured to receive a power supply signal VDD. Reference resistor unit 705 has a terminal 705-2 configured to be electrically coupled to fuse 701. In some embodiments, switch circuit TB can be electrically connected to fuse 701. Switch circuit TD can be electrically connected to reference resistor unit 705. In some embodiments, switch circuit TD can be electrically connected to switch circuit TB. In some embodiments, fuse 701 can be grounded via switch circuits TB and TC. Switch circuit TA is electrically connected to fuse 701. Switch circuit TA can be electrically connected to ground.

[0222] In some embodiments, latch circuit 730 is electrically coupled to reference resistor unit 705. Latch circuit 730 can be electrically coupled to fuse 701 via switch circuits TB, TD, and TE. In some embodiments, switch circuit TE is electrically connected to reference resistor unit 705. Switch circuit TE can be electrically connected to latch circuit 730. In some embodiments, switch circuit TE can be electrically connected to switch circuit TD. An evaluation / output signal can be obtained at a conductive terminal VE of latch circuit 730.

[0223] Please refer to Figure 11 Conductive terminal 722 can be electrically connected to fuse 701. Conductive terminal 722 can be a test pad, a probe pad, a conductive pad, a conductive terminal, or other suitable element. In some embodiments, conductive terminal 722 is configured to receive a state setting signal VB. In some embodiments, switch circuit TB can be electrically connected to fuse 701. Switch circuit TC can be electrically connected to switch circuit TB. Switch circuit TB can be electrically connected between switch circuit TC and fuse 701. Switch circuit TC can be electrically connected to ground.

[0224] In some embodiments, each of the switching circuits TA, TB, TC, TD, and TE may be a switch, a transistor, or other switchable circuit.

[0225] Figure 12Circuit 3 according to some embodiments of the present disclosure is illustrated. In some embodiments, switch circuits TB and TC are configured to conduct in response to a state setting signal VB to establish a conductive path 711A. In some embodiments, conductive path 711A can pass through fuse 701 to ground in response to state setting signal VB. In some embodiments, when state setting signal VB is applied to conductive terminal 722, conductive path 711A sequentially passes through fuse 701, switch circuits TB and TC, and then to ground. Alternatively, switch circuits TA, TD, and TE can be configured to be off, allowing conductive path 711A to pass through fuse 701.

[0226] In some embodiments, the state setting signal VB can be a voltage signal or a current signal. In some embodiments, the state setting signal VB can be a voltage signal having a voltage exceeding the normal operating voltage of the circuit 3. In some embodiments, the state setting signal VB can have a voltage in the range of 4-6V. When the state setting signal VB is applied, the state of the fuse 701 can be changed. For example, the state setting signal VB can be used to blow a fuse dielectric of the fuse 701. After the fuse dielectric of the fuse 701 is blown, the physical properties of the fuse dielectric of the fuse 701, such as the resistivity, density, or other properties, change. Before the state setting operation, the fuse 701 can have a relatively high (or low) resistance value. After the state setting operation, the fuse 701 can have a relatively low (or high) resistance value. In this disclosure, the fuse element before the state setting operation can be referred to as an "unblown" fuse element, and the fuse element after the state setting operation can be referred to as a "blown" fuse element.

[0227] In some embodiments, the blown fuse 701 has a resistance value that is higher than the resistance value of the unblown fuse 701. In other embodiments, the fuse 701 may be an antifuse, and the blown fuse 701 has a resistance value that is lower than the resistance value of the unblown fuse 701.

[0228] For example, when fuse 701 functions as an antifuse, the resistance of unblown fuse 701 may be in the range of 1.5M to 20MΩ. After the state setting operation, the resistance of blown fuse 701 may be approximately 2k to 800kΩ. In some embodiments, the resistance of blown fuse 701 may be approximately 100k to 800kΩ.

[0229] Figure 133 is a schematic diagram of a circuit 3 according to some embodiments of the present disclosure. In some embodiments, the switch circuits TA, TB, and TD are configured to be turned on to establish a conductive path 711B. In some embodiments, the conductive path 711B can pass through the reference resistor unit 705 and the fuse 701 in response to the power supply signal VDD and be connected to ground. In some embodiments, the switch circuit TC is configured to be turned off to establish the conductive path 711B. In some embodiments, when the power supply signal VDD is applied to the reference resistor unit 705, the conductive path 711B is connected to the fuse 701. Figure 11 At terminal 705-1, conductive path 711B sequentially passes through reference resistor unit 705, switch circuits TD and TB, fuse 701, and switch circuit TA, ultimately connecting to ground. In some embodiments, power signal VDD may be a normal operating voltage. In some embodiments, the power provided by power signal VDD may be less than the power provided by state setting signal VB. For example, power signal VDD may have a voltage of approximately 1.2V.

[0230] In some embodiments, in response to the power supply signal VDD, a signal X1 is generated at a node W between the reference resistor unit 705 and the fuse 701. Figure 13 , the signal X1 generated at the node W may be transmitted to the latch circuit 730 through the switch circuits TD and TE.

[0231] In some embodiments, latch circuit 730 is configured to read signal X1 generated at node W between reference resistor unit 705 and fuse 701. Node W is located between reference resistor unit 705 and fuse 701, with or without other components coupled therebetween. For example, node W may be located between switch circuits TB and TD. In one embodiment, node W may be located between switch circuit TD and reference resistor unit 705. In another embodiment, node W may be located between switch circuit TB and fuse 701. In some embodiments, signal X1 may include a voltage signal or a current signal.

[0232] In some embodiments, switch circuit TE is configured to conduct to transmit signal X1 to latch circuit 730. During an evaluation period, when switch circuits TA, TB, TD, and TE are configured to conduct to establish conductive path 711B, signal X1 can be obtained at node W and transmitted to latch circuit 730. In some embodiments, latch circuit 730 can read signal X1. In some embodiments, latch circuit 730 can convert signal X1 into a signal Y1. For example, the conversion of signal X1 by latch circuit 730 can include converting or inverting one signal into another signal. In one embodiment, the conversion of signal X1 by latch circuit 730 can include phase shifting. In another embodiment, the conversion of signal X1 by latch circuit 730 can include amplification.

[0233] In some embodiments, the latch circuit 730 can convert the analog signal X1 into a logic signal Y1. The latch circuit 730 can compare the signal X1 with a critical value and output the signal Y1 based on the comparison result between the signal X1 and the critical value. For example, when the signal X1 exceeds the critical value, the latch circuit 730 can output a logic low signal Y1. Conversely, when the signal X1 is below the critical value, the latch circuit 730 can output a logic high signal Y1. For example, when the signal X1 is a logic "0", the signal Y1 will be a logic "1". Conversely, when the signal X1 is a logic "1", the signal Y1 will be a logic "0". In some embodiments, the latch circuit 730 can store the signal Y1.

[0234] Please refer to Figure 13 , the latch circuit 730 may include two inverters 731 and 732. In some embodiments, the latch circuit 730 may include more than two inverters. In some embodiments, the latch circuit 730 may be another type of latch circuit. The inverter 731 has an input terminal IN_1 and an output terminal OUT_1. The inverter 732 has an input terminal IN_2 and an output terminal OUT_2. In some embodiments, the input terminal IN_1 of the inverter 731 may be coupled to the reference resistor unit 705 via the switch circuit TE. The input terminal IN_1 of the inverter 731 may be coupled to the fuse 701 via the switch circuits TB, TD, and TE. The output terminal OUT_1 of the inverter 731 may be coupled to the conductive terminal VE. In some embodiments, the input terminal IN_1 of the inverter 731 may be connected to the output terminal OUT_2 of the inverter 732. The output terminal OUT_1 of the inverter 731 may be connected to the input terminal IN_2 of the inverter 732. That is, the input terminal IN_2 of the inverter 732 may be coupled to the conductive terminal VE. The output terminal OUT_2 of the inverter 732 may be coupled to the reference resistor unit 705. The output terminal OUT_2 of the inverter 732 may be coupled to the fuse 701.

[0235] To assess the state of fuse 701 (i.e., whether fuse 701 is blown), signal X1 (or signal Y1) is monitored. Signal X1 depends on the resistance of fuse 701. Signal X1 is compared with a predetermined signal or a threshold value. Based on the comparison between signal X1 and the predetermined signal, a logic signal Y1 can be output at conductive terminal VE. When signal X1 exceeds the predetermined signal, it indicates that fuse 701 is not blown. When signal X1 fails to exceed the predetermined signal, it indicates that fuse 701 is blown.

[0236] In some embodiments, if the signal X1 exceeds a predetermined level, the latch circuit 730 may output a logic low signal Y1. In other words, the logic low signal Y1 indicates that the fuse 701 is not blown. When the signal X1 is lower than a predetermined level, the latch circuit 730 may output a logic high signal Y1. In other words, the logic high signal Y1 indicates that the fuse 701 is blown.

[0237] A signal Y1 can be obtained at the conductive terminal VE so as to determine the state of the fuse 701. The state of the fuse 701 can be used to determine whether the semiconductor device structure is a redundant device or a normal device.

[0238] Figure 14 An equivalent circuit 4 is shown, illustrating a portion of circuit 3 when conductive path 711B is established, according to an embodiment of the present disclosure. When switch circuits TA, TB, and TD are on, equivalent circuit 4 is configured with switch circuits TA, TB, and TD, and when switch circuit TC is off, equivalent circuit 4 is configured with switch circuit TC. In other words, equivalent circuit 4 represents a simplified circuit through which conductive path 711B passes.

[0239] The equivalent circuit 4 includes two resistors RR and RF. In some embodiments, the resistor RR can be the resistance value of the reference resistor unit 705. The resistor RF can be the resistance value of the fuse 701. In some embodiments, the resistor RR can be connected in series with the resistor RF. The node W is located between the resistor RR and the resistor RF. That is, Figure 14 The node W in corresponds to Figure 13 In some embodiments, resistor RR is configured to receive a power supply signal VDD. For example, power supply signal VDD may be a voltage of 1.2 V. In some embodiments, resistor RF is connected to resistor RR and ground.

[0240] Please refer to Figure 14 , the signal X1 may be a voltage signal obtained at the node W. Therefore, the signal X1 may be calculated according to Equation 1.

[0241]

[0242] In Equation 1, X represents the voltage of the signal X1; RR represents the resistance value of the reference resistor unit 705; RF represents the resistance value of the fuse 701; and VDD represents a power supply signal.

[0243] In order to accurately assess the state of fuse 701, resistance value RR can be reduced to below resistance value RF of an unblown fuse element. Alternatively, resistance value RR can exceed resistance value RF of a blown fuse element. In some embodiments, resistance value RR can be between resistance values ​​of an unblown fuse element and a blown fuse element. In some embodiments, resistance value RR can be between resistance values ​​of an unblown fuse element and a blown fuse element.

[0244] In some embodiments, the voltage of the predetermined signal is less than the voltage of the power supply signal VDD. In some embodiments, the predetermined signal has a voltage multiplied by the power supply signal VDD. For example, if the voltage of the predetermined signal is half of the power supply signal VDD, e.g., 1.2V, the voltage of the predetermined signal may be 0.6V. That is, when the result of Equation 1 exceeds 0.6V, the signal X1 at node W is determined to be a logic high voltage, indicating that the fuse 701 is not blown, and when it is less than 0.6V, the signal X1 at node W is determined to be a logic low voltage, indicating that the fuse 701 is blown.

[0245] Figure 15 1 is a flow chart illustrating a method 500 for fabricating a semiconductor device structure according to some embodiments of the present disclosure.

[0246] The fabrication method 500 begins at step 502, where a semiconductor substrate is provided. A buffer layer may be formed within the semiconductor substrate and exposed through the upper surface of the semiconductor substrate.

[0247] The fabrication method 500 continues with step 504 , where a trench formation technique includes removing a portion of the buffer layer.

[0248] The fabrication method 500 continues with step 506 , where a fuse structure is formed in the trench. The fuse structure may include a first fuse element, a fuse dielectric, and a second fuse element arranged along a direction from the lower surface to the upper surface of the semiconductor substrate.

[0249] The method 500 continues with step 508 , where a circuit region is formed adjacent to the upper surface of the semiconductor substrate.

[0250] The fabrication method 500 proceeds to step 510 , where a plurality of conductive vias and a plurality of conductive layers are formed to electrically connect the circuit region and the fuse structure.

[0251] The fabrication method 500 continues with step 512 , where the semiconductor substrate is polished to expose the first fuse element of the fuse structure.

[0252] Preparation method 500 is merely an example and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional steps may be provided before, during, or after each step of preparation method 500, and some of the steps described may be replaced, eliminated, or reordered for additional embodiments of the preparation method. In some embodiments, preparation method 500 may include Figure 15 In some embodiments, the preparation method 500 may include: Figure 15 One or more steps are depicted.

[0253] One embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a semiconductor substrate, a fuse structure, and a circuit area. The semiconductor substrate has a first surface and a second surface opposite the first surface. The fuse structure is at least partially disposed within the semiconductor substrate. The circuit area is electrically connected to the fuse structure. The fuse structure includes a first fuse element, a second fuse element, and a fuse medium connecting the first and second fuse elements. The first fuse element, the second fuse element, and the fuse medium are disposed along a first direction from the first surface of the semiconductor substrate toward the second surface.

[0254] Another embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a semiconductor substrate, a fuse structure, and a circuit region. The semiconductor substrate has a first surface and a second surface opposite the first surface. The fuse structure extends through the semiconductor substrate from the first surface to the second surface. The circuit region is electrically connected to the fuse structure.

[0255] Another embodiment of the present disclosure provides a method for fabricating a semiconductor device structure. The method includes providing a semiconductor substrate having a first surface and a second surface opposite the first surface; forming a fuse structure within the semiconductor substrate; and forming a circuit region within the semiconductor substrate, wherein the circuit region is electrically connected to the fuse structure.

[0256] The semiconductor device structure includes a vertical fuse structure that penetrates the semiconductor substrate. The process for producing the fuse structure can be integrated with the process for defining wiring paths (e.g., vias and metal layers) above the semiconductor substrate. This improves the device's power consumption without additional cost.

[0257] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations may be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above may be implemented in different ways, and other processes or combinations thereof may be substituted for many of the processes described above.

[0258] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machines, manufacture, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future developed processes, machines, manufacture, compositions of matter, means, methods, or steps that function the same as or achieve substantially the same results as the corresponding embodiments described herein may be used in accordance with this disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps are intended to be encompassed by the claims of this application.

Claims

1. A semiconductor device structure comprising: A semiconductor substrate having a first surface and a second surface opposite to the first surface; a fuse structure, at least partially disposed within the semiconductor substrate; as well as a circuit region electrically connected to the fuse structure, The fuse structure includes a first fuse element, a second fuse element, and a fuse medium connecting the first fuse element and the second fuse element, wherein the first fuse element, the second fuse element, and the fuse medium are arranged along a first direction from the first surface of the semiconductor substrate toward the second surface. 2 . The semiconductor device structure as claimed in claim 1 , wherein the first fuse element has a first surface exposed through the first surface of the semiconductor substrate. 3 . The semiconductor device structure as claimed in claim 2 , wherein the first fuse element has a second surface opposite to the first surface of the first fuse element and exposed through the second surface of the semiconductor substrate. 4 . The semiconductor device structure as claimed in claim 2 , wherein the second fuse element is disposed in the semiconductor substrate. 5 . The semiconductor device structure as claimed in claim 4 , wherein the second fuse element has a surface exposed through the second surface of the semiconductor substrate. The semiconductor device structure as claimed in claim 1 , wherein the fuse dielectric is embedded in the semiconductor substrate. 7 . The semiconductor device structure as claimed in claim 1 , wherein the first fuse element has a first width along a second direction substantially perpendicular to the first direction, and the fuse dielectric has a second width along the second direction that is smaller than the first width.

8. The semiconductor device structure according to claim 1 , further comprising: a conductive via disposed above the second surface of the semiconductor substrate; as well as a conductive layer disposed above the conductive through hole, The circuit area is electrically connected to the fuse structure via the conductive via and the conductive layer. 9 . The semiconductor device structure as claimed in claim 8 , wherein the fuse dielectric is located at a plane, wherein the plane of the fuse dielectric is substantially the same as a plane of the conductive via. 10 . The semiconductor device structure as claimed in claim 8 , wherein the second fuse element is located at a plane, wherein the plane at which the second fuse element is located is substantially the same as a plane of the conductive layer. 11 . The semiconductor device structure as claimed in claim 10 , wherein the second fuse element and the conductive layer are continuous. 12 . The semiconductor device structure as claimed in claim 1 , wherein the first fuse element tapers toward the first surface of the semiconductor substrate. 13 . The semiconductor device structure as claimed in claim 1 , wherein the first fuse element tapers toward the second surface of the semiconductor substrate. 14 . The semiconductor device structure as claimed in claim 1 , wherein the second fuse element tapers toward the first surface of the semiconductor substrate.

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