Optimal efficiency driven power factor correction converter

Abstract

The invention relates to an optimal efficiency driven power factor correction converter. Apparatuses, systems, and methods are provided for power factor correction (PFC) converters, including PFC converters that are driven at optimal efficiency. An exemplary PFC converter may include an input circuit device to receive an input voltage, an output circuit device to provide an output voltage, a boost circuit device coupled to the input circuit device and the output circuit device, and a switch. The boost circuit arrangement includes a capacitor. The switch is configured to operate in an on-state and an off-state, and operating in the on-state causes the capacitor to charge and operating in the off-state causes the capacitor to discharge. The PFC converter controller controls the switch to change state at a first ratio associated with one or more time periods for the on state and one or more time periods for the off state, and the first ratio is also associated with a first efficiency threshold associated with the on state.

Description

Technical Field

[0001] Example embodiments of the present disclosure relate generally to power factor correction (PFC) converters, and more particularly to PFC converters driven at optimal efficiency. Background Art

[0002] The power factor of an AC power system is the ratio of the actual power absorbed by the load to the apparent power flowing in the circuit. Various applications use power factor correction (PFC) to adjust the power factor and / or total harmonic distortion (THD) in the signal driving a load (e.g., a motor). A PFC converter can convert an alternating current (AC) input voltage and generate a direct current (DC) output voltage that drives one or more loads (e.g., a motor). PFC can be used with steady-state loads as well as loads that vary with time, which can be referred to as variable loads. For example, a fan can run at a constant speed and / or can change speed, and the motor driving the fan can be a load that can remain constant or vary with time.

[0003] The inventors have identified many areas of improvement in the prior art and technology that are the subject of the embodiments described herein. Through applied effort, ingenuity, and innovation, many of these deficiencies, challenges, and problems have been addressed by developing solutions embodied in the embodiments of the present disclosure, some examples of which are described in detail herein. Summary of the Invention

[0004] Various embodiments described herein relate to apparatus, systems, and methods for a PFC converter, and in particular, for driving a PFC converter at optimal efficiency.

[0005] According to some embodiments of the present disclosure, an example power factor correction converter is provided. The example power factor correction converter includes: an input circuit device for receiving at least an input voltage; an output circuit device for providing an output voltage; a boost circuit device electrically coupled to the input circuit device and the output circuit device, wherein the boost circuit device includes at least one capacitor; at least one switch, wherein the at least one switch is in the input circuit device or the boost circuit device, wherein the at least one switch is configured to operate in at least two states, the at least two states including an on state and an off state, wherein operating in the on state causes the boost circuit device to charge the at least one capacitor, and wherein operating in the off state causes the at least one capacitor to discharge; and a power factor correction converter controller configured to control the at least one switch to change state between the on state and the off state at a first ratio, wherein the first ratio is associated with one or more time periods for the on state and one or more time periods for the off state, and is further associated with a first efficiency threshold, the first efficiency threshold being associated with the on state.

[0006] In some embodiments, the first efficiency threshold is associated with best power factor efficiency.

[0007] In some embodiments, the input voltage comprises a single-phase voltage input.

[0008] In some embodiments, the input voltage comprises a three-phase voltage input.

[0009] In some embodiments, the power factor correction converter controller is further configured to determine the first ratio based on a current load associated with the power factor correction converter.

[0010] In some embodiments, the power factor correction converter controller is further configured to determine the first ratio based on the predicted load.

[0011] In some embodiments, the power factor correction converter controller is further configured to determine the first ratio based on a load curve.

[0012] According to some embodiments of the present disclosure, an example system is provided. An example system includes: a power supply; a load; a power factor correction converter, the power factor correction converter including: an input circuit device coupled to the power supply and configured to receive an input voltage from the power supply; an output circuit device coupled to the load and configured to provide an output voltage to the load; a boost circuit device electrically coupled to the input circuit device and the output circuit device, wherein the boost circuit device includes at least one capacitor; at least one switch, wherein the at least one switch is in the input circuit device or the boost circuit device; wherein the at least one switch is configured to operate in at least two states, the at least two states including an on state and an off state, wherein operating in the on state causes the boost circuit device to charge the at least one capacitor, and wherein operating in the off state causes the at least one capacitor to discharge; and a power factor correction converter controller, the power factor correction converter controller configured to control the at least one switch to change state between the on state and the off state at a first ratio, wherein the first ratio is associated with one or more time periods for the on state and one or more time periods for the off state, and is further associated with a first efficiency threshold, the first efficiency threshold being associated with the on state.

[0013] In some embodiments, the first efficiency threshold is associated with best power factor efficiency.

[0014] In some embodiments, the voltage input comprises a single-phase input voltage.

[0015] In some embodiments, the voltage input comprises a three-phase input voltage.

[0016] In some embodiments, the power factor correction converter controller is further configured to determine the first ratio based on a current load associated with the power factor correction converter.

[0017] In some embodiments, the power factor correction converter controller is further configured to determine the first ratio based on the predicted load.

[0018] In some embodiments, the power factor correction converter controller is further configured to determine the first ratio based on a load curve.

[0019] According to some embodiments of the present disclosure, an example method is provided. The example method includes providing a power factor correction converter, the power factor correction converter including an input circuit device, an output circuit device, a boost circuit device, at least one switch, and a power factor correction converter controller, wherein the input circuit device is coupled to a power source, wherein the output circuit device is coupled to a load, wherein the boost circuit device is coupled to the input circuit device and the output circuit device, and wherein the boost circuit device includes at least one capacitor, wherein the at least one switch is in the input circuit device or the boost circuit device; and operating the at least one switch to change state between an on-state and an off-state based on a first ratio, wherein operating in the on-state causes the boost circuit device to charge the at least one capacitor, and wherein operating in the off-state causes the at least one capacitor to discharge, and wherein the first ratio is associated with one or more time periods for the on-state and one or more time periods for the off-state, and is further associated with a first efficiency threshold, the first efficiency threshold being associated with the on-state.

[0020] In some embodiments, the first efficiency threshold is associated with best power factor efficiency.

[0021] In some embodiments, the voltage input comprises a single-phase input voltage.

[0022] In some embodiments, the voltage input comprises a three-phase input voltage.

[0023] In some embodiments, the method further includes determining, with the power factor correction converter controller, the first ratio based on a current load associated with the power factor correction converter.

[0024] In some embodiments, the method further includes determining, with the power factor correction converter controller, the first ratio based on the load curve.

[0025] The above summary of the invention is provided only for the purpose of summarizing some example embodiments to provide a basic understanding of some aspects of the present disclosure. Therefore, it will be understood that the above embodiments are merely examples and should not be interpreted as narrowing the scope or spirit of the present disclosure in any way. It will also be understood that in addition to the embodiments outlined herein, the scope of the present disclosure also includes many possible embodiments, some of which will be further described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Having thus described certain example embodiments of the present disclosure in general terms, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and in which:

[0027] Figure 1 illustrates an exemplary PFC converter configured for a single-phase input voltage according to one or more embodiments of the present disclosure;

[0028] Figure 2 illustrates an example graph of efficiency versus AC power according to one or more embodiments of the present disclosure;

[0029] Figure 3 illustrates a flow chart for the operation of a PFC converter according to one or more embodiments of the present disclosure;

[0030] Figure 4A and Figure 4B illustrates an exemplary diagram of a PFC converter configured for a single-phase input voltage according to one or more embodiments of the present disclosure;

[0031] Figure 5A and Figure 5B illustrates an exemplary PFC converter configured for a three-phase input voltage according to one or more embodiments of the present disclosure;

[0032] Figure 6A and Figure 6B illustrates an exemplary diagram of a PFC converter configured for a three-phase input voltage according to one or more embodiments of the present disclosure;

[0033] Figure 7A and Figure 7B illustrates an exemplary graph for a PFC converter according to one or more embodiments of the present disclosure;

[0034] Figure 8A and Figure 8B illustrates an exemplary graph for a PFC converter according to one or more embodiments of the present disclosure;

[0035] Figure 9 An exemplary device according to one or more embodiments of the present disclosure is illustrated.

[0036] Figure 10 illustrates an exemplary PFC converter configured with a dual-channel PFC topology according to one or more embodiments of the present disclosure;

[0037] Figure 11 illustrates an example graph associated with a PFC converter configured with a dual-channel topology and at least two modes according to one or more embodiments of the present disclosure;

[0038] Figure 12 illustrates an exemplary graph associated with a PFC converter configured with a dual-channel topology according to one or more embodiments of the present disclosure;

[0039] Figure 13illustrates an exemplary graph of current associated with a PFC converter configured with a dual-channel topology operating in a first mode according to one or more embodiments of the present disclosure;

[0040] Figure 14A 、 Figure 14B and Figure 14C illustrates an exemplary graph of current associated with a PFC converter configured with a dual-channel topology operating in a second mode according to one or more embodiments of the present disclosure;

[0041] Figure 15 Illustrated is an exemplary graph of current associated with a PFC converter configured with a dual-channel topology operating in a balanced mode, according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0042] Some embodiments of the present disclosure will now be described more fully herein with reference to the accompanying drawings, in which some, but not all, embodiments of the present disclosure are shown. Indeed, the various embodiments of the present disclosure may be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Like reference numerals refer to like elements throughout.

[0043] As used herein, the term "comprising" means including, but not limited to, and should be interpreted in the manner in which it is commonly used in a patent context. The use of broader terms such as include and comprises should be understood to provide support for narrower terms such as consisting of, consisting essentially of, and consisting essentially of.

[0044] Phrases such as "in various embodiments," "in one embodiment," "according to one embodiment," "in some embodiments," etc. generally mean that the particular feature, structure, or characteristic following the phrase may be included in at least one embodiment of the present disclosure, and may be included in more than one embodiment of the present disclosure (importantly, such phrases do not necessarily refer to the same embodiment).

[0045] The word “example” or “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other implementations.

[0046] If a specification states that a component or feature "may," "could," "might," "should," "will," "preferably," "likely," "typically," "optionally," "for example," "often," or "might" (or other such language) be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic. Such a component or feature may optionally be included in some embodiments, or it may be excluded.

[0047] The use of the term "circuitry" as used herein with respect to a component of a system or device should be understood to include specific hardware configured to perform the functions associated with the specific circuitry described herein. The term "circuitry" should be broadly interpreted to include hardware and, in some embodiments, software for configuring the hardware. For example, in some embodiments, "circuitry" may include processing circuitry, communication circuitry, input / output circuitry, etc. In some embodiments, other elements may provide or supplement the functionality of a specific circuitry.

[0048] Overview

[0049] Various embodiments of the present disclosure are directed to improved PFC converters.

[0050] Power factor correction attempts to improve the real power used by a circuit and / or load. Power factor is the ratio of real power to apparent power. Real power is the power used by a circuit and / or load. Apparent power is the power delivered to the circuit and / or load.

[0051] Conventional power factor correction converters are efficient within a narrow range or band and inefficient outside of that range or band. For example, a conventional PFC converter may be efficient at high loads and inefficient at low and / or medium loads. However, PFC converters can be used in applications that power one or more loads with variable power, including loads for which conventional PFC converters are inefficient. Operating in such a low efficiency range can cause the PFC converter to have multiple negative issues, including low efficiency, heat generation, noise generation, etc. This can also include total harmonic distortion (THD) in the output current or PFC converter circuitry, which can be associated with other negative issues.

[0052] The present disclosure includes a number of improvements, including providing a PFC converter that can operate at low loads, medium loads, and high loads with, among other things, improved efficiency, improved THD, improved power factor, improved thermal performance (e.g., less heat generation), and / or improved noise generation (e.g., less noise). Furthermore, the present disclosure can utilize certain components of conventional PFC converters, thereby keeping costs low and allowing improvements to the PFC converter without increasing the size and cost of the device to accommodate additional electrical components.

[0053] Power factor correction for variable load applications can be provided to a PFC converter, which generates an output voltage of a DC voltage from an input voltage. The input voltage can be, for example, an AC single-phase voltage or an AC three-phase voltage. By generating an output voltage, the PFC converter can be used to control one or more loads (e.g., motors), including variable loads. Such variable load applications may include, but are not limited to, providing power to variable speed loads (e.g., variable speed motors) and adding or removing loads with one or more loads. Such applications may include air conditioning systems, household appliances, battery chargers, power supplies for residential, commercial, and / or industrial applications, and the like.

[0054] The present disclosure generally relates to improved PFC converters. The disclosure includes, among other things, an improved PFC converter controller for operating a PFC converter, including a PFC converter having an input voltage of a single-phase AC input voltage and / or a three-phase AC input voltage. The disclosure also provides, among other things, for efficiently operating the PFC converter to provide DC power at both low and medium loads with the same or similar efficiency as at high loads.

[0055] Various embodiments of the PFC converter disclosed herein use one or more operations to charge and / or discharge one or more capacitors in the PFC converter so that the DC power output provided can consistently power the load while efficiently operating the PFC converter. Using one or more switches, the PFC converter can efficiently operate to charge these one or more capacitors. Then, under low and / or medium loads, the one or more switches can be operated to disconnect the capacitors from the input voltage, allowing the capacitors to provide DC power output. The closing or connecting operation and the closing or disconnecting operation can be referred to as discontinuous operation because power is not continuously provided. In contrast, in high-load applications, the PFC converter can keep the one or more switches closed and operate continuously at a high efficiency level or point. The PFC converter controller can be operated to cycle the one or more switches to, among other things, operate the PFC converter at or nearly at the same efficiency level and / or point as when power is continuously provided in high-load applications. Such operation provides the additional improvements described herein.

[0056] The PFC converter can be configured for continuous mode to provide power at maximum load or in high-load applications. The PFC converter can operate at high efficiency when under high load. Beyond high load, at low or medium loads, efficiency may decrease. The PFC converter can therefore be configured with a high efficiency point, which can be used as a threshold, which can be referred to as a first efficiency threshold. In various embodiments, this first efficiency threshold can be within the range of the high efficiency point (e.g., + / - 10% of the power from the high efficiency point).

[0057] To operate the PFC converter under loads associated with a first efficiency threshold, the PFC converter controller may operate the PFC converter in one or more modes. For example, when operating at or above the first efficiency threshold, the PFC converter may operate in a continuous mode, in which the PFC converter controller provides a continuously closed signal to one or more switches to provide continuous conversion of the AC input voltage to the DC output voltage. When operating below the first efficiency threshold, the PFC converter may operate in a low-power mode, in which the PFC converter controller performs discontinuous operation, in which discontinuous conversion of the AC input voltage to the DC output voltage occurs. This discontinuous conversion may be caused by operating one or more switches to connect and disconnect the AC input voltage from the DC output voltage for one or more time periods. With discontinuous operation, the PFC converter controller may allow the AC input voltage to charge one or more capacitors and then disconnect the AC input voltage to discharge the one or more capacitors and provide power to one or more loads. When the PFC converter controller operates the switches in a closed state, the PFC converter may operate at or near the first efficiency threshold, and then, when the switches are opened, the PFC converter does not convert the AC input voltage to a DC voltage. Thus, discontinuous operation of the low power mode may allow the PFC converter to operate efficiently while providing power to light and / or medium loads.

[0058] In a lower power mode, the period of time that the PFC converter closes the switch to the on-state compared to the period of time that the switch is open in the off-state can be expressed as a ratio. This can be referred to as the on-off ratio or the on-off duty cycle. While the switch is in the on-state, the PFC converter can be said to be on because the AC voltage is being converted to a DC voltage, and while the switch is open, the PFC converter can be said to be in the off-state because the AC voltage is not being converted to a DC voltage. However, in this off-state, it will be understood that the PFC converter can still provide power to the load by discharging one or more capacitors.

[0059] In various embodiments, the time periods during which the PFC converter is in the on state and the time periods during which the PFC converter is in the off state are each a multiple of one cycle of the AC input voltage waveform. This can provide improved THD by avoiding switching or stopping and / or starting the medium-wave input voltage during alternating cycles that could generate harmonics. The PFC converter controller can determine the timing for turning the PFC converter on and / or off by monitoring the applied load and / or the charging and / or discharging of one or more capacitors and by determining a prediction of the load in a future time period.

[0060] Exemplary Apparatus, Systems, and Methods

[0061] Figure 1 An exemplary PFC converter configured for a single-phase input voltage according to one or more embodiments of the present disclosure is illustrated. The PFC converter 100 may include an input circuitry 102 , an output circuitry 104 , a boost circuitry 106 , and a PFC converter controller 110 .

[0062] The input circuit arrangement 102 can be configured to receive an input signal of a single-phase voltage, which can be at a first input terminal 102A and a second input terminal 102B. In various embodiments, the input circuit arrangement can include a plurality of diodes 120 (e.g., 120A, 120B, 120C, 120D), which can be associated with rectification of the single-phase input.

[0063] Input circuitry 102 may be coupled to boost circuitry 106, which may be used to generate a DC voltage output signal to be provided via output circuitry 104. The output signal may be a DC voltage signal that may be provided to one or more loads, such as via first output terminal 104A and second output terminal 104B. In various embodiments, input circuitry 102 and / or output circuitry 104 may include additional circuitry and / or electrical components, such as filters, switches, capacitors, and the like.

[0064] The boost circuit arrangement 106 may include one or more inductors 140, one or more diodes 150, one or more switches 160, and one or more capacitors 170. In various embodiments, the one or more capacitors 170 may be referred to as bulk capacitors. The boost circuit arrangement may operate based on one or more signals from the PFC converter controller 110. For example, the switch 160 may be opened and / or closed based on a switching signal 118 generated and provided by the PFC converter controller 110. The switching signal 118 may be a pulse-width modulated (PWM) signal. Alternatively, it may be a binary signal that may indicate whether the switch is open and / or closed.

[0065] Boost circuitry 106 may provide one or more signals to PFC converter controller 110 that, among other things, may serve as a basis for generating switching signal 118. For example, AC voltage signal 112, AC current signal 116, and / or DC voltage signal 114 may be provided to PFC converter controller 110. AC voltage signal 112 may be derived from boost circuitry 106 at a point between first resistor 132A and second resistor 132B coupled to the output of input circuitry 102. DC voltage signal 114 may be derived from boost circuitry 106 at a point between first resistor 134A and second resistor 134B coupled to the output of boost circuitry 106.

[0066] In various embodiments, the PFC converter controller 110 can receive and / or transmit one or more load signals 180 from an external source. For example, the one or more load signals 180 can be received and / or transmitted to a load controller. The one or more load signals can be associated with load information for generating an output signal and providing the output signal at terminals 104A, 104B.

[0067] Figure 2 An example graph of efficiency versus AC power according to one or more embodiments of the present disclosure is illustrated. Example efficiency graph 200 illustrates efficiency for various AC powers. Various embodiments associated with curve 210 of graph 200 can be configured to deliver up to 2000 W of AC power. The maximum efficiency for the PFC converter can be at a highest efficiency point 220, which can represent a first efficiency threshold.

[0068] For graph 200 , low or medium loads may be associated with lower AC powers where efficiency begins to drop off sharply, such as below 1000 W. For various embodiments associated with graph 200 , loads providing power above 1000 W may be operated in continuous mode, while loads requiring power below 1000 W may be operated in low power mode.

[0069] In various embodiments, the PFC converter is operated to maintain operation at or near a first efficiency threshold. When operating in a second mode with a low-power mode of discontinuous operation, the PFC converter operates in the on-state at this highest efficiency point 220 and then switches to the off-state. In this manner, when the PFC converter 100 is in the on-state, it operates efficiently. When the PFC converter 100 is in the on-state but the power load is below the first efficiency threshold, the PFC converter 100 can charge the capacitor 170 to store energy that may be discharged to the load(s) when the PFC converter is switched to the off-state. The PFC converter 100 can then remain in the off-state for several cycles of the AC waveform while the power stored in the capacitor 170 is discharged to the load(s). In the off-state, the one or more diodes 150 prevent current from the discharging capacitor from flowing through the one or more diodes 150 and / or being provided to the rectified AC voltage.

[0070] When the PFC converter operates at the highest efficiency point 220 or within an associated range, the PFC converter operates at a higher power than required by one or more loads. During such operation, excess energy is stored in one or more capacitors 170. This can increase the voltage of the one or more capacitors 170. In various embodiments, excess energy can be stored in the one or more capacitors until a high capacitor voltage threshold is reached. When at the high capacitor voltage threshold, the PFC converter 100 can be switched to an off state by switching one or more switches 160 (e.g., from closed to open). The PFC converter controller 110 can then maintain the one or more switches 160 open for one or more time periods to discharge the one or more capacitors 170 and thereby allow the load to consume the energy stored in the one or more capacitors 170. The PFC converter controller 110 can maintain the one or more switches 160 in an open state until a lower capacitor voltage threshold is reached, at which point the PFC converter controller 110 can operate the one or more switches 160 closed.

[0071] Figure 3 A flow chart illustrating the operation of a PFC converter according to one or more embodiments of the present disclosure is shown. Regardless of the input voltage that the PFC converter is configured to receive, Figure 3All operations can be performed by the PFC converter.

[0072] At operation 302, a load power may be determined. The PFC converter 100 may determine the load power for one or more loads, or it may receive the load power for one or more loads.

[0073] At operation 304, it is determined whether the load power is less than the optimal power. The optimal power may be associated with a first efficiency threshold, which may be a first efficiency threshold associated with the highest efficiency point 220. If the load power is greater than or equal to the optimal power, the PFC converter 100 may perform operation 306. If the load power is less than the optimal power, the PFC converter 100 may perform operation 308.

[0074] At operation 306, execution is performed in a continuous mode. Figure 4A and Figure 6A Associated continuous operation mode.

[0075] At operation 308, execution is performed in a low power mode. Figure 4B and Figure 6B The associated low power mode.

[0076] At operation 310, a determination is made as to whether the operation is to end. If the operation is not to end, such that power continues to be provided to one or more loads, the PFC converter may proceed to operation 302 (or continue with operation 306 or 308) to continue or iterate one or more operations. If the operation is to end, such that power is no longer provided to one or more loads, the PFC converter may proceed to operation 312 to end the operation.

[0077] At operation 312, operation ends. If the PFC converter 100 is no longer providing power to one or more loads, the PFC converter 100 may end operation.

[0078] Figure 4A and Figure 4B Illustrative diagrams illustrate the operation of a PFC converter configured for a single-phase input voltage according to one or more embodiments of the present disclosure. These diagrams illustrate operations performed by the PFC converter controller 110. The operations may be performed by hardware, software, or a combination of hardware and software. The PFC converter controller may perform additional operations, including but not limited to converting one or more signals from analog to digital (e.g., using an analog-to-digital converter (ADC)) and / or receiving one or more signals from external to the PFC converter controller 110.

[0079] Figure 4AAn exemplary diagram illustrates the operation of a PFC converter configured for a single-phase input voltage in continuous mode according to one or more embodiments of the present disclosure. During continuous mode, the PFC converter controller 110 may generate a PWM signal that is used as a switching signal 118 to control the operation of one or more switches 160.

[0080] At operation 422, a subtraction operation is performed to generate a V_err signal. The V_err signal is based on subtracting the measured Vdc_meas signal from the Vdc_ref signal. The Vdc_meas signal may be the DC voltage signal 114. The Vdc_ref signal may be set in or provided to the PFC converter controller 110.

[0081] At operation 424, a PI operation is performed on the V_err signal to generate an I_ref_ampli signal. The PI operation may be performed by a proportional and integral controller. The PI operation may generate the I_ref_ampli signal based on the V_err signal.

[0082] At operation 426, the sine wave reference generator may generate I_ref. The sine wave reference generator may generate I_ref based on the I_ref_ampli signal and the V_meas_phase signal received from one or more measurements of the boost circuitry 106, such as from the AC voltage signal 112. I_ref may allow for measurement of the phase of the AC voltage signal 112. The I_ref signal may be based on the amplitude of the I_ref_ampli signal.

[0083] At operation 428 , a subtraction operation is performed to generate the I_err signal. The I_err signal is based on subtracting the measured I_meas signal from the I_ref signal. The I_meas signal may be the AC current signal 116 .

[0084] At operation 430 , a PI operation is performed on the I_err signal to generate a PWM signal. The PWM signal may be a pulse width modulation (PWM) signal used to control one or more switches 160 to change state from open to closed.

[0085] Figure 4B An exemplary diagram illustrates the operation of a PFC converter configured for a single-phase input voltage in a low power mode according to one or more embodiments of the present disclosure. During the low power mode, the PFC converter controller 110 may generate a PWM signal that is used as a switching signal 118 to control the operation of one or more switches 160.

[0086] At operation 442, a subtraction operation is performed to generate a V_err signal. The V_err signal is based on subtracting the measured Vdc_meas signal from the Vdc_ref_low signal. The Vdc_meas signal may be the DC voltage signal 114. The Vdc_ref_low signal may be set in the PFC converter controller 110 based on the highest efficiency point 220.

[0087] At operation 444, a multiplier operation can be performed on the V_err signal using the full_cycle signal. The full_cycle signal can be used to change the V_err signal to zero so that the operation no longer continues. Thus, operation 444 can be used to transmit information related to the voltage bias to operation 446 at the end of the entire cycle, and therefore, operation 446 can generate I_ref_op for rebalancing and / or balancing the DC output voltage during the next cycle. For example, operation 444 can generate a signal provided to operation 446 that can allow operation 446 to reduce or increase I_ref_op when V_err is negative or positive, respectively. Various embodiments can omit this operation and the V_err signal can be passed to operation 446.

[0088] At operation 446, and when the V_err signal is passed through operation 444, the I_ref_op generator can generate an I_ref_op signal. The I_ref_op signal is associated with a reference current, which is associated with the best efficiency of the current and / or next (multiple) cycles. In various embodiments, the I_ref_op generator is configured to generate the I_ref_op signal based on the received V_err signal and the load_meas signal. The load_meas signal can be associated with the current, determined and / or predicted load of the current and / or next (multiple) cycles. Operation 446 can also generate a cycle signal associated with multiple cycles of turning on and / or turning off the switch 160. The cycle signal can be one or more values, such as a first value for multiple on cycles and a second value associated with an off cycle.

[0089] In various embodiments, the PFC converter controller 110 can receive one or more load signals 180 as described herein. The one or more load signals 180 can include a load_meas signal. Thus, the PFC converter controller 110 can receive or be informed, for example, by a load controller, of one or more loads for one or more cycles. This can include, for example, the load controller providing a load_meas signal associated with the load required during the next cycle. In such an example, the load controller can know or be programmed to increase the speed of the motor during the next cycle(s), and the load controller can transmit a load_meas signal to the PFC converter controller 110 related to the DC output voltage generated during the next cycle(s) to support such loads.

[0090] At operation 448, a multiplier operation may be performed on the I_ref_op signal and the ON / OFF signal. The ON / OFF signal may be associated with controlling the generation of a PWM signal for one or more cycles. For example, for a cycle in which the switch 160 is turned on, the ON / OFF signal may be on or have a value of 1. For a cycle in which the switch 160 is to be turned off, the ON / OFF signal may be off or have a value of 0. The multiplier operation may thus pass a zero or off signal, or may pass the I_ref_ON signal to a subsequent operation (e.g., operation 454).

[0091] At operation 450, an ON / OFF signal generator may be used to generate an ON / OFF signal. The ON / OFF signal generator may receive a cycle signal and a V_meas_phase signal. The cycle signal may be received from operation 446 to indicate the number of on cycles and / or the number of off cycles. The V_meas_phase signal (e.g., 112) may be used to measure and / or determine the phase of the AC input signal for tracking or determining when a cycle is complete. For example, it may be used to determine when a signal crosses zero from negative to positive and / or from positive to negative. The ON / OFF signal generator may generate an ON / OFF signal for providing a value of 1 for the cycle when a PWM signal is generated to turn on switch 160, and for providing a value of 0 for the cycle when a PWM signal is not generated so that switch 160 can be turned off. The ON / OFF signal generator may also generate a cycle complete signal for providing to operation 452.

[0092] In various embodiments, the cycle signal may include a number of cycles for generating an ON signal and a number of cycles for generating an OFF signal. Alternatively, the cycle signal may include the number of cycles to be turned on and the total number of cycles until a subsequent ON signal should be generated. The ON signal generator may also function as a counter, among other things, to determine the number of cycles that have occurred and, therefore, when to generate an ON state and when to generate an OFF state for the ON / OFF signal.

[0093] In various embodiments, determining whether a full cycle is complete is based on a zero crossing associated with the V_meas_phase signal (e.g., based on a phase measurement of the AC voltage signal 112). This may allow for starting and / or stopping operations based on multiples of a full cycle, which may be based on time periods associated with the cycle and its multiples.

[0094] At operation 452, a full_cycle signal may be generated based on the cycle_complete signal and provided to operation 444. The cycle_complete signal may be, for example, a pulse each time a cycle is complete, which may cause the full_cycle signal to change state according to the operations described herein.

[0095] At operation 454, the sine wave reference generator may generate I_ref. The sine wave reference generator may generate I_ref based on the I_ref_ON signal and a V_meas_phase signal received from one or more measurements of the boost circuitry 106, such as from the AC voltage signal 112. I_ref may allow for measurement of the phase of the AC voltage signal 112. The I_ref signal may be based on the amplitude of the I_ref_ON signal.

[0096] At operation 456, a subtraction operation is performed to generate an I_err signal. The I_err signal is based on subtracting the measured I_meas signal from the I_ref signal. The I_meas signal can be a signal associated with a current measurement (e.g., the AC current signal 116). For example, in various embodiments, the I_meas signal measures AC current, such as using a shunt resistor or other isolated sensor.

[0097] At operation 458 , a PI operation is performed on the I_err signal to generate a PWM signal. The PWM signal may be a pulse width modulation (PWM) signal that is used to control one or more switches 160 to change state from open to closed.

[0098] In various embodiments, the PFC converter 100 may determine the present and / or future charge of the capacitor 170 and adjust operation in the lower power mode based on the determination.

[0099] For example, the PFC converter controller 110 may receive one or more signals (e.g., 112, 114, 116) and determine the charge on the capacitor and predict the charge of the capacitor over the remaining time period(s) of the charge-discharge cycle. In this way, the PFC converter controller 110 may determine when the capacitor is fully charged and when the capacitor is fully discharged.

[0100] The PFC converter controller 110 can then control and / or adjust operation so that capacitor 170 has a charge sufficient to provide energy to one or more loads. The PFC converter controller 110 can restart charging before capacitor 170 is fully discharged, allowing the load to be continuously powered, which may include adjusting current operation. Alternatively or additionally, in various embodiments, the PFC controller 110 can allow capacitor 170 to fully discharge. In various embodiments, full discharge can also refer to one or more parameters set in the PFC converter controller (e.g., Vdc_ref_min), which can maintain operation in a safe mode and / or boost mode. Additionally or alternatively, if capacitor 170 is fully charged, the PFC converter controller can stop operating the converter (e.g., via an OFF signal or a forced OFF signal). This can prevent capacitor 170 from being overcharged. In various embodiments, full charge can also refer to one or more parameters set in the PFC converter controller (e.g., Vdc_ref_max), which can maintain operation in a safe mode and / or at a convenient output level.

[0101] In various embodiments, the PFC converter controller 110 may predict, forecast, model, and / or determine the power required by the load for the current charge-discharge cycle and one or more subsequent charge-discharge cycles, including one or more time periods associated with waveforms in the current charge-discharge cycle and the subsequent charge-discharge cycles. This may be based on recent load experience, load control, and / or one or more signals received regarding future load control.

[0102] In various embodiments, the prediction, forecasting, modeling, and / or determination may be based on one or more configuration files (e.g., a device configuration file, a load configuration file, etc.) that are programmed and / or stored in the PFC converter controller 110 or received from an external source. For example, the PFC converter controller 110 may be configured with a known load and / or load configuration file.

[0103] In various embodiments, PFC converter controller 110 may determine the amount of remaining energy in capacitor 170 after each waveform cycle during the charge-discharge cycle. This may allow PFC converter controller 110 to determine that sufficient remaining energy exists in capacitor 170 to power load(s) during the capacitor's discharge period. In various embodiments, a minimum charge threshold may exist for capacitor 170, below which PFC converter controller 110 may not allow capacitor 170 to fall. Additionally or alternatively, a maximum charge threshold may exist for capacitor 170, above which PFC converter controller 110 may not charge capacitor 170. The minimum charge threshold and / or the maximum charge threshold may be set based on a safety margin associated with capacitor 170, where the safety margin is a percentage or value of charge associated with the minimum charge and / or maximum charge that capacitor 170 can hold. To prevent the minimum charge threshold and / or the maximum charge threshold from being crossed, PFC converter controller 110 may adjust the number of waveform cycles and / or the on-off ratio to control the charge of capacitor 170. Alternatively or additionally, the charge-discharge cycle may be based on reaching a minimum charge threshold and / or a maximum charge threshold, which may initiate the next charge-discharge cycle and / or adjust the current charge-discharge cycle.

[0104] Figure 5A An exemplary PFC converter configured for a three-phase input voltage according to one or more embodiments of the present disclosure is illustrated. PFC converter 500A may include input circuitry 502A, output circuitry 104, boost circuitry 506A, and a PFC converter controller 510. Output circuitry 104 may be similar to or different from PFC converter 100 configured for a single-phase voltage input. In various embodiments, input circuitry 502A, output circuitry 104, and / or boost circuitry 506A may include additional circuitry and / or electrical components, such as filters, switches, capacitors, inductors, etc., or may omit circuitry and / or electrical components, such as filters, switches, capacitors, inductors, etc.

[0105] I understand. Figure 5A The exemplary PFC converter of FIG. 1 illustrates one example and / or one topology of a three-phase PFC converter. It will be further understood that the present disclosure is not limited to the illustrated topology. For example, the present disclosure may also be applicable to other three-phase PFC converter topologies, such as Figure 5B The topology shown and / or the Vienna topology provided by STMicroelectronics.

[0106] Input circuitry 502A may be coupled to boost circuitry 506A, which may be used to generate an output signal for provision via output circuitry 104. Input circuitry 502A may include a plurality of inductors 540 (e.g., 540A, 540B, 540C) and a plurality of switches 560 (e.g., transistors 560A, 560B, 560C, 560D, 560E, 560F), which may be operated by PFC converter controller 510 to control three input phases 502 (e.g., 502A, 502B, 502C). In various embodiments, each of the three phases may be associated with one or more inductors 540. For example, the first phase received at input terminal 502A can be associated with first inductor 540A, the second phase received at input terminal 502B can be associated with second inductor 540B, and the third phase received at input terminal 502C can be associated with third inductor 540C. Each of the plurality of switches 560 can be operated by an associated control signal 568 (e.g., 568A, 568B, 568C, 568D, 568E, 568F). ​​The plurality of switches 560 can be operated to open and close the switches. The plurality of switches 560 can be operated to provide an AC signal to the boost circuitry 506A of the PFC converter 500, such as to charge capacitor 170. Additionally or alternatively, in various embodiments, the input circuitry 502A can further include one or more drivers associated with the control signal(s) 568. The one or more drivers can be used to drive the respective switches based on the control signal 568 from the PFC converter controller 510. Alternatively or additionally, various embodiments of input circuitry 502 may include a plurality of diodes, such as a diode in place of each of the illustrated switches 560, which may provide control of providing the AC voltage signal to boost circuitry 106. Input circuitry 502 may also include additional circuitry and / or electrical components, such as diodes, switches, capacitors, inductors, etc.

[0107] In various embodiments, input circuitry 502A may include AC voltage sensing circuitry and / or AC current sensing circuitry.

[0108] The AC voltage sensing circuitry may include a plurality of resistors 536 (eg, 536A1 , 536A2 , 536B1 , 536B2 , 536C1 , 536C2 ) that may be used to acquire an AC voltage signal for each of the phases provided to the PFC converter controller 510 .

[0109] For example, an AC voltage signal associated with phase A 512A of the three-phase input may include resistor 536A1 coupled to resistor 536A2, with resistor 536A2 coupled to ground as shown. The AC voltage signal associated with phase A 512A may be derived between resistor 536A1 and resistor 536B1 and provided to PFC converter controller 510. Similarly, an AC voltage signal associated with phase B 512B and resistors 536B1 and 536B2, as well as an AC voltage signal associated with phase C 512C and resistors 536C1 and 536C2, may be derived and provided to PFC converter controller 510. The AC voltage sensing circuitry may also include additional circuitry and / or electrical components, such as an analog-to-digital converter.

[0110] In various embodiments, the circuit arrangement can additionally be used to determine an AC voltage signal for each of phases A, B, and C, such as by taking voltages based on points between corresponding resistors and from points between the corresponding resistors and ground as shown. These voltages can be used to generate an AC voltage signal for the corresponding phase and provide it to the PFC converter controller 510.

[0111] The AC current sensing circuitry may include one or more AC current signals 513 obtained from the three-phase input 502 and the inductor 540. The AC current signal associated with phase A 513A may be provided to the PFC converter controller 510. Similarly, the AC current signal associated with phase B 513B and the AC current signal associated with phase C 513C may be provided to the PFC converter controller 510. The AC current sensing circuitry may also include additional circuitry and / or electrical components, such as an analog-to-digital converter, etc.

[0112] Boost circuitry 506A may include one or more resistors (e.g., 534) and one or more capacitors 170. In various embodiments, one or more capacitors 170 may be referred to as bulk capacitors. Input circuitry 502A and boost circuitry 506A may operate based on one or more signals from PFC converter controller 510. For example, one or more switches 560 may be opened and / or closed based on one or more switching signals 568 generated and provided by PFC converter controller 510. Switching signal(s) 568 may be PWM signal(s). Alternatively, they may be binary signals that may indicate whether a switch is open and / or closed.

[0113] Boost circuitry 506A may provide one or more signals to PFC converter controller 510, which may serve as a basis for, among other things, generating switching signal(s) 568. For example, a DC voltage signal 514 and a DC current signal 516 may be provided to PFC converter controller 510. DC voltage signal 514 may be derived from a point between a first resistor 534A and a second resistor 534B, which are coupled to the output of boost circuitry 506A.

[0114] Figure 5B An exemplary PFC converter configured for a three-phase input voltage according to one or more embodiments of the present disclosure is illustrated. PFC converter 500B may include input circuitry 502B, output circuitry 104, boost circuitry 506B, and a PFC converter controller 510. Output circuitry 104 may be similar to or different from PFC converter 100 configured for a single-phase voltage input. In various embodiments, input circuitry 502B, output circuitry 104, and / or boost circuitry 506B may include additional circuitry and / or electrical components, such as filters, switches, capacitors, inductors, etc., or may omit circuitry and / or electrical components, such as filters, switches, capacitors, inductors, etc.

[0115] Input circuitry 502B may be coupled to boost circuitry 506B, which may be used to generate an output signal provided via output circuitry 104. Input circuitry 502B may include a plurality of inductors 540 (e.g., 540A, 540B, 540C) and a plurality of diodes 120 (e.g., diodes 120A1, 120A2, 120B1, 120B2, 120C1, 120C2). In various embodiments, each of the three phases may be associated with one or more inductors 540. For example, a first phase received at input terminal 502A may be associated with first inductor 540A, a second phase received at input terminal 502B may be associated with second inductor 540B, and a third phase received at input terminal 502C may be associated with third inductor 540C. Input circuitry 502B may also include additional circuitry and / or electrical components, such as diodes, switches, capacitors, inductors, and the like.

[0116] In various embodiments, input circuitry 502A may include AC voltage sensing circuitry and / or AC current sensing circuitry.

[0117] The AC voltage sensing circuitry may include a plurality of resistors 536 (eg, 536A1 , 536A2 , 536B1 , 536B2 , 536C1 , 536C2 ) that may be used to acquire an AC voltage signal for each of the phases provided to the PFC converter controller 510 .

[0118] For example, an AC voltage signal associated with phase A 512A of the three-phase input may include resistor 536A1 coupled to resistor 536A2, with resistor 536A2 coupled to ground as shown. The AC voltage signal associated with phase A 512A may be derived between resistor 536A1 and resistor 536B1 and provided to PFC converter controller 510. Similarly, an AC voltage signal associated with phase B 512B and resistors 536B1 and 536B2, as well as an AC voltage signal associated with phase C 512C and resistors 536C1 and 536C2, may be derived and provided to PFC converter controller 510. The AC voltage sensing circuitry may also include additional circuitry and / or electrical components, such as an analog-to-digital converter.

[0119] In various embodiments, the circuit arrangement can additionally be used to determine an AC voltage signal for each of phases A, B, and C, such as by taking voltages based on points between corresponding resistors and from points between the corresponding resistors and ground as shown. These voltages can be used to generate an AC voltage signal for the corresponding phase and provide it to the PFC converter controller 510.

[0120] The AC current sensing circuitry may include one or more AC current signals 513 obtained from the three-phase input 502 and the inductor 540. The AC current signal associated with phase A 513A may be provided to the PFC converter controller 510. Similarly, the AC current signal associated with phase B 513B and the AC current signal associated with phase C 513C may be provided to the PFC converter controller 510. The AC current sensing circuitry may also include additional circuitry and / or electrical components, such as an analog-to-digital converter, etc.

[0121] Boost circuitry 506B may include one or more resistors 534 (e.g., 534A, 534B, 534C, 534D), one or more capacitors 170 (e.g., 170A, 170B), and multiple switches 560 (e.g., transistors 560A, 560B, 560C, 560D, 560E, 560F). The multiple switches 560 may be operated by PFC converter controller 510 to control the three input phases 502 (e.g., 502A, 502B, 502C) to charge and discharge the one or more capacitors 170. In various embodiments, the one or more capacitors 170 may be referred to as bulk capacitors. Input circuitry 502B and boost circuitry 506B may operate based on one or more signals from PFC converter controller 510. For example, the one or more switches 560 may be opened and / or closed based on one or more switching signals 568 generated and provided by PFC converter controller 510. The switching signal(s) 568 may be PWM signals. Alternatively, it may be a binary signal that may indicate whether a switch is open and / or closed.

[0122] Each of the plurality of switches 560 (e.g., 560A, 560B, 560C, 560D, 560E, 560F) can be operated by an associated control signal 568 (e.g., 568A, 568B, 568C, 568D, 568E, 568F). ​​The plurality of switches 560 can be operated to open and close the switches. The plurality of switches 560 can be operated to provide an AC signal to the boost circuit arrangement 506B of the PFC converter 500B, such as to charge the capacitor 170 (e.g., 570A, 570B). Additionally or alternatively, in various embodiments, the boost circuit arrangement 506B can further include one or more drivers associated with the control signal(s) 568. The one or more drivers can be used to drive the corresponding switches based on the control signal 568 from the PFC converter controller 510.

[0123] Boost circuitry 506B can provide one or more signals to PFC converter controller 510, which can serve as a basis for, among other things, generating switching signal(s) 568. For example, one or more DC voltage signals 514 (e.g., 514A, 514B) and a DC current signal 516 can be provided to PFC converter controller 510. First DC voltage signal 514A can be derived from a point between resistor 534A and resistor 534B. Second DC voltage signal 514B can be derived from a point between resistor 534C and resistor 534D. In various embodiments, the circuitry can also be used to determine DC voltage signals 514A, 514B, such as by deriving voltages from points on either side of the corresponding resistor (e.g., 534B or 534D) as shown. Each of these corresponding voltages from the two points can be used to generate a DC voltage signal across a resistor (e.g., 534B or 534D) and provide it to PFC converter controller 510. The DC voltage sensing circuitry may also include additional circuitry and / or electrical components, such as an analog-to-digital converter or the like.

[0124] In various embodiments, the first efficiency threshold associated with the highest efficiency point 220 can vary with temperature. The PFC converter controller (e.g., 110, 510) can provide, determine, adjust, or optimize the Vdc_ref signal and / or the Vdc_ref_low signal based on temperature. The temperature can be measured, for example, by a temperature sensor in the PFC converter (e.g., 100, 500).

[0125] In various embodiments, the first efficiency threshold associated with the highest efficiency point 220 can vary based on the DC voltage required by one or more loads. In various embodiments, the PFC converter (e.g., 100, 500) can have losses (e.g., switching losses) that can cause a change or decrease in the DC voltage. The PFC converter controller (e.g., 110, 510) can receive, determine, adjust, or optimize the Vdc_ref signal and / or the Vdc_ref_low signal based on the DC voltage (e.g., DC voltage signal 114, DC voltage signal 512).

[0126] In various embodiments, the on-off ratio in one or more switching signals (e.g., 118, 568) can be adjusted and / or changed to avoid and / or eliminate one or more unwanted harmonics. The PFC converter (e.g., 100, 500) can determine whether one or more harmonics are present, or predict that one or more harmonics may be generated based on past and current operations. The PFC converter (e.g., 100, 500) can adjust the on-off ratio by adjusting the number of on cycles and / or the number of off cycles in the charge-discharge cycle, which can eliminate or prevent harmonics. Alternatively or additionally, the PFC converter (e.g., 100, 500) can utilize one or more randomized charge-discharge cycles with a randomized on-off ratio to prevent harmonic generation.

[0127] Figure 6A and Figure 6B Illustrated are exemplary diagrams of a PFC converter configured for a three-phase input voltage according to one or more embodiments of the present disclosure. These diagrams illustrate operations performed by a PFC converter controller 510. The operations may be performed by hardware, software, or a combination of hardware and software. The PFC converter controller 510 may perform additional operations, including, but not limited to, converting one or more signals from analog to digital (e.g., using an analog-to-digital converter (ADC)), receiving one or more signals from outside the PFC converter controller 510, and / or performing one or more transformations on the signals. For example, the PFC converter 500 may have a DC current signal 516, which may be provided to an ADC and / or a transformer to transform the current using a direct quadrature (DQ) transformation (e.g., a Park transform or a Clarke transform). After the DQ transformation, the DC current signal 516 may be transformed into Id and Iq, which may be used in one or more operations described herein.

[0128] In various embodiments, Figure 6A and Figure 6B The exemplary diagram of can be used to generate one or more switching signals 568. Various embodiments may include a PFC converter controller 510 that can utilize Figure 6A and / or Figure 6B 568 (e.g., utilizing 6 separate PWM channels to generate 6 PWM signals). Alternatively or additionally, various embodiments may include a PFC converter controller 510 that may generate each of the one or more switching signals 568 according to the separate operations illustrated for the one or more switching signals 568. Figure 6A and / or Figure 6BThe operations illustrated in , generate one or more switching signals in the switching signals 568 by performing one or more shared operations for generating one or more switching signals 568 (eg, generating 6 PWM signals using 1 PWM channel).

[0129] Figure 6A An exemplary diagram illustrates the operation of a PFC converter configured for a three-phase input voltage in continuous mode according to one or more embodiments of the present disclosure. During continuous mode, the PFC converter controller 510 may generate one or more PWM signals that are used as one or more switching signals 518 to control the operation of one or more switches 560.

[0130] At operation 622, a subtraction operation is performed to generate a V_err signal. The V_err signal is based on subtracting the measured Vdc_meas signal from the Vdc_ref signal. The Vdc_meas signal may be the DC voltage signal 514. The Vdc_ref signal may be set in or provided to the PFC converter controller 510.

[0131] At operation 624, a PI operation is performed on the Verr signal to generate an Id_ref signal. The PI operation may be performed by a proportional and integral controller. The PI operation may generate the Id_ref signal based on the Verr signal.

[0132] At operation 626 , a subtraction operation is performed to generate the Id_err signal. The Id_err signal is based on subtracting the Id signal associated with the current measurement (eg, the DC current signal 516 ) from the Id_err signal.

[0133] At operation 628, a PI operation is performed on the Id_err signal to generate a Vd signal. The PI operation can be performed by a proportional and integral controller. The PI operation can generate a Vd signal based on the Id_err signal. The Vd signal can be associated with a voltage in the DQ domain.

[0134] At operation 630, a subtraction operation is performed to generate an Iq_err signal. The Iq_err signal is based on subtracting an Iq signal associated with a current measurement (e.g., DC current signal 516) from an Iq_ref signal. The Iq_ref signal may be set in or provided to the PFC converter controller 510.

[0135] At operation 632, a PI operation is performed on the Iq_err signal to generate a Vq signal. The PI operation can be performed by a proportional and integral controller. The PI operation can generate the Vq signal based on the Iq_err signal. The Vq signal can be associated with a voltage in the DQ domain.

[0136] At operation 634, a transformation from dq0 to abc is performed. The transformation of operation 634 can transform the vector voltage of the Vd signal and the vector voltage of the Vq signal into the abc domain. This can be referred to as an inverse transformation (e.g., inverse Park transform, inverse Clarke transform) because it can be associated with reversing one or more previous transformations that generated vectors in the DQ domain.

[0137] At operation 636 , an SPWM operation is performed on the Vabc signal to generate one or more PWM signals. The PWM signal(s) may be pulse width modulated (PWM) signals used to control one or more switches 560 to change state from open to closed.

[0138] Figure 6B An exemplary diagram illustrates operations performed in a low power mode by a PFC converter configured for a three-phase input voltage according to one or more embodiments of the present disclosure. During the low power mode, the PFC converter controller 510 may generate one or more PWM signals that are used as switching signals 518 to control the operation of one or more switches 560.

[0139] At operation 642, a subtraction operation is performed to generate a V_err signal. The V_err signal is based on subtracting the measured Vdc_meas signal from the Vdc_ref_low signal. The Vdc_meas signal may be the DC voltage signal 514. The Vdc_ref_low signal may be set in or received by the PFC converter controller 510 based on the maximum efficiency point 220.

[0140] At operation 644, a multiplier operation can be performed on the V_err signal using the full_cycle signal. Thus, operation 644 can be used to transmit information related to the voltage bias to operation 646 at the end of a full cycle, and thus operation 646 can generate I_ref_op for rebalancing and / or balancing the DC output voltage during the next cycle. For example, operation 644 can generate a signal provided to operation 646 that allows operation 646 to decrease or increase I_ref_op when V_err is negative or positive, respectively. Various embodiments may omit this operation, and the V_err signal can be passed to operation 646.

[0141] At operation 646, and when the V_err signal is passed through operation 644, the Id_ref_op generator can generate an Id_ref_op signal. The Id_ref_op signal is associated with a reference current, which is associated with the best efficiency of the current and / or next (multiple) cycles. In various embodiments, the Id_ref_op generator is configured to generate the Id_ref_op signal based on the received V_err signal and the load_meas signal. The load_meas signal can be associated with the current, determined and / or predicted load for the current and / or next (multiple) cycles. Operation 646 can also generate a cycle signal associated with multiple cycles of turning on and / or turning off the switch 560. The cycle signal can be one or more values, such as a first value for an on cycle and a second value associated with an off cycle.

[0142] At operation 648, a multiplier operation may be performed on the Id_ref_op signal and the ON / OFF signal. The ON / OFF signal may be associated with controlling the generation of a PWM signal for one or more cycles. For example, for a cycle in which the switch 560 is turned on, the ON / OFF signal may be on or have a value of 1. For a cycle in which the switch 560 is to be turned off, the ON / OFF signal may be off or have a value of 0. The multiplier operation may thus pass a zero or off signal and may also pass the Id_ref_ON signal to subsequent operations (e.g., operation 654).

[0143] At operation 650, an ON / OFF signal can be generated using an ON / OFF signal generator. The ON / OFF signal generator can receive a cycle signal and a V_meas_phase signal. The cycle signal can be received from operation 646 to indicate the number of on cycles and / or the number of off cycles. The V_meas_phase signal (e.g., 512) can be used to measure and / or determine the phase of the AC input signal for tracking or determining when a cycle is complete. For example, it can be used to determine when a signal crosses zero from negative to positive. The ON / OFF signal generator can generate an ON / OFF signal for providing a value of 1 for the cycle when a PWM signal is to be generated to turn on switch 560, and for providing a value of 0 for the cycle when a PWM signal is not generated so that switch 560 can be turned off. The ON / OFF signal generator can also generate a cycle complete signal for providing to operation 652.

[0144] In various embodiments, the cycle signal may include the number of cycles used to generate the ON signal and the number of cycles used to generate the OFF signal. Alternatively, the cycle signal may include the number of cycles to be turned on and then the total number of cycles until a subsequent ON signal should be generated. Among other things, the ON signal generator may act as a counter or the like to determine the number of cycles that have occurred and, therefore, when to generate the ON state and when to generate the OFF state for the ON / OFF signal.

[0145] In various embodiments, determining a complete cycle is based on a zero crossing associated with the V_meas_phase signal (e.g., based on the phase measurement value of 512). This can allow for starting and / or stopping operations based on multiples of a complete cycle, which can be based on time periods associated with the cycle and its multiples.

[0146] At operation 652, a full_cycle signal may be generated based on the cycle_complete signal and provided to operation 644. The cycle_complete signal may be, for example, a pulse each time a cycle is complete, which may cause the full_cycle signal to change state according to the operations described herein.

[0147] At operation 654 , a subtraction operation is performed to generate an Id_err signal. The Id_err signal is based on subtracting the Id signal associated with the current measurement (eg, the DC current signal 516 ) from the Id_ref_ON signal.

[0148] At operation 656, a PI operation is performed on the Id_err signal to generate a Vd signal. The PI operation can be performed by a proportional and integral controller. The PI operation can generate a Vd signal based on the Id_err signal. The Vd signal can be associated with a voltage in the DQ domain.

[0149] At operation 658, a subtraction operation is performed to generate an Iq_err signal. The Iq_err signal is based on subtracting the Iq signal associated with the current measurement (e.g., DC current signal 516) from the Iq_ref signal. In various embodiments, the Iq_ref signal, which may be associated with reactive power, may be set to 0. The Iq_ref signal may be set in or provided to the PFC converter controller 510.

[0150] At operation 660, a PI operation is performed on the Iq_err signal to generate a Vq signal. The PI operation can be performed by a proportional and integral controller. The PI operation can generate the Vq signal based on the Iq_err signal. The Vq signal can be associated with a voltage in the DQ domain.

[0151] At operation 662, a transformation from dq0 to abc is performed. The transformation of operation 634 may change the vector voltage of the Vd signal and the vector voltage of the Vq signal to the abc domain. This may be referred to as an inverse transformation (e.g., inverse Park transform, inverse Clark transform) because it may be associated with reversing one or more previous transformations that generated the vectors in the DQ domain.

[0152] At operation 664, an SPWM operation is performed on the Vabc signal to generate one or more PWM signals. The PWM signal(s) may be pulse width modulated (PWM) signals used to control one or more switches 560 to change state from open to closed.

[0153] Figure 7A and Figure 7B An exemplary graph for a PFC converter according to one or more embodiments of the present disclosure is illustrated.

[0154] Figure 7A A first exemplary graph for a PFC converter according to one or more embodiments of the present disclosure is illustrated. The first graph illustrates four curves: a Vac_in_meas curve 710A, an Iac_meas curve 720A, an Iac_meas curve 730A, and an Idc_out_meas curve 740A.

[0155] The Vac_in_meas curve 710A is an example of a measurement value, such as a single-phase input voltage at the input circuit arrangement 102. The lac_meas curve 720A is an example of a measurement value, such as an AC current measured at the AC current signal 116. The Vdc_out_meas curve 730A is an example of a measurement value, such as a DC output voltage measured between the first output terminal 104A and the second output terminal 104B. The ldc_out_meas curve 740A is an example of a measurement value, such as a DC output voltage measured between the first output terminal 104A and the second output terminal 104B.

[0156] like Figure 7A As shown, the lac_meas curve 720A can be a time period for a single cycle in a time period of 10 waves. As described herein, the lac_meas curve 720A that is on within one cycle can be associated with the switch 160 being in an on state, such as during operation (e.g., 308) in a low power mode. As shown, Figure 7AThe on-state of the capacitor 170 can be a ratio of 1:9 for one cycle on and nine cycles off. Alternatively, the ratio can be described as 1:10 for one cycle in a period of 10 cycles. While the lac_meas curve 720A is on, the capacitor 170 is charged during the same (multiple) time periods and / or (multiple) cycles. As shown by the lac_meas curve 730A and the idc_out_meas curve 740A, the capacitor discharges and provides current and / or voltage to one or more loads.

[0157] exist Figure 7A In the various embodiments shown, the exemplary load may be 100W, and the PFC converter 100 may be operated at a first efficiency threshold associated with a maximum efficiency point 220 of 1000W. Compared to 1000W, 100W is a low load. To operate efficiently, the PFC converter 100 may operate at 1000W in one cycle to convert 1000W of power from the AC input at the input circuitry 102. Of the 1000W of DC power, 100W may be used by one or more loads coupled to the output circuitry 104 in the first cycle, and the remaining 900W of energy may then be used by the one or more loads in the following nine cycles. The remaining 900W of energy in the first cycle may be stored by charging one or more capacitors 170. The one or more capacitors 170 may then be discharged in the following nine cycles to provide power to one or more loads. Therefore, the PFC converter 100 may be operated with an on-off ratio of 1:9, which also corresponds to an on-time period of 1:10 or a 10% duty cycle for the PFC converter 100 .

[0158] In various embodiments, the on-off ratio may be the total number of cycles associated with the power required to fully charge and discharge the capacitor. As described herein, one example may be an on-off ratio of 1:9, where 1000W of power is generated and 900W of energy is accumulated during a single on-state for one waveform cycle, such that nine waveform cycles discharging at 100W per waveform cycle discharge the accumulated energy in capacitor 170, such that capacitor 170 may be discharged at the end of nine waveform cycles when switch 160 is in the off state. Figure 7A The charge-discharge cycle shown lasts for 10 waveform cycles.

[0159] In various embodiments, the on-off ratio may be associated with a power that is not a multiple of the load, such that after one charge-discharge cycle, capacitor 170 still has accumulated power before the next charge-discharge cycle begins.

[0160] like Figure 7AAs shown, the Vac_in_meas curve 710A may have a time period of 10 cycles for turning the switch 160 on and off. Figure 7A The diagram illustrates that during the nine periods during which the switch 160 may be off, there may be a voltage that is not a flat curve of zero volts for the associated Vdc voltage (e.g., 730A). This may be due to, for example, reactive current flow, which may be associated with the voltage illustrated during these nine off cycles. Examples of circuit devices that may be associated with reactive current(ies) are capacitor filters, etc. In various embodiments, during such off cycles, the voltage may instead be zero. Additionally or alternatively, during one or more off cycles, the PFC converter controller 110 may set, provide, or generate an offset reference current that may offset or mitigate the effects of, for example, Figure 7A One or more currents present during the off cycle are shown. Such an offset reference current can offset the oscillations illustrated in the voltage of the Vac_in_meas curve 710A during the off cycle.

[0161] like Figure 7A As shown, Idc_out_meas curve 740A may include one or more high-frequency oscillations in the load current. For example, the conduction cycle illustrated in Idc_out_meas curve 740A includes high-frequency oscillations and, therefore, is not a clean, flat curve or line. In various embodiments, such high-frequency oscillations may be due to electronic load behavior. For example, this may be due to the load being a constant-power load. In various embodiments, Idc_out_meas curve 740A may be a curve without high-frequency oscillations for the conduction cycle. Thus, the output at output terminals 104A, 104B may be provided to one or more loads without high-frequency oscillations or with high-frequency oscillations compensated for in PFC converter controller 110.

[0162] Figure 7B A second exemplary graph for a PFC converter according to one or more embodiments of the present disclosure is illustrated. The second graph illustrates four curves: a Vac_in_meas curve 710B, an Iac_meas curve 720B, a Vdc_out_meas curve 730B, and an Idc_out_meas curve 740B.

[0163] The Vac_in_meas curve 710B is an example of a measured value, such as a single-phase input voltage at the input circuit arrangement 102. The lac_meas curve 720B is an example of a measured value, such as an AC current measured based on the AC current signal 116. The Vdc_out_meas curve 730B is an example of a measured value, such as a DC output voltage measured between the first output terminal 104A and the second output terminal 104B. The ldc_out_meas curve 740B is an example of a measured value, such as a DC output voltage measured between the first output terminal 104A and the second output terminal 104B.

[0164] like Figure 7B As shown, the lac_meas curve 720B can be for a single cycle of a period of 4 waves or waveform cycles. As described herein, the lac_meas curve 720B that is on within one cycle can be associated with the switch 160 being in the on state, such as during operation (e.g., 308) in a lower power mode. As shown, Figure 7A The on-state of the capacitor 170 can be a ratio of 1:3, with one waveform cycle on and three waveform cycles off. Alternatively, the ratio can be described as 1:4, with one waveform cycle on in a period of four waveform cycles. While the lac_meas curve 720B is on, the capacitor 170 is charged during the same (multiple) time periods and / or (multiple) waveform cycles. As illustrated using the Vdc_out_meas curves 730B and 740B, the capacitor discharges and provides current and / or voltage to one or more loads. Figure 7B The charge-discharge cycle shown lasts for 4 waveform cycles.

[0165] like Figure 7B As illustrated, the Vac_in_meas curve 710B may have a time period of 4 cycles for turning the switch 160 on and off. Figure 7B The diagram illustrates that during the three periods during which the switch 160 may be off, there may be a voltage that is not a flat curve for the associated Vdc voltage (e.g., 730B). This may be due to, for example, reactive current flow, which may be associated with the voltage illustrated during these three off cycles. Examples of circuit devices that may be associated with reactive current(ies) are capacitor filters, etc. In various embodiments, during such off cycles, the voltage may instead be zero. Additionally or alternatively, during one or more off cycles, the PFC converter controller 110 may set, provide, or generate an offset reference current that may offset or mitigate the effects of, for example, Figure 7BOne or more currents present during the off cycle are shown. Such an offset reference current can offset the oscillations illustrated in the voltage of the Vac_in_meas curve 710B during the off cycle.

[0166] like Figure 7B As shown, Idc_out_meas curve 740B may include one or more high-frequency oscillations in the load current. For example, the conduction cycle illustrated in Idc_out_meas curve 740B includes high-frequency oscillations and, therefore, is not a clean, flat curve or line. In various embodiments, such high-frequency oscillations may be due to electronic load behavior. For example, this may be due to the load being a constant-power load. In various embodiments, Idc_out_meas curve 740B may be a curve without high-frequency oscillations for the conduction cycle. Thus, the output at output terminals 104A, 104B may be provided to one or more loads without high-frequency oscillations or with high-frequency oscillations compensated for in PFC converter controller 110.

[0167] Figure 8A and Figure 8B An exemplary graph for a PFC converter according to one or more embodiments of the present disclosure is illustrated.

[0168] Figure 8A A first example graph 800A illustrates efficiency versus power for various embodiments of the present disclosure compared to a conventional PFC converter. Curve 810 is a curve associated with a conventional PFC converter. Curve 820 is an example of a curve associated with various embodiments of the present disclosure. As shown in graph 800A, the present disclosure provides improved efficiency when operating at low power (i.e., lower loads) compared to conventional PFC converters.

[0169] Figure 8B A second example graph 800B illustrates total harmonic distortion (THD) versus output current (ITHD) for various embodiments of the present disclosure compared to a conventional PFC converter. Curve 830 is a curve associated with a conventional PFC converter. Curve 840 is an example of a curve associated with various embodiments of the present disclosure. As shown in graph 800B, the present disclosure provides improved total harmonic distortion when operating at low power (i.e., lower loads) compared to conventional PFC converters.

[0170] In addition to lower THD (which is associated with lower or no harmonics in the current(s) in the PFC converter's circuitry), heat generation in the PFC converter can be reduced. Harmonics in the PFC converter may cause heat generation in the circuitry of the PFC converter (e.g., 100, 500), particularly in the inductor. The harmonics may be provided to one or more loads at the output circuitry 104, but conversely, the harmonics may circulate within the PFC converter's circuitry, which may generate losses, such as heat. Lowering THD allows for reduced heat generation by one or more electrical components. For example, during an off-time period, when one or more switches 160 may be open, the inductor(s) may not conduct any current, particularly in various embodiments with a single-phase input circuitry (e.g., 102). Energy input to the PFC converter circulates as harmonics and is not provided to one or more loads, which is associated with reduced efficiency. Therefore, improvements in lower THD are also associated with improved energy efficiency.

[0171] Additionally and / or alternatively, a reduction in THD may be associated with the improved acoustic noise reduction of the present disclosure. Harmonics in a system may generate vibrations, particularly in inductors. Vibrations may cause acoustic noise. For example, high-frequency harmonics may generate magnetic fields, which may generate microvibrations, which may generate acoustic noise. With the reduction in harmonics, acoustic noise, such as in inductors, may also be reduced.

[0172] Figure 9 An exemplary device according to one or more embodiments of the present disclosure is illustrated. The device 900 may be a device for an application, apparatus, and / or system. For example, the device 900 may be an air conditioning system or device for other applications such as those described herein. The illustrated device 900 may be a system and / or device, including a processor 902, a memory 904, a communication circuit device 906, an input / output circuit device 908, a PFC converter 912, all of which may be connected via one or more buses 910. Furthermore, the device 900 may include a power supply 920 and / or (multiple) loads 930. Alternatively or additionally, the power supply 920 and / or (multiple) loads 930 may be located external to the device and coupled to the device 900. The power supply 920 may be coupled to at least the PFC converter 912 via a bus or one or more connectors 922. The (multiple) loads 930 may be coupled to at least the PFC converter 912 via a bus or connector 932. Although Figure 9 Buses and / or connectors are shown, but it can be readily appreciated that numerous other connections may exist.

[0173] The processor 902, although illustrated as a single block, may be comprised of multiple components and / or processor circuitry. The processor 902 may be implemented as, for example, various components, including one or more microprocessors with accompanying digital signal processors; one or more processors without accompanying digital signal processors; one or more coprocessors; one or more multi-core processors; processing circuitry; and various other processing elements. The processor may include an integrated circuit. In various embodiments, the processor 902 may be configured to execute applications, instructions, and / or programs stored in the processor 902, the memory 904, or otherwise accessible to the processor 902. When executed by the processor 902, these applications, instructions, and / or programs may be capable of performing one or more operations and / or functions described herein. Whether configured by hardware, firmware / software methods, or a combination thereof, the processor 902 may include an entity capable of performing operations and / or functions according to embodiments of the present disclosure when configured accordingly.

[0174] The memory 904 may include, for example, volatile memory, non-volatile memory, or a specific combination thereof. Although illustrated as a single box, the memory 904 may include multiple memory components. In various embodiments, the memory 904 may include, for example, random access memory, cache, flash memory, a hard disk, a circuit configured to store information, or a combination thereof. The memory 904 may be configured to write or store data, information, applications, instructions, etc., so that the processor 904 can perform various operations and / or functions according to the embodiments of the present disclosure. For example, in at least some embodiments, the memory 904 may be configured to buffer or cache data to be processed by the processor 902. Additionally or alternatively, in at least some embodiments, the memory 904 may be configured to store program instructions for execution by the processor 902. The memory 904 may store information in the form of static and / or dynamic information. When the operations and / or functions are performed, the stored information may be stored and / or used by the processor 902.

[0175] The communication circuitry 906 can be implemented as circuitry, hardware, a computer program product, or a combination thereof configured to receive and / or transmit data from another component or device. The computer program product may include computer-readable program instructions stored on a computer-readable medium (e.g., memory 904) and executed by the processor 902. In various embodiments, the communication circuitry 906 (along with other components discussed herein) may be at least partially implemented as part of the processor 902 or otherwise controlled by the processor 902. The communication circuitry 906 may communicate with the processor 902, for example, via a bus 910. Such a bus 910 may be connected to the processor 902, and it may also be connected to one or more other components of the processor 902. The communication circuitry 906 may be comprised of, for example, a transmitter, a receiver, a transceiver, a network interface card, and / or supporting hardware and / or firmware / software, and may be used to establish communications with other component(s), device(s), and / or system(s). Communication circuitry 906 may be configured to receive and / or transmit data that may be stored by, for example, memory 904 using one or more protocols that can be used to communicate between components, devices, and / or systems.

[0176] Input / output circuitry 908 may communicate with processor 902 to receive instructions input by an operator and / or provide audible, visual, mechanical, or other output to the operator. Input / output circuitry 908 may include support devices such as a keyboard, a mouse, a user interface, a display, a touch screen display, lights (e.g., warning lights), indicators, speakers, and / or other input / output mechanisms. Input / output circuitry 908 may include one or more interfaces to which support devices may be connected. In various embodiments, various aspects of input / output circuitry 908 may be implemented on a device used by an operator to communicate with processor 902. Input / output circuitry 908 may communicate with memory 904, communication circuitry 906, and / or any other components, for example, via bus 910.

[0177] The PFC converter 912 receives power from the power source 920 and generates and / or provides power to the load(s) 930. The PFC converter can be as described herein (e.g., 100, 500). The PFC converter can include a PFC converter controller 914, which can be as described herein (e.g., 110, 510). In various embodiments, the PFC converter controller 914 can be on or mounted to a PCB in the device 900.

[0178] The PFC converter controller 914 can be implemented in hardware, software, or a combination of hardware and software. In various embodiments, the PFC controller can be embodied in an integrated circuit, an MCU (e.g., a virtual machine running in the MCU), etc. In various embodiments, the PFC converter controller 914 can be located external to the other circuitry of the PFC converter 912. In various embodiments, the PFC converter controller 914 can be configured with a table pre-programmed with, for example, a first efficiency threshold associated with the highest efficiency point 220, one or more on-off ratios, etc. Alternatively and / or in addition, the PFC converter controller 914 can be configured to determine and / or calculate the timing of a charge cycle and / or a discharge cycle. For example, the next charge time period during the charge-discharge cycle can be calculated using the ratio of waveform cycles that remain on and / or off, which ratio can be the on-off ratio.

[0179] In various embodiments, device 900 may be an air conditioner. Load 930 may be a motor for a compressor and / or fan. Power source 920 may be a single-phase or three-phase feed from an external power panel or power box. PFC converter controller 912 may also control the motors for the compressor and / or fan. PFC converter controller 912 may be configured to determine or predict the load for the next charge-discharge cycle, given that PFC converter controller 912 is controlling the motor(s), and thus control the operation of the motor(s) within one or more future time periods. For example, PFC converter controller 914 controls whether the motor(s) change speed or maintain their current speed. Alternatively or additionally, motor control may be provided by a separate processor (e.g., 902), an IC, an MCU, etc., providing one or more signals associated with motor control to PFC converter controller 914.

[0180] In various embodiments, the device 900 is used for battery charging. For example, the one or more loads may be one or more batteries that can be charged. The device 900 may include a battery management system, or alternatively, the device 900 may receive one or more signals (e.g., one or more load signals 180) and / or transmit one or more signals (e.g., one or more load signals 180) to a battery management system. Such a battery management system may provide a load curve, such as a charging curve associated with the load (s) of one or more batteries, via one or more signals. The device 900 may operate the PFC converter 912 according to the received load curve to generate an output for charging the battery (s).

[0181] Various embodiments may include a PFC converter in a single channel topology or a multi-channel topology. Various embodiments of the multi-channel topology include a dual channel topology, which may be an interleaved PFC topology.

[0182] Figure 10 An exemplary PFC converter configured with a dual-channel PFC topology according to one or more embodiments of the present disclosure is illustrated. In various embodiments, PFC converter 1000 may include input terminals 1002A, 1002B for receiving one or more AC voltages and output terminals 104A, 104B for providing DC power to one or more loads. Input terminals 1002A, 1002B may be coupled to EMI filter and rectification circuitry 1008, which may filter and / or rectify the AC signals received at input terminals 1002A, 1002B. EMI filter and rectification circuitry 1008 may provide rectified AC signal measurements as AC voltage input (Vac) signals 1012 to PFC converter 1010. EMI filter and rectification circuitry 1008 may provide rectified AC output signals to two or more channels, including a first channel and a second channel.

[0183] The first channel may include a first channel inductor 1040A, a first channel diode 1050A, a first channel switch 1060A, and a first channel resistor 1036A as shown. In various embodiments, a first channel current (Ich1) 1016A may be determined by the PFC converter controller 1010 based on the known resistance of the first channel resistor 1036A and a sampled voltage at a point between the first channel switch 1060A and the first channel resistor 1036A, as well as the known resistance of the first channel resistor 1036A.

[0184] In various embodiments, the second channel may include a second channel inductor 1040B, a second channel diode 1050B, a second channel switch 1060B, and a second channel resistor 1036B as shown. In various embodiments, a second channel current (Ich2) 1016B may be determined by the PFC converter controller 1010 based on the known resistance of the second channel resistor 1036B and a voltage sampled at a point between the second channel switch 1060B and the second channel resistor 1036B and the known resistance of the second channel resistor 1036B.

[0185] The first channel and the second channel may each be coupled at their respective outputs to one or more capacitors 170. The one or more capacitors 170 may be coupled to the output terminals 104A, 104B.

[0186] The PFC converter controller 1010 can receive multiple signals. For example, the PFC converter controller 1010 can receive an AC voltage input (Vac) signal 1012, a first channel current (Ich1) signal 1016A, a second channel current (Ich2) signal 1016B, a total current (Itot) signal 1019, and a DC voltage (Vbulk) signal 1014. In various embodiments, the total current (Itot) signal 1019 can be measured across a resistor 1038, which can be referred to as a total resistor (Rtot). The PFC converter controller can use the received signals to generate one or more switching signals 1018. In various embodiments, the PFC converter controller can generate the switching signals 1018 directly and / or can utilize the driver circuitry 1090 to generate the switching signals. For example, a first switching signal 1018A can be generated to operate the first channel switch 1060A, and a second switching signal 1018B can be generated to operate the second channel switch 1060B.

[0187] Figure 11 An example graph associated with a PFC converter configured with a dual-channel topology and at least two modes according to one or more embodiments of the present disclosure is illustrated. In various embodiments, a PFC converter (e.g., 1000) can operate in two or more modes. The number of modes can be associated with the number of channels in the PFC converter topology. For example, Figure 11 As shown, various embodiments can operate according to a first mode in which only the first channel is operated, and a second mode in which the first and second channels are operated simultaneously. The operating mode can be associated with the power required by one or more loads. When the required power is below a first threshold (e.g., 2000 W), the PFC converter can operate in the first mode. When the required power is above the first threshold (e.g., 2000 W), the PFC converter can operate in the second mode in which both the first and second channels are operated. As shown, each mode can be associated with a range of power that can be provided at output terminal 104. When the required power may overlap with the range for the first and second modes (e.g., between 1000 W and 2000 W), the PFC converter can operate in either the first or second mode. In various embodiments, when multiple modes are available, selecting which mode to operate in can be associated with operating one or more channels at the highest efficiency (e.g., 220) associated with the channel(s).

[0188] In various embodiments, a first channel can be associated with a first current and a second channel can be associated with a second current, and as described herein (eg, Figure 14A 、 Figure 14B and Figure 14C), the first current and the second current are unbalanced or different. Additionally or alternatively, in various embodiments, the first channel can be associated with the first current and the second channel can be associated with the second current, and the first current and the second current are balanced or different, such as described herein (e.g., Figure 15 ).

[0189] Figure 12 Illustrated are exemplary graphs associated with a PFC converter configured with a dual-channel topology according to one or more embodiments of the present disclosure.

[0190] In various embodiments, the first mode can be associated with operating or enabling the first channel (or the second channel) while the second channel (or the first channel) is not operated or enabled. The operation or enabling of the channel is associated with enabling the switch (e.g., 1060A, 1060B) associated with the corresponding channel. Figure 12 100 , there are multiple curves, including a Vac_in_meas curve 1210, an Iac_meas curve 1220, an Iac_meas curve 1230, and an Idc_out_meas curve 1240. The Vac_in_meas curve 1210 is an example of a measured value, such as a single-phase input voltage at the input circuit device 1002. The Iac_meas curve 1220 is an example of a measured value, such as an AC current measured under the AC voltage input (Vac) signal 1012. The Vdc_out_meas curve 1230 is an example of a measured value, such as a DC output voltage measured between the first output terminal 104A and the second output terminal 104B. The Idc_out_meas curve 1240 is an example of a measured value, such as a DC output voltage measured under the total current (Itot) signal 1019.

[0191] Figure 13 An exemplary graph of current associated with a PFC converter configured with a dual-channel topology operating in a first mode according to one or more embodiments of the present disclosure is illustrated. In various embodiments, the first mode may be associated with operating or enabling the first channel (or the second channel) while the second channel (or the first channel) is not operated or enabled. The operation or enabling of a channel is associated with enabling switches (e.g., 1060A, 1060B) associated with the respective channels. Figure 13 As shown, by operating or enabling switch 1060A between ON and OFF, a first current can be provided to charge and / or discharge capacitor(s) 170. As shown, switch 1060A can be operated to generate first current 1302 by allowing a wave of current to occur during the time period for operating switch 1060A.

[0192] In various embodiments, for example, each of the first and second channels can have a maximum power output of 2000W and a corresponding maximum efficiency point (e.g., 220) when operating at 1500W. When the power required by one or more loads is less than 1500W, the PFC converter having two channels (e.g., 1000) can be operated to operate only the first channel by operating and / or enabling switch 1060A. The first waveform can be, for example, Figure 13 shown.

[0193] 14A to 14C An exemplary graph of current associated with a PFC converter configured with a dual-channel topology operating in a second mode according to one or more embodiments of the present disclosure is illustrated. The first channel and the second channel may be operated simultaneously and each may have a different current. The first channel may have a current of Figure 14A The second channel can have a first current as shown. Figure 14B The second current is shown.

[0194] Figure 14A An exemplary graph of a first current is illustrated. Exemplary graph 1400A illustrates a first current 1402 running continuously. This may be associated with the first switch 1060A being continuously enabled or ON.

[0195] Figure 14B An exemplary graph of the second current is illustrated. Exemplary graph 1400B illustrates discontinuous operation of the second current 1404. This may be associated with the second switch 1060B intermittently switching between ON and OFF.

[0196] Figure 14C An exemplary graph illustrating the sum of the first current and the second current is illustrated.Exemplary graph 1400C illustrates a total current 1406 , which is the sum of the first current 1402 and the second current 1406 .

[0197] When operating in the second mode, the PFC converter (eg, 1000 ) may have a first channel and a second channel, each channel operating at a highest efficiency point (eg, 220 ) associated with the respective channel.

[0198] In various embodiments, a PFC converter (e.g., 1000) can operate according to a second mode, with a first channel operating continuously and a second channel operating intermittently. For example, the load can be between 1500W and 3000W. The first channel can be operated to provide a first current associated with a power of 1500W. The second channel can be operated to provide a second current associated with charging and discharging a capacitor using power associated with supplying a load between 1500W and 3000W. Thus, each channel can operate at maximum efficiency.

[0199] Figure 15 An exemplary graph illustrates currents associated with a PFC converter configured with a dual-channel topology operating in a balanced mode, according to one or more embodiments of the present disclosure. For example, a PFC converter (e.g., 1000) can operate using a first current 1502 associated with a first channel and a second current 1504 associated with a second channel provided in a continuous mode, wherein the first and second channels are balanced. When balanced, each channel shares the same amount of in-phase current (i.e., the currents in each channel are equal). Thus, the total AC current utilized by the PFC converter is illustrated as total current 1506.

[0200] Although a dual-channel topology is described herein, it is understood that more than two channels may be used. For example, a PFC topology may have three or more channels.

[0201] The embodiments of the present disclosure can be implemented in various embodiments. It should be readily understood that the embodiments of the systems, devices, and methods described herein can be configured in various additional and alternative ways beyond those explicitly described herein.

[0202] in conclusion

[0203] The operations and / or functions of the present disclosure have been described herein in such as flowcharts. As will be understood, one or more operations may be computer program instructions, which may be loaded onto a computer or other programmable device (e.g., hardware) to produce a machine so that the resulting computer or other programmable device implements the operations and / or functions described in the flowchart box herein. These computer program instructions may also be stored in a computer-readable memory, which may instruct a computer, processor, or other programmable device to operate and / or run in a particular manner so that the instructions stored in the computer-readable memory produce an article, and the execution of the article implements the operations and / or functions described in the flowchart box. Computer program instructions may also be loaded onto a computer, processor, or other programmable device so that a series of operations performed on a computer, processor, or other programmable device produce a computer-implemented process so that the instructions performed on a computer, processor, or other programmable device provide operations for implementing the functions and / or operations specified in the flowchart box. The flowchart box supports a combination of means for performing specified operations and / or functions, as well as a combination of operations and / or functions for performing specified operations and / or functions. It will be understood that one or more blocks of the flowchart, and combinations of blocks in the flowchart, can be implemented by special-purpose hardware-based computer systems that perform specified operations and / or functions, or combinations of special-purpose hardware and computer instructions.

[0204] Although this specification contains many specific embodiments and implementation details, these should not be interpreted as limitations on the scope of any disclosure or what may be claimed, but rather as descriptions of the features of specific disclosed embodiments. Specific features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although the features described above may be described as working in certain combinations, and even initially claimed as such, in some cases, one or more features in the claimed combination may be removed from the combination, and the claimed combination may point to a sub-combination or a variation of a sub-combination.

[0205] Although operations and / or functions are illustrated in a particular order in the drawings, this should not be understood as requiring that such operations and / or functions be performed in the particular order or sequential order shown, or that all illustrated operations be performed to achieve the desired result. In certain circumstances, it may be advantageous to perform the operations and / or functions in an alternative order. In some cases, the actions recited in the claims can be performed in a different order and still achieve the desired result. Therefore, although specific embodiments of the subject matter have been described, other embodiments are within the scope of the appended claims.

[0206] Although this detailed description has set forth certain embodiments of the invention, the appended claims cover other embodiments of the invention that differ from the described embodiments according to various modifications and improvements.

[0207] In the following claims, unless the specific terms "means for" or "the step of user" are used in a given claim, it is not intended that the claims be interpreted under 35 U.S.C. § 112(6).

Claims

1. A power factor correction converter comprising: an input circuit device for receiving at least an input voltage; an output circuit device, the output circuit device being configured to provide an output voltage; a boost circuit arrangement electrically coupled to the input circuit arrangement and the output circuit arrangement, wherein the boost circuit arrangement includes at least one capacitor; at least one switch, wherein the at least one switch is in the input circuit arrangement or the boost circuit arrangement, wherein the at least one switch is configured to operate in at least two states, the at least two states comprising an on state and an off state, wherein operating in the on state causes the boost circuit arrangement to charge the at least one capacitor, and wherein operating in the off state causes the at least one capacitor to discharge; as well as A power factor correction converter controller is configured to control the at least one switch to change state between the on-state and the off-state at a first ratio, wherein the first ratio is associated with one or more time periods for the on-state and one or more time periods for the off-state, and is also associated with a first efficiency threshold, the first efficiency threshold being associated with the on-state. 2 . The power factor correction converter of claim 1 , wherein the first efficiency threshold is associated with an optimal power factor efficiency.

3. The power factor correction converter of claim 1, wherein the input voltage comprises a single-phase voltage input.

4. The power factor correction converter of claim 1, wherein the input voltage comprises a three-phase voltage input. 5 . The power factor correction converter of claim 1 , wherein the power factor correction converter controller is further configured to determine the first ratio based on a current load associated with the power factor correction converter. 6 . The power factor correction converter of claim 1 , wherein the power factor correction converter controller is further configured to determine the first ratio based on a predicted load. 7 . The power factor correction converter of claim 1 , wherein the power factor correction converter controller is further configured to determine the first ratio based on a load curve.

8. A system comprising: power supply; load; A power factor correction converter, the power factor correction converter comprising: an input circuit arrangement coupled to the power supply and configured to receive an input voltage from the power supply; an output circuit device coupled to the load and configured to provide an output voltage to the load; a boost circuit arrangement electrically coupled to the input circuit arrangement and the output circuit arrangement, wherein the boost circuit arrangement includes at least one capacitor; at least one switch, wherein the at least one switch is in the input circuit arrangement or the boost circuit arrangement, wherein the at least one switch is configured to operate in at least two states, the at least two states comprising an on state and an off state, wherein operating in the on state causes the boost circuit arrangement to charge the at least one capacitor, and wherein operating in the off state causes the at least one capacitor to discharge; and A power factor correction converter controller is configured to control the at least one switch to change state between the on-state and the off-state at a first ratio, wherein the first ratio is associated with one or more time periods for the on-state and one or more time periods for the off-state, and is also associated with a first efficiency threshold, the first efficiency threshold being associated with the on-state.

9. The system of claim 8, wherein the first efficiency threshold is associated with best power factor efficiency.

10. The system of claim 8, wherein the voltage input comprises a single-phase input voltage.

11. The system of claim 8, wherein the voltage input comprises a three-phase input voltage.

12. The system of claim 8, wherein the power factor correction converter controller is further configured to determine the first ratio based on a current load associated with the power factor correction converter.

13. The system of claim 8, wherein the power factor correction converter controller is further configured to determine the first ratio based on a predicted load.

14. The system of claim 8, wherein the power factor correction converter controller is further configured to determine the first ratio based on a load curve.

15. A method comprising: A power factor correction converter is provided, the power factor correction converter comprising an input circuit device, an output circuit device, a boost circuit device, at least one switch, and a power factor correction converter controller, wherein the input circuit device is coupled to a power source, wherein the output circuit device is coupled to a load, wherein the boost circuit device is coupled to the input circuit device and the output circuit device, and wherein the boost circuit device comprises at least one capacitor, wherein the at least one switch is in the input circuit device or the boost circuit device; as well as The at least one switch is operated to change state between an on-state and an off-state based on a first ratio, wherein operation in the on-state causes the boost circuit device to charge the at least one capacitor, and wherein operation in the off-state causes the at least one capacitor to discharge, and wherein the first ratio is associated with one or more time periods for the on-state and one or more time periods for the off-state and is further associated with a first efficiency threshold, the first efficiency threshold being associated with the on-state. The method of claim 15 , wherein the first efficiency threshold is associated with best power factor efficiency. The method of claim 15 , wherein the voltage input comprises a single-phase input voltage. The method of claim 15 , wherein the voltage input comprises a three-phase input voltage.

19. The method according to claim 15, further comprising: The first ratio is determined, with the power factor correction converter controller, based on a current load associated with the power factor correction converter.

20. The method of claim 15, further comprising: The first ratio is determined, with the power factor correction converter controller, based on a load curve.

Images