An ultra-low phase noise low-power common-mode current circulating harmonic class-IV core voltage-controlled oscillator

Abstract

The application discloses a kind of ultra-low phase noise low-power common-mode current circulating harmonic class four nuclear voltage-controlled oscillator, including PMOS tube M1, NMOS tube M2, PMOS tube M3, NMOS tube M4, PMOS tube M5, NMOS tube M6, PMOS tube M7, NMOS tube M8, grid capacitor C G1 、Grid capacitor C G2 、Grid capacitor C G3 、Grid capacitor C G4 、Drain capacitor C D1 、Drain capacitor C D2 、Drain capacitor C D3 、Drain capacitor C D4 、Decoupling capacitor C decap And, inductance L D11 , inductance L D12 , inductance L D21 , inductance L D22 , inductance L D31 , inductance L D32 , inductance L D41 , inductance L D42 Transformer T1 of inductance L G11 , inductance L G12 , inductance L G21 , inductance L G22 , inductance L G31 , inductance L G32 , inductance L G41 , inductance L G42 Transformer T2 of inductance L S11 , inductance L S12 Transformer T3 of inductance L S21 , inductance L S22 Transformer T4 of inductance L S31 , inductance L S32 Transformer T5 of inductance L S41 , inductance L S42 Transformer T6 of inductance L.The application reduces the phase noise generated by voltage-controlled oscillator.

Description

TECHNICAL FIELD

[0001] The present application relates to micro single-chip integrated circuits and microelectronics, in particular to a super low phase noise low power common mode current circulating harmonic class four core voltage controlled oscillator. BACKGROUND

[0002] Voltage controlled oscillator plays an important role in frequency synthesis, modulation and demodulation, signal generation, etc. With the continuous development of wireless communication technology, the application of voltage controlled oscillator in radio frequency and microwave system becomes particularly critical, especially in the fields of modern cellular communication, satellite communication and wireless local area network. Since these applications require higher frequency, lower phase noise and more stable frequency output, the design of voltage controlled oscillator faces higher and higher requirements. Therefore, improving its performance, especially reducing phase noise and improving frequency stability, has become an important research direction in the field of electronic engineering and communication engineering. However, as the operating frequency increases, the quality factor of the passive device and the active device in the oscillator deteriorates rapidly, resulting in the deterioration of the phase noise.

[0003] To optimize the performance of voltage controlled oscillator at high frequency, multi-core class oscillator is proposed, which can continue to improve the phase noise performance on the basis of single-core oscillator. Through the trade-off of power consumption, area and phase noise, theoretically, four-core oscillator can reduce the phase noise by 6dB on the basis of unchanged FOM value. However, the existing multi-core voltage controlled oscillator has various deficiencies: only fixed tail inductance is used to filter the secondary noise current, and there is no clear secondary current path, which cannot reduce the phase noise at low frequency offset in the full frequency range. In addition, in the existing multi-core voltage controlled oscillator mode, due to the characteristics of the secondary current of the transistor from the source to the ground, there is no effective common mode loop circulating measure in the core.

[0004] At high frequency, by taking advantage of the low noise sensitivity of harmonic class oscillator and the phase noise reduction technology of multi-core structure, the phase noise can be further reduced and the overall performance can be optimized. SUMMARY

[0005] The purpose of the present application is to provide a super low phase noise low power common mode current circulating harmonic class four core voltage controlled oscillator.

[0006] The technical solution of the present application is as follows: a super low phase noise low power common mode current circulating harmonic class four core voltage controlled oscillator, comprising PMOS tube M1, NMOS tube M2, PMOS tube M3, NMOS tube M4, PMOS tube M5, NMOS tube M6, PMOS tube M7, NMOS tube M8, gate capacitor C G1 , gate capacitor C G2 , gate capacitor C G3 , gate capacitor C G4, drain capacitor C D1 , drain capacitor C D2 , drain capacitor C D3 , drain capacitor C D4 , decoupling capacitor C decap , and inductor L D11 , inductor L D12 , inductor L D21 , inductor L D22 , inductor L D31 , inductor L D32 , inductor L D41 , inductor L D42 , inductor L G11 , inductor L G12 , inductor L G21 , inductor L G22 , inductor L G31 , inductor L G32 , inductor L G41 , inductor L G42 , inductor L S11 , inductor L S12 , inductor L S21 , inductor L S22 , inductor L S31 , inductor L S32 , inductor L S41 , inductor L S42 , inductor L

[0007] The source of PMOS transistor Ml and the source of NMOS transistor M2 are connected to inductor L S11 and inductor L S12 at one end, and the other end of inductor L S11 and inductor L S12 are connected to power supply VDD potential and 0 potential VSS respectively; the drain of PMOS transistor Ml is connected to the positive pole of inductor L D11 , one end of drain capacitor C D1 , the gate of PMOS transistor Ml is connected to the negative pole of inductor L G22 , one end of gate capacitor C G1 ; the drain of NMOS transistor M2 is connected to the negative pole of inductor L D22 , the other end of drain capacitor C D1 , the gate of NMOS transistor M2 is connected to the other end of gate capacitor C G1 , the positive pole of inductor L G11 , in addition, the negative pole of inductor L D11 is connected to the negative pole of inductor L D12 , and the positive pole of inductor L G22 is connected to the positive pole of inductor L G21the negative pole of the inductor L

[0008] The source of the PMOS transistor M3 is connected to the source of the NMOS transistor M4 and to the inductor L S21 and the inductor L S22 One end of the inductor L S21 and the inductor L S22 The other end is connected to the power supply VDD potential and 0 potential VSS, respectively. The drain of the PMOS transistor M3 is connected to the negative pole of the inductor L D21 , the drain capacitor C D2 One end of the PMOS transistor M3 is connected to the negative pole of the inductor L G12 , the gate capacitor C G2 One end of the NMOS transistor M4 is connected to the positive pole of the inductor L D12 , the other end of the drain capacitor C D2 The gate of the NMOS transistor M4 is connected to the other end of the gate capacitor C G2 , the negative pole of the inductor L G21 In addition, the positive pole of the inductor L D21 is connected to the positive pole of the inductor L D22 The positive pole of the inductor L G12 is connected to the negative pole of the inductor L G11 ;

[0009] The source of the PMOS transistor M5 is connected to the source of the NMOS transistor M6 and to the inductor L S31 and the inductor L S32 One end of the inductor L S31 and the inductor L S32 The other end is connected to the power supply VDD potential and 0 potential VSS, respectively. The drain of the PMOS transistor M5 is connected to the negative pole of the inductor L D42 , the drain capacitor C D3 One end of the PMOS transistor M5 is connected to the positive pole of the inductor L G31 , the gate capacitor C G3 One end of the NMOS transistor M6 is connected to the positive pole of the inductor L D31 , the other end of the drain capacitor C D3 The gate of the NMOS transistor M6 is connected to the other end of the gate capacitor C G3 , the negative pole of the inductor L G42 In addition, the positive pole of the inductor L D42 is connected to the negative pole of the inductor L D41 The negative pole of the inductor L G31 is connected to the positive pole of the inductor L G32 ;

[0010] The source of the PMOS transistor M7 is connected to the source of the NMOS transistor M8 and to the inductor L S41 and the inductor L S42 One end of the inductor L S41and inductor L S42 The other end is connected to the power supply VDD potential and 0 potential VSS respectively; the drain of PMOS transistor M7 is connected to the negative pole of inductor L D32 , one end of drain capacitor C D4 , the gate of PMOS transistor M7 is connected to the positive pole of inductor L G41 , one end of gate capacitor C G4 ; the drain of NMOS transistor M8 is connected to the positive pole of inductor L D41 , the other end of drain capacitor C D4 , the gate of NMOS transistor M8 is connected to the other end of gate capacitor C G4 , the negative pole of inductor L G32 , in addition, the positive pole of inductor L D32 is connected to the negative pole of inductor L D31 , the negative pole of inductor L G41 is connected to the positive pole of inductor L G42 ;

[0011] The four-core voltage-controlled oscillator is connected between VDD potential and VSS potential by using decoupling capacitor C decap .

[0012] Further, the negative pole of inductor L G31 , the positive pole of inductor L G32 , the positive pole of inductor L D32 and the negative pole of inductor L D31 are connected to one side of interconnection line L1, and the negative pole of inductor L G41 , the positive pole of inductor L G42 , the positive pole of inductor L D42 and the negative pole of inductor L D41 are connected to the other side of interconnection line L1; the positive pole of inductor L G12 , the negative pole of inductor L G11 , the positive pole of inductor L D21 and the positive pole of inductor L D22 are connected to one side of interconnection line L2, and the positive pole of inductor L G12 , the negative pole of inductor L G11 , the negative pole of inductor L D11 and the negative pole of inductor L D12 are connected to the other side of interconnection line L2; the interconnection lines L1 and L2 intersect at the center of the four-core voltage-controlled oscillator.

[0013] Further, the inductor L D11 , the inductor L D12 , the inductor L D21 , the inductor L D22 , the inductor L D31 , the inductor L D32 , the inductor L D41 , the inductor L D42The inductance value is equal to L D ;

[0014] Inductor L G11 Inductor L G12 Inductor L G21 Inductor L G22 Inductor L G31 Inductor L G32 Inductor L G41 Inductor L G42 The inductance value is equal to L G ;

[0015] Inductor L s11 Inductor L s21 Inductor L s31 Inductor L s41 The inductance value is equal to L s1 ;

[0016] Inductor L s12 Inductor L s22 Inductor L s32 Inductor L s42 The inductance value is equal to L s2 ;

[0017] Gate capacitance C G1 Gate capacitance C G2 Gate capacitance C G3 Gate capacitance C G4 The capacitance value is equal to C G ;

[0018] Drain capacitance C D1 Drain capacitance C D2 Drain capacitance C D3 Drain capacitance C D4 The capacitance value is equal to C D ;

[0019] Decoupling capacitor C decap The capacitance value is equal to C d ;

[0020] Inductor L G11 With inductor L G31 Inductor L G22 With inductor L G32 Inductor L G12 With inductor L G42 Inductor L G41 With inductor L G21 The coupling coefficient between them is equal to K 12 ;

[0021] Inductor L D11 With inductor L D31 Inductor L D22The coupling coefficient between the inductance L D32 , the inductance L D12 , the inductance L D42 , the inductance L D41 , the inductance L D21 is equal to K 34 ;

[0022] The coupling coefficient between the inductance L G31 , the inductance L D11 , the inductance L G22 , the inductance L D32 , the inductance L G41 , the inductance L D21 , the inductance L G12 , the inductance L D42 is equal to K 23 ;

[0023] The coupling coefficient between the inductance L G11 , the inductance L D11 , the inductance L G21 , the inductance L D21 , the inductance L G32 , the inductance L D32 , the inductance L G42 , the inductance L D42 is equal to K 13 ;

[0024] The coupling coefficient between the inductance L G11 , the inductance L D31 , the inductance L G21 , the inductance L D41 , the inductance L G32 , the inductance L D22 , the inductance L G42 , the inductance L D12 is equal to K 14 ;

[0025] The coupling coefficient between the inductance L G12 , the inductance L D12 , the inductance L G22 , the inductance L D22 , the inductance L G31 , the inductance L D31 , the inductance L G41 , the inductance L D41 is equal to K 24 ;

[0026] The coupling coefficient between the inductance L S11 , the inductance L S12 , the inductance L S21 , the inductance L S22 , the inductance L S31 , the inductance L S32 , the inductance L S41 , the inductance LS42 The coupling coefficient between the gate and the drain is equal to K s .

[0027] Further, the gate capacitor C G1 , the gate capacitor C G2 , the gate capacitor C G3 , the gate capacitor C G4 and the transformer T2 form a differential mode resonant cavity tank of the four-core voltage-controlled oscillator G , the drain capacitor C D1 , the drain capacitor C D2 , the drain capacitor C D3 , the drain capacitor C D4 and the transformer T1 form a common mode resonant cavity tank of the four-core voltage-controlled oscillator D , the differential mode resonant cavity tank G and the common mode resonant cavity tank D together form a differential-common mode integrated resonant cavity of the four-core voltage-controlled oscillator, the decoupling capacitor C decap and the transformer T3, the transformer T4, the transformer T5, and the transformer T6 form an internal decoupling capacitor-inductor resonant cavity of the four-core voltage-controlled oscillator.

[0028] Further, the first resonant point of the differential-common mode integrated resonant cavity is designed at the fundamental frequency of the four-core voltage-controlled oscillator, and the second resonant point of the differential-common mode integrated resonant cavity is designed near the second harmonic of the four-core voltage-controlled oscillator, that is, the input impedance has an impedance peak near the first harmonic, and the input impedance has a second impedance peak near the second harmonic, forming a double-peak impedance.

[0029] Further, the common mode current is injected through the power supply VDD, forming four common mode current circulation loops, wherein:

[0030] The common mode current flows to the source of the PMOS transistor M1 through the decoupling capacitor C decap , and flows out from the drain of the PMOS transistor M1, and flows through the inductor L D11 , the inductor L D12 , the drain capacitor C D2 , the inductor L D21 , the inductor L D22 , the drain capacitor C D1 back to the drain of the PMOS transistor M1, forming a common mode current circulation loop 1;

[0031] The common mode current flows to the source of the PMOS transistor M3 through the decoupling capacitor C decap , and flows out from the drain of the PMOS transistor M3, and flows through the inductor L D21 , the inductor L D22 , the drain capacitor C D1 , the inductor L D11 , the inductor LD12 , drain capacitor C D2 Returning to the drain of PMOS transistor M3, a common-mode current circulation loop 2 is formed;

[0032] The common-mode current passes through decoupling capacitor C decap to the source of PMOS transistor M5 and out of the drain of PMOS transistor M5 and via inductor L D42 , inductor L D41 , drain capacitor C D4 , inductor L D32 , inductor L D31 , drain capacitor C D3 Returning to the drain of PMOS transistor M5, a common-mode current circulation loop 3 is formed;

[0033] The common-mode current passes through decoupling capacitor C decap to the source of PMOS transistor M7 and out of the drain of PMOS transistor M7 and via inductor L D32 , inductor L D31 , drain capacitor C D3 , inductor L D42 , inductor L D41 , drain capacitor C D4 Returning to the drain of PMOS transistor M7, a common-mode current circulation loop 4 is formed;

[0034] Inductor L D11 , inductor L D12 , inductor L D21 , inductor L D22 are respectively coupled to inductor L D31 , inductor L D42 , inductor L D41 , inductor L D32 are mutually enhanced by coupling coefficient K 34 , and synchronize the four common-mode current circulation loops.

[0035] Further, the differential-mode current is injected through power supply VDD, forming four differential-mode current circulation loops, wherein:

[0036] The differential-mode current passes through decoupling capacitor C decap to the source of PMOS transistor M1 and out of the drain of PMOS transistor M1 and via inductor L D11 , inductor L D12 , drain capacitor C D2 , inductor L D21 , inductor L D22 , drain capacitor C D1 Returning to the drain of PMOS transistor M1, a differential-mode current circulation loop 1 is formed;

[0037] The differential-mode current passes through decoupling capacitor C decapflows to the source of the PMOS transistor M3, and flows out from the drain of the PMOS transistor M3, and passes through the inductor L D21 , the inductor L D22 , the drain capacitor C D1 , the inductor L D11 , the inductor L D12 , the drain capacitor C D2 flows back to the drain of the PMOS transistor M3, forming a differential mode current circulation loop 2;

[0038] The differential mode current passes through the decoupling capacitor C decap flows to the source of the PMOS transistor M3, and flows out from the drain of the PMOS transistor M5, and passes through the inductor L D42 , the inductor L D41 , the drain capacitor C D4 , the inductor L D32 , the inductor L D31 , the drain capacitor C D3 flows back to the drain of the PMOS transistor M5, forming a differential mode current circulation loop 3;

[0039] The differential mode current passes through the decoupling capacitor C decap flows to the source of the PMOS transistor M3, and flows out from the drain of the PMOS transistor M7, and passes through the inductor L D32 , the inductor L D31 , the drain capacitor C D3 , the inductor L D42 , the inductor L D41 , the drain capacitor C D4 flows back to the drain of the PMOS transistor M7, forming a differential mode current circulation loop 4;

[0040] The inductor L G11 , the inductor L G21 , the inductor L G12 , the inductor L G22 respectively with the inductor L G31 , the inductor L G42 , the inductor L G41 , the inductor L G32 mutually enhance through the coupling coefficient K 12 , and synchronize the four groups of differential mode current circulation loops.

[0041] Further, the structures of the transformer T1 and the transformer T2 are completely consistent, and both adopt a double-coil toroidal transformer form.

[0042] Further, in order to make the common mode current loop controllable, the inductor L S11 , the inductor L S21 , the inductor L S31 , the inductor L S41 , the inductor L S12 , the inductor L S22 , the inductor LS32 Inductor L S42 A linear inductor is used, wherein the inductance L S11 With inductor L S12 Overlapping arrangement, inductor L S21 With inductor L S22 Overlapping arrangement, inductor L S31 With inductor L S32 Overlapping arrangement, inductor L S41 With inductor L S42 Arranged in an overlapping manner.

[0043] Furthermore, the design process is as follows:

[0044] Step 1: Optimize at the required frequency according to the voltage-controlled oscillator. Determine the fundamental frequency parameters, and then determine the inductance L. G11 Inductor L G12 Inductor L G21 Inductor L G22 Inductor L G31 Inductor L G32 Inductor L G41 Inductor L G42 The value of L G and gate capacitance C G1 Gate capacitance C G2 Gate capacitance C G3 Gate capacitance C G4 The capacitance value C G ;

[0045] Sensitivity L G Capacity C G With oscillation frequency The relationship is:

[0046]

[0047] Step 2: According to the second harmonic frequency required by the voltage-controlled oscillator. Determine the second harmonic parameters, and then determine the inductance L. D11 Inductor L D12 Inductor L D21 Inductor L D22 Inductor L D31 Inductor L D32 Inductor L D41 The value of L D Drain capacitance C D1 Drain capacitance C D2 Drain capacitance C D3 Drain capacitance C D4 The capacitance value C D ;

[0048] Inductance L D Capacitance C D Relationship with the second harmonic frequency

[0049]

[0050] Step 3, Adjusting inductance L G11 Inductance L D11 Inductance L G21 Inductance L D21 Inductance L G32 Inductance L D32 Inductance L G42 Inductance L D42 Coupling coefficient K 13 Inductance L G12 Inductance L D12 Inductance L G22 Inductance L D22 Inductance L G31 Inductance L D31 Inductance L G41 Inductance L D41 Coupling coefficient K 24 Simulate the primary fundamental and secondary harmonic impedance to determine inductance L G11 Inductance L G12 Inductance L G21 Inductance L G22 Inductance L G31 Inductance L G32 Inductance L G41 Inductance L G42 Gate capacitance C G1 Gate capacitance C G2 Gate capacitance C G3 Gate capacitance C G4 Frequency at which the peak impedance of the differential mode path resonant tank tank G Inductance L D11 Inductance L D12 Inductance L D21 Inductance L D22 Inductance L D31 Inductance L D32 Inductance L D41 Drain capacitance C D1 Drain capacitance C D2 Drain capacitance C D3 Drain capacitance C D4 Frequency at which the peak impedance of the common mode path resonant tank tank D ;

[0051] ​​​The relationship between is:

[0052]

[0053] Step 4, adjust the inductance L G11 The inductance L G31 , the inductance L G12 The inductance L G42 , the inductance L G21 The inductance L G41 , the inductance L G22 The inductance L G32 , the inductance L D11 The inductance L D31 , the inductance L D12 The inductance L D42 , the inductance L D21 The inductance L D41 , the inductance L D22 The inductance L D32 The distance between each other to 3um, determine the inductance L G11 The inductance L G31 , the inductance L G22 The inductance L G32 , the inductance L G12 The inductance L G42 , the inductance L G41 The inductance L G21 The coupling coefficient K 12 between each other; and the inductance L D11 The inductance L D31 , the inductance L D22 The inductance L D32 , the inductance L D12 The inductance L D42 The inductance L D41 The inductance L D21 The coupling coefficient K 34 , the coupling coefficient K 13 , the coupling coefficient K 24 is determined, so as to determine the coupling coefficient K 23 and the coupling coefficient K 14 synchronously;

[0054] Step 5, set the inductance value L s11 , the inductance L s21 , the inductance L s31 , the inductance L s41 , and the inductance value L s1 , the inductance L s12 , the inductance L s22 , the inductance L s32 , the inductance L s42 , and the inductance value L s2To avoid its influence on the fundamental oscillation, the size of the decoupling capacitor is adjusted so that the resonant cavity peak impedance frequency is far less than the oscillation frequency , ,

[0055] The condition to be met is:

[0056]

[0057] Step 6, according to steps 1 to 5, build a four-core voltage-controlled oscillator.

[0058] Compared with the prior art, the present application has the following advantages:

[0059] (1) A differential common mode integrated resonant cavity four-core voltage-controlled oscillator is designed, which innovatively makes the resonant cavity differential mode and common mode loop of the multi-core voltage-controlled oscillator consistent, and makes the common mode current loop circulate, thereby enhancing the secondary common mode resonant impedance, reducing the transformation of current thermal noise and flicker noise into high-frequency phase noise;

[0060] (2) The high-order resonant cavity composed of transformer T1, transformer T2, gate capacitor C G1 , gate capacitor C G2 , gate capacitor C G3 , gate capacitor C G4 , drain capacitor C D1 , drain capacitor C D2 , drain capacitor C D3 , drain capacitor C D4 , realizes the Class-F -1 oscillator structure of multi-core, and at the same time generates a high input impedance peak near the secondary frequency, realizes the input impedance enhancement of the second harmonic, realizes the Class-F -1 operation to reduce the influence of the resonant cavity on the unbalanced parasitic capacitance and inductance;

[0061] (3) The four-core voltage-controlled oscillator internal decoupling capacitor inductance resonant cavity composed of decoupling capacitor C decap , transformer T3, transformer T4, transformer T5 and transformer T6 realizes controllable current return path, and provides partial noise cancellation effect to reduce the deterioration of flicker noise on phase noise;

[0062] (4) Due to the adoption of the ring inductance structure, the inductance loss is reduced, and compared with the traditional octagonal inductance, the quality factor has the characteristics of high quality factor, and the quality factor can be improved to twice of the traditional inductance, which greatly improves the overall noise and power consumption performance;

[0063] (5) The resonant cavity based on the transformers T1 and T2 has larger passive gain than the resonant cavity based on inductance, the increase of the oscillation amplitude finally has great improvement on the phase noise, meanwhile, the intermediate tap from the power supply to the ground is avoided, and the mode ambiguity problem of the multi-core oscillator is eliminated;

[0064] (6) The resonant cavity based on the transformers T1 and T2 increases the inductance inductance by using the double-loop inductance structure, effectively reduces the oscillator power consumption, and enhances the inductance quality factor by the double-loop close coupling, and improves the utilization rate of the chip area. BRIEF DESCRIPTION OF DRAWINGS

[0065] Figure 1 It is the overall circuit structure schematic diagram of the super low phase noise low power consumption common mode current circulation harmonic type four-core voltage controlled oscillator of the application, and the part in the dashed box is the single core CORE#1 part of the four-core voltage controlled oscillator;

[0066] Figure 2 It is the transformer structure schematic diagram of the application;

[0067] Figure 3 It is the resonant cavity difference common mode integrated input impedance simulation result of the application;

[0068] Figure 4 It is the design flow chart of the super low phase noise low power consumption common mode current circulation harmonic type four-core voltage controlled oscillator of the application;

[0069] Figure 5 It is the schematic diagram of the linear inductor overlapped arrangement up and down;

[0070] Figure 6 It is the single core circuit CORE#X complete principle diagram of the super low phase noise low power consumption common mode current circulation harmonic type four-core voltage controlled oscillator of the application;

[0071] Figure 7 It is the frequency regulation range curve of the super low phase noise low power consumption common mode current circulation harmonic type four-core voltage controlled oscillator of the application;

[0072] Figure 8 It is the phase noise change curve with frequency of the super low phase noise low power consumption common mode current circulation harmonic type four-core voltage controlled oscillator of the application under 100KHz, 1MHz and 10MHz frequency offset;

[0073] Figure 9 It is the pulse sensitivity function, noise modulation function and effective pulse sensitivity function diagram of the super low phase noise low power consumption common mode current circulation harmonic type four-core voltage controlled oscillator of the application;

[0074] Figure 10 It is the chip real object diagram of the super low phase noise low power consumption common mode current circulation harmonic type four-core voltage controlled oscillator of the application. DETAILED DESCRIPTION

[0075] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the drawings and embodiments. It should be understood that the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the protection scope of the present application.

[0076] The present application is a kind of ultra-low phase noise low-power common-mode current circulating harmonic class four core voltage-controlled oscillator, including PMOS tube M1, NMOS tube M2, PMOS tube M3, NMOS tube M4, PMOS tube M5, NMOS tube M6, PMOS tube M7, NMOS tube M8, gate capacitor C G1 , gate capacitor C G2 , gate capacitor C G3 , gate capacitor C G4 , drain capacitor C D1 , drain capacitor C D2 , drain capacitor C D3 , drain capacitor C D4 , decoupling capacitor C decap , and inductor L D11 , inductor L D12 , inductor L D21 , inductor L D22 , inductor L D31 , inductor L D32 , inductor L D41 , inductor L D42 Transformer T1 composed of inductor L G11 , inductor L G12 , inductor L G21 , inductor L G22 , inductor L G31 , inductor L G32 , inductor L G41 , inductor L G42 Transformer T2 composed of inductor L S11 , inductor L S12 Transformer T3 composed of inductor L S21 , inductor L S22 Transformer T4 composed of inductor L S31 , inductor L S32 Transformer T5 composed of inductor L S41 , inductor L S42 Transformer T6 composed of inductor L Figure 1

[0077] ​The source of the PMOS transistor M1 and the source of the NMOS transistor M2 are connected to the inductor L S11 and the inductor L S12 One end of the inductor L S11 and the inductor L S12 The other end is connected to the power supply VDD potential and 0 potential VSS respectively; the drain of the PMOS transistor M1 is connected to the positive electrode of the inductor L D11 , one end of the drain capacitor C D1 , the gate of the PMOS transistor M1 is connected to the negative electrode of the inductor L G22 , one end of the gate capacitor C G1 ; the drain of the NMOS transistor M2 is connected to the negative electrode of the inductor L D22 , the other end of the drain capacitor C D1 , the gate of the NMOS transistor M2 is connected to the other end of the gate capacitor C G1 , the positive electrode of the inductor L G11 In addition, the negative electrode of the inductor L D11 is connected to the negative electrode of the inductor L D12 , the positive electrode of the inductor L G22 is connected to the negative electrode of the inductor L G21 ;

[0078] The source of the PMOS transistor M3 and the source of the NMOS transistor M4 are connected to the inductor L S21 and the inductor L S22 One end of the inductor L S21 and the inductor L S22 The other end is connected to the power supply VDD potential and 0 potential VSS respectively; the drain of the PMOS transistor M3 is connected to the negative electrode of the inductor L D21 , one end of the drain capacitor C D2 , the gate of the PMOS transistor M3 is connected to the negative electrode of the inductor L G12 , one end of the gate capacitor C G2 ; the drain of the NMOS transistor M4 is connected to the positive electrode of the inductor L D12 , the other end of the drain capacitor C D2 , the gate of the NMOS transistor M4 is connected to the other end of the gate capacitor C G2 , the positive electrode of the inductor L G21 In addition, the positive electrode of the inductor L D21 is connected to the positive electrode of the inductor L D22 , the positive electrode of the inductor L G12 is connected to the negative electrode of the inductor L G11 ;

[0079] The source of the PMOS transistor M5 and the source of the NMOS transistor M6 are connected to the inductor L S31 and the inductor L S32 One end of the inductor L S31 and the inductor L S32The other end is connected to the power supply VDD potential and 0 potential VSS respectively; the drain of PMOS transistor M5 is connected to the negative pole of inductor L D42 , one end of drain capacitor C D3 , the gate of PMOS transistor M5 is connected to the positive pole of inductor L G31 , one end of gate capacitor C G3 ; the drain of NMOS transistor M6 is connected to the positive pole of inductor L D31 , the other end of drain capacitor C D3 , the gate of NMOS transistor M6 is connected to the other end of gate capacitor C G3 , the negative pole of inductor L G42 ; in addition, the positive pole of inductor L D42 is connected to the negative pole of inductor L D41 , the negative pole of inductor L G31 is connected to the positive pole of inductor L G32 ;

[0080] The source of PMOS transistor M7 is connected to the source of NMOS transistor M8, and is connected to one end of inductor L S41 and inductor L S42 ; the other end of inductor L S41 and inductor L S42 is connected to the power supply VDD potential and 0 potential VSS respectively; the drain of PMOS transistor M7 is connected to the negative pole of inductor L D32 , one end of drain capacitor C D4 , the gate of PMOS transistor M7 is connected to the positive pole of inductor L G41 , one end of gate capacitor C G4 ; the drain of NMOS transistor M8 is connected to the positive pole of inductor L D41 , the other end of drain capacitor C D4 , the gate of NMOS transistor M8 is connected to the other end of gate capacitor C G4 , the negative pole of inductor L G32 ; in addition, the positive pole of inductor L D32 is connected to the negative pole of inductor L D31 , the negative pole of inductor L G41 is connected to the positive pole of inductor L G42 ; the four-core voltage-controlled oscillator is connected between the VDD potential and the VSS potential by using a decoupling capacitor C decap .

[0081] The negative pole of inductor L G31 , the positive pole of inductor L G32 , the positive pole of inductor L D32 , and the negative pole of inductor L D31 are connected to one side of interconnection line L1, and the other side of interconnection line L1 is connected to the negative pole of inductor L G41 , the positive pole of inductor L G42 , the positive pole of inductor L D42The positive terminal and inductor L D41 The negative terminal; inductor L G12 Positive electrode, inductor L G11 negative electrode, inductor L D21 The positive terminal and inductor L D22 The positive terminal is connected to one side of interconnect L2, and the other side of interconnect L2 is connected to inductor L. G12 Positive electrode, inductor L G11 negative electrode, inductor L D11 The negative electrode and inductor L D12 The negative terminal; interconnects L1 and L2 intersect at the center of the quad-core voltage-controlled oscillator.

[0082] like Figure 1 As shown, inductor L G11 With inductor L G31 Inductor L G22 With inductor L G32 Inductor L G12 With inductor L G42 Inductor L G41 With inductor L G21 The coupling coefficient between them is equal to K 12 ;

[0083] Inductor L D11 With inductor L D31 Inductor L D22 With inductor L D32 Inductor L D12 With inductor L D42 Inductor L D41 With inductor L D21 The coupling coefficient between them is equal to K 34 ;

[0084] Inductor L G31 With inductor L D11 Inductor L G22 With inductor L D32 Inductor L G41 With inductor L D21 Inductor L G12 With inductor L D42 The coupling coefficient between them is equal to K 23 ;

[0085] Inductor L G11 With inductor L D11 Inductor L G21 With inductor L D21 Inductor L G32 With inductor L D32 Inductor L G42 With inductor L D42 The coupling coefficient between them is equal to K 13 ;

[0086] Inductance L G11 Inductance L D31 Inductance L G21 Inductance L D41 Inductance L G32 Inductance L D22 Inductance L G42 Inductance L D12 The coupling coefficient between Inductance L 14 ;

[0087] Inductance L G12 Inductance L D12 Inductance L G22 Inductance L D22 Inductance L G31 Inductance L D31 Inductance L G41 Inductance L D41 The coupling coefficient between Inductance L 24 ;

[0088] Inductance L S11 Inductance L S12 Inductance L S21 Inductance L S22 Inductance L S31 Inductance L S32 Inductance L S41 Inductance L S42 The coupling coefficient between Inductance L s .

[0089] As Figure 2 shown in the schematic diagram of the transformer structure of the present application, Inductance L G11 Inductance L G12 Inductance L G21 Inductance L G22 Inductance L G31 Inductance L G32 Inductance L G41 Inductance L G42 Inductance L D11 Inductance L D12 Inductance L D21 Inductance L D22 Inductance L D31 Inductance L D32 Inductance L D41 Inductance L D42 Inductance L s11 Inductance L s21 Inductance L s31 Inductance L s41 Inductance L s12 Inductance L s22 Inductance L s32 Inductance Ls42 Metal AP and M8 layer are used respectively, and interconnection lines L1 and L2 use metal M7 layer. Gate capacitor C G1 , gate capacitor C G2 , gate capacitor C G3 , gate capacitor C G4 and transformer T2 form a differential mode resonant cavity tank of the four-core voltage-controlled oscillator G , drain capacitor C D1 , drain capacitor C D2 , drain capacitor C D3 , drain capacitor C D4 and transformer T1 form a common mode resonant cavity tank of the four-core voltage-controlled oscillator D , differential mode resonant cavity tank G and common mode resonant cavity tank D together form a differential common mode integrated resonant cavity of the four-core voltage-controlled oscillator, decoupling capacitor C decap and transformers T3, T4, T5 and T6 form an internal decoupling capacitor inductor resonant cavity of the four-core voltage-controlled oscillator.

[0090] As shown in Figure 5 , a single set of upper and lower overlapping linear inductors is shown. Inductor L S11 , inductor L S21 , inductor L S31 , inductor L S41 , inductor L S12 , inductor L S22 , inductor L S32 , inductor L S42 uses linear inductor, wherein inductor L S11 and inductor L S12 are arranged in an upper and lower overlapping manner, inductor L S21 and inductor L S22 are arranged in an upper and lower overlapping manner, inductor L S31 and inductor L S32 are arranged in an upper and lower overlapping manner, inductor L S41 and inductor L S42 are arranged in an upper and lower overlapping manner.

[0091] Inductor L S11 , inductor L S21 , inductor L S31 , inductor L S41 is connected to the source end of PMOS tube M1, PMOS tube M3, PMOS tube M5 and PMOS tube M7 respectively, and the other end is connected to VDD potential, inductor L S12 , inductor L S22 , inductor L S32 , inductor L S42One end is connected to the source terminals of NMOS transistors M2, M4, M6, and M8 respectively, and the other end is connected to the VSS potential.

[0092] The working mode and performance of the ultra-low noise, low power consumption common-mode current cyclic quad-core harmonic voltage-controlled oscillator proposed in this invention will be analyzed next.

[0093] To further clarify the internal structure of the circuit core and analyze its equivalent operating mode, only the following is taken: Figure 1 The section within the dashed box will be used to illustrate this, such as... Figure 6 As shown, current is injected from the power supply VDD, and the PMOS transistor M... P NMOS transistor M N It starts working as an equivalent negative resistance unit, serving as the differential mode resonant cavity tank. G With common-mode resonant cavity tank D Power is supplied to compensate for losses caused by the non-ideal resonant cavity. Among these, the differential-mode resonant cavity tank... G Provides a fundamental oscillation, common-mode resonant cavity tank D With a primary fundamental frequency load, a secondary harmonic carrier is provided to achieve waveform shaping.

[0094] In addition, to extend the frequency tuning range, besides the gate capacitance C G1 Gate capacitance C G2 Gate capacitance C G3 Gate capacitance C G4 In addition, a gate four-bit differential switched capacitor array C is designed. G_BANK and differential connection type of variable capacitance tube C G_VAR Except for the drain capacitance C D1 Drain capacitance C D2 Drain capacitance C D3 Drain capacitance C D4 In addition, a four-position differential switched capacitor array C with drain is designed. D_BANK This is to achieve the change in the peak impedance of the resonant cavity mentioned above, thereby achieving the change in frequency.

[0095] The reason for the equivalent decrease in phase noise is:

[0096] The drain current of the PMOS tube M1, the PMOS tube M3, the PMOS tube M5, the PMOS tube M7 and the NMOS tube M2, the NMOS tube M4, the NMOS tube M6, the NMOS tube M8 varies with the gate voltage, when the gate voltage of the PMOS tube M1, the PMOS tube M3, the PMOS tube M5, the PMOS tube M7 rises, the gate voltage of the NMOS tube M2, the NMOS tube M4, the NMOS tube M6, the NMOS tube M8 reversely decreases due to the coupling of the resonant cavity, so that the PMOS tube M1, the PMOS tube M3, the PMOS tube M5, the PMOS tube M7 and the NMOS tube M2, the NMOS tube M4, the NMOS tube M6, the NMOS tube M8 are simultaneously turned off, at this time, the circuit works in the resonant cavity resonance, no current flows out of the resonant cavity, and the voltage oscillates in a sinusoidal state; at the same time, the current noise NMF is equivalent to 0, and the noise transfer function ISF increases. The phase noise L is calculated by the ISF function:

[0097] , is a normalized ISF function, is a transistor current noise, k is a constant variable related to the frequency offset, it can be found that, due to the simultaneous turn-off of the PMOS tube M1, the PMOS tube M3, the PMOS tube M5, the PMOS tube M7 and the NMOS tube M2, the NMOS tube M4, the NMOS tube M6, the NMOS tube M8, the ISF function increases while the transistor noise tends to 0, at this time, the phase noise equivalently decreases. As shown in Figure 9

[0098] When the gate voltage of the NMOS tube M2, the NMOS tube M4, the NMOS tube M6, the NMOS tube M8 rises, the gate voltage of the PMOS tube M1, the PMOS tube M3, the PMOS tube M5, the PMOS tube M7 reversely decreases due to the coupling of the resonant cavity, so that the PMOS tube M1, the PMOS tube M3, the PMOS tube M5, the PMOS tube M7 and the NMOS tube M2, the NMOS tube M4, the NMOS tube M6, the NMOS tube M8 are simultaneously turned on, at this time, the circuit works in the resonant cavity resonance, the current flows from the power supply to the ground, and the voltage oscillates in an explicit common mode state; at the same time, the current noise NMF gradually increases, while the noise transfer function ISF tends to 0, it can be found that, due to the simultaneous turn-on of the PMOS tube M1, the PMOS tube M3, the PMOS tube M5, the PMOS tube M7 and the NMOS tube M2, the NMOS tube M4, the NMOS tube M6, the NMOS tube M8, the transistor noise increases, while the ISF function gradually tends to 0, at this time, the phase noise equivalently decreases.

[0099] The specific working voltage changes as follows:

[0100] ​The gate input voltages of PMOS transistors M1, M3, M5, and M7 are achieved through transformers T1 and T2. The gate input voltages of NMOS transistors M2, M4, M6, and M8 are also achieved through transformers T1 and T2. PMOS transistors M1, M3, M5, and M7, and NMOS transistors M2, M4, M6, and M8 are simultaneously turned on and off. Within half an oscillation cycle, when the drains of PMOS transistors M1, M3, M5, and M7 are at high potentials, the gates of PMOS transistors M1, M3, M5, and M7 are at low potentials due to transformers T1 and T2; when the drains of NMOS transistors M2, M4, M6, and M8 are at high potentials, the gates of NMOS transistors M2, M4, M6, and M8 are at low potentials due to transformers T1 and T2. Within half an oscillation cycle, when the drains of PMOS transistors M1, M3, M5, and M7 are at low potentials, the gates of PMOS transistors M1, M3, M5, and M7 are at high potentials due to transformers T1 and T2; when the drains of NMOS transistors M2, M4, M6, and M8 are at low potentials, the gates of NMOS transistors M2, M4, M6, and M8 are at high potentials due to transformers T1 and T2.

[0101] The specific design steps of an ultra-low phase noise, low power consumption common-mode current cyclic harmonic quad-core voltage-controlled oscillator are as follows: Figure 4 As shown:

[0102] Step 1: Optimize at the required frequency according to the voltage-controlled oscillator. Determine the fundamental frequency parameters, and then determine the inductance L. G11 Inductor L G12 Inductor L G21 Inductor L G22 Inductor L G31 Inductor L G32 Inductor L G41 Inductor L G42 The value of L G and gate capacitance C G1 Gate capacitance C G2 Gate capacitance C G3 Gate capacitance C G4 The capacitance value C G ;

[0103] Sensitivity LG , the capacitance C G and the oscillation frequency is:

[0104]

[0105] Step 2, determine the second harmonic parameters according to the requirements of the voltage-controlled oscillator , and then determine the inductance L D11 , the inductance L D12 , the inductance L D21 , the inductance L D22 , the inductance L D31 , the inductance L D32 , the inductance L D41 , the inductance L D , the drain capacitance C D1 , the drain capacitance C D2 , the drain capacitance C D3 , the drain capacitance C D4 , the capacitance C D ;

[0106] , the inductance L D , the capacitance C D and the second harmonic frequency is:

[0107]

[0108] Step 3, adjust the inductance L G11 , the inductance L D11 , the inductance L G21 , the inductance L D21 , the inductance L G32 , the inductance L D32 , the inductance L G42 , the inductance L D42 , the coupling coefficient K 13 between the inductance L G12 , the inductance L D12 , the inductance L G22 , the inductance L D22 , the inductance L G31 , the inductance L D31 , the inductance L G41 , the inductance L D41 , the inductance L 24 , the coupling coefficient K G11 , the inductance L G12 , the inductance L G21 , the inductance L G22 , the inductance L G31 , the inductance L G32 , the inductance L G41 , the inductance LG42 with gate capacitance C G1 , gate capacitance C G2 , gate capacitance C G3 , gate capacitance C G4 of the differential mode path resonant tank tank G at which the peak impedance of the differential mode path resonant tank tank with inductance L D11 , inductance L D12 , inductance L D21 , inductance L D22 , inductance L D31 , inductance L D32 , inductance L D41 with drain capacitance C D1 , drain capacitance C D2 , drain capacitance C D3 , drain capacitance C D4 of the common mode path resonant tank tank D at which the peak impedance of the common mode path resonant tank tank

[0109] with is related as:

[0110]

[0111] Step 4, adjusting inductance L G11 with inductance L G31 , inductance L G12 with inductance L G42 , inductance L G21 with inductance L G41 , inductance L G22 with inductance L G32 , inductance L D11 with inductance L D31 , inductance L D12 with inductance L D42 , inductance L D21 with inductance L D41 , inductance L D22 with inductance L D32 to 3um, determining the coupling coefficient K G11 between inductance L G31 , inductance L G22 with inductance L G32 , inductance L G12 with inductance L G42 , inductance L G41 with inductance L G21 ; and inductance L 12 with inductance L D11 , inductance L D31 , inductance L D22 ​With inductor L D32 Inductor L D12 With inductor L D42 Inductor L D41 With inductor L D21 The coupling coefficient K between 34 Furthermore, due to K 13 K 24 K is determined, thus K is determined synchronously. 23 With K 14 ;

[0112] Step 5: Set the inductor L s11 Inductor L s21 Inductor L s31 Inductor L s41 inductance value L s1 and inductor L s12 Inductor L s22 Inductor L s32 Inductor L s42 inductance value L s2 To avoid its impact on the fundamental oscillation, the decoupling capacitor was adjusted. The size of this value ensures that the peak impedance frequency of the resonant cavity is much smaller than the oscillation frequency. ,

[0113] The conditions to be met are:

[0114]

[0115] Step 6: Based on steps 1 to 5, build a quad-core voltage-controlled oscillator.

[0116] Example

[0117] To verify the effectiveness of the present invention, the following experimental design was conducted.

[0118] The following section details the design process:

[0119] Determine the inductance value L D11 L D21 L D31 L D41 L G12 L G22 L G32 L G42 L S11 L S12 L S21 L S22 L S31 L S32 L S41 L S42 With capacitance value C D1 CD2 C D3 C D4 C G1 C G2 C G3 C G4 C decap Size, as described above, is L D L G C D C G C d L S1 L S2 Coupling coefficient K in transformers T1 and T2 13 K 24 K 23 K 12 K 34 K 14 In addition, determine the decoupling capacitor C. decap Quantity values, coupling coefficient K s The value is chosen to reduce the area; here, the decoupling capacitor C... decap The quantity is set to 4. Furthermore, to ensure design integrity, the gate four-bit differential switched capacitor array C is determined. G_BANK With drain four-position differential switched capacitor array C D_BANK The range of values ​​C G_tank With C D_tank The specific values ​​are shown in Table 1:

[0120] Table 1. Values ​​of key oscillator parameters

[0121]

[0122] In this embodiment, achieved by the above parameters, the fundamental frequency f of the ultra-low phase noise, low power common-mode cyclic harmonic quad-core voltage-controlled oscillator proposed in this invention at its lowest frequency is [value missing]. 0,min The peak impedance at point 2f and the second harmonic frequency 0,min The impedance peak at the highest frequency and the fundamental frequency f at the highest frequency. 0,max The peak impedance at point 2f and the second harmonic frequency 0,max The peak impedance at the point is as follows Figure 3 As shown. Because the resonant cavity composed of the transformer and capacitor has high-order characteristics, it can generate two resonant points. The first resonant point of the differential-mode resonant cavity is designed at the fundamental frequency f of the oscillator. 0,min -f 0,max The second resonant point is designed at the second frequency 2f of the oscillator. 0,min -2f 0,maxNearby position. Input impedance image is consistent with the design requirement of differential common mode integrated resonant cavity input impedance in the design process described above, and simulation experiment proves that the application greatly improves the effect of improving input impedance near the second frequency.

[0123] According to the inductance value, the capacitance value and the coupling coefficient, an inductance layout and a capacitance layout as shown in Figure 2 are drawn, and post-simulation is performed, and the specific steps are shown in a flow chart. Figure 4

[0124] The necessary performance data of the embodiment are shown in Figure 7 , 8 , 9, including a frequency tuning range, a phase noise and an impulse sensitivity function (ISF), a noise modulation function (NMF) and an effective impulse sensitivity function (ISF ,eff ), which are further described below:

[0125] The frequency adjustment range realized by the embodiment is shown in Figure 7 , and the frequency adjustment range curve from 14.3 GHz to 17.9 GHz can be realized by designing a switch capacitor array C G_BANK , C D_BANK and a varactor C G_VAR in the core as shown in Figure 6 .

[0126] Figure 8 The phase noise curves of the super-low phase noise and low-power common-mode current circulation harmonic four-core voltage-controlled oscillator provided by the embodiment of the application at 100 kHz, 1 MHz and 10 MHz frequency offsets are shown. By making the NMOS and PMOS tubes on and off in the multi-core state, the phase noise performance of the oscillator is optimized from multiple aspects such as inductance loss and noise conversion to phase noise. At 100 kHz frequency offset, the minimum phase noise can reach -101.9 dBc / Hz, at 1 MHz frequency offset, the minimum phase noise is -122.1 dBc / Hz, and at 10 MHz frequency offset, the minimum phase noise is -142.1 dBc / Hz.

[0127] Figure 9 The impulse sensitivity function (ISF), the noise modulation function (NMF) and the effective impulse sensitivity function (ISF eff ) of the super-low phase noise and low-power common-mode current circulation harmonic four-core voltage-controlled oscillator provided by the embodiment of the application are shown. Through the design of the second harmonic resonance, the ISF ,eff curve obtained by multiplying the ISF and the NMF has a large number of 0 areas, representing that part of the noise is not converted into phase noise due to the on and off of the transistor; the ISF ,eff ​The integral value of the phase noise tends to 0, which represents that the influence of the partial flicker noise on the phase noise is eliminated due to the design of the secondary harmonic resonant loop.

[0128] Figure 10 A chip physical map of the super-low phase noise low-power common-mode current circulating harmonic four-core-like voltage-controlled oscillator provided by the embodiment of the present application is shown in the figure. 2 .

[0129] The technical features of the above embodiments can be combined in any manner, and to make the description concise, all possible combinations of the technical features in the above embodiments are not described, but as long as the combinations of the technical features do not exist, they should be considered as the scope of the present application.

[0130] The above embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the present application. It should be pointed out that, for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A quad-core voltage-controlled oscillator with ultra-low phase noise, low power consumption, and common-mode current cyclic harmonics, characterized in that... Includes PMOS transistors M1, M2, M3, M4, M5, M6, M7, and M8, and gate capacitor C. G1 Gate capacitance C G2 Gate capacitance C G3 Gate capacitance C G4 Drain capacitance C D1 Drain capacitance C D2 Drain capacitance C D3 Drain capacitance C D4 Decoupling capacitor C decap And, inductor L D11 Inductor L D12 Inductor L D21 Inductor L D22 Inductor L D31 Inductor L D32 Inductor L D41 Inductor L D42 The transformer T1 is composed of an inductor L. G11 Inductor L G12 Inductor L G21 Inductor L G22 Inductor L G31 Inductor L G32 Inductor L G41 Inductor L G42 The transformer T2 consists of an inductor L. S11 Inductor L S12 The transformer T3 consists of an inductor L. S21 Inductor L S22 The transformer T4 is composed of an inductor L. S31 Inductor L S32 The transformer T5 consists of an inductor L. S41 Inductor L S42 The transformer T6 consists of: The sources of PMOS transistor M1 and NMOS transistor M2 are connected to inductor L. S11 and inductor L S12 One end, inductor L S11 and inductor L S12 The other end is connected to the power supply potential VDD and the 0 potential VSS respectively; the drain of PMOS transistor M1 is connected to the inductor L. D11 The positive and drain capacitance C D1 One end is connected, and the gate of PMOS transistor M1 is connected to inductor L. G22 negative electrode, gate capacitance C G1 One end is connected; the drain of NMOS transistor M2 is connected to inductor L. D22 The negative and drain capacitance C D1 The other end is connected, and the gate of NMOS transistor M2 is connected to the gate capacitance C. G1 At the other end, inductor L G11 The positive terminal is connected, and in addition, the inductor L D11 negative terminal and inductor L D12 The negative terminal is connected, and the inductor L G22 The positive terminal and the inductor L G21 The negative terminal is connected; The source of PMOS transistor M3 and the source of NMOS transistor M4 are connected to inductor L. S21 and inductor L S22 One end, inductor L S21 and inductor L S22 The other end is connected to the power supply potential VDD and the 0 potential VSS respectively; the drain of PMOS transistor M3 is connected to the inductor L. D21 The negative and drain capacitance C D2 One end is connected, and the gate of PMOS transistor M3 is connected to inductor L. G12 negative electrode, gate capacitance C G2 One end is connected; the drain of NMOS transistor M4 is connected to inductor L. D12 The positive and drain capacitance C D2 The other end is connected, and the gate of NMOS transistor M4 is connected to the gate capacitance C. G2 At the other end, inductor L G21 The positive terminal is connected, and in addition, the inductor L D21 The positive terminal and the inductor L D22 The positive terminal is connected, and the inductor L G12 The positive terminal and the inductor L G11 The negative terminal is connected; The source of PMOS transistor M5 and the source of NMOS transistor M6 are connected to inductor L. S31 and inductor L S32 One end, inductor L S31 and inductor L S32 The other end is connected to the power supply potential VDD and the 0 potential VSS respectively; the drain of PMOS transistor M5 is connected to inductor L. D42 The negative and drain capacitance C D3 One end is connected, and the gate of PMOS transistor M5 is connected to inductor L. G31 The positive electrode and gate capacitance C G3 One end is connected; the drain of NMOS transistor M6 is connected to inductor L. D31 The positive and drain capacitance C D3 The other end is connected, and the gate of NMOS transistor M6 is connected to the gate capacitance C. G3 At the other end, inductor L G42 The negative terminal is connected, and in addition, the inductor L D42 The positive terminal and the inductor L D41 The negative terminal is connected, and the inductor L G31 negative terminal and inductor L G32 The positive terminals are connected; The source of PMOS transistor M7 and the source of NMOS transistor M8 are connected to inductor L. S41 and inductor L S42 One end, inductor L S41 and inductor L S42 The other end is connected to the power supply potential VDD and the 0 potential VSS respectively; the drain of PMOS transistor M7 is connected to inductor L. D32 The negative and drain capacitance C D4 One end is connected, and the gate of PMOS transistor M7 is connected to inductor L. G41 The positive electrode and gate capacitance C G4 One end is connected; the drain of NMOS transistor M8 is connected to inductor L. D41 The positive and drain capacitance C D4 The other end is connected, and the gate of NMOS transistor M8 is connected to the gate capacitance C. G4 At the other end, inductor L G32 The negative terminal is connected, and in addition, the inductor L D32 The positive terminal and the inductor L D31 The negative terminal is connected, and the inductor L G41 negative terminal and inductor L G42 The positive terminals are connected; A decoupling capacitor C is used between the VDD and VSS potentials of the quad-core voltage-controlled oscillator. decap connect.

2. The ultra-low phase noise, low power consumption common-mode current cyclic harmonic quad-core voltage-controlled oscillator according to claim 1, characterized in that, Inductor L G31 negative electrode, inductor L G32 Positive electrode, inductor L D32 The positive terminal and inductor L D31 The negative terminal is connected to one side of interconnect L1, and the other side of interconnect L1 is connected to inductor L. G41 negative electrode, inductor L G42 Positive electrode, inductor L D42 The positive terminal and inductor L D41 The negative terminal; inductor L G12 Positive electrode, inductor L G11 negative electrode, inductor L D21 The positive terminal and inductor L D22 The positive terminal is connected to one side of interconnect L2, and the other side of interconnect L2 is connected to inductor L. G12 Positive electrode, inductor L G11 negative electrode, inductor L D11 The negative electrode and inductor L D12 The negative terminal; interconnects L1 and L2 intersect at the center of the quad-core voltage-controlled oscillator.

3. The ultra-low phase noise, low power consumption common-mode current cyclic harmonic quad-core voltage-controlled oscillator according to claim 1, characterized in that, Inductor L D11 Inductor L D12 Inductor L D21 Inductor L D22 Inductor L D31 Inductor L D32 Inductor L D41 Inductor L D42 The inductance value is equal to L D ; Inductor L G11 Inductor L G12 Inductor L G21 Inductor L G22 Inductor L G31 Inductor L G32 Inductor L G41 Inductor L G42 The inductance value is equal to L G ; Inductor L s11 Inductor L s21 Inductor L s31 Inductor L s41 The inductance value is equal to L s1 ; Inductor L s12 Inductor L s22 Inductor L s32 Inductor L s42 The inductance value is equal to L s2 ; Gate capacitance C G1 Gate capacitance C G2 Gate capacitance C G3 Gate capacitance C G4 The capacitance value is equal to C G ; Drain capacitance C D1 Drain capacitance C D2 Drain capacitance C D3 Drain capacitance C D4 The capacitance value is equal to C D ; Decoupling capacitor C decap The capacitance value is equal to C d ; Inductor L G11 With inductor L G31 Inductor L G22 With inductor L G32 Inductor L G12 With inductor L G42 Inductor L G41 With inductor L G21 The coupling coefficient between them is equal to K 12 ; Inductor L D11 With inductor L D31 Inductor L D22 With inductor L D32 Inductor L D12 With inductor L D42 Inductor L D41 With inductor L D21 The coupling coefficient between them is equal to K 34 ; Inductor L G31 With inductor L D11 Inductor L G22 With inductor L D32 Inductor L G41 With inductor L D21 Inductor L G12 With inductor L D42 The coupling coefficient between them is equal to K 23 ; Inductor L G11 With inductor L D11 Inductor L G21 With inductor L D21 Inductor L G32 With inductor L D32 Inductor L G42 With inductor L D42 The coupling coefficient between them is equal to K 13 ; Inductor L G11 With inductor L D31 Inductor L G21 With inductor L D41 Inductor L G32 With inductor L D22 Inductor L G42 With inductor L D12 The coupling coefficient between them is equal to K 14 ; Inductor L G12 With inductor L D12 Inductor L G22 With inductor L D22 Inductor L G31 With inductor L D31 Inductor L G41 With inductor L D41 The coupling coefficient between them is equal to K 24 ; Inductor L S11 With inductor L S12 Inductor L S21 With inductor L S22 Inductor L S31 With inductor L S32 Inductor L S41 With inductor L S42 The coupling coefficient between them is equal to K s .

4. The ultra-low phase noise, low power consumption common-mode current cyclic harmonic quad-core voltage-controlled oscillator according to claim 1, characterized in that, Gate capacitance C G1 Gate capacitance C G2 Gate capacitance C G3 Gate capacitance C G4 The differential-mode resonant cavity tank of the quad-core voltage-controlled oscillator, together with transformer T2, is formed. G Drain capacitance C D1 Drain capacitance C D2 Drain capacitance C D3 Drain capacitance C D4 The common-mode resonant cavity tank of the quad-core voltage-controlled oscillator, together with transformer T1, is formed. D Differential mode resonator tank G With common-mode resonant cavity tank D Together, they form the differential and common-mode integrated resonant cavity of the quad-core voltage-controlled oscillator, with decoupling capacitor C. decap The transformers T3, T4, T5, and T6 together form the internal decoupling capacitor-inductor resonant cavity of the quad-core voltage-controlled oscillator.

5. The ultra-low phase noise, low power consumption common-mode current cyclic harmonic quad-core voltage-controlled oscillator according to claim 4, characterized in that, The first resonant point of the differential-common-mode integrated resonant cavity is designed at the fundamental frequency of the quad-core voltage-controlled oscillator, and the second resonant point of the differential-common-mode integrated resonant cavity is designed near the second harmonic of the quad-core voltage-controlled oscillator. That is, the input impedance has an impedance peak near the first harmonic and a second impedance peak near the second harmonic, forming a double-peak impedance.

6. The ultra-low phase noise, low power consumption common-mode current cyclic harmonic quad-core voltage-controlled oscillator according to claim 5, characterized in that, Common-mode current is injected through the power supply VDD, forming four common-mode current loops, among which: Common-mode current flows through decoupling capacitor C decap The current flows to the source of PMOS transistor M1 and out from the drain of PMOS transistor M1, and then through inductor L. D11 Inductor L D12 Drain capacitance C D2 Inductor L D21 Inductor L D22 Drain capacitance C D1 Returning to the drain of PMOS transistor M1, common-mode current loop 1 is formed; Common-mode current flows through decoupling capacitor C decap The current flows to the source of PMOS transistor M3 and out from the drain of PMOS transistor M3, and then through inductor L. D21 Inductor L D22 Drain capacitance C D1 Inductor L D11 Inductor L D12 Drain capacitance C D2 Returning to the drain of PMOS transistor M3, a common-mode current loop 2 is formed; Common-mode current flows through decoupling capacitor C decap The current flows to the source of PMOS transistor M5 and out from the drain of PMOS transistor M5, and then through inductor L. D42 Inductor L D41 Drain capacitance C D4 Inductor L D32 Inductor L D31 Drain capacitance C D3 Returning to the drain of PMOS transistor M5, a common-mode current loop 3 is formed; Common-mode current flows through decoupling capacitor C decap The current flows to the source of PMOS transistor M7 and out from the drain of PMOS transistor M7, and then through inductor L. D32 Inductor L D31 Drain capacitance C D3 Inductor L D42 Inductor L D41 Drain capacitance C D4 Returning to the drain of PMOS transistor M7, a common-mode current loop 4 is formed; Inductor L D11 Inductor L D12 Inductor L D21 Inductor L D22 With inductor L respectively D31 Inductor L D42 Inductor L D41 Inductor L D32 Through the coupling coefficient K 34 They reinforce each other and synchronize the four common-mode current circulation loops.

7. The ultra-low phase noise, low power consumption common-mode current cyclic harmonic quad-core voltage-controlled oscillator according to claim 5, characterized in that, Differential mode current is injected through the power supply VDD, forming four differential mode current loops, among which: Differential mode current flows through decoupling capacitor C decap The current flows to the source of PMOS transistor M1 and out from the drain of PMOS transistor M1, and then through inductor L. D11 Inductor L D12 Drain capacitance C D2 Inductor L D21 Inductor L D22 Drain capacitance C D1 Returning to the drain of PMOS transistor M1, a differential mode current loop 1 is formed; Differential mode current flows through decoupling capacitor C decap The current flows to the source of PMOS transistor M3 and out from the drain of PMOS transistor M3, and then through inductor L. D21 Inductor L D22 Drain capacitance C D1 Inductor L D11 Inductor L D12 Drain capacitance C D2 Returning to the drain of PMOS transistor M3, a differential mode current loop 2 is formed; Differential mode current flows through decoupling capacitor C decap The current flows to the source of PMOS transistor M3 and out from the drain of PMOS transistor M5, and then through inductor L. D42 Inductor L D41 Drain capacitance C D4 Inductor L D32 Inductor L D31 Drain capacitance C D3 Returning to the drain of PMOS transistor M5, a differential mode current loop 3 is formed; Differential mode current flows through decoupling capacitor C decap The current flows to the source of PMOS transistor M3 and out from the drain of PMOS transistor M7, and then through inductor L. D32 Inductor L D31 Drain capacitance C D3 Inductor L D42 Inductor L D41 Drain capacitance C D4 Returning to the drain of PMOS transistor M7, a differential mode current loop 4 is formed; Inductor L G11 Inductor L G21 Inductor L G12 Inductor L G22 With inductor L respectively G31 Inductor L G42 Inductor L G41 Inductor L G32 Through the coupling coefficient K 12 They reinforce each other and synchronize the four core differential-mode current circulation loops.

8. The ultra-low phase noise, low power consumption common-mode current cyclic harmonic quad-core voltage-controlled oscillator according to claim 1, characterized in that, Transformer T1 and transformer T2 have completely identical structures, both adopting the form of a double-ring toroidal transformer.

9. The ultra-low phase noise, low power consumption common-mode current cyclic harmonic quad-core voltage-controlled oscillator according to claim 6, characterized in that, In order to make the common-mode current loop controllable, inductor L S11 Inductor L S21 Inductor L S31 Inductor L S41 Inductor L S12 Inductor L S22 Inductor L S32 Inductor L S42 A linear inductor is used, wherein the inductance L S11 With inductor L S12 Overlapping arrangement, inductor L S21 With inductor L S22 Overlapping arrangement, inductor L S31 With inductor L S32 Overlapping arrangement, inductor L S41 With inductor L S42 Arranged in an overlapping manner.

10. The ultra-low phase noise, low power consumption common-mode current cyclic harmonic quad-core voltage-controlled oscillator according to claim 1, characterized in that, The design process is as follows: Step 1: Optimize at the required frequency according to the voltage-controlled oscillator. Determine the fundamental frequency parameters, and then determine the inductance L. G11 Inductor L G12 Inductor L G21 Inductor L G22 Inductor L G31 Inductor L G32 Inductor L G41 Inductor L G42 The value of L G and gate capacitance C G1 Gate capacitance C G2 Gate capacitance C G3 Gate capacitance C G4 The capacitance value C G ; Sensitivity L G Capacity C G With oscillation frequency The relationship is: ； Step 2: According to the second harmonic frequency required by the voltage-controlled oscillator. Determine the second harmonic parameters, and then determine the inductance L. D11 Inductor L D12 Inductor L D21 Inductor L D22 Inductor L D31 Inductor L D32 Inductor L D41 The value of L D Drain capacitance C D1 Drain capacitance C D2 Drain capacitance C D3 Drain capacitance C D4 The capacitance value C D ; Sensitivity L D Capacity C D With second harmonic frequency The relationship is: ； Step 3: Adjust inductor L G11 With inductor L D11 Inductor L G21 With inductor L D21 Inductor L G32 With inductor L D32 Inductor L G42 With inductor L D42 The coupling coefficient K between 13 Inductor L G12 With inductor L D12 Inductor L G22 With inductor L D22 Inductor L G31 With inductor L D31 Inductor L G41 With inductor L D41 The coupling coefficient K between 24 Simulate the impedance of the first fundamental frequency and the second harmonic frequency to determine the inductance L. G11 Inductor L G12 Inductor L G21 Inductor L G22 Inductor L G31 Inductor L G32 Inductor L G41 Inductor L G42 With gate capacitance C G1 Gate capacitance C G2 Gate capacitance C G3 Gate capacitance C G4 The differential-mode path resonant cavity tank G The frequency of the peak impedance With inductor L D11 Inductor L D12 Inductor L D21 Inductor L D22 Inductor L D31 Inductor L D32 Inductor L D41 With drain capacitance C D1 Drain capacitance C D2 Drain capacitance C D3 Drain capacitance C D4 The common-mode path resonant cavity tank D The frequency of the peak impedance ; and The relationship is: ； Step 4: Adjust inductor L G11 With inductor L G31 Inductor L G12 With inductor L G42 Inductor L G21 With inductor L G41 Inductor L G22 With inductor L G32 Inductor L D11 With inductor L D31 Inductor L D12 With inductor L D42 Inductor L D21 With inductor L D41 Inductor L D22 With inductor L D32 The distance between each pair is 3µm, and the inductance L is determined. G11 With inductor L G31 Inductor L G22 With inductor L G32 Inductor L G12 With inductor L G42 Inductor L G41 With inductor L G21 The coupling coefficient K between 12 ; and inductor L D11 With inductor L D31 Inductor L D22 With inductor L D32 Inductor L D12 With inductor L D42 Inductor L D41 With inductor L D21 The coupling coefficient K between 34 Furthermore, due to the coupling coefficient K 13 Coupling coefficient K 24 The coupling coefficient K is determined, thereby simultaneously determining the coupling coefficient K. 23 With coupling coefficient K 14 ; Step 5: Set the inductor L s11 Inductor L s21 Inductor L s31 Inductor L s41 inductance value L s1 and inductor L s12 Inductor L s22 Inductor L s32 Inductor L s42 inductance value L s2 To avoid its impact on the fundamental oscillation, the decoupling capacitor was adjusted. The size of this value ensures that the peak impedance frequency of the resonant cavity is much smaller than the oscillation frequency. , The conditions to be met are: ； Step 6: Based on steps 1 to 5, build a quad-core voltage-controlled oscillator.

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