Digitally controlled programmable gain amplifier chip

Abstract

The application belongs to the technical field of integrated circuits, and specifically discloses a digital control programmable gain amplifier chip, which adopts an SIP packaged operational amplifier, a digital potentiometer, an input end Vin and an output end Vout, an alternating current signal is input from the Vin end, is connected to the inverting input end of the operational amplifier through a capacitor C1 and an input resistor R1, a positive power supply pin of the operational amplifier is connected to a positive electrode VDD of a power supply, a negative power supply pin is connected to the ground, a same-phase input end obtains a VDD / 2 direct current bias voltage through a precision resistor voltage dividing network and is connected after low-pass filtering, a high end of the digital potentiometer is connected to the Vout end, a low end is connected to the inverting input end of the operational amplifier, and a feedback path is formed through a sliding end. The operational amplifier and the digital potentiometer are integrated, high integration and modularization of the programmable gain amplification circuit are realized, and the problems of insufficient gain precision, decreased reliability of a multi-element system and large circuit volume caused by the on-resistance of an analog switch in a traditional discrete scheme are solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a digital controlled programmable gain amplifier chip. BACKGROUND

[0002] In a complex underwater acoustic environment, the target echo signal is usually weak and the signal amplitude fluctuation is significant, and the signal-to-noise ratio is low, so accurate gain control is essential for adjusting the dynamic range of the signal and optimizing the signal-to-noise ratio. The traditional programmable gain amplification circuit mainly adopts the combination of analog switches and resistance networks to realize gain adjustment. The specific implementation scheme is to switch different input resistors or feedback resistors through electronic switches, so as to change the amplification factor of the operational amplifier. This architecture is usually based on the classic inverting amplifier structure, which uses analog switches to select different resistor combinations to provide multi-position gain selection.

[0003] However, this traditional scheme has obvious limitations in practical application. The on-resistance of the analog switch will cause the equivalent impedance of the signal path to change, introducing additional gain error; at the same time, the parasitic capacitance of the switch will affect the transmission characteristics of the high-frequency signal, causing signal distortion. In addition, the use of multiple switches and discrete components not only increases the complexity of the circuit, but also reduces the reliability of the system, especially in a humid and high-salinity underwater acoustic detection environment. Since a single analog switch chip can usually only provide a limited number of gain positions (generally 4-8 positions), to achieve more precise gain control, multiple chips need to be cascaded, which not only increases the system size, but also brings additional power consumption and noise. These factors together limit the performance of the traditional scheme in high-performance applications such as underwater acoustic signal processing, making it difficult to meet the stringent requirements for gain accuracy, stability and environmental adaptability. SUMMARY

[0004] The purpose of the present application is to provide a digital controlled programmable gain amplifier chip, which uses a digital potentiometer to replace an analog switch to adjust the gain, solving the problem of gain error caused by the on-resistance of the analog switch; and uses SIP packaging technology to integrate the digital potentiometer and the operational amplifier, shortening the signal path and reducing parasitic parameters and interference.

[0005] To achieve the above purpose, the present application provides a digital controlled programmable gain amplifier chip, which comprises an operational amplifier U1 and a digital potentiometer U2 integrated by SIP packaging, an input end Vin and an output end Vout, an alternating current signal is input through the input end Vin and coupled through a direct current blocking capacitor C1, and then connected to the inverting input end of the operational amplifier U1 through an input resistor R1.

[0006] The positive power pin of the operational amplifier U1 is connected to the positive electrode VDD of the power supply, and the negative power pin is connected to the ground GND; the non-inverting input end of the operational amplifier U1 is connected to the DC bias voltage VDD / 2 obtained through the precision resistor voltage division network, and is connected to the low-pass filter after being filtered;

[0007] The high end of the digital potentiometer U2 is connected to the output end Vout, the low end is connected to the inverting input end of the operational amplifier U1, and the feedback path is formed through the sliding end.

[0008] Preferably, the precision resistor voltage division network is composed of resistors R3 and R4, and R3=R4; the resistor R4 is connected in parallel with the capacitor C2, the capacitor C2 is connected in parallel with the resistor R2, and the capacitor C2 and the resistor R2 form a low-pass filter structure to remove noise from the obtained DC bias voltage VDD / 2.

[0009] Preferably, the SIP packaging integrated specific is: the bare chips of the operational amplifier U1 and the digital potentiometer U2 are integrated in the same layer, and the pin interconnection is realized by using gold wire bonding technology; the independent power supply network and the separated ground architecture are adopted to physically isolate the power supply and ground pins of the operational amplifier U1 and the digital potentiometer U2.

[0010] Preferably, the DFN10 packaging is adopted to form the digitally controlled programmable gain amplifier, the packaging size is 3mm×3mm×0.75mm, and 10 pins are led out, including the non-inverting input port IN+, the inverting input port IN-, the digital potentiometer ground GND, the chip selection signal input CSB, the serial data input DIN, the serial clock input SCLK, the digital potentiometer power supply VDD, the output port OUT, the operational amplifier power supply VCC and the operational amplifier ground VSS.

[0011] Preferably, the resistance value RW of the digital potentiometer U2 is dynamically configured through the three-wire serial SPI digital interface, and then the amplifier gain is controlled, and the specific process is as follows:

[0012] The three-wire serial SPI digital interface is a write-only interface, including the chip selection signal CSB, the data input signal DIN and the data clock signal SCLK;

[0013] When the chip selection signal CSB is at a low level, the data at the data input signal DIN end is synchronized and loaded into the 8-bit serial shift register at the rising edge of each data clock signal SCLK, and the highest bit is shifted first.

[0014] After all the 8-bit data are loaded into the 8-bit serial shift register, the chip selection signal CSB becomes high, and all the 8-bit data are latched through the 8-bit latch;

[0015] The decoder decodes 8-bit data of the 8-bit latch output, and the gain module adjusts the amplification multiple of the input data, and switches the amplifier to any one of the 256 gain levels.

[0016] Therefore, the application has the following beneficial effects by using the above-mentioned digital programmable gain amplifier chip:

[0017] (1) The application uses a digital potentiometer to directly digitally control the gain, eliminates the gain error caused by the on-resistance of the analog switch, realizes digital precise adjustment of the system gain G=-RW / R1, and accurately switches in the 256 gain levels, greatly improving the precision and flexibility of gain adjustment.

[0018] (2) The application uses SIP packaging technology to integrate the digital potentiometer and the operational amplifier, physically isolates the power supply and ground pins, uses an independent power supply network and a separate ground architecture to block the interference of digital noise on analog signals; at the same time, it simplifies the peripheral circuit, reduces the use of multi-level switches and discrete components, reduces the circuit complexity, and improves the system reliability, which can also work stably in harsh underwater acoustic environments.

[0019] (3) The application uses a core device system-in-package to integrate the operational amplifier die and the digital potentiometer die on the same layer, uses gold wire bonding technology for interconnection, forms a DFN10 package with a size of only 3mmx3mmx0.75mm, significantly reduces the volume; reduces the influence of signal path parasitic parameters, improves the signal-to-noise ratio, and can better adapt to underwater acoustic signal processing and other scenes with strict requirements on space, signal quality and dynamic range, and effectively process weak and large fluctuation signals.

[0020] The technical solutions of the application will be further described in detail below with reference to the drawings and examples. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is the overall schematic diagram of the digital programmable gain amplifier chip of the application;

[0022] Figure 2 is the pin layout schematic diagram of the digital programmable gain amplifier chip of the application;

[0023] Figure 3 is the gain adjustment schematic diagram of the digital programmable gain amplifier chip of the application;

[0024] Figure 4 is the serial interface timing diagram of the digital programmable gain amplifier chip of the application;

[0025] Figure 5This is a circuit schematic diagram of a numerically controlled programmable gain amplifier chip embodiment of the present invention. Detailed Implementation

[0026] The technical solution of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0027] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0028] This invention is based on the principle of inverting amplifier circuit. It uses a single-supply operational amplifier U1 and a digital potentiometer U2 to work together to achieve programmable gain control.

[0029] like Figure 1 As shown, a numerically controlled programmable gain amplifier chip includes an operational amplifier U1 and a digital potentiometer U2 integrated in a SIP package, an input terminal Vin, and an output terminal Vout. An AC signal is input through the Vin terminal, coupled via a DC blocking capacitor C1, and then connected to the inverting input terminal (-) of the operational amplifier U1 through an input resistor R1. The capacitor C1 acts as a DC blocker, allowing AC signals to pass while blocking DC signals, preventing DC bias from affecting subsequent parts of the circuit. The resistor R1, along with other components, determines the circuit's gain and other characteristics.

[0030] Operational amplifier U1 features high gain, high input impedance, and low output impedance, enabling it to effectively process and amplify input signals. The positive power supply pin of operational amplifier U1 is connected to the positive terminal VDD, and the negative power supply pin is grounded (GND). The non-inverting input of operational amplifier U1 obtains a DC bias voltage of VDD / 2 through a precision resistor divider network, which is then low-pass filtered before being connected to establish a stable quiescent operating point for processing bidirectional AC signals.

[0031] The digital potentiometer U2 is connected with the output end Vout at the high end, connected with the inverting input end of the operational amplifier U1 at the low end, and directly forms a feedback path through the sliding end, thereby constituting a standard inverting amplifier architecture.

[0032] In the application, the precise resistance voltage dividing network is composed of resistors R3 and R4, and R3=R4, which is used to provide a suitable DC bias voltage for the non-inverting input end (+) of the operational amplifier U1, so that the operational amplifier works at a suitable static working point.

[0033] The resistor R4 is connected with the capacitor C2 in parallel, the capacitor C2 is connected with the resistor R2 in parallel, and the capacitor C2 and the resistor R2 form a low-pass filter structure, thereby further stabilizing the DC bias voltage of the non-inverting input end, removing the noise of the DC bias voltage VDD / 2, and reducing the influence of power supply noise and other interferences on the bias voltage.

[0034] Physical package:

[0035] In order to realize miniaturization and compact integration, the application adopts a SIP core device system-level package, that is, the operational amplifier U1 die and the digital potentiometer U2 die are integrated on the same layer, and then the pin interconnection is realized by using gold wire bonding technology; in the package design, an independent power supply network and a separated ground architecture are adopted, the power supply and ground pins of the operational amplifier U1 and the digital potentiometer U2 are physically isolated, thereby effectively blocking the interference of digital noise on the analog signal, and improving the signal processing precision and system reliability.

[0036] According to actual use requirements, the DFN10 package is adopted to form the digital programmable gain amplifier, the package size is 3mm*3mm*0.75mm, and the volume is significantly reduced compared with the traditional discrete scheme. Ten pins are led out, including the non-inverting input port IN+, the inverting input port IN-, the digital potentiometer ground GND, the chip selection signal input CSB, the serial data input DIN, the serial clock input SCLK, the digital potentiometer power supply VDD, the output port OUT, the operational amplifier power supply VCC and the operational amplifier ground VSS.

[0037] As shown in Figure 3 In the application, the resistance RW of the digital potentiometer U2 can be dynamically configured through a three-wire serial SPI digital interface, and then the corresponding precise gain of the amplifier is rapidly controlled, and the specific process is as follows:

[0038] The three-wire serial SPI digital interface is a write-only interface, including a chip selection signal CSB, a data input signal DIN and a data clock signal SCLK.

[0039] When chip select signal CSB is low, the data at the data input signal DIN end is loaded into the 8-bit serial shift register and shifted and stored bit by bit at the rising edge of each data clock signal SCLK, and the highest bit is shifted first.

[0040] Figure 4 The timing diagram describes the process of inputting 8-bit serial data from the DIN port to the 8-bit serial shift register inside the chip bit by bit through synchronization of SCLK.

[0041] In the figure, the chip select signal CSB signal is usually low active, and the CSB signal is first in the low state, at which time the chip is selected and data transmission is allowed. When CSB becomes high, the data transmission ends, corresponding to "POT REGISTER LOADED" in the figure, indicating that the potentiometer register has loaded data.

[0042] The serial clock signal SCLK is a series of pulse signals that provide a clock reference for serial data transmission. Each rising edge (or falling edge, depending on the chip design, which is generally a rising edge here) corresponds to the transmission time of a bit of data. Through these clock pulses, the chip can sequentially receive the data input from DIN bit by bit.

[0043] The data input signal DIN is a serial input data signal. The figure shows the transmission of 8-bit data (D7-D0), where D7 is the most significant bit (MSB) and D0 is the least significant bit (LSB). When CSB is low and each valid edge (rising edge) of SCLK, a bit of data is input to the 8-bit serial shift register inside the chip, and the 8-bit data is transmitted in turn.

[0044] When all 8-bit data is loaded into the 8-bit serial shift register, once the chip select signal CSB becomes high, all 8-bit data is latched through the 8-bit latch.

[0045] After the decoder decodes the 8-bit data output by the 8-bit latch, the gain module adjusts the amplification factor of the input data, and switches the amplifier to any one of the 256 gain levels.

[0046] Embodiment One

[0047] To verify the effectiveness of the present application, this embodiment provides a single power supply digital controlled programmable gain amplifier chip application scheme. As shown in Figure 5As shown, the input signal is connected to the signal input pin IN- (i.e. the inverting input terminal of the operational amplifier) of the chip through the input resistor R1, and the bias circuit of the non-inverting input terminal of the operational amplifier adopts two equal resistors R3 and R5 to divide the power supply voltage VCC to obtain a reference voltage of VCC / 2. The reference voltage is filtered of noise by an RC low-pass filter composed of resistor R4 and capacitor C1, and then is connected to the IN+ pin through the series resistor R2 to form a stable reference potential. The power input end adopts a multi-stage decoupling capacitor network (C2, C3, C4) to realize full-band noise suppression.

[0048] In operation, the input signal is sent to the inverting terminal of the operational amplifier through R1, and the resistance range set by the digital potentiometer determines the amplification factor together, and the output signal realizes bidirectional swing with VCC / 2 as the reference. When powered on, the digital potentiometer is reset to the middle range, and then the feedback resistance range can be flexibly adjusted through the program to realize different gain factors. The design optimizes the bias network and filter circuit, effectively suppresses the power supply noise and common-mode interference while ensuring the gain accuracy, and is particularly suitable for low-noise application occasions such as sensor signal conditioning.

[0049] Therefore, the application adopts the above-mentioned digitally controlled programmable gain amplifier chip, integrates the digital potentiometer and the operational amplifier by SIP packaging, and innovatively realizes the high integration and modularization of the programmable gain amplification circuit, effectively solving the technical problems of insufficient gain accuracy caused by the on-resistance of the analog switch, the decrease of system reliability caused by multi-component combination, and the large circuit size in the traditional discrete scheme. The design not only simplifies the complexity of the peripheral circuit, but also realizes more precise and flexible gain adjustment capability through the direct digital control characteristics of the digital potentiometer. At the same time, thanks to the compact structure of SIP packaging, the influence of parasitic parameters on the signal path is significantly reduced, so that the overall circuit is significantly improved in gain stability, environmental adaptability and integration, and is particularly suitable for underwater acoustic signal processing and other application scenarios with strict requirements on space size, signal quality and dynamic range, and can effectively handle the complex situation of common weak signals and large amplitude signal fluctuations in underwater acoustic detection.

[0050] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application but not to limit it, although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can still be modified or equivalently replaced, and these modifications or equivalent replacements cannot make the modified technical solutions deviate from the spirit and scope of the technical solutions of the present application.

Claims

1. A digitally controlled programmable gain amplifier chip, characterized by: The operational amplifier U1 and the digital potentiometer U2, the input terminal Vin and the output terminal Vout are packaged and integrated by using SIP, and an AC signal is input through the input terminal Vin and coupled through the direct current blocking capacitor C1, and then connected to the inverting input terminal of the operational amplifier U1 through the input resistor R1; The positive power supply pin of the operational amplifier U1 is connected to the positive electrode VDD of the power supply, and the negative power supply pin is connected to the ground GND; the non-inverting input terminal of the operational amplifier U1 obtains a DC bias voltage of VDD / 2 through a precision resistor voltage dividing network, and is connected after low-pass filtering; The high end of the digital potentiometer U2 is connected to the output terminal Vout, the low end is connected to the inverting input terminal of the operational amplifier U1, and a feedback path is formed through the sliding end; The precision resistor voltage dividing network is composed of resistors R3 and R4, and R3=R4; the resistor R4 is connected in parallel with the capacitor C2, the capacitor C2 is connected in parallel with the resistor R2, and the capacitor C2 and the resistor R2 form a low-pass filter structure to remove noise from the obtained DC bias voltage of VDD / 2; The operational amplifier U1 die and the digital potentiometer U2 die are integrated in the same layer, and then the pin interconnection is realized by using gold wire bonding technology; an independent power supply network and a separate ground architecture are adopted to physically isolate the power supply and ground pins of the operational amplifier U1 and the digital potentiometer U2; The resistance RW of the digital potentiometer U2 is dynamically configured through a three-wire serial SPI digital interface, and then the amplifier gain is controlled, and the specific process is as follows: The three-wire serial SPI digital interface is a write-only interface, including a chip select signal CSB, a data input signal DIN and a data clock signal SCLK; When the chip select signal CSB is at a low level, the data at the data input signal DIN is synchronized and loaded into an 8-bit serial shift register at the rising edge of each data clock signal SCLK, and the highest bit is shifted first; After all 8-bit data is loaded into the 8-bit serial shift register, the chip select signal CSB becomes high, and all 8-bit data is latched through the 8-bit latch; After the 8-bit data output by the 8-bit latch is decoded by the decoder, the gain module adjusts the amplification multiple of the input data, and switches the amplifier to any one of the 256 gain levels.

2. The digitally controlled programmable gain amplifier chip of claim 1, wherein: A DFN10 package is adopted to form a digitally controlled programmable gain amplifier, and the package size is 3mm×3mm×0.75mm, and 10 pins are led out, including the non-inverting input port IN+, the inverting input port IN-, the digital potentiometer ground GND, the chip select signal input CSB, the serial data input DIN, the serial clock input SCLK, the digital potentiometer power supply VDD, the output port OUT, the operational amplifier power supply VCC and the operational amplifier ground VSS.

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