Single-ended to differential signal conversion device, integrated circuit, chip and package structure

Abstract

The specification discloses a single-ended to differential signal conversion device, integrated circuit, chip and packaging structure, wherein the single-ended to differential signal conversion device comprises a waveform shaping and amplifying unit, a differential signal generating unit and an output driving unit; the waveform shaping and amplifying unit is configured to perform waveform shaping and amplitude boosting on a first single-ended signal to obtain a second single-ended signal; the differential signal generating unit is coupled to the waveform shaping and amplifying unit and configured to generate a positive-phase signal and a negative-phase signal through an active mode according to the second single-ended signal; and the output driving unit is coupled to the differential signal generating unit and configured to output the positive-phase signal and the negative-phase signal with the same driving capability. The single-ended to differential signal conversion device helps to simplify the existing single-ended to differential structure and improve the integration of circuit implementation.

Description

Technical Field

[0001] This specification relates to the field of integrated circuit technology, and more specifically, to a single-ended to differential signal conversion device, integrated circuit, chip, and packaging structure. Background Technology

[0002] With increasing chip integration and growing demands for high-speed communication, differential signals are often required between or within chips to improve signal interference immunity. However, due to limitations in pin and wiring resources, single-ended signal transmission is commonly used in practical applications, with the signal converted to differential signals at the receiving end. Existing single-ended to differential conversion methods often employ passive devices such as baluns, which are complex, bulky, and occupy chip area, hindering the design of highly integrated chips. Therefore, there is an urgent need for a simplified, easily integrated single-ended to differential signal conversion solution. Summary of the Invention

[0003] To address the technical issues of existing single-ended to differential conversion methods being complex in structure, large in size, and unfavorable for the design of highly integrated chips, this specification proposes a single-ended to differential signal conversion device, integrated circuit, chip, and packaging structure.

[0004] The first aspect of this specification provides a single-ended to differential signal conversion device, comprising: a waveform shaping and amplification unit, a differential signal generation unit, and an output driving unit;

[0005] The waveform shaping and amplification unit is used to shape the waveform and amplify the amplitude of the first single-ended signal to obtain the second single-ended signal.

[0006] The differential signal generation unit, coupled to the waveform shaping and amplification unit, is used to generate an in-phase signal and an out-of-phase signal in an active manner based on the second single-ended signal.

[0007] The output driving unit is coupled to the differential signal generation unit and is used to output the positive phase signal and the negative phase signal with the same driving capability.

[0008] As a further aspect of this specification, the single-ended to differential signal conversion device further includes:

[0009] The delay and duty cycle adjustment unit is disposed between the differential signal generation unit and the output driving unit, and is used to synchronously or independently adjust the delay and duty cycle of the positive phase signal and the negative phase signal.

[0010] As a further aspect of this specification, the single-ended to differential signal conversion device further includes:

[0011] A symmetry compensation unit is disposed between the differential signal generation unit and the output driving unit, and is used to symmetrically compensate the parasitic parameters of the positive phase signal and the negative phase signal.

[0012] As a further aspect of this specification, the single-ended to differential signal conversion device further includes:

[0013] A differential signal shaping and amplification unit is disposed between the differential signal generation unit and the output driving unit, and is used to perform waveform shaping and amplitude enhancement on the positive phase signal and the negative phase signal, respectively.

[0014] As a further aspect of this specification, the single-ended to differential signal conversion device further includes:

[0015] An input matching unit is used to receive a third single-ended signal from an external input, perform impedance matching on the third single-ended signal to obtain a first single-ended signal, and then transmit the first single-ended signal to the waveform shaping and amplification unit.

[0016] As a further aspect of this specification, the differential signal generation unit is used to output the second single-ended signal as the positive phase signal, and to reverse the polarity of the second single-ended signal through an inverting circuit to output the inverted signal.

[0017] As a further aspect of this specification, the differential signal generation unit includes: a center-tapped input node and a symmetrical common-source MOS transistor connected to the center-tapped input node;

[0018] The center tap input node is used to symmetrically distribute the second single-ended signal to the gate of the common-source MOS transistor; the output terminal of the common-source MOS transistor is connected to the positive signal path and the negative signal path respectively, and is used to output the positive signal and the negative signal respectively.

[0019] As a further aspect of this specification, the output drive unit includes multiple digital buffers with the same driving force for providing multiple differential output ports.

[0020] As a further aspect of this specification, the symmetrical compensation unit is disposed in the positive phase signal path and its structure is symmetrical to the inverting circuit in the negative phase signal path. It is used to compensate for the difference in parasitic parameters between the positive and negative phase signal paths. The differential signal generation unit outputs the second single-ended signal as the positive phase signal in the positive phase signal path and reverses the polarity of the second single-ended signal through the inverting circuit in the negative phase signal path to output the negative phase signal.

[0021] As a further aspect of this specification, the delay and duty cycle adjustment unit includes two digitally controllable switched capacitor arrays with symmetrical structure and capacitance distribution, respectively used for the positive phase signal and the negative phase signal. The number of capacitor elements and the capacitance distribution of each switched capacitor array are used to realize digital delay adjustment and digital duty cycle adjustment of the corresponding signal.

[0022] As a further aspect of this specification, the single-ended to differential signal conversion device further includes:

[0023] A controllable switching unit is used to control the waveform shaping and amplification unit to be turned on or off at full amplitude according to an external control signal.

[0024] As a further aspect of this specification, the first single-ended signal is a clock signal.

[0025] A second aspect of this specification provides an integrated circuit that includes the single-ended to differential signal conversion device described above.

[0026] A third aspect of this specification provides a chip that includes the aforementioned single-ended to differential signal conversion device.

[0027] The fourth aspect of this specification provides a multi-chip package structure, which includes the chips described above.

[0028] The single-ended to differential signal conversion device in the embodiments of this specification converts single-ended signals into differential signals in an active manner by setting up a waveform shaping and amplification unit, a differential signal generation unit, and an output driving unit. This structure is simpler than the existing passive Balun solution, effectively reducing the structural complexity of the circuit, reducing the chip area occupied, and facilitating the miniaturization and high integration of the circuit, thus meeting the actual needs of high-integration chip design. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0030] Figure 1 This is a schematic diagram of a single-ended to differential signal conversion device in the embodiments of this specification;

[0031] Figure 2 This is another schematic diagram of the single-ended to differential signal conversion device in the embodiments of this specification;

[0032] Figure 3 This is another schematic diagram of the single-ended to differential signal conversion device in the embodiments of this specification;

[0033] Figure 4 This is another schematic diagram of the single-ended to differential signal conversion device in the embodiments of this specification;

[0034] Figure 5 This is another schematic diagram of the single-ended to differential signal conversion device in the embodiments of this specification;

[0035] Figure 6 This is a schematic diagram of a differential signal generation unit in an embodiment of this specification;

[0036] Figure 7 This is another schematic diagram of the differential signal generation unit in the embodiments of this specification;

[0037] Figure 8 This is a schematic diagram of the symmetry compensation unit in the embodiments of this specification;

[0038] Figure 9 This is a schematic diagram of the delay and duty cycle adjustment unit in the embodiments of this specification;

[0039] Figure 10 This is a schematic diagram of the output driving unit in the embodiments of this specification. Detailed Implementation

[0040] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0041] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, apparatus, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0042] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0043] To address the technical problems of complex structures and difficulty in ensuring signal output consistency in existing single-ended to differential conversion methods, this application proposes a single-ended to differential signal conversion device, integrated circuit, chip, and packaging structure.

[0044] It should be noted that the single-ended to differential signal conversion device of this application can be flexibly applied to different levels of a chip system. It can serve as an interface module for communication between chips, or as an interface unit between different functional modules within a chip, suitable for various signal transmission and synchronization requirements. Specifically, it can be applied to the following scenarios:

[0045] 1. Inter-chip communication applications. In systems where multiple chips work together, this device can be deployed at the input interface of the receiving chip to convert single-ended signals from external sources into differential signals, improving the anti-interference capability and reception quality of inter-chip signals. This solution is suitable for high-speed operating frequency bands such as 5G NR (Sub-6GHz), and can meet the clock synchronization requirements in MIMO or one-to-many structures, especially suitable for single-wire communication designs under conditions of limited pin resources.

[0046] 2. Communication Applications Between Chips in the Same Package. In a multi-chip package (SiP) architecture, different chips often have differences in voltage domain, process technology, or interface. This device can be used as an interface module between chips, utilizing its signal conversion and matching capabilities to solve coupling and mismatch problems in cross-voltage domain transmission, ensuring communication stability. The device supports adaptive biasing and impedance matching design for the interface, adapting to various packaging environments.

[0047] 3. Internal Module Communication Applications. Within a chip, especially in large SoCs, there may be long physical distances or cross-regional communication requirements between different functional modules. This device can embed inter-module pathways for signal conversion and driving, improving timing consistency and anti-interference performance. In this application, AC coupling devices and terminating resistors can be omitted at the interface, simplifying the circuit structure, saving area, and improving chip integration efficiency.

[0048] It should be noted that the single-ended to differential signal conversion device described in this application is applicable to the conversion of various types of single-ended signals to differential signals, including clock signals, data signals, and control signals. For ease of understanding and explanation, some embodiments in this specification are described using clock signals as examples, but these should be understood as merely illustrative examples and do not constitute a limitation on the scope of application of this application. It is understood that the single-ended to differential signal conversion device described in this application is also applicable to differential conversion application scenarios for other types of single-ended signals.

[0049] Figure 1 This is a schematic diagram of a single-ended to differential signal conversion device in an embodiment of this application, as shown below. Figure 1 As shown in one embodiment of this application, the single-ended to differential signal conversion device includes: a waveform shaping and amplification unit, a differential signal generation unit, and an output driving unit.

[0050] The waveform shaping and amplification unit is used to shape the waveform and increase the amplitude of the first single-ended signal to obtain the second single-ended signal.

[0051] The differential signal generation unit, coupled to the waveform shaping and amplification unit, is used to actively generate an in-phase signal and an inverted signal based on the second single-ended signal.

[0052] An output driving unit, coupled to the differential signal generation unit, is used to output the positive phase signal and the negative phase signal with the same driving capability.

[0053] In this application, the purpose of setting up a waveform shaping and amplification unit is to address issues such as insufficient amplitude and edge blunting that may exist in the first single-ended signal in practical applications, especially in long-distance signal transmission scenarios. Due to factors such as line loss and interference, signal attenuation is easily caused. If the single-ended signal is directly converted to a differential signal, it will affect the accuracy and stability of subsequent signal conversion. By configuring a waveform shaping and amplification unit at the front end of the signal link, this application can effectively amplify and optimize the input signal, which not only enhances the driving capability but also improves the signal morphology, thereby providing a stable and reliable input foundation for the generation and output of the subsequent differential signal.

[0054] In one embodiment of this application, in response to the amplitude attenuation and waveform distortion problems that may occur during long-distance transmission of the input signal, the waveform shaping and amplification unit of this application adopts a saturated gain amplification method to enhance the amplitude and shape the waveform of the signal, so that the output signal has sufficient amplitude and has relatively ideal rising and falling edge characteristics, thereby providing a stable and reliable input basis for subsequent differential signal generation, which helps to improve the signal conversion quality and consistency.

[0055] In one embodiment of this application, the waveform shaping and amplification unit can employ a common-emitter amplifier (or common-source amplifier), a differential amplifier, an inverting amplifier, or a high-gain operational amplifier to perform waveform shaping and amplitude enhancement. By appropriately designing the bias and gain parameters, these structures can sufficiently amplify the input signal in amplitude and effectively optimize its edge characteristics, achieving saturated or near-saturated output.

[0056] In this application, the differential signal generation unit is mainly used to convert the second single-ended signal output by the waveform shaping and amplification unit into a positive-phase signal and an inverted signal to meet the requirements of subsequent differential signal processing. This unit enables effective conversion from single-ended to differential signals.

[0057] In one embodiment of this application, the differential signal generation unit employs an active signal conversion method. This involves actively amplifying or inverting the input signal using active devices (such as symmetrical transistor structures or active inverter circuits) to generate a pair of differential signals with matching amplitudes and opposite polarities. Compared to traditional passive differential schemes (such as the existing Balun scheme), the active method offers advantages such as compact structure, controllable power consumption, and high output consistency. It is particularly suitable for applications requiring high signal integrity and output consistency, such as inter-chip communication and intra-chip package communication. Furthermore, the active method supports flexible circuit design and automatic bias adjustment, effectively adapting to different input signal amplitudes and bias conditions, thus avoiding conversion distortion caused by input signal attenuation or mismatch.

[0058] In one embodiment of this application, the differential signal generation unit can generate a positive-phase signal and an inverted signal through active differential or signal inversion. Active differential refers to using an active circuit with a symmetrical structure (such as a common-source symmetrical structure or a differential pair structure) to actively convert the input single-ended signal, thereby simultaneously generating two output signals with opposite polarities and matched amplitudes. This method has good signal consistency and electrical symmetry, and is suitable for applications requiring high consistency and high-speed communication, where differential quality is critical. Signal inversion typically outputs the original signal as a positive-phase signal through a direct path, while simultaneously inverting the polarity of the input signal through an inverted signal path (such as using an inverter), outputting an inverted signal. This method has a simple structure and is suitable for resource-constrained or layout-constrained applications. Both methods are implemented using active circuits, offering advantages such as small size, strong controllability, and ease of integration compared to traditional passive device solutions.

[0059] In this application, the output driver unit is used to drive the generated positive and negative signals to ensure that the signals have sufficient transmission capability to meet the receiving requirements of subsequent circuits or transmission links. The main purpose of setting up the output driver unit is to improve the signal driving capability and load matching performance, and to prevent signal distortion, transmission instability, or decreased anti-interference capability due to insufficient driving capability.

[0060] In one embodiment of this application, "outputting with the same driving capability" means that the output driving unit employs symmetrical output paths or device structures for the inverted and non-inverted signals, such as buffers or inverters with consistent parameters, to ensure that the two signals maintain consistency in key indicators such as amplitude, rise / fall rate, and output impedance. This significantly improves the consistency, symmetry, and common-mode rejection ratio (CMRR) of the differential signal, enhancing the overall signal integrity of the system, and is particularly suitable for high-speed, long-distance, or electromagnetically sensitive communication environments.

[0061] In one embodiment of this application, the single-ended to differential signal conversion device can be applied to a differential conversion application scenario for clock signals, i.e., the first single-ended signal is a clock signal. In other embodiments of this application, the single-ended to differential signal conversion device can also be applied to differential conversion application scenarios for other signals.

[0062] In one embodiment of this application, the single-ended to differential signal conversion device of this application further includes:

[0063] The delay and duty cycle adjustment unit is disposed between the differential signal generation unit and the output driving unit, and is used to synchronously or independently adjust the delay and duty cycle of the positive phase signal and the negative phase signal.

[0064] This application utilizes delay and duty cycle adjustment units to achieve synchronous or independent delay and duty cycle adjustment of positive and negative signals. Delay adjustment can effectively compensate for signal timing offsets caused by factors such as process differences and inconsistent trace lengths, achieving precise synchronization of positive and negative signals in time. Duty cycle adjustment helps optimize the duration of high and low levels of the signal, ensuring the symmetry and stability of the output signal, thereby improving the system's synchronization performance and anti-interference capability.

[0065] In one embodiment of this application, the delay and duty cycle adjustment unit can be implemented using a digitally controllable switched capacitor array, which facilitates flexible adjustment of delay and duty cycle parameters to meet the needs of different application scenarios. A digitally controllable switched capacitor array consists of multiple capacitor units with increasing weights (such as C, 2C, 4C, 8C, etc.) and their corresponding electronic switches, which are driven by digital control signals. By combining digital control signals, different capacitor paths can be flexibly selected, thereby achieving precise digital adjustment of parameters such as signal delay and filtering. The higher the number of control bits, the finer the adjustment step, meeting the requirements of high-precision adjustment.

[0066] In one embodiment of this application, the delay and duty cycle adjustment unit may adopt a structure with a weighted C-type switched capacitor combination, and realize digital adjustment of signal delay and duty cycle by forming a 4-bit control bit.

[0067] like Figure 9 As shown, in another embodiment of this application, the delay and duty cycle adjustment unit includes two digitally controllable switched capacitor arrays with symmetrical structure and capacitance distribution, respectively used for the positive-phase signal and the negative-phase signal. The number and capacitance distribution of capacitor elements in each switched capacitor array are used to realize digital delay adjustment and digital duty cycle adjustment of the corresponding signal. In this embodiment, each digitally controllable switched capacitor array consists of several capacitor units with different weights and corresponding electronic switches, which can flexibly adjust the total capacitance of the actual circuit connected in the array through digital control, thereby performing high-precision delay and duty cycle adjustment of the input positive-phase or negative-phase signal.

[0068] In one embodiment of this application, the single-ended to differential signal conversion device of this application further includes:

[0069] A symmetry compensation unit is disposed between the differential signal generation unit and the output driving unit, and is used to symmetrically compensate the parasitic parameters of the positive phase signal and the negative phase signal.

[0070] In one embodiment of this application, a symmetry compensation unit is used to symmetrically compensate for the parasitic parameters of the in-phase and out-of-phase signals to improve the consistency and symmetry of the differential signal output. In this application, parasitic parameters may include parasitic capacitance, parasitic inductance, and parasitic resistance, etc. These parameters originate from factors such as the transistor device itself, circuit layout and wiring, and connection structure, and may cause deviations in signal amplitude, delay, edge rate, etc. If the parasitic parameters of the in-phase and out-of-phase signal paths are mismatched, it will cause differential signal asymmetry, affecting the common-mode rejection ratio (CMRR) and signal integrity. Therefore, this application introduces a symmetrical compensation structure, such as a transmission gate, to achieve symmetrical compensation of the parasitic parameters of the out-of-phase signal path, thereby effectively improving the consistency and stability of the differential signal output.

[0071] In one embodiment of this application, the single-ended to differential signal conversion device of this application further includes:

[0072] A differential signal shaping and amplification unit is disposed between the differential signal generation unit and the output driving unit, and is used to perform waveform shaping and amplitude enhancement on the positive phase signal and the negative phase signal, respectively.

[0073] In this application, the differential signal shaping and amplification unit is used to perform waveform shaping and amplitude enhancement on the positive and negative signals respectively, so as to further optimize the symmetry and amplitude consistency of the output signal.

[0074] In some embodiments of this application, the differential signal shaping and amplification unit can employ structures such as a common-emitter (common-source) amplifier, a differential amplifier, an inverting amplifier, or a high-gain operational amplifier to achieve waveform shaping and amplitude enhancement. The specific type can be selected according to requirements. By adjusting the gain and bias conditions, the above structures can achieve amplitude enhancement and saturation shaping of the input signal, satisfying the requirements for signal shaping and amplitude consistency.

[0075] In one embodiment of this application, the single-ended to differential signal conversion device of this application further includes:

[0076] An input matching unit is used to receive a third single-ended signal from an external input, perform impedance matching on the third single-ended signal to obtain a first single-ended signal, and then transmit the first single-ended signal to the waveform shaping and amplification unit.

[0077] like Figure 5 As shown, in one embodiment of this application, the input matching unit is coupled to the waveform shaping and amplification unit, forming the front-end input path of the single-ended to differential signal conversion device of this application. The input matching unit serves as the receiving interface for external signals, used to receive single-ended signals from external or internal modules of the chip, and to perform impedance matching processing on the input signals. By reasonably setting the input matching unit, it is possible not only to adapt to the characteristic impedance of different signal sources, reduce the signal attenuation caused by long-distance transmission, and effectively suppress signal reflection and energy loss, but also to improve the quality and stability of the signals processed by the subsequent waveform shaping and amplification unit, providing a reliable signal input foundation for the entire single-ended to differential signal conversion link.

[0078] In one embodiment of this application, the input matching unit includes a matching resistor connected in series or in parallel with the input terminal for impedance matching of the single-ended signal input from the outside.

[0079] In some embodiments of this application, the input matching unit may specifically employ a series or parallel matching resistor, a π-type or T-type impedance network, or other similar structures. For example, a resistor with a resistance value matching the characteristic impedance of the signal source can be connected in series or parallel at the input terminal to achieve basic impedance matching requirements. For higher bandwidth or complex application scenarios, a multi-component passive impedance network can also be used for precise matching. By reasonably selecting and configuring device parameters, the input matching unit can effectively adapt to different signal source types and transmission conditions, improving the signal integrity and anti-interference capability of the system.

[0080] In one embodiment of this application, the differential signal generation unit is specifically used to output the second single-ended signal as the positive phase signal, and to reverse the polarity of the second single-ended signal through an inverting circuit to output the inverted signal.

[0081] like Figure 6As shown in one embodiment of this application, the differential signal generation unit includes two signal paths, corresponding to the output of a positive-phase signal and an inverted signal, respectively. Specifically, the second single-ended signal is directly output as a positive-phase signal via the positive-phase signal path, and is input to the inverting circuit via the inverting signal path, where it is output as an inverted signal after polarity reversal. This structure is simple, easy to implement, and can effectively convert a single-ended signal into a differential signal.

[0082] Although this structure is easy to implement, during signal transmission, due to differences in circuits and devices, slight asymmetry in amplitude or transmission characteristics between the positive and negative signals can easily occur. In particular, when the negative signal is generated by the negative circuit and the path parasitic parameters are not completely consistent, it is difficult to fully guarantee the consistency and symmetry of the signal amplitude.

[0083] Therefore, in this embodiment, a symmetry compensation unit and a differential signal shaping and amplification unit are also required after the differential signal generation unit. The symmetry compensation unit is used to symmetrically match the parasitic parameters of the signal paths of the positive and negative signals. For example, by introducing compensation structures such as transmission gates in the positive signal path, the two signals are made as symmetrical as possible in terms of structure and device size, thereby improving signal consistency. The differential signal shaping and amplification unit is used to further saturate amplify and shape the compensated positive and negative signals, making up for the amplitude unevenness and edge degradation caused by phase inversion or signal attenuation during transmission. This ensures that the final output pair of differential signals is highly consistent in key parameters such as amplitude and timing, improving the decision-making and recognition capabilities of subsequent circuits for differential signals. Through the above cascaded design, this application can effectively improve the output consistency of differential signals and the overall signal integrity of the system, meeting the requirements of high reliability and high performance application scenarios.

[0084] In some embodiments of this application, the inverting circuit can adopt various structures according to actual needs, such as an operational amplifier-based inverting amplifier (which sets the gain through a feedback resistor to achieve amplitude amplification and polarity reversal), a common-emitter (common-source) inverting amplifier implemented with a transistor or MOSFET, or an integrated digital inverter such as CMOS or TTL (suitable for fast polarity reversal of digital signals), so as to flexibly meet the inverting requirements of different signal types and application scenarios.

[0085] like Figure 8 As shown, in one embodiment of this application, a symmetrical compensation unit is disposed in the positive phase signal path, and its structure is symmetrical with the inverting circuit in the negative phase signal path, and is used to compensate for the difference in parasitic parameters between the positive and negative phase signal paths.

[0086] In one embodiment of this application, the symmetrical compensation unit includes a series transmission gate structure, and the symmetrical compensation unit and the inverting circuit are symmetrical in structural layout and device parameters. Through this symmetrical design, the differences in parasitic effects between the positive and negative paths caused by factors such as circuit layout can be effectively compensated, ensuring that the parasitic parameters such as load, capacitance, and resistance of the two signals are accurately matched during transmission, thereby improving the consistency and stability of the differential signal output.

[0087] A transmission gate is a bidirectional switching structure composed of NMOS and PMOS transistors connected in parallel. Its control terminals receive complementary control signals (such as high and low levels). When the control signal is on, both the NMOS and PMOS transistors conduct simultaneously, enabling the transmission of analog or digital signals between circuit nodes with low on-resistance, achieving lossless or low-loss signal transmission. Due to the complementary conduction characteristics of NMOS and PMOS transistors, the transmission gate possesses good symmetry, effectively reducing level loss and distortion during switching. This application's embodiment uses a transmission gate structure to construct a symmetrical compensation unit primarily because the transmission gate can achieve a highly symmetrical distribution of parasitic parameters in different signal paths, ensuring consistent load, capacitance, and other characteristics in the positive and negative signal paths, effectively improving the output symmetry of the differential signal and the system's anti-interference capability.

[0088] like Figure 7 As shown, in another embodiment of this application, the differential signal generation unit includes: a center tap input node and a symmetrical common-source MOS transistor connected to the center tap input node.

[0089] The center tap input node is used to symmetrically distribute the second single-ended signal to the gate of the common-source MOS transistor; the output terminal of the common-source MOS transistor is connected to the positive signal path and the negative signal path respectively, and is used to output the positive signal and the negative signal respectively.

[0090] In one embodiment of this application, the differential signal generation unit includes a center-tapped input node and a pair of symmetrical common-source MOS transistors connected to the input node. The center-tapped input node serves as a signal distribution point, used to symmetrically send the second single-ended signal to the gates of the pair of common-source MOS transistors. The pair of common-source MOS transistors have a completely symmetrical structural layout and size parameters, corresponding to the positive and negative output channels, respectively.

[0091] During circuit operation, the second single-ended signal is simultaneously applied to the input terminals (gates) of both common-source transistors via the center-tapped input node, and the two signals are transmitted along two symmetrical signal paths. The common-source structure not only effectively suppresses common-mode interference but also ensures a high degree of consistency in key parameters such as amplitude, timing, and dynamic response between the positive and negative output signals. Ultimately, the output terminals of the two common-source MOS transistors are connected to the positive and negative signal paths, respectively, achieving a pair of high-quality differential signal outputs with opposite polarities and consistent amplitudes.

[0092] This structure, due to its high symmetry in physical layout, electrical parameters, and signal path, ensures consistency between the positive and negative signals in amplitude, timing, and dynamic response during the signal generation stage. Compared to embodiments using inverting circuits, this embodiment effectively suppresses parasitic parameter inconsistencies and signal mismatch issues, significantly improving the symmetry and common-mode rejection capability of the differential signal output. Therefore, in this embodiment, it is generally unnecessary to subsequently set up symmetry compensation units or differential signal shaping and amplification units to meet the design requirements of high consistency and high-performance differential signal output, simplifying the overall circuit structure and facilitating system integration and stable operation.

[0093] like Figure 10 As shown in one embodiment of this application, the output driving unit includes multiple digital buffers with the same driving force, used to provide multiple differential output ports. Each digital buffer takes a positive or negative signal as input and outputs to an independent port, thereby supporting various expansion requirements such as one-to-two conversion of single-ended to differential signals, or even one-to-many conversion. Since all digital buffers have consistent structural parameters and driving capabilities, it can ensure that the output signals of each channel have high consistency in key indicators such as amplitude and timing, which is beneficial to the synchronization and integrity of multi-channel, high-speed signal transmission.

[0094] like Figure 10 As shown, in one embodiment of this application, digital buffers 1 to n are used for driving the output of positive phase signals, and outputs 1 to n are the output ports of positive phase signals. Digital buffers m to p are used for driving the output of inverted phase signals, and outputs m to p are the output ports of inverted phase signals.

[0095] Specifically, using a simple digital buffer for output driving effectively enhances signal driving capability and facilitates the expansion of the number of output ports without signal amplitude attenuation caused by parallel branches. Compared to traditional analog circuit structures with fixed driving capability, digital buffers offer flexible adjustment of driving capability, covering a wider frequency range, making them particularly suitable for high-speed or high-bandwidth signal transmission scenarios. Furthermore, the buffer parameters for each output branch can be adjusted individually, enabling on-demand allocation and dynamic optimization, further improving the overall signal output consistency and flexibility of the system and meeting the design requirements of various highly integrated, multi-channel applications.

[0096] In some embodiments of this application, the digital buffer can take many forms, such as a CMOS inverter, a digital NOT gate, a non-inverting buffer, a multi-stage gate circuit, etc.

[0097] like Figure 5 As shown, in one embodiment of this application, the single-ended to differential signal conversion device further includes:

[0098] A controllable switching unit, coupled to a waveform shaping and amplifying unit, is used to control the waveform shaping and amplifying unit to be fully turned on or off according to an external control signal.

[0099] In one embodiment of this application, the controllable switching unit may use an NMOS transistor as a switching device, located in the current path of the waveform shaping and amplifying unit (such as below a current source or load), to control the full-amplitude turn-on (conduct) or turn-off (cut-off) of the entire waveform shaping and amplifying unit according to an external control signal. Specifically, when the external control signal is high, the NMOS transistor is turned on, the waveform shaping and amplifying unit works normally, amplifying and shaping the input signal; when the external control signal is low, the NMOS transistor is turned off, the waveform shaping and amplifying unit is turned off, the input signal no longer passes through, and there is no valid signal at the output terminal.

[0100] This application introduces a full-amplitude switching control method, making the circuit's start-up, power management, and signal on / off more flexible, thus meeting various application requirements such as dynamic startup, testing, or low-power operation. Because the waveform shaping and amplification unit uses a saturated switching amplification mode, even with switching control, there is no signal amplitude distortion, ensuring stable and consistent output signal amplitude. The impact of switching operation on subsequent circuits is mainly reflected in delay accuracy, without affecting the signal quality itself.

[0101] Figure 2 This is another schematic diagram of the single-ended to differential signal conversion device in the embodiments of this specification, as shown below. Figure 2 As shown in one embodiment of this specification, the single-ended to differential signal conversion device includes: a waveform shaping and amplification unit, a differential signal generation unit, a delay and duty cycle adjustment unit, and an output driving unit.

[0102] The waveform shaping and amplification unit is used to shape the waveform and increase the amplitude of the first single-ended signal to obtain the second single-ended signal.

[0103] A differential signal generation unit, coupled to the waveform shaping and amplification unit, is used to actively generate a positive-phase signal and an inverted signal based on the second single-ended signal. Specifically, in this embodiment, the differential signal generation unit includes a center-tapped input node and a symmetrical common-source MOS transistor connected to the center-tapped input node. The center-tapped input node is used to symmetrically distribute the second single-ended signal to the gate of the common-source MOS transistor; the output terminal of the common-source MOS transistor is connected to the positive-phase signal path and the inverted signal path, respectively, for outputting the positive-phase signal and the inverted signal, respectively.

[0104] The delay and duty cycle adjustment unit is coupled to the differential signal generation unit and is used to synchronously or independently adjust the delay and duty cycle of the positive phase signal and the negative phase signal.

[0105] The output drive unit, coupled to the delay and duty cycle adjustment unit, is used to output the adjusted positive and negative signals with the same driving capability.

[0106] exist Figure 2 In this embodiment, the waveform shaping and amplification unit performs waveform saturation amplification on the input single-ended signal to obtain a stable second single-ended signal. Subsequently, the differential signal generation unit actively converts this signal into a positive-phase signal and an inverted signal. The delay and duty cycle adjustment unit synchronously or independently adjusts the delay and duty cycle of the positive and inverted signals to meet the system's precise requirements for signal timing and pulse width. Finally, the output driving unit outputs the adjusted positive and inverted signals with the same driving capability, ensuring the consistency of the differential signal in amplitude and timing.

[0107] exist Figure 2 In this embodiment, the differential signal generation unit employs a center-tapped input node and a pair of symmetrical common-source MOS transistors. Through symmetrical allocation and consistent structural parameters, the amplitude and timing of the positive and negative signals are highly consistent. Because the structure itself possesses excellent symmetry and consistency, no subsequent symmetry compensation unit or differential signal shaping and amplification unit is required to meet the demands of high-performance differential signal output, simplifying the circuit structure and facilitating system integration and stability improvement.

[0108] Figure 3 This is another schematic diagram of the single-ended to differential signal conversion device in the embodiments of this specification, as shown below. Figure 3As shown in one embodiment of this specification, the single-ended to differential signal conversion device includes: a waveform shaping and amplification unit, a differential signal generation unit, a symmetry compensation unit, a differential signal shaping and amplification unit, and an output driving unit.

[0109] The waveform shaping and amplification unit is used to shape the waveform and increase the amplitude of the first single-ended signal to obtain the second single-ended signal.

[0110] A differential signal generation unit, coupled to the waveform shaping and amplification unit, is used to actively generate a positive-phase signal and an inverted-phase signal based on the second single-ended signal. Specifically, in this embodiment, the differential signal generation unit outputs the second single-ended signal as a positive-phase signal and inverts the polarity of the second single-ended signal using an inverter to output an inverted signal.

[0111] A symmetrical compensation unit, coupled to both the differential signal generation unit and the differential signal shaping and amplification unit, is used to symmetrically compensate the parasitic parameters of the positive-phase signal and the negative-phase signal, and transmit the compensated signal to the differential signal shaping and amplification unit. Specifically, in this embodiment, the symmetrical compensation unit is located in the positive-phase signal path, and its structure is symmetrical to the inverter circuit in the negative-phase signal path. This ensures that the positive-phase signal path and the negative-phase signal path (containing an inverter for reversing signal polarity) are as symmetrical as possible in terms of structural layout, device type, and size, thereby effectively compensating for the parasitic parameters of the two signals.

[0112] The differential signal shaping and amplification unit, coupled to the output driving unit, is used to perform waveform shaping and amplitude enhancement on the compensated positive and negative signals respectively, and to transmit the waveform-shaped positive and negative signals to the output driving unit.

[0113] The output drive unit is used to drive the waveform-shaped positive and negative signals with the same driving capability for output.

[0114] exist Figure 3 In this embodiment, the waveform shaping and amplification unit performs waveform saturation amplification on the input first single-ended signal to obtain a second single-ended signal. The differential signal generation unit then outputs a positive-phase signal and an inverted signal based on the second single-ended signal through two signal paths: a forward pass-through circuit and an inverting circuit. In this scheme, when the inverted signal is generated by the inverting circuit and the parasitic parameters of the two signal paths are not perfectly symmetrical, inconsistencies in amplitude or timing characteristics between the positive and inverted signals may occur.

[0115] To further improve the consistency and symmetry of the signal output, this embodiment adds a symmetry compensation unit and a differential signal shaping and amplification unit after the differential signal generation unit. Specifically, the symmetry compensation unit introduces compensation structures such as transmission gates into the positive phase signal path to make the positive and negative phase paths as symmetrical as possible in terms of structural layout, device type, and size, thereby effectively compensating for the parasitic parameters of the two signals and improving signal consistency. The differential signal shaping and amplification unit is used to further saturate amplify and shape the compensated positive and negative phase signals to compensate for the amplitude unevenness caused by phase inversion or signal attenuation, ensuring the consistency of the output differential signal in key parameters such as amplitude and timing.

[0116] Figure 4 This is another schematic diagram of the single-ended to differential signal conversion device in the embodiments of this specification, as shown below. Figure 4 As shown in one embodiment of this specification, the single-ended to differential signal conversion device includes: a waveform shaping and amplification unit, a differential signal generation unit, a symmetry compensation unit, a differential signal shaping and amplification unit, a delay and duty cycle adjustment unit, and an output drive unit.

[0117] The waveform shaping and amplification unit is used to shape the waveform and increase the amplitude of the first single-ended signal to obtain the second single-ended signal.

[0118] A differential signal generation unit, coupled to the waveform shaping and amplification unit, is used to actively generate a positive-phase signal and an inverted-phase signal based on the second single-ended signal. Specifically, in this embodiment, the differential signal generation unit outputs the second single-ended signal as a positive-phase signal and inverts the polarity of the second single-ended signal using an inverter to output an inverted signal.

[0119] A symmetrical compensation unit, coupled to both the differential signal generation unit and the differential signal shaping and amplification unit, is used to symmetrically compensate the parasitic parameters of the positive-phase signal and the negative-phase signal, and transmit the compensated signal to the differential signal shaping and amplification unit. Specifically, in this embodiment, the symmetrical compensation unit is located in the positive-phase signal path, and its structure is symmetrical to the inverter circuit in the negative-phase signal path. This ensures that the positive-phase signal path and the negative-phase signal path (containing an inverter for reversing signal polarity) are as symmetrical as possible in terms of structural layout, device type, and size, thereby effectively compensating for the parasitic parameters of the two signals.

[0120] The differential signal shaping and amplification unit, coupled to the delay and duty cycle adjustment unit, is used to perform waveform shaping and amplitude enhancement on the compensated positive and negative signals respectively, and transmit the waveform-shaped signals to the delay and duty cycle adjustment unit.

[0121] The delay and duty cycle adjustment unit, coupled to the output drive unit, is used to synchronously or independently adjust the delay and duty cycle of the waveform-shaped positive and negative signals, and transmit the adjusted positive and negative signals to the output drive unit.

[0122] The output drive unit is used to drive the regulated positive and negative signals with the same driving capability for output.

[0123] exist Figure 4 In this embodiment, the waveform shaping and amplification unit is used to saturate and amplify the input first single-ended signal to obtain a second single-ended signal. The differential signal generation unit uses this signal as a basis to output a positive-phase signal and an inverted signal through a forward pass-through and an inverting circuit. Because the inverted signal is generated by the inverting circuit, the parasitic parameters of the two signal paths may not be completely consistent, easily causing amplitude or timing inconsistencies.

[0124] To improve signal consistency and symmetry, this embodiment adds a symmetry compensation unit and a differential signal shaping and amplification unit after the differential signal generation unit. By introducing structures such as transmission gates into the in-phase signal path, parasitic parameter compensation is achieved, and the two signals are saturated and amplified and shaped to ensure consistency in amplitude and timing. In addition, a delay and duty cycle adjustment unit is used to finely adjust the delay and duty cycle of the signal, and the output drive unit outputs each signal with the same drive capability to ensure high consistency in amplitude and timing of the multi-channel output.

[0125] Based on the above embodiments, the device of this application adopts an on-chip digital single-ended to differential structure, which can accurately meet the system design requirements in terms of phase noise control, signal delay, and duty cycle adjustment. The device of this application is highly integrated inside the chip, occupying a significantly smaller chip area than traditional Balun solutions. In practical applications, by introducing a coupling AC capacitor of approximately 0.4pF at the input, an input matching performance of S11 better than -15dB can be effectively achieved, ensuring that the device has excellent signal adaptability in a wide frequency range, including sub-6GHz.

[0126] Furthermore, the device in this application is highly simple in implementation, supports flexible on-chip and off-chip connections, and has a small on-chip footprint, facilitating integration. Through a 1-to-N output architecture, it can meet the multi-channel clock synchronization requirements between M×N array chips such as phased arrays, exhibiting excellent scalability. Utilizing pure digital numerical control, it requires no additional bias circuitry, offers flexible adjustment methods, adapts to different frequency bands, and has broad frequency adaptability. With the trend towards higher clock signals, compared to traditional Balun solutions, the device in this application has significant advantages in terms of area, process compatibility, and design flexibility. Digital design eliminates dependence on bias voltage and power supply voltage ranges; saturation operating mode, combined with switching control and stable core power supply, effectively simplifies auxiliary circuits, reduces noise introduction and system design complexity, and further improves circuit integration and reliability.

[0127] Based on the above embodiments, this application also proposes an integrated circuit that includes the single-ended to differential signal conversion device described in the above embodiments.

[0128] Based on the above embodiments, this application also proposes a chip that includes the single-ended to differential signal conversion device described in the above embodiments.

[0129] Based on the above embodiments, this application also proposes a multi-chip packaging structure, which includes the chip described in the above embodiments.

[0130] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A single-ended to differential signal conversion device, characterized by, The application discloses a device for converting a single-ended signal of a clock signal into a differential signal, and the device comprises a waveform shaping and amplifying unit, a differential signal generating unit, a symmetric compensation unit, a differential signal shaping and amplifying unit, a delay and duty cycle adjusting unit and an output driving unit. The waveform shaping and amplifying unit is configured to perform waveform shaping and amplitude boosting on a first single-ended signal to obtain a second single-ended signal. The differential signal generating unit is coupled to the waveform shaping and amplifying unit and configured to output the second single-ended signal as a positive-phase signal and perform polarity inversion on the second single-ended signal through an inverting circuit to output a negative-phase signal. The symmetric compensation unit is arranged in a positive-phase signal path and is symmetric to the inverting circuit in a negative-phase signal path, and is configured to compensate for differences in parasitic parameters of the positive-phase and negative-phase signal paths. The differential signal shaping and amplifying unit is coupled to the delay and duty cycle adjusting unit and configured to perform waveform shaping and amplitude boosting on the compensated positive-phase and negative-phase signals respectively, and transmit the waveform-shaped signals to the delay and duty cycle adjusting unit. The delay and duty cycle adjusting unit is coupled to the output driving unit and configured to perform synchronous or independent delay adjustment and duty cycle adjustment on the waveform-shaped positive-phase and negative-phase signals, and transmit the adjusted positive-phase and negative-phase signals to the output driving unit. The output driving unit is coupled to the differential signal generating unit and configured to output the positive-phase and negative-phase signals with the same driving capability.

2. The single-ended to differential signal conversion device of claim 1, wherein, Further comprising: An input matching unit is configured to receive a third single-ended signal input from outside, perform impedance matching on the third single-ended signal to obtain the first single-ended signal, and then transmit the first single-ended signal to the waveform shaping and amplifying unit.

3. The single-ended to differential signal conversion device of claim 1, wherein, The differential signal generating unit comprises a center-tapped input node and symmetric common-source MOS transistors connected to the center-tapped input node. The center-tapped input node is configured to symmetrically distribute the second single-ended signal to the gates of the common-source MOS transistors, and the output ends of the common-source MOS transistors are respectively connected to a positive-phase signal path and a negative-phase signal path, and are configured to respectively output the positive-phase signal and the negative-phase signal.

4. The single-ended to differential signal conversion device of claim 1, wherein, The output driving unit comprises a plurality of digital buffers with the same driving force, and is configured to provide a plurality of differential output ports.

5. The single-ended to differential signal conversion device of claim 1, wherein, The delay and duty cycle adjusting unit comprises two digital controllable switched capacitor arrays with symmetric structures and capacitance distributions, and is respectively configured to the positive-phase signal and the negative-phase signal, and the number and capacitance distribution of the capacitor elements of each switched capacitor array are configured to realize digital delay adjustment and digital duty cycle adjustment on the corresponding signal.

6. The single-ended to differential signal conversion device of claim 1, wherein, Further comprising: A controllable switch unit is configured to perform full-amplitude on or off control on the waveform shaping and amplifying unit according to an external control signal.

7. An integrated circuit, characterized by The single-ended to differential signal conversion device comprises any one of the single-ended to differential signal conversion devices according to claims 1 to 6.

8. A chip, characterized by The single-ended to differential signal conversion device comprises any one of the single-ended to differential signal conversion devices according to claims 1 to 6.

9. A multi-chip package structure, comprising: The chip comprises the chip according to claim 8.

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