Clock delay circuit and multi-phase clock generation apparatus

Abstract

The application discloses a clock delay circuit and a multi-phase clock generating device, relates to the technical field of clock integrated circuits, and synchronously tunes the delay of an output multi-phase clock by adjusting the proportion of charging current and discharging current, so that the multi-phase clock generation and delay adjustment can be combined together, and the power consumption and area of a traditional multi-phase clock circuit can be greatly reduced. The application can help reduce the power consumption and area of a D2D interconnection circuit, realize higher density integration, increase the overall interaction total bandwidth of a chip, and promote the algorithm power improvement of an artificial intelligence chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of clock integrated circuits, in particular to a clock delay circuit and a multiphase clock generation device. BACKGROUND

[0002] The traditional multiphase clock circuit structure adopts a separate multiphase clock generator and an adjustable delay circuit unit, which has many problems: first, the delay unit can usually only delay a group of differential clocks in the multiphase clock, and multiple delay units are needed to meet the synchronous adjustable requirement; second, the delay unit will introduce additional clock jitter, which is more obvious when the delay is large, in order to realize low-jitter large-range delay adjustment, the transition edge slope and the circuit stage number need to be increased, resulting in high power consumption and large area; third, there is a delay mismatch between multiple delay units, and an additional phase interval calibration circuit module is needed, further increasing the power consumption and area.

[0003] At the same time, the traditional multiphase clock generator is usually implemented by a delay-locked loop (DLL) or an injection-locked ring oscillator, which also has some shortcomings, for example: the DLL needs multiple high-speed delay units, which has high power consumption under low-jitter conditions, and an additional phase interval calibration circuit module is needed to calibrate the mismatch of the delay units; the injection-locked oscillator can achieve low jitter and low power consumption synchronously, but it will cause a mismatch in the phase output by the ring oscillator, and an additional phase interval calibration circuit module is also needed to calibrate the phase deviation. SUMMARY

[0004] The present application provides a clock delay circuit and a multiphase clock generation device to at least solve the problem of how to reduce the power consumption and area of the traditional multiphase clock circuit in the related art.

[0005] The present application provides a clock delay circuit, comprising: a single-ended-to-differential circuit, a switch circuit, a plurality of charging current sources, a plurality of discharging current sources, and a loop filter circuit, wherein the input end of the single-ended-to-differential circuit receives a clock signal, and the first output end and the second output end of the single-ended-to-differential circuit are connected to the control end of the switch circuit; the input end of each charging current source is connected to a supply voltage, the output end of each charging current source is connected to the first end of the switch circuit, and the control end of each charging current source is connected to a first control signal; the input end of each discharging current source is connected to the second end of the switch circuit, the output end of each discharging current source is grounded, and the control end of each charging current source is connected to a second control signal; the third end of the switch circuit is connected to the ground through the loop filter circuit, and the third end of the switch circuit outputs a clock delay signal; in one control period, the first control signal and the second control signal are complementary.

[0006] The application provides a multiphase clock generation device, comprising: a phase discriminator circuit, an oscillation circuit and a clock delay circuit above the oscillation circuit, the clock delay circuit comprising: a single-ended to differential circuit, a switch circuit, a plurality of charging current sources, a plurality of discharging current sources and a loop filter circuit, wherein the first input end of the phase discriminator circuit is connected to a clock signal, the second input end of the phase discriminator circuit is connected to the output end of the oscillation circuit, and the output end of the phase discriminator circuit is connected to the input end of the single-ended to differential circuit; the input end of the single-ended to differential circuit receives the clock signal, and the first output end and the second output end of the single-ended to differential circuit are connected to the control end of the switch circuit; the input end of each charging current source is connected to a power supply voltage, the output end of each charging current source is connected to the first end of the switch circuit, and the control end of each charging current source is connected to a first control signal; the input end of each discharging current source is connected to the second end of the switch circuit, the output end of each discharging current source is grounded, and the control end of each charging current source is connected to a second control signal; the third end of the switch circuit is connected to the ground through the loop filter circuit, and the third end of the switch circuit is connected to the input end of the oscillation circuit; the output end of the oscillation circuit outputs a multiphase clock signal; and the first control signal and the second control signal are complementary in one control period.

[0007] By adjusting the ratio of charging current and discharging current to synchronously tune the delay of the output multiphase clock, the application can combine the multiphase clock generation and delay adjustment together, greatly reducing the power consumption and area of the traditional multiphase clock circuit. The application can help reduce the power consumption and area of the D2D interface circuit, realize higher density integration, thereby increasing the overall interaction bandwidth of the chip and promoting the algorithm power of the artificial intelligence chip.

[0008] Through the application, the multiphase clock generation device realizes accurate conversion from a reference clock to a multiphase clock through the closed-loop cooperation of the phase discriminator circuit, the oscillation circuit and the clock delay circuit. The clock delay circuit is the core of delay adjustment, and provides a stable and adjustable delay reference for the whole device through the complementary control of the first and second control signals. The phase discriminator circuit and the oscillation circuit are responsible for error correction and multiphase output respectively, and the three together constitute a multiphase clock generation system with high precision and high stability, which can be widely applied to electronic devices requiring multiphase timing cooperation (such as communication chips and data converters). BRIEF DESCRIPTION OF DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0010] Figure 1A multi-phase clock circuit module block diagram of the related art;

[0011] Fig. 2(a) is a multi-phase clock circuit module block diagram of the related art employing a DLL;

[0012] Fig. 2(b) is a multi-phase clock circuit module block diagram of the related art employing an injection-locked ring oscillator;

[0013] Figure 3 A clock delay circuit module block diagram provided for an embodiment of the present application;

[0014] Figure 4 A circuit structure diagram of a single-ended to differential circuit provided for an embodiment of the present application;

[0015] Figure 5 A circuit structure diagram of a switching circuit, a charging current source, and a discharging current source provided for an embodiment of the present application;

[0016] Figure 6 Another clock delay circuit module block diagram provided for an embodiment of the present application;

[0017] Figure 7 A multi-phase clock generation apparatus module block diagram provided for an embodiment of the present application;

[0018] Figure 8 A circuit structure diagram of a phase detector provided for an embodiment of the present application;

[0019] Figure 9 A circuit structure diagram of an oscillation circuit provided for an embodiment of the present application. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, any other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0021] It should be noted that, in the description of the present application, the terms “comprise”, “contain” or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed, or includes elements inherent to such process, method, article or device. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0022] In order for those skilled in the art of the present technology to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] A multi-phase clock generator with four or more phases has a wide range of application requirements in scenarios such as high-density Die-to-Die (D2D) interconnection interfaces, multi-channel Serilize-Deserilize (SerDes) transceiver circuits, etc. At the same time, the delay of the multi-phase clock also needs to be adjustable so as to meet the requirements of data symbol center and clock edge alignment in D2D, SerDes, and other application scenarios, thereby realizing low error rate data interaction.

[0024] In a conventional multi-phase clock circuit structure, a separate multi-phase clock generator and an adjustable delay circuit unit are used, as shown in Figure 1 There are the following problems: 1) The delay unit usually uses an inverter-based adjustable delay chain or a phase interpolator, which can only delay one group of differential clocks in the multi-phase clock, so multiple delay units are needed to realize the synchronous adjustable delay of the multi-phase clock (for example, two delay units are needed for a commonly used 4-phase clock, as shown in Figure 1 ); 2) The delay unit introduces additional clock jitter, especially when a large delay is needed, the clock signal transition edge in the delay unit needs to become slower, that is, more transistor noise is injected into the clock transition edge, resulting in larger clock jitter, so it is usually necessary to increase the transition edge slope and the number of delay unit circuits to realize low-jitter large-range delay adjustment, resulting in high power consumption and large area; 3) There is a delay mismatch between multiple delay units, so an additional phase interval calibration circuit module is needed, which also increases power consumption and area.

[0025] At the same time, the conventional multi-phase clock generator usually uses a DLL or an injection-locked ring oscillator, as shown in FIGS. 2(a) and 2(b), which has the following problems: 1) The DLL needs multiple high-speed delay units, as described above, under the condition of ensuring low jitter, the delay unit has high power consumption, and an additional phase interval calibration circuit module is needed to calibrate the mismatch of the delay units; 2) The injection-locked oscillator can realize low jitter and low power consumption synchronously, but the injection locking causes a mismatch in the phase output by the ring oscillator, so an additional phase interval calibration circuit module is needed to calibrate the phase deviation.

[0026] Based on the above problems, an embodiment of the present application provides a clock delay circuit, as shown in Figure 3 , which includes a single-ended-to-differential circuit 1, a switch circuit 2, a plurality of charging current sources 3, a plurality of discharging current sources 4, and a loop filter circuit 5. Figure 3The three discharging current sources 4 and the three charging current sources 3 are taken as examples, but the number of current sources is set as required.

[0027] As shown in Figure 3 The input end of the single-ended-to-differential circuit 1 receives a clock signal, and the first output end and the second output end of the single-ended-to-differential circuit 1 are connected to the control end of the switch circuit 2. The input end of each charging current source 3 is connected to a power supply voltage, the output end of each charging current source 3 is connected to the first end of the switch circuit 2, and the control end of each charging current source 3 is connected to a first control signal. The input end of each discharging current source 4 is connected to the second end of the switch circuit 2, the output end of each discharging current source 4 is grounded, and the control end of each charging current source 3 is connected to a second control signal. The third end of the switch circuit 2 is connected to the ground through the loop filter circuit 5, and the third end of the switch circuit 2 outputs a clock delay signal. In one control period, the first control signal and the second control signal are complementary.

[0028] Specifically, the input end of the single-ended-to-differential circuit 1 is specially used to receive an externally input single-ended clock signal. As a “signal conversion station” of the circuit, its main function is to convert the single-ended clock signal into a differential signal. The converted differential signal is output from the first output end and the second output end respectively, and is connected to the control end of the switch circuit 2 to control the on-off state of the switch circuit 2, thereby laying a foundation for subsequent delay adjustment.

[0029] Specifically, in a complete control period, the first control signal and the second control signal present a strict complementary relationship - this means that when one of the signals is in an effective state (for example, high), the other signal must be in an ineffective state (for example, low), and both cannot be effective or ineffective at the same time, just like the “on” and “off” of a switch, which are opposite and cooperate with each other.

[0030] For example, assuming that the first control signal is high, the second control signal must be low; and when the first control signal turns to low, the second control signal turns to high at the same time. The effective intervals of the two on the time axis are completely staggered, and cover the entire control period, without signal overlap or gap.

[0031] Taking the scenario of three charging current sources 3 and three discharging current sources 4 as an example, if the first control signal is “1”, some charging current sources 3 are activated (turned on), and the second control signal must be “0” at this time, and all discharging current sources 4 are in the off state; conversely, when the second control signal is “1”, some or all of the discharging current sources 4 are started, and the first control signal is “0”, and the charging current sources 3 stop working. This kind of either-or state ensures that the charging and discharging processes do not occur at the same time in the same control period, avoiding circuit abnormalities caused by current conflicts.

[0032] Specifically, the input end of each charging current source 3 is connected to the power supply voltage, which provides the energy required for its operation. The output end of each charging current source 3 is connected to the first end of the switch circuit 2, and the control end is connected to the first control signal, which determines whether each charging current source 3 is working. When the charging current source 3 is working, it will provide a charging current to the subsequent circuit, affecting the charging speed of the circuit, and thus changing the delay time.

[0033] Specifically, the input end of each discharging current source 4 is connected to the second end of the switch circuit 2 corresponding to the charging current source 3, and the output end is connected to the ground. Its control end is connected to the second control signal, which controls the working state of the discharging current source 4. When the discharging current source 4 is working, it will speed up the discharging speed of the circuit, which also affects the delay time.

[0034] Specifically, the switch circuit 2 acts as a "valve" in the circuit, which switches the working state under the control of the differential signal output by the single-ended to differential circuit 1. When the switch circuit 2 is turned on, the charging current source 3 or the discharging current source 4 forms a path with the loop filter circuit 5, and the current starts to charge or discharge the energy storage element (such as a capacitor) in the loop filter circuit 5.

[0035] Specifically, the third end of the switch circuit 2 is connected to the ground through the loop filter circuit 5, and at the same time, the third end is also the output end of the clock delay signal. The loop filter circuit 5 is mainly composed of capacitors, resistors and other elements, which plays a role in smoothing and filtering the current in the charging and discharging process. During the charging and discharging process, the voltage across the energy storage element changes gradually, and when it reaches a certain threshold, the delayed clock signal is output. The faster the charging and discharging speed, the shorter the delay time; on the contrary, the longer the delay time.

[0036] The core of the clock delay circuit in this embodiment is to use multiple charging and discharging current sources 4 to change the charging and discharging current size by controlling the number of current sources, and then adjust the charging and discharging speed of the energy storage element in the loop filter circuit 5, and finally realize the precise control of the clock signal delay. The single-ended to differential circuit 1 and the switch circuit 2 play a key role in signal conversion and path control, which guarantees the flexibility and stability of the circuit delay adjustment. This structure design makes the circuit can be widely used in various electronic systems that need clock signal delay control, and meets the timing requirements in different scenarios.

[0037] In some alternative embodiments, for example, Figure 4As shown, the single-ended-to-differential circuit 1 comprises a first inverter N1, a second inverter N2, a third inverter N3 and a transmission gate U1. The input terminal of the first inverter N1 is connected to the input terminal of the transmission gate U1, and the input terminal of the first inverter N1 is also connected to a clock signal. The output terminal of the first inverter N1 is connected to the input terminal of the second inverter N2. The output terminal of the second inverter N2 is connected to the control terminal of the switching circuit 2. The input terminal of the third inverter N3 is connected to the input terminal of the transmission gate U1, and the output terminal of the third inverter N3 is connected to the control terminal of the switching circuit 2.

[0038] Specifically, the input terminal of the first inverter N1 has a dual role. On the one hand, it is directly connected to the input terminal of the transmission gate U1. On the other hand, it is specially connected to an externally input single-ended clock signal. This means that the first inverter N1 is connected to the original clock signal from the beginning and transmits it to the transmission gate U1, while also inverting the signal itself. The output terminal is connected to the input terminal of the second inverter N2, transmitting the inverted signal to the next inverter.

[0039] Specifically, the second inverter N2 is the subsequent stage of the first inverter N1, receiving the inverted signal from N1 and inverting it again. After two inversions, the output signal remains logically consistent with the original clock signal, but is delayed and shaped by two inverters. This output terminal is directly connected to the control terminal of the switching circuit 2, providing one of the control signals for the switching circuit 2.

[0040] Specifically, the input terminal of the third inverter N3 is also connected to the input terminal of the transmission gate U1, which is connected to the input terminal of the first inverter N1. This means that the signal input to the third inverter N3 is the same as the original clock signal input to the first inverter N1. N3 inverts the original signal, and the inverted signal is directly output to the control terminal of the switching circuit 2, becoming another signal for controlling the switching circuit 2.

[0041] Specifically, the input terminal of the transmission gate U1 is connected to the input terminal of the first inverter N1 and the input terminal of the third inverter N3, which are connected to the original clock signal. The transmission gate U1 here mainly functions as a signal transmission and isolation, ensuring that the original signal is stably transmitted to the relevant inverters, while reducing signal interference between different inverters and ensuring the consistency of the input signals of the inverters.

[0042] Based on Figure 4The key to converting the single-ended signal into the differential signal lies in the cooperation of the three inverters. After the original clock signal enters the first inverter N1, it is outputted to the second inverter N2 after being inverted, and the signal outputted by the second inverter N2 after being inverted again is in phase with the original signal. The third inverter N3 directly inverts the original signal, and outputs the inverted signal of the original signal. In this way, the in-phase signal outputted by the second inverter N2 and the inverted signal outputted by the third inverter N3 form a pair of complementary differential signals, and the differential signals are connected to the control ends of the switch circuit 2, which exactly meets the requirement of the switch circuit 2 for differential control signals.

[0043] In some optional embodiments, as shown in FIG. 2, the switch circuit 2 includes a first switch Q1, a second switch Q2, a third switch Q3, a fourth switch Q4 and an operational amplifier U2. Figure 5 The first end of the first switch Q1 is connected with the output end of each charging current source 3 and the first end of the third switch Q3, the second end of the first switch Q1 is connected with the first end of the second switch Q2, the output end of the operational amplifier U2 and the inverting input end of the operational amplifier U2, and the control end of the first switch Q1 is connected with the output end of the second inverter N2. The second end of the second switch Q2 is connected with the input end of each discharging current source 4 and the second end of the fourth switch Q4, and the control end of the second switch Q2 is connected with the output end of the third inverter N3. The second end of the third switch Q3 is connected with the non-inverting input end of the operational amplifier U2 and the first end of the fourth switch Q4, and the second end of the third switch Q3 is also connected with the ground through a loop filter circuit 5. The second end of the third switch Q3 outputs a clock delay signal, and the control end of the third switch Q3 is connected with the output end of the third inverter N3. The control end of the fourth switch Q4 is connected with the output end of the second inverter N2.

[0044] Optionally, the first switch Q1 and the third switch Q3 are PMOS tubes, the first end of the first switch Q1 and the second end of the third switch Q3 are the sources of the PMOS tubes, and the second end of the first switch Q1 and the first end of the third switch Q3 are the drains of the PMOS tubes. The second switch Q2 and the fourth switch Q4 are NMOS tubes, the second end of the second switch Q2 and the first end of the fourth switch Q4 are the sources of the NMOS tubes, and the first end of the second switch Q2 and the second end of the fourth switch Q4 are the drains of the NMOS tubes.

[0045] Specifically, the operational amplifier U2 as the "error correction center" of the circuit stabilizes the circuit state through a feedback mechanism: the inverting input is connected with the second end of the first switch Q1, the first end of the second switch Q2 and the output end of itself, forming a negative feedback loop; the non-inverting input is connected with the second end of the third switch Q3 and the first end of the fourth switch Q4, receiving signals from the loop filter circuit 5; the output end adjusts the output voltage in real time through the connection with the inverting input, ensuring the signal stability of the non-inverting input and the inverting input, and providing an accurate reference for the switching action.

[0046] Specifically, the core of the switching circuit 2 is to control the on-off state of the four switches through a pair of complementary differential signals (the non-inverting signal of the second inverter N2 and the inverting signal of the third inverter N3) output by the single-ended to differential circuit 1, so as to realize the alternation of the charging and discharging processes:

[0047] (1) When the second inverter N2 outputs a high level (the non-inverting signal is valid) and the third inverter N3 outputs a low level (the inverting signal is invalid), Q1 and Q4 are turned on, and Q2 and Q3 are turned off. At this time, the current output by the charging current source 3 flows into the discharge current source 4 side through the inverting input of the operational amplifier U2 and Q4, but the discharge current source 4 does not work because Q2 is turned off. Therefore, the current actually flows through the turned-on Q1 and Q4 to charge the loop filter circuit 5, starting the charging process.

[0048] (2) When the second inverter N2 outputs a low level (the non-inverting signal is invalid) and the third inverter N3 outputs a high level (the inverting signal is valid), Q1 and Q4 are turned off, and Q2 and Q3 are turned on. At this time, the discharge current source 4 is started, and the current flows into the loop filter circuit 5 through Q2, the inverting input of the operational amplifier U2 and Q3, accelerating the discharge of the energy storage element, starting the discharging process.

[0049] In this embodiment, the switching circuit 2 realizes the alternating action of the charging current and the discharging current through the orderly on-off of the four switches under the control of the complementary differential signals, in cooperation with the feedback regulation of the operational amplifier U2. During charging, the current flows through Q1 and Q4 to the loop filter circuit 5 to store energy; during discharging, the current flows through Q2 and Q3 to accelerate the release of energy storage. This structure not only ensures the strict separation of the charging and discharging processes (to avoid current conflict), but also stabilizes the circuit state through the feedback of the operational amplifier U2, providing a reliable hardware foundation for the accurate output of the clock delay signal.

[0050] In some optional embodiments, for example, Figure 5As shown, the charging current source 3 comprises a fifth switch MP1 and a sixth switch MP2, wherein the first end of the fifth switch MP1 is connected to the supply voltage, the second end of the fifth switch MP1 is connected to the first end of the sixth switch MP2, and the control end of the fifth switch MP1 is connected to the first control voltage; the second end of the sixth switch MP2 is connected to the first end of the switch circuit 2, and the control end of the sixth switch MP2 is connected to the first control signal.

[0051] Optionally, the fifth switch MP1 and the sixth switch MP2 are both PMOS tubes, the first end of the fifth switch MP1 and the first end of the sixth switch MP2 are the sources of the PMOS tubes, and the second end of the fifth switch MP1 and the second end of the sixth switch MP2 are the drains of the PMOS tubes.

[0052] Specifically, the fifth switch MP1 is an "upstream regulation valve" of the charging current source 3, and its connection is directly related to the basic supply of current: the first end is connected to the supply voltage, which is the energy source of the entire charging current source 3, providing a stable voltage basis for subsequent current output; the second end is connected to the first end of the sixth switch MP2, forming a cascaded path, so that the current flows to the switch circuit 2 through MP1 and MP2 in sequence; the control end is connected to the first control voltage, which determines the conduction degree of MP1. Unlike simple on-off control, the first control voltage can precisely control the current size by adjusting the conduction resistance of MP1 (such as the gate voltage affecting the channel resistance in a MOS tube), which is the core link for realizing fine adjustment of the charging current.

[0053] Specifically, the sixth switch MP2 is a "downstream switch valve" of the charging current source 3, and its role is more inclined to the on-off management of the path: the first end is connected to the second end of the fifth switch MP1 to receive the current regulated by MP1; the second end is directly connected to the first end of the switch circuit 2 to deliver the final charging current to the switch circuit 2 and participate in the subsequent charging and discharging process; the control end is connected to the first control signal, which is a digital logic signal (such as high / low level), directly controlling the conduction or shutdown of MP2. When the first control signal is valid, MP2 is turned on, and the charging current source 3 forms a path with the switch circuit 2; when it is invalid, MP2 is turned off, cutting off the charging current output, ensuring that the charging process is started only when needed.

[0054] In this embodiment, the charging current source 3 is cascaded through the fifth switch MP1 (the first control voltage regulates the current size) and the sixth switch MP2 (the first control signal controls the on-off), realizing double control of the charging current: the current intensity can be finely adjusted through MP1 to meet the needs of different delay accuracy, and the timing of current output can be precisely controlled through MP2 to ensure the working state of the switch circuit 2. This structure takes into account the flexibility of adjustment and the reliability of control, providing a solid support for the precise regulation of the charging process in the clock delay circuit.

[0055] In some optional embodiments, as shown in Figure 5 The discharge current source 4 includes a seventh switch MN2 and an eighth switch MN1. The first end of the seventh switch MN2 is connected to the second end of the switch circuit 2, the second end of the seventh switch MN2 is connected to the first end of the eighth switch MN1, and the control end of the seventh switch MN2 is connected to the second control signal. The second end of the eighth switch MN1 is grounded, and the control end of the eighth switch MN1 is connected to the second control voltage.

[0056] Optionally, the seventh switch MN2 and the eighth switch MN1 are both NMOS tubes, the first end of the seventh switch MN2 and the first end of the eighth switch MN1 are the drains of the NMOS tubes, and the second end of the seventh switch MN2 and the second end of the eighth switch MN1 are the sources of the NMOS tubes.

[0057] Specifically, the seventh switch MN2 serves as the "front-end switch" of the discharge current source 4 and undertakes the on-off control role of the discharge path. The first end is directly connected to the second end of the switch circuit 2, which is the entrance of the discharge current, meaning that the charge to be released from the switch circuit 2 needs to flow through MN2 first. The second end is connected to the first end of the eighth switch MN1, forming a cascaded structure, so that the discharge current must pass through MN2 and MN1 in sequence to complete the grounding release. The control end is connected to the second control signal, which is a digital logic signal (such as high-level active or low-level active), directly determining the conduction state of MN2. When the second control signal is active, MN2 is turned on to provide a flow path for the discharge current; when it is inactive, MN2 is turned off to cut off the discharge path, ensuring that the discharge process is started only when needed.

[0058] Specifically, the eighth switch MN1 serves as the "back-end regulator" of the discharge current source 4 and is responsible for fine control of the size of the discharge current. The first end is connected to the second end of the seventh switch MN2 to receive the discharge current transmitted through MN2. The second end is directly grounded to form the final loop of the discharge current, allowing the charge to be released through the grounding end. The control end is connected to the second control voltage, which continuously adjusts the size of the discharge current by changing the conduction degree of MN1 (for example, in MOS tubes, the change of gate voltage will affect the channel resistance). Different voltage values will result in different conduction resistances of MN1, thereby causing differences in the discharge current flowing through.

[0059] In this embodiment, the discharge current source 4 realizes the "on-demand start" and "rate controllability" of the discharge process through the timing control of the seventh switch MN2 and the current regulation of the eighth switch MN1. The symmetrical design with the charging current source 3 further ensures the adjustment balance of the clock delay circuit in both charging and discharging directions, providing a reliable current release mechanism for realizing stable and accurate clock signal delay. Whether it is fast discharge to shorten the delay or slow discharge to extend the delay, this structure can accurately meet the timing requirements in different scenarios through the cooperative work of the two-stage switches.

[0060] In some optional embodiments, as shown in Figure 6 The loop filter circuit 5 includes a first resistor R1 and a first capacitor C1, wherein the first end of the first resistor R1 is connected with the third end of the switch circuit 2, and the second end of the first resistor R1 is grounded through the first capacitor C1.

[0061] Specifically, the delay effect of the loop filter circuit 5 is derived from the charging and discharging characteristics of the RC circuit. During the charging and discharging process, the voltage change at both ends of C1 follows the exponential law (the voltage gradually approaches the supply voltage from 0 during charging, and gradually approaches 0 from the supply voltage during discharging), and the voltage at the output node of the clock delay signal (i.e. the connection point of R1 and C1) needs to reach a certain threshold value to trigger an effective signal. The charging and discharging time constant τ (τ = R1 x C1) directly determines the time when the voltage reaches the threshold value - the larger the τ value, the slower the charging and discharging speed, and the longer the delay time. By adjusting the parameters of R1 or C1, the τ value can be flexibly changed, thereby realizing accurate control of the delay range.

[0062] When the switch circuit 2 switches the charging and discharging states, the output current may be accompanied by high-frequency noise or transient pulses, and the RC structure can effectively filter out these disturbances. The hindering effect of R1 on high-frequency signals and the bypassing characteristics of C1 on high-frequency signals (high-frequency signals are more likely to pass through the capacitor to ground) can greatly attenuate the high-frequency components in the current, making the voltage change at both ends of C1 smoother and avoiding the jitter of the delay signal caused by noise. This filtering effect ensures that the output clock delay signal has good stability and provides a reliable timing reference for subsequent circuits.

[0063] Specifically, the loop filter circuit 5 is connected with the switch circuit 2 through R1, becoming the "necessary passage" of the charging and discharging current. When the charging current source 3 works, the current flows into R1 through the switch circuit 2, and then slowly charges C1, and the energy stored in C1 gradually increases, and the voltage across the two ends steadily rises; when the discharging current source 4 works, the energy stored in C1 flows to the ground end through R1 and the switch circuit 2, and the voltage steadily decreases. The accumulation and release process of such energy is directly converted into the time delay of the voltage signal, and the parameters of R1 and C1 determine the rate of voltage change, ultimately affecting the accuracy and adjustable range of the clock delay signal. It can be said that the loop filter circuit 5 is a "converter" that converts current change into time delay, and is the core carrier for the whole clock delay circuit to realize accurate delay control.

[0064] In some optional embodiments, the clock delay circuit further comprises: an inverting circuit, wherein a first end of the inverting circuit is connected to the first control signal, and a second end of the inverting circuit is connected to the control end of each charging current source 3.

[0065] Optionally, as shown in Figure 5 the inverting circuit comprises: a fourth inverter N4, wherein an input end of the fourth inverter N4 is connected to the first control signal, and an output end of the fourth inverter N4 is connected to the control end of each charging current source 3.

[0066] For example, taking the sixth switch MP2 in the charging current source 3 as an example (the control end thereof needs to be connected to the control signal to determine whether to conduct or not): if the sixth switch MP2 is a high-level conduction type, and the effective level (i.e. the level triggering charging) of the original first control signal is low, then direct connection will cause the switch to fail to normally conduct. At this time, the inverting circuit (such as the fourth inverter N4) inverts the low-level first control signal to high level, which exactly meets the conduction condition of the sixth switch MP2, ensuring that the charging current source 3 can be reliably started when needed.

[0067] On the contrary, if the effective level of the first control signal is consistent with the requirement of the switch, the introduction of the inverting circuit can also realize "in-phase delay" through multiple levels of inversion. By using the inherent transmission delay of the inverter, the trigger time of the control signal is fine-tuned, so that the start of the charging current and the path establishment of the switch circuit 2 form a small time sequence difference, reduce the instantaneous current impact, and improve the stability of the circuit.

[0068] In some optional embodiments, in the clock delay circuit, the delay precision and the phase consistency of the multi-phase clock are greatly affected by environmental factors such as temperature, power voltage fluctuation and chip aging, resulting in insufficient performance stability in high-precision timing control scenarios (such as high-speed communication, precision measurement, etc.). Therefore, an environmental parameter real-time monitoring and adaptive compensation module is introduced. Specifically, the environmental parameter monitoring unit integrates a micro temperature sensor and a voltage sensor, which real-time collects the temperature and power voltage data of the circuit working environment, and converts them into digital signals transmitted to the adaptive compensation algorithm unit. The adaptive compensation algorithm unit calculates the delay deviation under the current environment based on the preset temperature-delay characteristic curve, voltage-delay characteristic curve (obtained through multi-temperature zone and multi-voltage point calibration before leaving the factory), and the real-time monitoring data, and then generates the corresponding compensation control signal. The compensation control signal is transmitted to the programmable delay unit in the delay chain circuit, and the real-time calibration of the clock delay is realized by dynamically adjusting the load capacitance or the size of the current source of the delay unit.

[0069] In the embodiment, a multi-phase clock generation device is provided, as shown in Figure 7 The device comprises a phase discriminator 6, an oscillation circuit 7, and a clock delay circuit and an oscillation circuit 7 of any one of the above embodiments and optional embodiments thereof. The clock delay circuit comprises a single-ended to differential circuit 1, a switch circuit 2, a plurality of charging current sources 3, a plurality of discharging current sources 4, and a loop filter circuit 5.

[0070] As shown in Figure 7 The first input end of the phase discriminator 6 is connected to the clock signal, the second input end of the phase discriminator 6 is connected to the output end of the oscillation circuit 7, and the output end of the phase discriminator 6 is connected to the input end of the single-ended to differential circuit 1. The input end of the single-ended to differential circuit 1 receives the clock signal, and the first output end and the second output end of the single-ended to differential circuit 1 are connected to the control end of the switch circuit 2. The input end of each charging current source 3 is connected to the power supply voltage, the output end of each charging current source 3 is connected to the first end of the switch circuit 2, and the control end of each charging current source 3 is connected to the first control signal. The input end of each discharging current source 4 is connected to the second end of the switch circuit 2, the output end of each discharging current source 4 is grounded, and the control end of each charging current source 3 is connected to the second control signal. The third end of the switch circuit 2 is connected to the ground through the loop filter circuit 5, and the third end of the switch circuit 2 is connected to the input end of the oscillation circuit 7. The output end of the oscillation circuit 7 outputs a multi-phase clock signal. In one control period, the first control signal and the second control signal are complementary.

[0071] Specifically, the phase discriminator 6 is the "signal comparison center" of the device, the first input end of which is specially connected to the external reference clock signal, and the second input end is connected to the output end of the oscillation circuit 7 to receive the feedback signal from the oscillation circuit 7. By comparing the phase difference of the two signals, the phase discriminator 6 can generate a corresponding error control signal and transmit it from the output end to the input end of the single-ended-to-differential circuit 1 in the clock delay circuit. This connection forms a closed loop of "input reference-feedback comparison-error output", which ensures that the device can adjust the working state of the delay circuit in real time according to the phase deviation of the output signal.

[0072] Specifically, the oscillation circuit 7 is a "multi-phase signal generator" of the device, the input end of which receives the delay signal from the clock delay circuit, and the single delay signal is converted into a multi-phase clock signal through the internal oscillation mechanism (such as a ring oscillator or an LC oscillator) and output from the output end. At the same time, the output end of the oscillation circuit 7 is also connected to the second input end of the phase discriminator 6 to form a signal feedback, so that the phase discriminator 6 can continuously monitor the phase state of the output signal to provide a basis for the adjustment of the delay circuit.

[0073] Specifically, Figure 7 In this way, the phase discriminator 6 and the clock delay circuit form a PLL loop, and the frequency of the oscillation circuit 7 is locked on the input clock frequency by the PLL loop. Since the input and output frequencies are equal, a wide loop bandwidth can be obtained at a high clock frequency, thereby significantly suppressing the phase noise of the ring oscillator, achieving low jitter, maintaining low power consumption of the ring oscillator, and avoiding the problem of phase interval mismatch caused by injection locking.

[0074] In some optional embodiments, as shown in Figure 8 The phase discriminator includes an XOR gate U3, wherein the first input end of the XOR gate U3 is connected to the clock signal, the second input end of the XOR gate U3 is connected to the output end of the oscillation circuit 7, and the output end of the XOR gate U3 is connected to the input end of the single-ended-to-differential circuit 1. It should be noted that Figure 8 The internal structure of the current adjustable charge pump is as shown in Figure 7 That is, the current adjustable charge pump is composed of the single-ended-to-differential circuit 1, the charging current source 3, the discharging current source 4, and the switching circuit 2.

[0075] Referring to Figure 8 , the entire multi-phase clock circuit is generated by a PLL based on the XOR gate U3, including the XOR gate U3, the charge pump circuit, the loop filter circuit 5, and the oscillation circuit 7. Through the PLL, the output multi-phase clock is locked on the frequency of the input single-phase clock, thereby realizing the generation of the multi-phase clock.

[0076] Specifically, when the feedback signal output by the oscillation circuit 7 lags behind the reference clock signal, the width of the high-level pulse output by the XOR gate U3 will increase as the lag angle increases. After this signal is transmitted to the clock delay circuit, it will trigger the charging current source 3 to increase the charging current (or the discharging current source 4 to decrease the discharging current), accelerate the charging and discharging speed of the loop filter circuit 5, thereby shortening the delay time and pushing the output phase of the oscillation circuit 7 to adjust forward until it is in phase with the reference clock signal.

[0077] In some alternative implementations, such as Figure 8 As shown, the charge pump in the PLL includes a charging current I. UP and discharge current I DN When the XOR gate U3 outputs a high level, the charge pump charges the loop filter circuit 5; when the XOR gate U3 outputs a low level, the charge pump discharges the loop filter circuit 5. Assume the high-level pulse width of the XOR gate U3 output signal is τ. UP The low-level pulse width is τ DN Therefore, the following conditions must be met when the PLL is locked:

[0078] (1)

[0079] (2)

[0080] When the phase-locked loop is locked and I UP =I DN At that time, τ UP =τ DN =T CK / 4, where TCK is the period of the output and input clocks (input and output clocks have the same frequency). According to the PLL locking timing of the XOR gate U3, the delay difference between the rising edge of the input clock and the next rising edge of the feedback clock when the PLL is locked is τ. UP .

[0081] If I change UP and I DN The ratio between them can be obtained from formulas (1) and (2), τ UP and τ DN The delay of the output multiphase clock relative to the input clock will change synchronously, thus achieving synchronously adjustable multiphase clock delays and preventing mismatch between the delays of clocks of different phases. τ can be obtained from formulas (1) and (2). UP and τ DN The expression is shown below.

[0082] (3)

[0083] (3)

[0084] Thus, by controlling the ratio between I UP and I DN , τ UP and τ DN can be adjusted, thereby controlling the delay of the output multi-phase clock.

[0085] In some optional embodiments, as shown in FIG. 7, the oscillation circuit 7 comprises a ninth switch Q9 and at least one differential unit 71, wherein the first end of the ninth switch Q9 is connected with the power supply, the second end of the ninth switch Q9 is connected with the input end of the differential unit 71, the control end of the ninth switch Q9 is connected with the third end of the switch circuit 2, and the output end of the differential unit 71 outputs the multi-phase clock signal. Figure 9 Specifically, the ninth switch Q9 serves as an “input control valve” of the oscillation circuit 7, and the first end thereof is directly connected with the third end of the switch circuit 2 to receive the delay signal from the clock delay circuit, which is smoothed by the loop filter circuit 5 and serves as the reference for the oscillation circuit 7 to generate the multi-phase clock. The second end is connected with the input end of the differential unit 71 to form a signal transmission link of “delay signal→ninth switch Q9→differential unit 71”, thereby ensuring that the delay signal can be stably input to the oscillation core. The control end is connected with the tuning voltage, which adjusts the signal strength input to the differential unit 71 by changing the conduction characteristic (such as the channel resistance of the MOS tube) of Q9. For example, when the tuning voltage rises, the conduction resistance of Q9 decreases, more energy is transferred to the differential unit 71, and the oscillation frequency can be increased; when the tuning voltage decreases, the conduction resistance increases, the energy transfer is weakened, and the oscillation frequency decreases. This design enables the oscillation circuit 7 to flexibly adjust the frequency of the output clock within a certain range, thereby adapting to the timing requirements of different scenarios.

[0086] Specifically, the differential unit 71 is the “core oscillator” of the oscillation circuit 7 to generate the multi-phase clock, and the number thereof can be flexibly set according to the number of required phases (for example, two differential units 71 can be cascaded to generate a four-phase clock). Each differential unit 71 is usually composed of a pair of complementary amplification tubes and a load element (such as a resistor or a current source), and has the functions of differential signal amplification and phase shift. The input end is connected with the second end of the ninth switch Q9 to receive the tuned delay signal, which serves as the excitation of the differential unit 71 to trigger the internal oscillation mechanism. The output end can directly output the differential form of the clock signal, and the cascade or phase staggered layout of multiple differential units 71 can generate a multi-phase clock with fixed phase difference. For example, a single differential unit 71 outputs two-phase quadrature signals (0° and 180°), and two differential units 71 in cascade can be expanded to four-phase signals (0°, 90°, 180°, and 270°), with strictly equal phase difference, thereby ensuring the timing consistency of the multi-phase clock.

[0087] ​

[0088] In some alternative implementations, such as Figure 9 As shown, the differential unit 71 includes: a first main inverter INV1, a second main inverter INV2, a first cross-coupled inverter INV3, and a second cross-coupled inverter INV4. The input terminal of the first main inverter is connected to the second terminal of the ninth switch Q9, and the output terminal of the first main inverter is connected to the input terminal of the first cross-coupled inverter and the output terminal of the second cross-coupled inverter, outputting one phase clock signal. The input terminal of the second main inverter is connected to the second terminal of the ninth switch Q9, and the output terminal of the second main inverter is connected to the output terminal of the first cross-coupled inverter and the input terminal of the second cross-coupled inverter, outputting another phase clock signal.

[0089] In a practical application scenario, based on Figure 4 , Figure 5 , Figure 8 , Figure 9 The process of obtaining the multiphase clock signal in this embodiment is as follows:

[0090] (1) Taking a 1 / 4 rate D2D interconnect interface as an application scenario, a multi-phase clock circuit with a four-phase clock and a delay adjustment range of TCK / 4 (i.e., one data symbol length) needs to be implemented. The overall architecture is as follows: Figure 8 As shown, it includes an XOR gate U3, a current-adjustable charge pump circuit, a loop filter circuit 5, and an oscillation circuit 7. The oscillation circuit 7 is a four-phase voltage-controlled ring oscillator (VCO), which converts the input single-phase or differential clock into a four-phase clock at the same frequency through the PLL, and can tune the delay relationship between the output clock and the input clock.

[0091] (2) The cascaded gain expression of the XOR gate U3 and the charge pump circuit is K. XOR-CP =(I UP +I DN From this, we can deduce that the loop bandwidth expression of the PLL is f / π. BW =K XOR-CP R1K VCO K VCO The tuning gain of the VCO can be determined through simulation. To significantly suppress the phase noise of the ring oscillation, f... BW It needs to be as large as possible, taking into account system stability, f BW It can be selected as 1 / 10 of the clock frequency. Determine f. BW and K VCO Then, R1 and C1 are determined to ensure that the zero point of the loop is less than f. BW One-third of the value is used to maintain loop stability. The larger R1 is, the smaller IC is. UP +I DNThe smaller the R1 value, the higher the jitter will be; therefore, a trade-off needs to be considered. Once R1 and C1 are determined, the bandwidth requirement can be used to determine (I...). UP +I DN ).

[0092] (3) The charge pump circuit in the PLL is as follows Figure 5 As shown, the charge pump employs a current-rudder structure, ensuring that the current source within the pump is always on, thus enabling rapid switching between current charging and discharging to meet the demands of high-speed D2D applications. Since the current-rudder structure requires a differential phase detector output signal to switch between two complementary current paths, and the XOR gate U3 outputs a single-ended signal, a single-ended to differential converter is needed to convert the single-ended pulse from the phase detector output into a differential pulse to control the charge pump.

[0093] (4) The charging and discharging currents of the charge pump are both composed of multiple gated current source units. The discharging current source 4 unit is composed of a current source transistor MN1 operating in the saturation region and a switching transistor MN2, and the charging current source 3 unit is composed of a current source transistor MP1 operating in the saturation region and a switching transistor MP2. The switching control signal bit SWP for the charging current and the switching control signal bit SWN for the discharging current are set to a complementary relationship, that is, each time a charging current source 3 unit is turned on, a discharging current source 4 unit is turned off, and vice versa. This allows for the adjustment of the delay while maintaining (I UP +I DN This ensures that the PLL maintains a constant loop bandwidth and can operate stably under different delays.

[0094] (5) The four-phase ring oscillator in the PLL is as follows Figure 9 As shown, the ring oscillator is constructed using two differential units 71, enabling it to output a four-phase clock. Each differential unit 71 consists of a main inverter (INV1) and a cross-coupled inverter (INV2). INV2 ensures that both stages of the ring oscillator can oscillate and that the input and output signals of each stage are differential. The ring oscillator uses a current source composed of a PMOS transistor MP to convert its tuning voltage VC into a current to tune and change the frequency of the VCO. The operating frequency is adjusted by changing the width-to-length ratio of the transistors INV1 and INV2, as well as the ratio of their width-to-length ratios.

[0095] The clock delay circuit and multiphase clock generation device provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A multiphase clock generation device, characterized in that, include: The circuit includes a phase detector, an oscillation circuit, and a clock delay circuit. The clock delay circuit comprises a single-ended to differential converter, a switching circuit, multiple charging current sources, multiple discharging current sources, and a loop filter circuit. The first input terminal of the phase detector circuit is connected to a clock signal, the second input terminal of the phase detector circuit is connected to the output terminal of the oscillation circuit, and the output terminal of the phase detector circuit is connected to the input terminal of the single-ended to differential circuit. The first and second output terminals of the single-ended to differential circuit are connected to the control terminal of the switching circuit. The input terminal of each charging current source is connected to the power supply voltage, the output terminal of each charging current source is connected to the first terminal of the switching circuit, and the control terminal of each charging current source is connected to the first control signal. The input terminal of each discharge current source is connected to the second terminal of the switching circuit, the output terminal of each discharge current source is grounded, and the control terminal of each discharge current source is connected to the second control signal. The third terminal of the switching circuit is grounded through the loop filter circuit, and the third terminal of the switching circuit is connected to the input terminal of the oscillation circuit. The output terminal of the oscillation circuit outputs a multi-phase clock signal; Within one control cycle, the first control signal and the second control signal are complementary; The delay of the multiphase clock output is synchronized by adjusting the ratio of charging current to discharging current. For each charging current source turned on, a discharging current source is turned off, and vice versa, so as to keep the sum of the charging current and the discharging current constant while adjusting the delay, thereby maintaining a constant loop bandwidth. The oscillation circuit includes: a ninth switch and at least one differential unit, wherein the first terminal of the ninth switch is connected to a power supply, the second terminal of the ninth switch is connected to the input terminal of the differential unit, and the control terminal of the ninth switch is connected to the third terminal of the switching circuit; the output terminal of the differential unit outputs a multi-phase clock signal. The differential unit includes: a first main inverter, a second main inverter, a first cross-coupled inverter, and a second cross-coupled inverter. The input terminal of the first main inverter is connected to the second terminal of the ninth switch, and the output terminal of the first main inverter is connected to the input terminal of the first cross-coupled inverter and the output terminal of the second cross-coupled inverter, outputting one phase clock signal. The input terminal of the second main inverter is connected to the second terminal of the ninth switch, and the output terminal of the second main inverter is connected to the output terminal of the first cross-coupled inverter and the input terminal of the second cross-coupled inverter, outputting another phase clock signal.

2. The multiphase clock generation device according to claim 1, characterized in that, The phase detection circuit includes an XOR gate, wherein... The first input terminal of the XOR gate is connected to the clock signal, the second input terminal of the XOR gate is connected to the output terminal of the oscillation circuit, and the output terminal of the XOR gate is connected to the input terminal of the single-ended to differential circuit.

3. The multiphase clock generation device according to claim 1, characterized in that, The single-ended to differential circuit includes: a first inverter, a second inverter, a third inverter, and a transmission gate, wherein, The input terminal of the first inverter is connected to the input terminal of the transmission gate, and the clock signal is also connected to the input terminal of the first inverter. The output terminal of the first inverter is connected to the input terminal of the second inverter. The output terminal of the second inverter is connected to part of the control terminal of the switching circuit; The input terminal of the third inverter is connected to the input terminal of the transmission gate, and the output terminal of the third inverter is connected to the control terminals of other parts of the switching circuit.

4. The multiphase clock generation device according to claim 1, characterized in that, The charging current source includes: a fifth switch and a sixth switch, wherein, The first terminal of the fifth switch is connected to the power supply voltage, the second terminal of the fifth switch is connected to the first terminal of the sixth switch, and the control terminal of the fifth switch is connected to the first control voltage. The second terminal of the sixth switch is connected to the first terminal of the switch circuit, and the control terminal of the sixth switch is connected to the first control signal.

5. The multiphase clock generation device according to claim 1, characterized in that, The discharge current source includes: a seventh switch and an eighth switch, wherein... The first terminal of the seventh switch is connected to the second terminal of the switch circuit, the second terminal of the seventh switch is connected to the first terminal of the eighth switch, and the control terminal of the seventh switch is connected to the second control signal; The second terminal of the eighth switch is grounded, and the control terminal of the eighth switch is connected to the second control voltage.

6. The multiphase clock generation device according to claim 1, characterized in that, The loop filter circuit includes: a first resistor and a first capacitor, wherein... The first end of the first resistor is connected to the third end of the switching circuit, and the second end of the first resistor is grounded through the first capacitor.

7. The multiphase clock generation device according to claim 1, characterized in that, Also includes: inverted The circuit, in which, The first terminal of the inverting circuit is connected to the second control signal, and the second terminal of the inverting circuit is connected to the control terminal of each of the charging current sources.

8. The multiphase clock generation device according to claim 7, characterized in that, The inverting circuit includes: a fourth inverter, wherein, The input terminal of the fourth inverter is connected to the second control signal, and the output terminal of the fourth inverter is connected to the control terminal of each of the charging current sources.

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