Voltage generation circuit and writing device

Abstract

A voltage generation circuit and a write device. Provided is a voltage generation circuit capable of setting an output voltage with high resolution. A voltage generation circuit is provided with: a smoothing circuit to which a pulse width modulation signal is input and which outputs, to a first node, a voltage obtained by smoothing the pulse width modulation signal; a first resistor connected between the output node and the second node; a second resistor connected between the first node and the second node; a third resistor connected between the second node and a ground node; and a voltage control circuit that generates a second voltage on the basis of a first voltage input to an input node, outputs the second voltage to the output node, and controls the second voltage such that the voltage of the second node becomes a predetermined voltage.

Description

Technical Field

[0001] The present invention relates to a voltage generating circuit and a writing device. Background Art

[0002] Patent Document 1 describes a power supply circuit equipped with a variable output regulator, enabling simple and highly accurate user settings. In the power supply circuit described in Patent Document 1, the output from a microcomputer is converted into a pulse-width modulated signal, which is smoothed and then input to the other end of a resistor connected to the output terminal of the variable output regulator.

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 9-034568

[0004] In the power supply circuit described in Patent Document 1, it is difficult to expand the setting range of the pulse width of the pulse width modulation signal that can change the output voltage. As a result, the resolution of the output voltage change becomes low. Summary of the Invention

[0005] One embodiment of a voltage generating circuit according to the present invention includes:

[0006] a smoothing circuit which receives a pulse width modulation signal as input and outputs a voltage obtained by smoothing the pulse width modulation signal to the first node;

[0007] a first resistor connected between the output node and the second node;

[0008] a second resistor connected between the first node and the second node;

[0009] a third resistor connected between the second node and a ground node; and

[0010] The voltage control circuit generates a second voltage based on a first voltage input to an input node and outputs the second voltage to the output node, and controls the second voltage so that the voltage of the second node becomes a predetermined voltage.

[0011] One embodiment of the writing device according to the present invention includes:

[0012] One embodiment of the voltage generating circuit; and

[0013] a pulse width modulation circuit that generates the pulse width modulation signal and outputs it to the voltage generation circuit,

[0014] The second voltage generated by the voltage generating circuit is supplied to an electronic component. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1It is a diagram showing the configuration of the voltage generating circuit according to the first embodiment.

[0016] Figure 2 It is a diagram showing a configuration example of a regulator.

[0017] Figure 3 This is a diagram showing an example of the relationship between the pulse width modulation signal and the voltage in the voltage generating circuit according to the first embodiment.

[0018] Figure 4 1 is a diagram showing a configuration of a voltage generating circuit according to a comparative example.

[0019] Figure 5 1 is a diagram showing an example of the relationship between a pulse width modulation signal and voltage in a voltage generating circuit of a comparative example.

[0020] Figure 6 It is a diagram showing the configuration of a voltage generating circuit according to the second embodiment.

[0021] Figure 7 It is a diagram showing a configuration example of a DC-DC converter.

[0022] Figure 8 This is a functional block diagram of the writing device of this embodiment.

[0023] Description of labels

[0024] 1, 1A: Voltage generation circuit; 10: Voltage control circuit; 11: Regulator; 12: Reference voltage generation circuit; 13: Error amplifier; 14: MOSFET; 20: Logic buffer; 30: Smoothing circuit; 31: Resistor; 32: Capacitor; 41, 42, 43: Resistors; 44, 45: Capacitors; 50: Voltage control circuit; 51: DC-DC converter; 52: Inductor; 53: Diode; 54: Reference voltage generation circuit; 55: Error amplifier; 56: Pulse-width modulation circuit; 57: MOSFET; 100: Writing device; 110: Microcontroller unit; 111: Control circuit; 112: A / D conversion circuit; 113: Pulse-width modulation circuit; 114, 115: General-purpose input / output circuit; 120: Reference voltage generation circuit; 130: Switch circuit; 140, 141, 142, 143: Digital input / output circuit; 200: Personal computer; 300: Electronic component. DETAILED DESCRIPTION

[0025] Hereinafter, preferred embodiments of the present invention will be described in detail using the accompanying drawings. In addition, the embodiments described below do not unduly limit the contents of the present invention as described in the claims. In addition, the structures described below are not necessarily all essential structural elements of the present invention.

[0026] 1. Voltage generation circuit

[0027] 1-1. First embodiment

[0028] The voltage generating circuit according to the first embodiment is a linear regulator that steps down an input voltage and outputs the resultant voltage. Figure 1 1 is a diagram showing the structure of the voltage generating circuit of the first embodiment. Figure 1 As shown, the voltage generating circuit 1 of the first embodiment includes a voltage control circuit 10 , a logic buffer 20 , a smoothing circuit 30 , resistors 41 , 42 , and 43 , and capacitors 44 and 45 .

[0029] Logic buffer 20 buffers the pulse-width modulation signal PWMIN input from outside voltage generation circuit 1 and outputs a pulse-width modulation signal PWMX, which is a combination of power supply voltage VCC set to a high level and ground voltage VSS set to a low level. Power supply voltage VCC is supplied from outside voltage generation circuit 1 and is, for example, 3.3V. Logic buffer 20 can also be replaced with a logic inverter that outputs a pulse-width modulation signal PWMX that is a logical inversion of pulse-width modulation signal PWMIN.

[0030] Smoothing circuit 30 receives a pulse-width modulated signal PWMX as input and outputs a voltage V1 smoothed from the pulse-width modulated signal PWMX to node N1. Specifically, smoothing circuit 30 is a low-pass filter consisting of a resistor 31 and a capacitor 32 connected in series between the output terminal of logic buffer 20 and ground. The node where resistor 31 and capacitor 32 are connected is node N1.

[0031] The voltage V1 of the node N1 is an average voltage of the pulse width modulation signal PWMX. If the period of the pulse width modulation signal PWMX is tPeriod and the high-level pulse width is tWHigh, it is expressed by equation (1).

[0032]

[0033] Resistor 41 is connected between output node NO and node N2. Resistor 42 is connected between node N1 and node N2. Resistor 43 is connected between node N2 and ground node NG.

[0034] Capacitor 44 is connected between input node NI and ground node NG. Capacitor 45 is connected between output node NO and ground node NG.

[0035] The voltage control circuit 10 includes a regulator 11. The regulator 11 has an input terminal IN, an output terminal OUT, a feedback terminal FB, and a ground terminal GND. The regulator 11 outputs a voltage from the output terminal OUT that is a step-down voltage from the input terminal IN, with the voltage supplied to the ground terminal GND as a reference. Furthermore, the regulator 11 controls the voltage input to the feedback terminal FB so that it matches a predetermined voltage, thereby outputting a constant voltage from the output terminal OUT.

[0036] Figure 2 1 is a diagram showing a configuration example of the regulator 11. Figure 2 As shown, the regulator 11 includes a reference voltage generating circuit 12, an error amplifier 13, and a P-channel MOSFET 14. MOSFET is an abbreviation of Metal Oxide Semiconductor Field Effect Transistor.

[0037] The reference voltage generating circuit 12 generates a constant reference voltage VREF and outputs it to the inverting input terminal of the error amplifier 13. For example, the reference voltage generating circuit 12 utilizes the bandgap voltage of silicon to generate a constant reference voltage VREF regardless of the power supply voltage or temperature.

[0038] The non-inverting input terminal of the error amplifier 13 is connected to the feedback terminal FB. Therefore, the error amplifier 13 compares the voltage of the feedback terminal FB with the reference voltage VREF and controls the gate voltage of the MOSFET 14 so that the voltage of the feedback terminal FB matches the reference voltage VREF.

[0039] MOSFET 14 has a gate connected to the output terminal of error amplifier 13, a source connected to input terminal IN, and a drain connected to output terminal OUT. The voltage VFB at feedback terminal FB is the voltage obtained by dividing the output voltage VOUT by two resistors 41 and 42. If this divided voltage falls below reference voltage VREF, the gate voltage of MOSFET 14 decreases, the current supply capability of MOSFET 14 increases, and output voltage VOUT increases. When the divided voltage VFB matches reference voltage VREF, a balanced state is achieved. In the opposite case, the same operation is performed, controlling the current supply capability of MOSFET 14 so that reference voltage VREF and divided voltage VFB match, resulting in a constant output voltage VOUT.

[0040] like Figure 1As shown, the input terminal IN of the regulator 11 is connected to the input node NI, the output terminal OUT is connected to the output node NO, the feedback terminal FB is connected to the node N2, and the ground terminal GND is connected to the ground node NG. A voltage VIN is input to the input node NI from outside the voltage generating circuit 1, and a ground voltage VSS is supplied to the ground node NG. Therefore, the regulator 11 compares the voltage at the node N2 with a reference voltage VREF, which is a predetermined voltage, and controls the current supply capacity from the input terminal IN to the output terminal OUT based on the comparison result. In addition, the voltage VIN is a voltage higher than the output voltage VOUT, for example, 5V. If the feedback voltage based on the voltage VOUT of NO is VFB, and the resistance values ​​of the resistors 41, 42, 43, and 31 are set to R1, R2, R3, and R4, respectively, the currents I1, I2, and I3 flowing through the resistors 41, 42, and 43 are expressed by equations (2), (3), and (4), respectively.

[0041]

[0042] According to equation (2), the voltage VOUT of the output node NO is expressed by equation (5). Substituting equations (3) and (4) into equation (5), equation (6) is obtained.

[0043] VOUT=VFB+R1×I1=VFB+R1×(I2+I3)…(5)

[0044]

[0045] The voltage control circuit 10 generates a voltage VOUT based on the voltage VIN input to the input node N1 and outputs it to the output node NO. The voltage VOUT is controlled so that the voltage at the node N2, namely the feedback voltage VFB, reaches a predetermined voltage, namely the reference voltage VREF. In equation (6), the feedback voltage VFB is a constant reference voltage VREF, so the higher the voltage V1, the lower the voltage VOUT. However, when the voltage VOUT falls below the feedback voltage VFB, that is, below the reference voltage VREF, current flows from the node N2 through the output node NO into the subsequent circuit connected to the output node NO. Therefore, the range in which the voltage VOUT falls below the reference voltage VREF is prohibited. In other words, the voltage generating circuit 1 cannot output a voltage VOUT below the feedback voltage VFB when the subsequent circuit connected to the output node NO is not connected. Therefore, according to equation (6), the voltage generating circuit 1 can be used within the range in which the voltage V1 satisfies equation (7).

[0046]

[0047] Figure 3An example of the relationship between the pulse width modulation signal PWMX and the voltage VOUT in the voltage generating circuit 1 of the first embodiment is shown. Figure 3 In the example, assuming VCC = 3.3V, VREF = 1.2V, R1 = 22kΩ, R2 = R3 = 15kΩ, and R4 = 20kΩ, the calculated value of the voltage VOUT when the high-level pulse width of the pulse width modulation signal PWMX is linearly changed in 256 steps from 0 to 255 is plotted as a graph. Figure 3 In the example shown, when the period tPeriod of the pulse-width modulation signal PWMX and the high-level pulse width tWHigh are equal to 232 / 256, the voltage VOUT reaches 1.207V, roughly coinciding with the reference voltage VREF = 1.2V. Therefore, the voltage VOUT can be adjusted in 233 steps, from tWHigh / tPeriod = 0 to 232 / 256. When tWHigh / tPeriod = 0, the voltage VOUT is 3.4V, and when tWHigh / tPeriod = 233 / 256, the voltage VOUT is 1.2V. Therefore, each step is (3.4V - 1.2V) / (233 - 1) ≈ 9mV. In other words, the voltage VOUT can be adjusted in 9mV steps.

[0048] The voltage generating circuit 1 of this embodiment is characterized in that a resistor 43 is provided between the node N2 and the ground node NG. Figure 4 As shown in FIG. 2 , a voltage generating circuit 2 of a comparative example in which no resistor 43 is provided between the node N2 and the ground node NG is assumed, and the effects are compared. Figure 4 In the voltage generating circuit 2 of the comparative example shown, the current I1 flowing through the resistor 41 is expressed by the equation (8), and the current I2 flowing through the resistor 42 is expressed by the above-mentioned equation (3).

[0049]

[0050] According to equation (8), the voltage VOUT of the output node NO is expressed by equation (9). Substituting equation (3) into equation (9) yields equation (10).

[0051] VOUT=VFB+R1×I1=VFB+R1×I2…(9)

[0052]

[0053] According to the formula (10), the voltage generating circuit 2 can be used within the range in which the voltage V1 satisfies the formula (11).

[0054]

[0055] Figure 5FIG. 2 shows an example of the relationship between the pulse width modulation signal PWMX and the voltage VOUT in the voltage generating circuit 2 of the comparative example. Figure 5 In the example, assuming VCC = 3.3V, VREF = 1.2V, R1 = 20kΩ, R2 = 5.6kΩ, and R4 = 5.6kΩ, the calculated value of the voltage VOUT when the high-level pulse width of the pulse width modulation signal PWMX is linearly changed in 256 steps from 0 to 255 is plotted as a graph. Figure 5 In the example shown, when tWHigh / tPeriod = 93 / 256 for the pulse-width modulation signal PWMX and the high-level pulse width tWHigh, the voltage VOUT is 1.202V, roughly matching the reference voltage VREF = 1.2V. Therefore, the voltage VOUT can be adjusted in 94 steps, ranging from tWHigh / tPeriod = 0 to 93 / 256. When tWHigh / tPeriod = 0, the voltage VOUT is 3.343V, and when tWHigh / tPeriod = 93 / 256, the voltage VOUT is 1.202V. Therefore, each step is (3.343V - 1.202V) / (94 - 1) ≈ 23mV. In other words, the voltage VOUT can be adjusted in 23mV steps.

[0056] As described above, in the voltage generating circuit 1 of this embodiment, by providing the resistor 43 between the node N2 and the ground node NG, the voltage VOUT can be adjusted in 9 mV steps, which is significantly smaller than that of the voltage generating circuit 2 of the comparative example.

[0057] In the first embodiment, node N1 is an example of a "first node," and node N2 is an example of a "second node." Furthermore, resistor 41 is an example of a "first resistor," resistor 42 is an example of a "second resistor," and resistor 43 is an example of a "third resistor." Furthermore, voltage VIN is an example of a "first voltage," and voltage VOUT is an example of a "second voltage."

[0058] As described above, in the voltage generating circuit 1 of the first embodiment, a current path exists not only from the output node NO through resistors 41 and 42, but also from the output node NO through resistors 41 and 43. Therefore, the current flowing through resistor 41 is greater than in a case where the latter current path is absent. Therefore, even if the high-level pulse width of the pulse-width modulated signal PWMIN is increased, thereby increasing the voltage V1 output to node N1, the voltage VOUT at the output node NO does not significantly decrease. Therefore, the voltage VOUT is less likely to fall below the voltage at node N2, i.e., the reference voltage VREF. Therefore, the voltage generating circuit 1 of the first embodiment can expand the setting range of the pulse width of the pulse-width modulated signal PWMIN that varies the voltage VOUT, thereby enabling the output voltage VOUT to be set with high resolution.

[0059] 1-2. Second embodiment

[0060] Hereinafter, regarding the second embodiment, the same reference numerals are used to designate the same structures as those in the first embodiment, and the same description as that in the first embodiment will be omitted or simplified, and the description will focus on the differences from the first embodiment.

[0061] The voltage generating circuit according to the second embodiment is a switching regulator that boosts an input voltage and outputs the boosted voltage. Figure 6 1 is a diagram showing the structure of a voltage generating circuit according to the second embodiment. Figure 6 As shown, in the voltage generating circuit 1A of the second embodiment, the voltage control circuit 10 of the voltage generating circuit 1 of the first embodiment is replaced with a voltage control circuit 50 .

[0062] The voltage control circuit 50 includes a DC-DC converter 51, an inductor 52, and a diode 53. The inductor 52 is connected between the input node N1 and the node N3. The diode 53 is connected between the node N3 and the output node NO. The DC-DC converter 51 includes a power supply terminal VDD, a switch terminal SW, a feedback terminal FB, and a ground terminal GND. The DC-DC converter 51 switches whether the switch terminal SW is connected to the ground terminal GND by controlling the voltage input to the feedback terminal FB to match a predetermined voltage.

[0063] Figure 7 : is a diagram showing a configuration example of the DC-DC converter 51. Figure 7 As shown, the DC-DC converter 51 includes a reference voltage generating circuit 54 , an error amplifier 55 , a pulse width modulation circuit 56 , and an N-channel MOSFET 57 .

[0064] The reference voltage generating circuit 54 generates a constant reference voltage VREF and outputs it to the inverting input terminal of the error amplifier 55. For example, the reference voltage generating circuit 54 utilizes the bandgap voltage of silicon to generate a constant reference voltage VREF regardless of the power supply voltage or temperature.

[0065] The non-inverting input terminal of the error amplifier 55 is connected to the feedback terminal FB. Therefore, the error amplifier 55 compares the voltage at the feedback terminal FB with the reference voltage VREF. If the voltage at the feedback terminal FB is higher than the reference voltage VREF, the error amplifier 55 outputs a high-level voltage. If the voltage at the feedback terminal FB is lower than the reference voltage VREF, the error amplifier 55 outputs a low-level voltage. The high-level voltage is the voltage input from the power supply terminal VDD, while the low-level voltage is the voltage supplied to the ground terminal GND.

[0066] The pulse width modulation circuit 56 generates a control signal DRV for controlling the on / off state of the MOSFET 57 based on the output voltage of the error amplifier 55, and outputs the control signal DRV to the gate of the MOSFET 57. For example, the pulse width modulation circuit 56 compares the output voltage of the error amplifier 55 with a triangular wave, generates a pulse width modulation signal having a pulse width corresponding to the output voltage of the error amplifier 55 as the control signal DRV, and outputs the control signal DRV to the gate of the MOSFET 57.

[0067] The gate of MOSFET 57 receives the control signal DRV output from the pulse-width modulation circuit 56, the source is connected to the switch terminal SW, and the drain is connected to the ground terminal GND. Therefore, when the control signal DRV is at a high level, the switch terminal SW is electrically connected to the ground terminal GND. When the control signal DRV is at a low level, the switch terminal SW is electrically disconnected from the ground terminal GND. In other words, MOSFET 57 switches whether to connect the switch terminal SW to the ground terminal GND based on the output voltage of the error amplifier 55.

[0068] like Figure 6 As shown, DC-DC converter 51 has power supply terminal VDD connected to input node N1, switch terminal SW connected to node N3, feedback terminal FB connected to node N2, and ground terminal GND connected to ground node NG. Voltage VIN is input to input node N1 from outside voltage generating circuit 1A, and ground voltage VSS is supplied to ground node NG. Therefore, DC-DC converter 51 operates using voltage VIN supplied to power supply terminal VDD as its power supply voltage, switching whether to connect the voltage at node N3 to ground node NG.

[0069] In the voltage control circuit 50 thus configured, when the MOSFET 57 of the DC-DC converter 51 is on, current flows from the input node N1 through the inductor 52 and the MOSFET 57 to the ground node. This current accumulates energy in the inductor 52. When the MOSFET 57 is off, a current corresponding to the voltage VIN input to the input node N1 and the energy accumulated in the inductor 52 flows through the diode 53 to the output node NO. This current charges the capacitor 45, causing the voltage VOUT at the output node NO to increase. The diode 53 may be, for example, a Schottky barrier diode. Schottky barrier diodes have a low forward voltage, resulting in low losses and enabling high-speed switching.

[0070] In the voltage generating circuit 1A of the second embodiment, the circuit structure other than the voltage control circuit 50 is the same as that of the voltage generating circuit 1 of the first embodiment, and therefore its description is omitted. In the voltage generating circuit 1A of the second embodiment, the voltage VOUT at the output node NO is also expressed by the above-mentioned equation (6), where the higher the voltage V1, the lower the voltage VOUT. That is, the voltage control circuit 50 generates the voltage VOUT based on the voltage VIN input to the input node N1 and outputs it to the output node NO. The voltage VOUT is controlled so that the voltage at the node N2, i.e., the feedback voltage VFB, reaches a predetermined voltage, i.e., the reference voltage VREF. Furthermore, in the voltage generating circuit 1A of the second embodiment, by providing the resistor 43 between the node N2 and the ground node NG, the voltage VOUT can be adjusted in steps that are significantly smaller than when the resistor 43 is not provided.

[0071] In the second embodiment, node N1 is an example of a "first node," node N2 is an example of a "second node," and node N3 is an example of a "third node." Furthermore, resistor 41 is an example of a "first resistor," resistor 42 is an example of a "second resistor," and resistor 43 is an example of a "third resistor." Furthermore, voltage VIN is an example of a "first voltage," and voltage VOUT is an example of a "second voltage."

[0072] According to the voltage generating circuit 1A of the second embodiment described above, similarly to the voltage generating circuit 1 of the first embodiment, the setting range of the pulse width of the pulse width modulation signal PWMIN that can change the voltage VOUT can be expanded, thereby enabling the output voltage VOUT to be set with high resolution.

[0073] 2. Writing device

[0074] Figure 8 This is a functional block diagram of the writing device of this embodiment. Figure 8As shown, the writing device 100 of this embodiment includes the voltage generating circuit 1 of the first embodiment and the voltage generating circuit 1A of the second embodiment. Furthermore, the writing device 100 includes a microcontroller unit 110, a reference voltage generating circuit 120, a switch circuit 130, and digital input / output circuits 140, 141, 142, and 143.

[0075] The microcontroller unit 110 includes a control circuit 111 , an A / D conversion circuit 112 , a pulse width modulation circuit 113 , and general-purpose input and output circuits 114 and 115 .

[0076] The A / D conversion circuit 112 converts the voltage fed back from the output node of the voltage generating circuit 1 into a first digital signal based on the reference voltage generated by the reference voltage generating circuit 120, and outputs the first digital signal to the pulse-width modulation circuit 113. Furthermore, the A / D conversion circuit 112 converts the voltage fed back from the output node of the voltage generating circuit 1A into a second digital signal based on the reference voltage, and outputs the second digital signal to the pulse-width modulation circuit 113.

[0077] Pulse-width modulation circuit 113 outputs a pulse-width modulated signal based on the voltage fed back from the output node of voltage generation circuits 1 and 1A. Specifically, pulse-width modulation circuit 113 generates a first pulse-width modulated signal based on the first digital signal and outputs the first pulse-width modulated signal to voltage generation circuit 1 via general-purpose input / output circuit 114. Furthermore, pulse-width modulation circuit 113 generates a second pulse-width modulated signal based on the second digital signal and outputs the second pulse-width modulated signal to voltage generation circuit 1A via general-purpose input / output circuit 115.

[0078] The control circuit 111 communicates with the personal computer 200 connected to the writing device 100, and receives from the personal computer 200 setting data for the output voltage of the voltage generating circuits 1 and 1A and data to be written to the electronic component 300. Based on the setting data for the output voltage of the voltage generating circuits 1 and 1A, the control circuit 111 sets the pulse width of the pulse-width modulated signal output by the pulse-width modulating circuit 113. The pulse-width modulating circuit 113 generates a pulse-width modulated signal having the set pulse width based on the digital signal output from the A / D conversion circuit 112.

[0079] In addition, the control circuit 111 communicates with the electronic component 300 via the digital input / output circuits 140, 141, 142, and 143. That is, the digital signals DIO0, DIO1, DIO2, and DIO3 input and output from the digital input / output circuits 140, 141, 142, and 143 become communication signals corresponding to a specified communication standard. The specified communication standard may be, for example, SPI. SPI is the abbreviation for Serial Peripheral Interface. The control circuit 111 writes write data received from the personal computer 200 to the non-volatile memory of the electronic component 300 and reads the written data using the digital signals DIO0, DIO1, DIO2, and DIO3. The non-volatile memory may be, for example, a MONOS memory, an EEPROM, or the like. MONOS is the abbreviation of Metal Oxide Nitride Oxide Silicon, and EEPROM is the abbreviation of Erasable Programmable Read-Only Memory.

[0080] Voltage generating circuit 1 generates voltage VOUT using the first pulse-width modulated signal as the aforementioned pulse-width modulated signal PWMIN, and outputs generated voltage VOUT as power supply voltage VCC. Power supply voltage VCC is supplied to digital input / output circuits 140, 141, 142, and 143, and digital input / output circuits 140, 141, 142, and 143 operate in response to power supply voltage VCC.

[0081] The switch circuit 130 is turned on / off according to a control signal output from the control circuit 111. When the switch circuit 130 is turned on, the power supply voltage VCC output from the voltage generating circuit 1 is output from the writing device 100 and supplied to the electronic component 300.

[0082] The voltage generating circuit 1A generates a voltage VOUT using the second pulse width modulation signal as the pulse width modulation signal PWMIN, and outputs the generated voltage VOUT as a write voltage VPP. When writing data to the electronic component 300 , the write voltage VPP is supplied to the electronic component 300 via the digital input / output circuit 140 .

[0083] According to the writing device 100 of this embodiment, the voltage generating circuits 1 and 1A, which can set the output voltage with high resolution, can supply the optimal power supply voltage VCC and write voltage VPP to the electronic component 300, thereby improving the reliability of data writing to the electronic component 300. Furthermore, according to the writing device 100 of this embodiment, the microcontroller unit 110 generates a pulse-width modulation signal supplied to the voltage generating circuits 1 and 1A based on the fed-back power supply voltage VCC and write voltage VPP, thereby stabilizing the power supply voltage VCC and write voltage VPP, thereby improving the reliability of data writing to the electronic component 300.

[0084] The present invention is not limited to the present embodiment, and various modifications can be implemented within the scope of the gist of the present invention.

[0085] The above-mentioned embodiment and modification examples are merely examples and are not limiting. For example, the embodiments and modification examples may be appropriately combined.

[0086] The present invention includes structures that are substantially the same as the structures described in the embodiments, such as structures having the same functions, methods, and results, or structures having the same purposes and effects. In addition, the present invention includes structures that replace non-essential parts of the structures described in the embodiments. In addition, the present invention includes structures that have the same effects as the structures described in the embodiments, or structures that can achieve the same purposes. In addition, the present invention includes structures that add known technologies to the structures described in the embodiments.

[0087] The following contents are derived from the above-mentioned embodiment and modification examples.

[0088] One embodiment of a voltage generating circuit includes:

[0089] a smoothing circuit which receives a pulse width modulation signal as input and outputs a voltage obtained by smoothing the pulse width modulation signal to the first node;

[0090] a first resistor connected between the output node and the second node;

[0091] a second resistor connected between the first node and the second node;

[0092] a third resistor connected between the second node and a ground node; and

[0093] The voltage control circuit generates a second voltage based on a first voltage input to an input node and outputs the second voltage to the output node, and controls the second voltage so that the voltage of the second node becomes a predetermined voltage.

[0094] In this voltage generation circuit, a current path exists not only from the output node through the first and second resistors, but also through the first and third resistors. Therefore, the current flowing through the first resistor connected between the output node and the second node is greater than in a case where the latter current path is absent. Consequently, even if the voltage output to the first node is increased by increasing the high-level pulse width of the pulse-width modulated signal, the voltage at the output node does not drop significantly, and the voltage at the output node is unlikely to fall below the specified voltage at the second node. Consequently, this voltage generation circuit expands the setting range of the pulse width of the pulse-width modulated signal that varies the output voltage, enabling high-resolution setting of the output voltage.

[0095] One embodiment of the voltage generating circuit may be:

[0096] A capacitor connected between the output node and the ground node is provided,

[0097] The voltage control circuit includes a regulator that compares the voltage of the second node with the predetermined voltage and switches whether to output the first voltage to the output node based on the comparison result.

[0098] According to this voltage generating circuit, the output voltage obtained by stepping down the input voltage can be set with high resolution.

[0099] One embodiment of the voltage generating circuit may include:

[0100] an inductor connected between the input node and a third node;

[0101] a diode connected between the third node and the output node; and

[0102] a capacitor connected between the output node and the ground node,

[0103] The voltage control circuit compares the voltage of the second node with the predetermined voltage, and switches whether to connect the third node to the ground node based on the comparison result.

[0104] According to this voltage generating circuit, the output voltage obtained by boosting the input voltage can be set with high resolution.

[0105] One embodiment of the writing device has:

[0106] One embodiment of the voltage generating circuit; and

[0107] a pulse width modulation circuit that generates the pulse width modulation signal and outputs it to the voltage generation circuit,

[0108] The second voltage generated by the voltage generating circuit is supplied to an electronic component.

[0109] According to this writing device, an optimum voltage can be supplied to the electronic component by the voltage generating circuit capable of setting the output voltage with high resolution, thereby improving the reliability of data writing to the electronic component.

[0110] In one embodiment of the writing device, it may be that:

[0111] The pulse width modulation circuit generates the pulse width modulation signal based on the voltage fed back from the output node.

[0112] According to this writing device, the output voltage of the voltage generating circuit can be stabilized, thereby improving the reliability of data writing to the electronic component.

[0113] One embodiment of the writing device may also include:

[0114] An A / D conversion circuit that converts the voltage fed back from the output node into a digital signal; and

[0115] a control circuit that sets the pulse width of the pulse width modulation signal,

[0116] The pulse width modulation circuit generates the pulse width modulation signal having the set pulse width based on the digital signal.

Claims

1. A voltage generating circuit comprising: a smoothing circuit which receives a pulse width modulation signal as input and outputs a voltage obtained by smoothing the pulse width modulation signal to the first node; a first resistor connected between the output node and the second node; a second resistor connected between the first node and the second node; a third resistor connected between the second node and a ground node; and The voltage control circuit generates a second voltage based on a first voltage input to an input node and outputs the second voltage to the output node, and controls the second voltage so that the voltage of the second node becomes a predetermined voltage.

2. The voltage generating circuit according to claim 1, wherein: The voltage generating circuit includes a capacitor connected between the output node and the ground node. The voltage control circuit includes a regulator that compares the voltage of the second node with the predetermined voltage and switches whether to output the first voltage to the output node based on the comparison result.

3. The voltage generating circuit according to claim 1, wherein: The voltage generating circuit comprises: an inductor connected between the input node and a third node; a diode connected between the third node and the output node; and a capacitor connected between the output node and the ground node, The voltage control circuit compares the voltage of the second node with the predetermined voltage, and switches whether to connect the third node to the ground node based on the comparison result.

4. A writing device comprising: The voltage generating circuit according to any one of claims 1 to 3; and a pulse width modulation circuit that generates the pulse width modulation signal and outputs it to the voltage generation circuit, The second voltage generated by the voltage generating circuit is supplied to the electronic component.

5. The writing device according to claim 4, wherein The pulse width modulation circuit generates the pulse width modulation signal based on the voltage fed back from the output node. The writing device according to claim 5 , wherein: The writing device comprises: An A / D conversion circuit that converts the voltage fed back from the output node into a digital signal; and a control circuit that sets the pulse width of the pulse width modulation signal, The pulse width modulation circuit generates the pulse width modulation signal having the set pulse width based on the digital signal.

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