A data converter with integrated voltage-capacitance-temperature conversion function

Abstract

This invention discloses a data converter with integrated voltage-capacitance-temperature conversion function, belonging to the field of data converters. The integrated voltage-capacitance-temperature conversion data converter includes a sampling and feedback module and a modulator. The sampling and feedback module acquires capacitance signals, voltage signals, and temperature signals from a temperature sensing module, and transmits them to the modulator. The modulator, based on a 24-bit Sigma-Delta core, converts the capacitance signals, voltage signals, and temperature signals into digital signals, realizing multi-functional conversion of capacitance, voltage, and temperature signals.

Description

Technical Field

[0001] This invention relates to the field of data converter technology, and in particular to a data converter with integrated voltage-capacitance-temperature conversion function. Background Technology

[0002] With the advancement of the internet society and the popularization of information technology, the connection between human life and the data field is becoming increasingly close, placing higher demands on the performance and accuracy of data converters. Traditional Nyquist ADCs often cannot achieve such high accuracy, while Sigma-Delta, based on oversampling technology, can effectively push in-band noise out of the passband through a sampling rate much higher than that of the Nyquist, and obtain high-precision data conversion results after passing through a digital half-band filter and other sampling filters. When the input signal is a low-frequency or DC signal, it is an incremental Sigma-Delta modulator. The characteristic of DC incremental ADCs is that the modulator is periodically reset after a certain quantization period. This quantization period is called the conversion period. After each conversion period, a reset signal is added to the modulator system. The overall conversion accuracy of the modulator is positively correlated with the conversion period.

[0003] Different functional data converters often use different sampling modules. These modules convert various external signals into signals that are easily processed by the core. Based on the Sigma-Delta core, different sampling conversion methods can also be used to oversample multiple different types of signals, achieving power and area savings. Traditional data converters are often single-function, requiring the integration of different functional data converters into a single system, resulting in significant waste of area and power.

[0004] Against this backdrop, there is an urgent need for a data converter that integrates multiple functions to optimize or solve the above problems. Summary of the Invention

[0005] The purpose of this invention is to provide a data converter with integrated voltage-capacitance-temperature conversion function to solve the problems in the background art.

[0006] To address the aforementioned technical problems, this invention provides a data converter integrating voltage-capacitance-temperature conversion, comprising: a sampling and feedback module and a modulator;

[0007] The sampling and feedback module consists of three sampling modules with different functions: voltage, capacitance, and temperature. Based on the different functions, different sampling circuits are selected to collect capacitance signals, voltage signals, and temperature signals from the temperature sensing module, and then transmit them to the modulator.

[0008] The modulator, based on a Sigma-Delta core, converts capacitance, voltage, and temperature signals into digital signals, achieving multi-functional conversion of capacitance, voltage, and temperature signals; among which,

[0009] The sampling of the capacitor signal is driven by a four-phase clock, which enables it to complete two samplings and charge transfers within one cycle of the subsequent two non-overlapping clocks. The signal is integrated by two-stage integrators and compared with the voltage of the comparator to obtain a digital code stream, thus completing the conversion process from capacitor signal to digital signal.

[0010] The voltage signal is sampled twice within one cycle of the two phases and integrated twice. The sampled voltage signal is added to the feedback signal of the comparator and then compared with the standard level of the comparator after being integrated twice by the Sigma-Delta core of the modulator to obtain the digital code stream, thus completing the conversion process from voltage signal to digital signal.

[0011] The temperature sensing module converts the temperature signal into VBE. A pair of capacitors sample the VBE through the upper and lower plates, and under the drive of the clock signal, converts the VBE into a corresponding amount of charge, which is then transferred to the modulator's Sigma-Delta core for use.

[0012] In one embodiment, when the modulator converts the capacitance signal, the sampling and feedback module includes the capacitance C to be measured. SENSOR Parasitic capacitance at the positive terminal Cp_para, parasitic capacitance at the negative terminal Cn_para, a pair of capacitors CDACP, a pair of capacitors CDACN, capacitor CFB1, capacitor CFB2, capacitor CFB3, capacitor CFB4;

[0013] Capacitor C under test SENSOR One end of the capacitor is grounded, and the other end is connected to the positive reference voltage VRP, the common-mode voltage VCM, and the negative reference voltage VRN through three switches, and is always connected to the upper plate of the Cp_para capacitor; the lower plate of the Cp_para capacitor is grounded, and the upper plate is connected to VRN, VRP, and the positive and negative input stages of the first-stage integrator through four switches; the lower plate of the Cn_para capacitor is grounded, and the upper plate is connected to VRN, VRP, and the positive and negative input stages of the first-stage integrator through four switches.

[0014] A pair of connectable capacitors CDACP and a pair of connectable capacitors CDACN are provided to extend the measurement range. The upper plate of the pair of capacitors CDACP is connected to VRN and VRP respectively through two switches, and the lower plate is connected to the positive input terminal of the first-stage integrator through two switches. The upper plate of the pair of capacitors CDACN is connected to VRN and VRP respectively through two switches, and the lower plate is connected to the negative input terminal of the first-stage integrator through two switches.

[0015] CDACP, CDACN, and the capacitor under test C SENSOR The sampling and integration are driven by four-phase clocks Φ1, 2, 3, and 4:

[0016] In the Φ1 stage, the capacitor under test, C SENSOR During the negative sampling phase, the capacitance C under test SENSOR One end is grounded, and the other end is connected to VRN to supply the capacitor C under test. SENSOR Charging, once completed, is the process of charging the capacitor C under test. SENSOR The signal is sampled;

[0017] Φ3 stage, the capacitor under test C SENSOR During the forward sampling phase, the capacitance C to be measured SENSOR One end is grounded, and the other end is connected to VRP to supply the capacitor C under test. SENSOR Charging, once completed, is the process of charging the capacitor C under test. SENSOR The signal is sampled;

[0018] In the Φ2 and Φ4 stages, the capacitance C under test SENSOR The upper plate of the capacitor is connected to the VCM voltage. The transfer voltages for stages Φ2 and Φ4 are |VRN-VCM| and |VRP-VCM|, respectively. The lower plate of the Cp_para capacitor is grounded. The upper plate of the Cp_para capacitor in stage Φ1 is connected to VRN to charge the Cp_para capacitor. The upper plate of the Cp_para capacitor in stage Φ2 is connected to the positive input terminal of the first-stage integrator. Since the capacitor under test C... SENSOR The upper plate of the capacitor is always connected to the upper plate of the capacitor Cp_para. At this time, the capacitor C under test is... SENSOR The charge on the capacitor is also transferred to the first positive integrating capacitor of the first-stage integrator during this cycle; in stage Φ3, the upper plate of the Cp_para capacitor is connected to VRP to charge the Cp_para capacitor; in stage Φ4, the upper plate of the Cp_para capacitor is connected to the negative input terminal of the first-stage integrator, since the capacitor under test C... SENSOR The upper plate of the capacitor is always connected to the upper plate of the capacitor Cp_para. At this time, the capacitor C under test is... SENSOR The charge on the capacitor is also transferred to the first negative integrating capacitor of the first-stage integrator during this cycle; wherein, the first positive integrating capacitor is connected in parallel to the positive input terminal and the positive output terminal of the first-stage integrator, and the first negative integrating capacitor is connected in parallel to the negative input terminal and the negative output terminal of the first-stage integrator.

[0019] The lower plate of the Cn_para capacitor is grounded. In stage Φ1, the upper plate of the Cn_para capacitor is connected to VRN to charge the Cn_para capacitor. In stage Φ2, the upper plate of the Cn_para capacitor is connected to the positive input terminal of the first-stage integrator. In stage Φ3, the upper plate of the Cn_para capacitor is connected to VRP to charge the Cn_para capacitor. In stage Φ4, the upper plate of the Cn_para capacitor is connected to the negative input terminal of the first-stage integrator. The differential input of the Cn_para capacitor and the Cp_para capacitor can effectively suppress the influence of parasitic capacitance on the first-stage integrator.

[0020] In stages Φ1 and 4, the upper plates of a pair of capacitors CDACP are connected to VRN; in stages Φ2 and 3, the upper plates of a pair of capacitors CDACP are connected to VRP. In stages Φ1 and 2, the lower plates of a pair of capacitors CDACP are connected to the positive input terminal of the first-stage integrator; in stages Φ3 and 4, the lower plates of a pair of capacitors CDACP are connected to the negative input terminal of the first-stage integrator. In stages Φ1 and 4, the upper plates of a pair of capacitors CDACN are connected to VRP; in stages Φ2 and 3, the upper plates of a pair of capacitors CDACN are connected to VRN; in stages Φ1 and 2, the lower plates of a pair of capacitors CDACN are connected to the negative input terminal of the first-stage integrator; in stages Φ3 and 4, the upper plates of a pair of capacitors CDACN are connected to the positive input terminal of the first-stage integrator. The range of the entire circuit is controlled by adjusting the size of the connections of CDACN and CDACP to the circuit.

[0021] Capacitor C under test SENSOR Dual sampling is employed, with Φ1, 2, 3, and 4 cycles identical to clocks CLK1 and CLK2, and a duty cycle half that of CLK1 and CLK2. During the Φ1 phase, the capacitance C under test is measured via VRN excitation. SENSOR Sampling; Φ2 stage, the capacitance C under test SENSOR When connected to VCM, the voltage difference between the upper plates of the two cycles causes part of the charge charged in the Φ1 stage to be transferred to the first positive integrating capacitor to complete the integration.

[0022] Similarly, the Φ3 stage completes the excitation of the capacitor C under test through VRP. SENSOR Sampling; Φ2 stage, capacitance C under test SENSOR With the VCM connected, the voltage difference between the upper plates in two cycles causes some of the charge from the Φ3 stage to be transferred to the first negative integrating capacitor to complete the integration; thus, in one cycle of CLK1 and CLK2, Φ1, 2, 3, 4 complete two integrations of the capacitor C under test. SENSORThe system performs two sampling and integration operations; the remaining part is controlled by two non-overlapping clocks CLK1, CLK1D, CLK2, and CLK2D. The upper plate of CFB1 is connected to VRP during CLK1D and to VRN during CLK2D. The lower plate of CFB1 is connected to VCOM during CLK1, and to the positive input of the first-stage integrator during CLK2 when the output code stream BS is negative; it is also connected to the negative output of the first-stage integrator during CLK2. The upper plate of CFB2 is connected to VRN during CLK1D and to VRP during CLK2D. The lower plate of CFB2 is connected to VCOM during CLK2, and to the positive input of the first-stage integrator during CLK1 when the output code stream BS is negative. When K1 is connected to the negative output terminal of the first-stage integrator and the output bitstream is BS, the upper plate of CFB3 is connected to VRP when CLK1D and to VRN when CLK2D. The lower plate of CFB3 is connected to VCOM when CLK2, to the negative input terminal of the first-stage integrator when CLK1 is connected to the negative output terminal of the first-stage integrator when the output bitstream is BS, and to the positive output terminal of the first-stage integrator when CLK1 is connected to the positive output terminal of the first-stage integrator when the output bitstream is BS. The upper plate of CFB4 is connected to VRP when CLK2D and to VRN when CLK1D. The lower plate of CFB4 is connected to VCOM when CLK1 is connected to the negative input terminal of the first-stage integrator when CLK2 is connected to the negative output terminal of the first-stage integrator when the output bitstream is BS, and to the positive output terminal of the first-stage integrator when CLK1 is connected to the positive output terminal of the first-stage integrator.

[0023] In one embodiment, when the modulator converts the voltage signal, the sampling and feedback module includes capacitors CFB1, CFB2, CFB3, CFB4, sampling capacitor Cs1n, and sampling capacitor Cs1p.

[0024] Capacitors Cs1n and Cs1p serve as the first-stage sampling capacitors. The upper plate of capacitor Cs1n is connected to the MUX_IN0 terminal via a two-way switch, and the lower plate is connected to the positive input terminal of the first-stage integrator via a two-way switch. Similarly, the upper plate of capacitor Cs1p is connected to the MUX_IN1 terminal via a two-way switch, and the lower plate is connected to the negative input terminal of the first-stage integrator via a two-way switch. Both MUX_IN0 and MUX_IN1 terminals are for the voltage to be measured. When CLK1 is active, the upper plate of capacitor Cs1n is connected to the MUX_IN1 terminal, and the upper plate of capacitor Cs1p is connected to the MUX_IN0 terminal. Both capacitors are connected in the following ways: At CLK2, the capacitors are swapped: the upper plate of capacitor Cs1p is connected to the MUX_IN1 terminal, and the upper plate of capacitor Cs1n is connected to the MUX_IN0 terminal; at CLK1, the lower plate of capacitor Cs1n is connected to the negative input terminal of the first-stage integrator, and the lower plate of capacitor Cs1p is connected to the positive input terminal of the first-stage integrator; at CLK2, the two are swapped: at CLK2, the lower plate of capacitor Cs1n is connected to the positive input terminal of the first-stage integrator, and the lower plate of capacitor Cs1p is connected to the negative input terminal of the first-stage integrator; in this way, dual sampling completes sampling and integration simultaneously in one cycle to improve clock utilization.

[0025] The upper plate of capacitor CFB1 is connected to VRP during CLK1D and to VRN during CLK2D; the lower plate of capacitor CFB1 is connected to VCOM during CLK1, to the positive input of the first-stage integrator during CLK2 when the output bitstream BS is negative, and to the negative output of the first-stage integrator during CLK2 when the output bitstream BS is negative; the upper plate of capacitor CFB2 is connected to VRN during CLK1D and to VRP during CLK2D; the lower plate of capacitor CFB2 is connected to VCOM during CLK2, to the positive input of the first-stage integrator during CLK1 when the output bitstream BS is negative, and to the negative output of the first-stage integrator during CLK1 when the output bitstream BS is negative. The upper plate of capacitor CFB3 is connected to VRP during CLK1D and to VRN during CLK2D; the lower plate of capacitor CFB3 is connected to VCOM during CLK2, to the negative input of the first-stage integrator during CLK1 and when the output bitstream BS is negative, and to the positive output of the first-stage integrator during CLK1 and when the output bitstream BS is positive; the upper plate of capacitor CFB4 is connected to VRP during CLK2D and to VRN during CLK1D; the lower plate of capacitor CFB4 is connected to VCOM during CLK1, to the negative input of the first-stage integrator during CLK2 and when the output bitstream BS is negative, and to the positive output of the first-stage integrator during CLK1 and when the output bitstream BS is positive.

[0026] In one embodiment, when the modulator converts the temperature signal, the sampling and feedback module includes capacitors CFB1, CFB2, CFB3, CFB4, feedback capacitors CTEM1, CTEM2, CTEM3, and CTEM4.

[0027] The temperature sensing module is an internal temperature detection mode. Under different current operating conditions, the module generates a voltage difference VBE, which is transmitted to the sampling and feedback module and then input to the modulator for digital conversion.

[0028] Four capacitors CFB are paired up, with their upper plates connected to voltage VBE. Specifically, the upper plate of capacitor CFB1 is connected to VBE at a high level, and its lower plate is connected to VCM and the positive and negative inputs of the first-stage integrator via a three-way switch. The upper plate of capacitor CFB2 is connected to VBE at a low level, and its lower plate is connected to VCM and the positive and negative inputs of the first-stage integrator via a three-way switch. The upper plate of capacitor CFB3 is connected to VBE at a high level, and its lower plate is connected to VCM and the positive and negative inputs of the first-stage integrator via a three-way switch. The upper plate of capacitor CFB4 is connected to VBE at a low level, and its lower plate is connected to VCM and the positive and negative inputs of the first-stage integrator via a three-way switch.

[0029] Four new capacitors (CTEM) are added for feedback. The upper plate of capacitor CTEM1 is connected to VRP during CLK1D and to VRN during CLK2D. The lower plate of capacitor CTEM1 is connected to VCOM during CLK1, to the positive input of the first-stage integrator during CLK2 when the output bitstream BS is negative, and to the negative output of the first-stage integrator during CLK2 and the output bitstream BS. The upper plate of capacitor CTEM2 is connected to VRN during CLK1D and to VRP during CLK2D. The lower plate of capacitor CTEM2 is connected to VCOM during CLK2, to the positive input of the first-stage integrator during CLK1 when the output bitstream BS is negative, and to the first-stage integrator during CLK1 and the output bitstream BS. The negative output terminal of the integrator; the upper plate of capacitor CTEM3 is connected to VRP when CLK1D, and to VRN when CLK2D; the lower plate of capacitor CTEM3 is connected to VCOM when CLK2, to the negative input terminal of the first-stage integrator when CLK1 and the output bitstream BS is negative, and to the positive output terminal of the first-stage integrator when CLK1 and the output bitstream BS; the upper plate of capacitor CTEM4 is connected to VRP when CLK2D, and to VRN when CLK1D; the lower plate of capacitor CTEM4 is connected to VCOM when CLK1, to the negative input terminal of the first-stage integrator when CLK2 and the output bitstream BS is negative, and to the positive output terminal of the first-stage integrator when CLK1 and the output bitstream BS.

[0030] In one embodiment, the modulator has a first-stage amplifier that is a chopper operational amplifier. A capacitor and a switch are connected in parallel between the positive input terminal and the positive output terminal, and between the negative input terminal and the negative output terminal of the chopper operational amplifier, respectively, as an integrating capacitor and a clearing switch.

[0031] The modulator also includes: two adder circuit capacitors Csum1, the upper plate of which is connected to the differential output of the first-stage integrator and VCOM respectively via two switches; the lower plate is connected to the positive input and negative input of the comparator respectively.

[0032] The second-stage integrator consists of two sampling capacitors Cs2. The upper plate of one sampling capacitor Cs2 is connected to the positive output terminal of the first-stage integrator and VCM via two switches, and the lower plate is connected to the positive input terminal of the second-stage integrator and VCM via two switches. The upper plate of the other sampling capacitor Cs2 is connected to the negative output terminal of the first-stage integrator and VCM via two switches, and the lower plate is connected to the negative input terminal of the second-stage integrator and VCM via two switches. The second-stage integrator includes an operational amplifier, and a capacitor and a reset switch are connected in parallel between the positive input terminal and the positive output terminal, and between the negative input terminal and the negative output terminal of the operational amplifier, respectively.

[0033] Two capacitors Csum2 in the adder circuit. The upper plate of one capacitor Csum2 is connected to the positive terminal of the differential output of the second-stage integrator and VCM via two switches, and the lower plate is always connected to the positive input of the comparator. The upper plate of the other capacitor Csum2 is connected to the negative terminal of the differential output of the second-stage integrator and VCM via two switches, and the lower plate is always connected to the negative input of the comparator.

[0034] The positive and negative input terminals of the comparator are connected to the VCM via switches, and the output code stream BS of the comparator is passed through a latch and a filter to obtain the output Dout.

[0035] This invention provides a data converter integrating voltage-capacitance-temperature conversion, comprising a sampling and feedback module and a modulator. The sampling and feedback module consists of three sampling modules with different functions: voltage, capacitance, and temperature. Based on different functions, different sampling circuits are selected to acquire capacitance signals, voltage signals, and temperature signals from the temperature sensing module, and transmit them to the modulator. The modulator, based on a 24-bit Sigma-Delta core, converts the capacitance signals, voltage signals, and temperature signals into digital signals, realizing multi-functional conversion of capacitance, voltage, and temperature signals. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the structure of a capacitance, voltage, and temperature functional data converter provided by the present invention;

[0037] Figure 2 This is a schematic diagram of the capacitor sampling function downsampling and feedback module and modulator core structure provided by the present invention;

[0038] Figure 3 This is a schematic diagram of the voltage sampling function downsampling and feedback module and modulator core structure provided by the present invention;

[0039] Figure 4 This is a schematic diagram of the temperature sampling function downsampling and feedback module and modulator core structure provided by the present invention. Detailed Implementation

[0040] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the data converter integrating voltage-capacitance-temperature conversion functionality proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0041] This invention provides a data converter with integrated voltage-capacitance-temperature conversion function, such as... Figure 1As shown, it includes a sampling and feedback module and a modulator. The sampling and feedback module consists of three sampling modules with different functions: voltage, capacitance, and temperature. Based on different functions, different sampling circuits are selected to collect capacitance signals, voltage signals, and temperature signals from the temperature sensing module, and transmit them to the modulator. The modulator is based on a 24-bit Sigma-Delta core and converts capacitance signals, voltage signals, and temperature signals into digital signals, realizing multi-functional conversion of capacitance, voltage, and temperature signals.

[0042] The sampling and feedback module, as described in this invention, can perform three different functions, with sampling and feedback occurring through three channels. The three modes have three different signal sampling and feedback circuits, but all share a common Sigma-Delta modulator core.

[0043] Capacitor-mode signal sampling is driven by a four-phase clock, enabling it to complete two sampling and charge transfers within one cycle of the subsequent two non-overlapping clock phases, including C. SENSOR Sampling of two different reference voltages, VRN and VRP, and sampling of subsequent circuits C SENSOR ∙|VRN-VCM| and C SENSOR • Charge transfer in |VRP-VCM|. The capacitance mode range can be extended by controlling the number of CDAC inputs, and a four-phase clock drive is used to match the sampling module. The feedback input is determined by the comparator result and two non-overlapping clocks, providing global feedback to the modulator core to achieve noise shaping for the entire modulator core, similar to a Sigma-Delta modulator. Integration through two stages of integrators, compared with the comparator voltage, yields the digital bitstream, completing the conversion from capacitance signal to digital signal.

[0044] like Figure 2 As shown, the first stage of the circuit core is driven by a four-phase clock; the second stage and other parts are driven by two-phase non-overlapping clocks. The capacitor under test, C... SENSOROne end is grounded, and the other end is connected to VRP, VCM, and VRN via three switches, and is always connected to the upper plate of the Cp_para capacitor. The lower plate of the Cp_para capacitor is grounded, and the upper plate is connected to VRN, VRP, and the positive and negative input stages of the first-stage integrator via four switches. The lower plate of the Cn_para capacitor is grounded, and the upper plate is connected to VRN, VRP, and the positive and negative input stages of the first-stage integrator via four switches. Additionally, a pair (two) of connectable capacitors CDACN and a pair (two) of connectable capacitors CDACP are provided to extend the measurement range. The upper plates of the two connectable capacitors CDACP are connected to VRN and VRP via two switches, and the lower plates are connected to the positive and negative input terminals of the first-stage integrator via two switches. The modulator is based on a 24-bit Sigma-Delta core. The first-stage amplifier is a chopper operational amplifier. A capacitor and a switch are connected in parallel between the positive input and positive output terminals and between the negative input and negative output terminals of the chopper operational amplifier, respectively, as an integrating capacitor and a clearing switch. The modulator also includes two adder circuit capacitors Csum1, a second-stage integrator, two sampling capacitors Cs2, and two adder circuit capacitors Csum2. The upper plates of the two adder capacitors Csum1 are connected via two switches to the differential output and VCOM of the first-stage integrator, respectively; the lower plates are connected to the positive and negative inputs of the comparator, respectively. The upper plate of a sampling capacitor Cs2 is connected via two switches to the positive output and VCM of the first-stage integrator, respectively; the lower plate is connected via two switches to the positive input and VCM of the second-stage integrator, respectively. The upper plate of another sampling capacitor Cs2 is connected via two switches to the negative output and VCM of the first-stage integrator, respectively; the lower plate is connected via two switches to the negative input and VCM of the second-stage integrator, respectively. The second-stage integrator includes an operational amplifier... A capacitor and a reset switch are connected in parallel between the positive input and positive output terminals, and between the negative input and negative output terminals of the amplifier, respectively. The upper plate of one adder capacitor Csum2 is connected to the positive terminal of the differential output of the second-stage integrator and VCM via two switches, and the lower plate is always connected to the positive input of the comparator. The upper plate of another adder capacitor Csum2 is connected to the negative terminal of the differential output of the second-stage integrator and VCM via two switches, and the lower plate is always connected to the negative input of the comparator. The positive and negative input terminals of the comparator are connected to VCM via switches, and the result BS (Bitstream, output code stream) of the comparator is passed through a latch and a filter to obtain the output Dout.

[0045] CDAC and C SENSOR Partial sampling and integration are driven by a four-phase clock Φ1, 2, 3, 4. In phase Φ1, the capacitance C under test... SENSOR During the negative sampling phase, the capacitance C under test SENSOR One end is grounded, and the other end is connected to VRN to supply the capacitor C under test. SENSORCharging, once completed, is the process of charging the capacitor C under test. SENSOR The signal is sampled; in the Φ3 stage, the capacitor C under test... SENSOR During the forward sampling phase, the capacitance C to be measured SENSOR One end is grounded, and the other end is connected to VRP to supply the capacitor C under test. SENSOR Charging, once completed, is the process of charging the capacitor C under test. SENSOR The signal is sampled; in stages Φ2 and Φ4, the capacitor C under test is... SENSOR The upper plate of the capacitor is connected to the VCM voltage. The transfer voltages for stages Φ2 and Φ4 are |VRN-VCM| and |VRP-VCM|, respectively. The lower plate of the Cp_para capacitor is grounded. The upper plate of the Cp_para capacitor in stage Φ1 is connected to VRN to charge the Cp_para capacitor. The upper plate of the Cp_para capacitor in stage Φ2 is connected to the positive input terminal of the first-stage integrator. Since the capacitor under test C... SENSOR The upper plate of the capacitor is always connected to the upper plate of the capacitor Cp_para. At this time, the capacitor C under test is... SENSOR The charge on the capacitor is also transferred to the first positive integrating capacitor CI1 of the first-stage integrator during this cycle; in the Φ3 stage, the upper plate of the Cp_para capacitor is connected to VRP to charge the Cp_para capacitor; in the Φ4 stage, the upper plate of the Cp_para capacitor is connected to the negative input terminal of the first-stage integrator, since the capacitor C under test... SENSOR The upper plate of the capacitor is always connected to the upper plate of the capacitor Cp_para. At this time, the capacitor C under test is... SENSORThe charge on the capacitor is also transferred to the first negative integrating capacitor CI1' of the first-stage integrator during this cycle; wherein, the first positive integrating capacitor CI1 is connected in parallel to the positive input and positive output of the first-stage integrator, and the first negative integrating capacitor CI1' is connected in parallel to the negative input and negative output of the first-stage integrator. The lower plate of the Cn_para capacitor is grounded, the upper plate of the Cn_para capacitor in stage Φ1 is connected to VRN to charge the Cn_para capacitor; the upper plate of the Cn_para capacitor in stage Φ2 is connected to the positive input of the first-stage integrator; the upper plate of the Cn_para capacitor in stage Φ3 is connected to VRP to charge the Cn_para capacitor; the upper plate of the Cn_para capacitor in stage Φ4 is connected to the negative input of the first-stage integrator; the differential input of the Cn_para capacitor and the Cp_para capacitor can effectively suppress the influence of parasitic capacitance on the first-stage integrator. In stages Φ1 and 4, the upper plates of a pair of capacitors CDACP are connected to VRN; in stages Φ2 and 3, the upper plates of a pair of capacitors CDACP are connected to VRP. In stages Φ1 and 2, the lower plates of a pair of capacitors CDACP are connected to the positive input of the first-stage integrator; in stages Φ3 and 4, the lower plates of a pair of capacitors CDACP are connected to the negative input of the first-stage integrator. In stages Φ1 and 4, the upper plates of a pair of capacitors CDACN are connected to VRP; in stages Φ2 and 3, the upper plates of a pair of capacitors CDACN are connected to VRN; in stages Φ1 and 2, the lower plates of a pair of capacitors CDACN are connected to the negative input of the first-stage integrator; in stages Φ3 and 4, the upper plates of a pair of capacitors CDACN are connected to the positive input of the first-stage integrator. The range of the entire circuit can be controlled by adjusting the size of the two DAC connections. Since the capacitor C under test... SENSOR Dual sampling is employed, with Φ1, 2, 3, and 4 cycles identical to clocks CLK1 and CLK2, and a duty cycle half that of CLK1 and CLK2. During the Φ1 phase, the capacitance C under test is measured via VRN excitation. SENSOR Sampling; Φ2 stage, the capacitance C under test SENSOR With VCM connected, the voltage difference between the upper plates in the two cycles causes part of the charge charged in the Φ1 stage to be transferred to the first positive integrating capacitor CI1 to complete the integration. Similarly, in the Φ3 stage, the capacitor C under test is excited by VRP to complete the integration. SENSOR Sampling; Φ2 stage, capacitance C under test SENSOR With the VCM connected, the voltage difference between the upper plates in two cycles causes part of the charge charged in the Φ3 stage to be transferred to the first negative integrating capacitor CI1' to complete the integration; thus, in one cycle of CLK1 and CLK2, Φ1, 2, 3, 4 complete two cycles of integration on the capacitor C under test. SENSOR The two samplings and integrations.

[0046] The remaining parts are controlled by two non-overlapping clocks CLK1, CLK1D, CLK2, and CLK2D; the upper plate of CFB1 is connected to VRP during CLK1D and to VRN during CLK2D; the lower plate of CFB1 is connected to VCOM during CLK1, to the positive input of the first-stage integrator during CLK2 and BSN (Bitstream negative), and to the negative output of the first-stage integrator during CLK2 and BS; the upper plate of CFB2 is connected to VRN during CLK1D and to VRP during CLK2D; the lower plate of CFB2 is connected to VCOM during CLK2, to the positive input of the first-stage integrator during CLK1 and BSN, and to the negative output of the first-stage integrator during CLK1 and BS; the upper plate of CFB3 is connected to VRP during CLK1D and to VRP during CLK2D. When K2D is connected to VRN; the lower plate of CFB3 is connected to VCOM when CLK2, to the negative input of the first-stage integrator when CLK1 and BSN, and to the positive output of the first-stage integrator when CLK1 and BS; the upper plate of CFB4 is connected to VRP when CLK2D, and to VRN when CLK1D; the lower plate of CFB4 is connected to VCOM when CLK1, to the negative input of the first-stage integrator when CLK2 and BSN, and to the positive output of the first-stage integrator when CLK1 and BS.

[0047] Although CFB1, CFB, CFB3, and CFB4 are not driven by a four-phase clock, the first-stage integrator uses dual sampling, so integration and sampling need to be completed within one cycle. The clock CLK1D is a delayed clock for CLK1, and CLK2D is a delayed clock for CLK. This two-phase non-overlapping clock design effectively suppresses charge leakage. CFB1 and CFB2 are grouped together, and CFB3 and CFB4 are grouped together, ensuring simultaneous integration and sampling of the feedback capacitors. In the CLK1 stage, the upper plates of CFB1 and CFB4 are connected to VRP and VRN respectively, and the lower plate is connected to VCOM, completing the sampling of the positive and negative VREF, accumulating charge for the next clock cycle based on the positive and negative values ​​of BS. Simultaneously, the upper plates of CFB2 and CFB3 are connected to VRN and VNP respectively, and the lower plate transfers charge to the positive and negative input capacitors of the first-stage integrator based on the high and low levels of BS. In CLK2, their functions are interchanged, thus completing simultaneous sampling and integration.

[0048] The voltage mode employs double sampling, meaning it performs two samplings and integrations within one cycle of two phases. This effectively utilizes the clock, achieving higher accuracy within the same reset time, and also matches the four-phase sampling clock of the capacitor mode, better realizing the multiplexing function of the Sigma-Delta modulator core. The sampled voltage signal is added to the comparator's feedback signal, and after two integrations by the Sigma-Delta modulator core, it is compared with the comparator's standard level to obtain the digital code stream, completing the conversion from voltage signal to digital signal.

[0049] like Figure 3 As shown, the voltage mode employs dual sampling. The sampling loop uses dual sampling to sample the input signal. Unlike ordinary sampling, the dual sampling loop samples and integrates in both the original sampling phase and the original integration phase, improving efficiency and increasing SNR (signal-to-noise ratio). The first stage uses dual sampling and dual integration, while the second stage still uses single sampling and single integration. Unlike the capacitor mode circuit, the four-phase capacitor-driven CDAC and capacitor sampling module are not involved. Capacitors Cs1n and Cs1p are added as first-stage sampling capacitors. The upper plate of capacitor Cs1n is connected to the MUX_IN0 terminal via two switches, and the lower plate is connected to the positive input terminal of the first-stage integrator via two switches. Similarly, the upper plate of capacitor Cs1p is connected to the MUX_IN1 terminal via two switches, and the lower plate is connected to the negative input terminal of the first-stage integrator via two switches. Both MUX_IN0 and MUX_IN1 terminals are the voltages to be measured.

[0050] The specific timing kernel is the same as in capacitor mode, only the sampling module differs. In CLK1, the upper plate of capacitor Cs1n is connected to the MUX_IN1 terminal, and the upper plate of capacitor Cs1p is connected to the MUX_IN0 terminal. In CLK2, they are swapped, with the upper plate of capacitor Cs1p connected to the MUX_IN1 terminal and the upper plate of capacitor Cs1n connected to the MUX_IN0 terminal. In CLK1, the lower plate of capacitor Cs1n is connected to the negative input of the first-stage integrator, and the lower plate of capacitor Cs1p is connected to the positive input of the first-stage integrator. In CLK2, they are swapped, with the lower plate of capacitor Cs1n connected to the positive input of the first-stage integrator and the lower plate of capacitor Cs1p connected to the negative input of the first-stage integrator. This dual sampling process completes sampling and integration simultaneously within one cycle, improving clock utilization.

[0051] The upper plate of capacitor CFB1 is connected to VRP when CLK1D is active and to VRN when CLK2D is active; the lower plate of capacitor CFB1 is connected to VCOM when CLK1 is active, to the positive input of the first-stage integrator when CLK2 is active and BSN is active, and to the negative output of the first-stage integrator when CLK2 is active and BS is active; the upper plate of capacitor CFB2 is connected to VRN when CLK1D is active and to VRP when CLK2D is active; the lower plate of capacitor CFB2 is connected to VCOM when CLK2 is active, to the positive input of the first-stage integrator when CLK1 is active and BSN is active, and to the negative output of the first-stage integrator when CLK1 is active and BS is active. The upper plate of capacitor CFB3 is connected to VRP when CLK1D and to VRN when CLK2D; the lower plate of capacitor CFB3 is connected to VCOM when CLK2, to the negative input terminal of the first-stage integrator when CLK1 and BSN, and to the positive output terminal of the first-stage integrator when CLK1 and BS; the upper plate of capacitor CFB4 is connected to VRP when CLK2D and to VRN when CLK1D; the lower plate of capacitor CFB4 is connected to VCOM when CLK1, to the negative input terminal of the first-stage integrator when CLK2 and BSN, and to the positive output terminal of the first-stage integrator when CLK1 and BS.

[0052] Because the temperature mode requires normalization parameters and subsequent digital circuit processing, the capacitors in the sampling and feedback modules differ from those in the previous two functions. The temperature sensing module converts the temperature signal into VBE. A pair of capacitors samples the VBE through the upper and lower plates, and under the drive of the clock signal, converts the VBE into a corresponding amount of charge for transfer to the subsequent Sigma-Delta modulator core.

[0053] like Figure 4As shown, the temperature sensing module operates in internal temperature detection mode. This module generates a voltage difference VBE under different current conditions, which is transmitted to the sampling and feedback module and then input to the modulator for digital conversion. Due to the need for normalization during the temperature mode sampling stage, a new set of capacitors is used as the core of the sampling and feedback capacitors; the subsequent circuit remains unchanged. The four capacitors CFB are paired, with their upper plates connected to the voltage VBE. Specifically, the upper plate of capacitor CFB1 is connected to a high level VBE, and its lower plate is connected to VCM and the positive and negative inputs of the first-stage integrator via a three-way switch; the upper plate of capacitor CFB2 is connected to a low level VBE, and its lower plate is connected to VCM and the positive and negative inputs of the first-stage integrator via a three-way switch; the upper plate of capacitor CFB3 is connected to a high level VBE, and its lower plate is connected to VCM and the positive and negative inputs of the first-stage integrator via a three-way switch; the upper plate of capacitor CFB4 is connected to a low level VBE, and its lower plate is connected to VCM and the positive and negative inputs of the first-stage integrator via a three-way switch. Four new capacitors (CTEM) are added for feedback. The upper plate of capacitor CTEM1 is connected to VRP during CLK1D and to VRN during CLK2D. The lower plate of capacitor CTEM1 is connected to VCOM during CLK1, to the positive input of the first-stage integrator during CLK2 and BSN, and to the negative output of the first-stage integrator during CLK2 and BS. The upper plate of capacitor CTEM2 is connected to VRN during CLK1D and to VRP during CLK2D. The lower plate of capacitor CTEM2 is connected to VCOM during CLK2, to the positive input of the first-stage integrator during CLK1 and BSN, and to the negative output of the first-stage integrator during CLK1 and BS. The negative output terminal of the integrator; the upper plate of capacitor CTEM3 is connected to VRP when CLK1D, and to VRN when CLK2D; the lower plate of capacitor CTEM3 is connected to VCOM when CLK2, to the negative input terminal of the first-stage integrator when CLK1 and BSN, and to the positive output terminal of the first-stage integrator when CLK1 and BS; the upper plate of capacitor CTEM4 is connected to VRP when CLK2D, and to VRN when CLK1D; the lower plate of capacitor CTEM4 is connected to VCOM when CLK1, to the negative input terminal of the first-stage integrator when CLK2 and BSN, and to the positive output terminal of the first-stage integrator when CLK1 and BS.

[0054] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A data converter integrating voltage-capacitance-temperature conversion function, characterized in that, include: Sampling and feedback module, modulator; The sampling and feedback module consists of three sampling modules with different functions: voltage, capacitance, and temperature. Based on the different functions, different sampling circuits are selected to collect capacitance signals, voltage signals, and temperature signals from the temperature sensing module, and then transmit them to the modulator. The modulator, based on a Sigma-Delta core, converts capacitance, voltage, and temperature signals into digital signals, achieving multi-functional conversion of capacitance, voltage, and temperature signals; among which, The sampling of the capacitor signal is driven by a four-phase clock, which enables it to complete two samplings and charge transfers within one cycle of the subsequent two non-overlapping clocks. The signal is integrated by two-stage integrators and compared with the voltage of the comparator to obtain a digital code stream, thus completing the conversion process from capacitor signal to digital signal. The voltage signal is sampled twice within one cycle of the two phases and integrated twice. The sampled voltage signal is added to the feedback signal of the comparator and then compared with the standard level of the comparator after being integrated twice by the Sigma-Delta core of the modulator to obtain the digital code stream, thus completing the conversion process from voltage signal to digital signal. The temperature sensing module converts the temperature signal into VBE. A pair of capacitors sample the VBE through the upper and lower plates, and under the drive of the clock signal, converts the VBE into a corresponding amount of charge, which is then transferred to the Sigma-Delta core of the modulator. When the modulator converts the capacitance signal, the sampling and feedback module includes the capacitance C to be measured. SENSOR Parasitic capacitance at the positive terminal Cp_para, parasitic capacitance at the negative terminal Cn_para, a pair of capacitors CDACP, a pair of capacitors CDACN, capacitor CFB1, capacitor CFB2, capacitor CFB3, capacitor CFB4; Capacitor C under test SENSOR One end of the capacitor is grounded, and the other end is connected to the positive reference voltage VRP, the common-mode voltage VCM, and the negative reference voltage VRN through three switches, and is always connected to the upper plate of the Cp_para capacitor; the lower plate of the Cp_para capacitor is grounded, and the upper plate is connected to VRN, VRP, and the positive and negative input stages of the first-stage integrator through four switches; the lower plate of the Cn_para capacitor is grounded, and the upper plate is connected to VRN, VRP, and the positive and negative input stages of the first-stage integrator through four switches. A pair of connectable capacitors CDACP and a pair of connectable capacitors CDACN are provided to extend the measurement range. The upper plate of the pair of capacitors CDACP is connected to VRN and VRP respectively through two switches, and the lower plate is connected to the positive input terminal of the first-stage integrator through two switches. The upper plate of the pair of capacitors CDACN is connected to VRN and VRP respectively through two switches, and the lower plate is connected to the negative input terminal of the first-stage integrator through two switches. CDACN, CADCP, and the capacitor under test C SENSOR The sampling and integration are driven by four-phase clocks Φ1, 2, 3, and 4: In the Φ1 stage, the capacitor under test, C SENSOR During the negative sampling phase, the capacitance C under test SENSOR One end is grounded, and the other end is connected to VRN to supply the capacitor C under test. SENSOR Charging, once completed, is the process of charging the capacitor C under test. SENSOR The signal is sampled; Φ3 stage, the capacitor under test C SENSOR During the forward sampling phase, the capacitance C to be measured SENSOR One end is grounded, and the other end is connected to VRP to supply the capacitor C under test. SENSOR Charging, once completed, is the process of charging the capacitor C under test. SENSOR The signal is sampled; In the Φ2 and Φ4 stages, the capacitance C under test SENSOR The upper plate of the capacitor is connected to the VCM voltage. The transfer voltages for stages Φ2 and Φ4 are |VRN-VCM| and |VRP-VCM|, respectively. The lower plate of the Cp_para capacitor is grounded. The upper plate of the Cp_para capacitor in stage Φ1 is connected to VRN to charge the Cp_para capacitor. The upper plate of the Cp_para capacitor in stage Φ2 is connected to the positive input terminal of the first-stage integrator. Since the capacitor under test C... SENSOR The upper plate of the capacitor is always connected to the upper plate of the capacitor Cp_para. At this time, the capacitor C under test is... SENSOR The charge on the capacitor is also transferred to the first positive integrating capacitor of the first-stage integrator during this cycle; in stage Φ3, the upper plate of the Cp_para capacitor is connected to VRP to charge the Cp_para capacitor; in stage Φ4, the upper plate of the Cp_para capacitor is connected to the negative input terminal of the first-stage integrator, since the capacitor under test C... SENSOR The upper plate of the capacitor is always connected to the upper plate of the capacitor Cp_para. At this time, the capacitor C under test is... SENSOR The charge on the capacitor is also transferred to the first negative integrating capacitor of the first-stage integrator during this cycle; wherein, the first positive integrating capacitor is connected in parallel to the positive input terminal and the positive output terminal of the first-stage integrator, and the first negative integrating capacitor is connected in parallel to the negative input terminal and the negative output terminal of the first-stage integrator. The lower plate of the Cn_para capacitor is grounded. In stage Φ1, the upper plate of the Cn_para capacitor is connected to VRN to charge the Cn_para capacitor. In stage Φ2, the upper plate of the Cn_para capacitor is connected to the positive input terminal of the first-stage integrator. In stage Φ3, the upper plate of the Cn_para capacitor is connected to VRP to charge the Cn_para capacitor. In stage Φ4, the upper plate of the Cn_para capacitor is connected to the negative input terminal of the first-stage integrator. The differential input of the Cn_para capacitor and the Cp_para capacitor can effectively suppress the influence of parasitic capacitance on the first-stage integrator. In stages Φ1 and 4, the upper plates of a pair of capacitors CDACP are connected to VRN; in stages Φ2 and 3, the upper plates of a pair of capacitors CDACP are connected to VRP; in stages Φ1 and 2, the lower plates of a pair of capacitors CDACP are connected to the positive input terminal of the first-stage integrator; in stages Φ3 and 4, the lower plates of a pair of capacitors CDACP are connected to the negative input terminal of the first-stage integrator; in stages Φ1 and 4, the upper plates of a pair of capacitors CDACN are connected to VRP; in stages Φ2 and 3, the upper plates of a pair of capacitors CDACN are connected to VRN; in stages Φ1 and 2, the lower plates of a pair of capacitors CDACN are connected to the negative input terminal of the first-stage integrator; in stages Φ3 and 4, the upper plates of a pair of capacitors CDACN are connected to the positive input terminal of the first-stage integrator; the range of the entire circuit is controlled by adjusting the size of the connections of CDACP and CDACN in the circuit. Capacitor C under test SENSOR Dual sampling is employed, with Φ1, 2, 3, and 4 cycles identical to clocks CLK1 and CLK2, and a duty cycle half that of CLK1 and CLK2. During the Φ1 phase, the capacitance C under test is measured via VRN excitation. SENSOR Sampling; Φ2 stage, the capacitance C under test SENSOR When connected to VCM, the voltage difference between the upper plates of the two cycles causes part of the charge charged in the Φ1 stage to be transferred to the first positive integrating capacitor to complete the integration. Similarly, the Φ3 stage completes the excitation of the capacitor C under test through VRP. SENSOR Sampling; Φ2 stage, capacitance C under test SENSOR With the VCM connected, the voltage difference between the upper plates in two cycles causes some of the charge from the Φ3 stage to be transferred to the first negative integrating capacitor to complete the integration; thus, in one cycle of CLK1 and CLK2, Φ1, 2, 3, 4 complete two integrations of the capacitor C under test. SENSOR The system performs two sampling and integration operations; the remaining part is controlled by two non-overlapping clocks CLK1, CLK1D, CLK2, and CLK2D. The upper plate of CFB1 is connected to VRP during CLK1D and to VRN during CLK2D. The lower plate of CFB1 is connected to VCOM during CLK1, and to the positive input of the first-stage integrator during CLK2 when the output code stream BS is negative; it is also connected to the negative output of the first-stage integrator during CLK2. The upper plate of CFB2 is connected to VRN during CLK1D and to VRP during CLK2D. The lower plate of CFB2 is connected to VCOM during CLK2, and to the positive input of the first-stage integrator during CLK1 when the output code stream BS is negative. When K1 is connected to the negative output terminal of the first-stage integrator and the output bitstream is BS, the upper plate of CFB3 is connected to VRP when CLK1D and to VRN when CLK2D. The lower plate of CFB3 is connected to VCOM when CLK2, to the negative input terminal of the first-stage integrator when CLK1 is connected to the negative output terminal of the first-stage integrator when the output bitstream is BS, and to the positive output terminal of the first-stage integrator when CLK1 is connected to the positive output terminal of the first-stage integrator when the output bitstream is BS. The upper plate of CFB4 is connected to VRP when CLK2D and to VRN when CLK1D. The lower plate of CFB4 is connected to VCOM when CLK1 is connected to the negative input terminal of the first-stage integrator when CLK2 is connected to the negative output terminal of the first-stage integrator when the output bitstream is BS, and to the positive output terminal of the first-stage integrator when CLK1 is connected to the positive output terminal of the first-stage integrator.

2. The data converter with integrated voltage-capacitance-temperature conversion function as described in claim 1, characterized in that, When the modulator converts the voltage signal, the sampling and feedback module includes capacitors CFB1, CFB2, CFB3, CFB4, sampling capacitor Cs1n, and sampling capacitor Cs1p. Capacitors Cs1n and Cs1p serve as the first-stage sampling capacitors. The upper plate of capacitor Cs1n is connected to the MUX_IN0 terminal via a two-way switch, and the lower plate is connected to the positive input terminal of the first-stage integrator via a two-way switch. The upper plate of capacitor Cs1p is connected to the MUX_IN1 terminal via a two-way switch, and the lower plate is connected to the negative input terminal of the first-stage integrator via a two-way switch. Both MUX_IN0 and MUX_IN1 terminals are the voltages to be measured. When CLK1 is active, the upper plate of capacitor Cs1n is connected to the MUX_IN1 terminal, and the upper plate of capacitor Cs1p is connected to the MUX_IN0 terminal. When CLK2 is active, the two are reversed: the upper plate of capacitor Cs1p is connected to the MUX_IN1 terminal, and the upper plate of capacitor Cs1n is connected to the MUX_IN0 terminal. The lower plate of capacitor Cs1n is connected to the negative input terminal of the first-stage integrator when CLK1 is active, and the lower plate of capacitor Cs1p is connected to the positive input terminal of the first-stage integrator when CLK1 is active. The two are swapped at CLK2. The lower plate of capacitor Cs1n is connected to the positive input of the first-stage integrator at CLK2, and the lower plate of capacitor Cs1p is connected to the negative input of the first-stage integrator at CLK2. In this way, dual sampling completes sampling and integration simultaneously in one cycle to improve clock utilization. The upper plate of capacitor CFB1 is connected to VRP during CLK1D and to VRN during CLK2D; the lower plate of capacitor CFB1 is connected to VCOM during CLK1, to the positive input of the first-stage integrator during CLK2 when the output bitstream BS is negative, and to the negative output of the first-stage integrator during CLK2 when the output bitstream BS is negative; the upper plate of capacitor CFB2 is connected to VRN during CLK1D and to VRP during CLK2D; the lower plate of capacitor CFB2 is connected to VCOM during CLK2, to the positive input of the first-stage integrator during CLK1 when the output bitstream BS is negative, and to the negative output of the first-stage integrator during CLK1 when the output bitstream BS is negative. The upper plate of capacitor CFB3 is connected to VRP during CLK1D and to VRN during CLK2D; the lower plate of capacitor CFB3 is connected to VCOM during CLK2, to the negative input of the first-stage integrator during CLK1 and when the output bitstream BS is negative, and to the positive output of the first-stage integrator during CLK1 and when the output bitstream BS is positive; the upper plate of capacitor CFB4 is connected to VRP during CLK2D and to VRN during CLK1D; the lower plate of capacitor CFB4 is connected to VCOM during CLK1, to the negative input of the first-stage integrator during CLK2 and when the output bitstream BS is negative, and to the positive output of the first-stage integrator during CLK1 and when the output bitstream BS is positive.

3. The data converter with integrated voltage-capacitance-temperature conversion function as described in claim 2, characterized in that, When the modulator converts the temperature signal, the sampling and feedback module includes capacitors CFB1, CFB2, CFB3, CFB4, feedback capacitors CTEM1, CTEM2, CTEM3, and CTEM4. The temperature sensing module is an internal temperature detection mode. Under different current operating conditions, the module generates a voltage difference VBE, which is transmitted to the sampling and feedback module and then input to the modulator for digital conversion. Four capacitors CFB are paired up, with their upper plates connected to voltage VBE. Specifically, the upper plate of capacitor CFB1 is connected to VBE at a high level, and its lower plate is connected to VCM and the positive and negative inputs of the first-stage integrator via a three-way switch. The upper plate of capacitor CFB2 is connected to VBE at a low level, and its lower plate is connected to VCM and the positive and negative inputs of the first-stage integrator via a three-way switch. The upper plate of capacitor CFB3 is connected to VBE at a high level, and its lower plate is connected to VCM and the positive and negative inputs of the first-stage integrator via a three-way switch. The upper plate of capacitor CFB4 is connected to VBE at a low level, and its lower plate is connected to VCM and the positive and negative inputs of the first-stage integrator via a three-way switch. Four new capacitors (CTEM) are added for feedback. The upper plate of capacitor CTEM1 is connected to VRP during CLK1D and to VRN during CLK2D. The lower plate of capacitor CTEM1 is connected to VCOM during CLK1, to the positive input of the first-stage integrator during CLK2 when the output bitstream BS is negative, and to the negative output of the first-stage integrator during CLK2 and the output bitstream BS. The upper plate of capacitor CTEM2 is connected to VRN during CLK1D and to VRP during CLK2D. The lower plate of capacitor CTEM2 is connected to VCOM during CLK2, to the positive input of the first-stage integrator during CLK1 when the output bitstream BS is negative, and to the first-stage integrator during CLK1 and the output bitstream BS. The negative output terminal of the integrator; the upper plate of capacitor CTEM3 is connected to VRP when CLK1D, and to VRN when CLK2D; the lower plate of capacitor CTEM3 is connected to VCOM when CLK2, to the negative input terminal of the first-stage integrator when CLK1 and the output bitstream BS is negative, and to the positive output terminal of the first-stage integrator when CLK1 and the output bitstream BS; the upper plate of capacitor CTEM4 is connected to VRP when CLK2D, and to VRN when CLK1D; the lower plate of capacitor CTEM4 is connected to VCOM when CLK1, to the negative input terminal of the first-stage integrator when CLK2 and the output bitstream BS is negative, and to the positive output terminal of the first-stage integrator when CLK1 and the output bitstream BS.

4. The data converter with integrated voltage-capacitance-temperature conversion function as described in claim 3, characterized in that, In the modulator, the first-stage amplifier is a chopper operational amplifier. A capacitor and a switch are connected in parallel between the positive input terminal and the positive output terminal, and between the negative input terminal and the negative output terminal of the chopper operational amplifier, respectively, as an integrating capacitor and a clearing switch. The modulator also includes: two adder circuit capacitors Csum1, the upper plate of which is connected to the differential output of the first-stage integrator and VCOM respectively via two switches; the lower plate is connected to the positive input and negative input of the comparator respectively. The second-stage integrator consists of two sampling capacitors Cs2. The upper plate of one sampling capacitor Cs2 is connected to the positive output terminal of the first-stage integrator and VCM via two switches, and the lower plate is connected to the positive input terminal of the second-stage integrator and VCM via two switches. The upper plate of the other sampling capacitor Cs2 is connected to the negative output terminal of the first-stage integrator and VCM via two switches, and the lower plate is connected to the negative input terminal of the second-stage integrator and VCM via two switches. The second-stage integrator includes an operational amplifier, and a capacitor and a reset switch are connected in parallel between the positive input terminal and the positive output terminal, and between the negative input terminal and the negative output terminal of the operational amplifier, respectively. Two capacitors Csum2 in the adder circuit. The upper plate of one capacitor Csum2 is connected to the positive terminal of the differential output of the second-stage integrator and VCM via two switches, and the lower plate is always connected to the positive input of the comparator. The upper plate of the other capacitor Csum2 is connected to the negative terminal of the differential output of the second-stage integrator and VCM via two switches, and the lower plate is always connected to the negative input of the comparator. The positive and negative input terminals of the comparator are connected to the VCM via switches, and the output code stream BS of the comparator is passed through a latch and a filter to obtain the output Dout.

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