Anti-fuse memory cell and manufacturing method thereof, and anti-fuse OTP memory

Abstract

The invention provides an anti-fuse memory cell, a manufacturing method thereof and an anti-fuse OTP memory, and belongs to the field of semiconductors. The anti-fuse memory cell comprises a well region formed on the surface of a substrate, a grid electrode formed on the surface of the well region, a first isolation region structure and a second isolation region structure, the grid electrode serves as a grid electrode of a control tube, and the well region on the two sides of the grid electrode is provided with a source region and a drain region; the first isolation region structure is filled with an insulating material; the second isolation region structure comprises an isolation groove, an insulating layer is formed on the side wall of the isolation groove, and the isolation groove is filled with a conductive material. According to the invention, by using the parasitic equivalent capacitor device between the MOS tubes and the memory unit composed of the transistor and the capacitor, the area of the memory unit is equivalent to the area of only one transistor, the size of the memory unit is obviously reduced, and the memory unit is adaptive to the existing process flow. The memory designed according to the memory unit is smaller in area and has competitiveness of manufacturing cost.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an anti-fuse memory unit and a manufacturing method thereof, and a fuse OTP memory. Background Art

[0002] One-Time-Programmable (OTP) memory is a commonly used embedded memory. Its storage principle is to write data by breaking down the capacitor device through high voltage, turning it into an equivalent resistor device. Therefore, it is also called an anti-fuse device.

[0003] The existing patents and papers all use the gate dielectric layer as the capacitor of the anti-fuse device. The circuit structure is as follows Figure 1 As shown, Figure 1 This is a circuit diagram of a traditional antifuse memory cell. Figure 1 The illustrated fuse OTP memory includes an antifuse device 101, a current regulator 102, and a gate control transistor 103. Because of its thinness (typically less than 5 nm), it does not require high voltage for breakdown (typically less than 8 V), making it easy to design the memory's control circuits. Furthermore, its process is compatible with traditional MOS device technology, resulting in low manufacturing costs and high storage density. It is widely used in scenarios where large-capacity single-shot data writes are required.

[0004] However, the anti-fuse OTP memory designed using the anti-fuse device of this structure requires at least one additional selection control tube decoded by the address. A single storage unit is a dual MOS tube or even a multi-MOS tube structure, and there is still room for further optimization of the size.

[0005] In addition, with the continuous miniaturization of process technology, the structure of the gate dielectric layer has become increasingly complex. The stacking process of multiple dielectric materials will cause the breakdown voltage to drift. After the transition from planar process to fin process, the manufacturing uniformity of the gate dielectric layer has further deteriorated, posing challenges to the yield and reliability of OTP memory.

[0006] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art. Summary of the Invention

[0007] The object of the present invention is to provide an anti-fuse memory unit and a manufacturing method thereof, and a fuse OTP memory, so as to solve the problem of low density of the anti-fuse OTP memory.

[0008] In order to solve the above technical problems, the present invention provides an anti-fuse memory cell, comprising:

[0009] A well region is formed on the surface of the substrate, and a gate, a first isolation region structure, and a second isolation region structure are formed on the surface of the well region. The gate serves as the gate of the control transistor, and the well regions on both sides of the gate are provided with a source region and a drain region.

[0010] The first isolation region structure is filled with an insulating material;

[0011] The second isolation region structure includes an isolation trench, a sidewall of the isolation trench is formed with an insulating layer, and the interior of the isolation trench is filled with a conductive material;

[0012] A power contact hole is provided on the surface of the conductive material, a word line contact hole is formed on the surface of the gate, a bit line contact hole is provided in the drain region, the power contact hole is connected to the source region, the source region is connected to the bit line contact hole, and the gate is connected to the word line contact hole.

[0013] Preferably, the thickness of the insulating layer is 2-5 nm.

[0014] Preferably, a buffer material layer is further provided between the insulating layer and the conductive material.

[0015] Preferably, the conductive material includes one of copper, tungsten, ruthenium, nickel, tantalum, polysilicon, or any combination thereof.

[0016] Preferably, the control tube is an NMOS tube or a PMOS tube.

[0017] Based on the same inventive concept, the present invention also provides a method for manufacturing an antifuse memory cell, comprising:

[0018] Providing a substrate, wherein an isolation trench and an insulation trench are formed on a surface of the substrate;

[0019] forming an insulating layer on sidewalls of the isolation trench and the insulation trench;

[0020] Filling the isolation trench with the insulating layer with a conductive material;

[0021] The insulating trench is filled with insulating material.

[0022] Preferably, the thickness of the insulating layer is 2-5 nm.

[0023] Preferably, the conductive material includes one of copper, tungsten, ruthenium, nickel, tantalum, polysilicon, or any combination thereof.

[0024] Based on the same inventive concept, the present invention further provides an anti-fuse OTP memory, comprising the anti-fuse storage unit as described above.

[0025] Preferably, the memory array comprises a plurality of antifuse memory cells arranged to form a memory array, wherein the memory cells in the same row share a word line and are interconnected through gates or high-level metals;

[0026] Memory cells in the same column share a bit line, which is connected to the metal layer through contact holes;

[0027] In the same column of memory cells, the active regions of two adjacent cells are interconnected and share a contact hole to connect to the bit line, and the two adjacent cells share a second isolation region structure.

[0028] Compared with the prior art, the anti-fuse memory cell manufacturing method of the present invention has the following advantages:

[0029] By utilizing the parasitic equivalent capacitor between MOS transistors, the present invention creates a memory cell consisting of a transistor and a capacitor, which is equivalent in area to that of a single transistor. This significantly reduces the size of the memory cell and is compatible with existing process flows. The memory cell designed based on this memory cell has a smaller area and competitive manufacturing costs. Furthermore, the dielectric layer of the equivalent capacitor of the antifuse device of this patent is made of a single material, silicon dioxide, with good thickness uniformity, thereby improving the yield and reliability of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a circuit diagram of an antifuse memory cell;

[0031] Figure 2 is a flow chart of a method for manufacturing an antifuse memory cell in one embodiment of the present invention;

[0032] Figure 3 is a cross-sectional schematic diagram of an antifuse memory cell according to an embodiment of the present invention;

[0033] Figure 4 1 is a schematic diagram of the layout of an antifuse memory cell according to an embodiment of the present invention;

[0034] Figures 5 to 8 FIG1 is a schematic diagram of manufacturing an antifuse memory cell according to an embodiment of the present invention;

[0035] Figure 9 is a circuit diagram of four memory arrays in a row according to an embodiment of the present invention;

[0036] Figure 10 This is a schematic diagram of the device layout in one embodiment of the present invention.

[0037] Figure 11 This is a schematic diagram of the structure of a device in one embodiment of the present invention.

[0038] Figure 12A large-capacity antifuse memory array according to an embodiment of the present invention;

[0039] Figure 13 A large-capacity antifuse memory array according to another embodiment of the present invention;

[0040] In the figure,

[0041] 101- anti-fuse device; 102- current adjustment tube;

[0042] 103-control tube; 201-substrate;

[0043] 202 - well region; 203 - isolation region STI;

[0044] 204-source and drain ion implantation regions; 205-lightly doped drain LDD;

[0045] 206 - gate of the control tube; 207 - anti-fuse STI sidewall;

[0046] 208-conductive material; 209-antifuse power contact hole;

[0047] 210 - control tube gate word line contact hole; 211 - control tube source and drain bit line contact hole;

[0048] 303 - antifuse STI identification layer; 401 - isolation trench;

[0049] 402-insulation trench; 403-STI hard mask;

[0050] 404 - photoresist; 505 - first metal layer. DETAILED DESCRIPTION

[0051] To further clarify the objectives, advantages, and features of the present invention, the antifuse memory cell, its manufacturing method, and the fuse OTP memory proposed in the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not to exact scale, and are only used to facilitate and clearly illustrate the purpose of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention to scale, and the illustrative features used in the drawings to illustrate certain principles of the present invention may also be slightly simplified. The specific design features of the present invention disclosed herein, including, for example, specific dimensions, directions, positions, and shapes, will be determined in part by the specific application and use environment. In addition, in the embodiments described below, the same reference numerals are sometimes used across different drawings to represent the same parts or parts with the same function, and their repeated descriptions are omitted. In this specification, similar numbers and letters are used to represent similar items. Therefore, once a certain item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0052] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0053] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0054] The core idea of ​​the present invention is to provide a method for manufacturing an anti-fuse memory cell, which can increase the density of the OTP memory cell and improve the yield and reliability of the memory.

[0055] In order to realize the above idea, the present invention provides a method for manufacturing an anti-fuse memory cell. Figures 1 to 13 A specific embodiment of a method for manufacturing an antifuse memory cell disclosed herein includes the following steps S1 to S5.

[0056] Step S1: providing a substrate 201 , wherein an isolation trench 401 and an insulation trench 402 are formed on a surface of the substrate 201 .

[0057] Specifically, refer to Figure 2 and Figure 5 As shown, an STI hard mask 403 is placed on a substrate 201, and an isolation trench 401 and an insulation trench 402 are first formed on the surface of the substrate 201 through an etching process. The isolation trench 401 and the insulation trench 402 are both shallow trench isolation trenches in the STI process.

[0058] Step S2 : forming an insulating layer on the sidewalls of the isolation trench 401 and the insulation trench 402 .

[0059] Specifically, refer to Figure 2 、 Figure 3 and Figure 5As shown in the existing STI process, after the single crystal silicon in the STI region is etched, a thin layer of silicon dioxide is oxidized and grown on the sidewalls of the isolation trench 401 and the insulation trench 402 as an insulating layer. The thickness of the insulating layer is between 2 and 5 nm, which is used to smooth the surface damage of the single crystal silicon and help the subsequent filling of silicon dioxide. Among them, the structure formed after the isolation trench 401 is filled with the insulating layer is Figure 3 The structure formed after the insulating trench 402 is filled with the insulating layer is Figure 3 The isolation area STI203 in the.

[0060] Step S3: Filling the isolation trench 401 with the insulating layer with a conductive material 208 .

[0061] Specifically, refer to Figure 2 、 Figure 3 、 Figure 4 and Figure 6 As shown, after the sidewall growth of the isolation trench 401 and the insulation trench 402 is completed, a mask calculated by the anti-fuse device identification layer (the layout diagram of the identification layer is shown in FIG. Figure 4 The antifuse STI identification layer 303 is shown, and the photoresist 404 above the isolation trench 401 is opened, and this area is filled with a conductive material 208. The filling material can be a metal commonly used in MOS processes, such as copper, tungsten, ruthenium, nickel, tantalum, or polysilicon. To improve the morphology and contact between the thin layer of silicon dioxide and the filling material, an intermediate buffer layer, such as titanium nitride, can be deposited before filling.

[0062] In addition, if the thickness of the thin silicon dioxide layer is not appropriate, the capacitor may be difficult to program or may be too easy to program, affecting reliability. The thickness of the silicon dioxide can be further adjusted by opening the photoresist 404 before filling the conductive material 208.

[0063] Step S4: filling the insulating trench 402 with insulating material.

[0064] Specifically, refer to Figure 2 、 Figure 6 and Figure 7 As shown, after the conductive material 208 is filled in the isolation trench 401, the photoresist 404 is removed and other areas are filled with silicon dioxide, for example, the isolation trench 402 is filled with insulating material. Finally, the filled insulating material is polished by chemical mechanical polishing to form a shallow trench isolation structure.

[0065] Step S5 : After the insulating trench 402 is filled with insulating material, a control transistor connected in series with the anti-fuse device is manufactured on the substrate 201 .

[0066] Specifically, refer to Figures 2 to 11 As shown, the MOS transistor manufacturing process is then used to manufacture the control transistor connected in series with the antifuse device. For example, the gate 206 of the control transistor is fabricated. It should be noted that between step S5 and step S4, the process also includes forming a well region 202; implanting ions into the source and drain ion implantation region 204 to form the source and drain; and lightly doping the drain region to form a lightly doped drain LDD 205. Furthermore, after step S5, the process of fabricating the antifuse power supply contact hole 209, the control transistor gate wordline contact hole 210, the control transistor source and drain bitline contact hole 211, and the first metal layer 505, etc., all of which are currently available and will not be elaborated on in detail here.

[0067] The antifuse needs to be connected to the first metal layer 505 through a contact hole. This process is similar to the process of making contact holes in the source and drain regions. Figure 3 The structure shown. The programming and reading methods of this OTP memory cell are consistent with those of traditional OTP memory cells. Taking the NMOS gate control transistor as an example, the P-well of the gate control transistor is grounded, and the anti-fuse VPP is set to a high voltage: For the memory cell to be programmed, the gate WL of the gate control transistor is high and the drain BL is grounded. At this time, the gate control transistor is turned on, causing the other end of the anti-fuse capacitor to also be grounded. Some lattice defects in the thin silicon dioxide layer form a weak leakage current. Over time, the lattice defects near the charge path gradually increase, and the leakage current also increases, forming positive feedback, eventually forming a large leakage current, breaking down the capacitor into an equivalent resistor device, and the stored data is programmed and flipped.

[0068] For unselected memory cells, WL is low or BL is high. At this point, the other end of the antifuse capacitor is floating or high, and the leakage current through the thin silicon dioxide layer is negligible, preventing the capacitor from being broken down and programmed. The silicon dioxide on the sidewalls of the shallow trench isolation (STI) region serves as the equivalent capacitor of the antifuse device. Conductive material 208 is filled within the STI region to connect to the power supply of the antifuse memory cell. The other end of the antifuse equivalent capacitor is directly connected to the select control transistor through the source and drain regions of the MOS transistor. The source and drain regions on the other side of the select control transistor are connected to the bit line BL, and the gate is connected to the word line WL. In a memory array designed using this memory cell, the select control transistor can be an NMOS or PMOS transistor. The gate of the select control transistor is connected to the word line WL, the source is connected to the bit line BL, and the drain is interconnected to the antifuse through source and drain ion implantation. The antifuse power supply is connected to VPP. Memory cells in the same row share a single WL, interconnected through the gate or high-level metal. Memory cells in the same column share a single BL, connected to the metal layer through contact holes. In the same column of memory cells, the active areas of two adjacent cells "head to head" are interconnected and share a contact hole to connect BL, and the two adjacent cells "tail to tail" share a STI anti-fuse. When the memory array is expanded in the row direction, the word line WL of the selection control tube is interconnected to the row decoding and word line driver module through the same root gate, or high-level metal interconnection is added every few columns according to the load and resistance conditions. The bit lines BL are each connected to the bit line driver module and the data reading module through column decoding. The anti-fuse power supply VPP can form a power supply network through high-level metal, and all memory cells are connected in parallel to the same VPP power supply (such as Figure 12 Alternatively, according to the leakage of the memory cell, several columns of VPP form a VPP that is selected by address decoding. During programming, only the VPP power supply of the address corresponding area is turned on to reduce the leakage of the entire memory array (as shown in FIG. Figure 13 The storage array design shown in FIG2 includes: for medium-capacity storage arrays, the entire array can share a VPP power supply, which is powered by the power grid; for large-capacity storage arrays, the VPP power supply can be divided into multiple blocks for separate power supply.

[0069] This embodiment utilizes the parasitic equivalent capacitor device between MOS tubes. The "1T1C" memory cell, consisting of one transistor and one capacitor, is equivalent in area to that of a single transistor, significantly reducing the size of the memory cell and being compatible with existing process flows. The memory designed based on this memory cell has a smaller area and competitive manufacturing costs. In addition, the dielectric layer of the equivalent capacitor of the anti-fuse device of this patent is made of only a single material, silicon dioxide, with good thickness uniformity, thereby improving the yield and reliability of the memory.

[0070] To realize the above idea, Figure 3 As shown, this embodiment also discloses an anti-fuse memory cell, comprising:

[0071] A well region 202 is formed on the surface of a substrate 201. A gate, a first isolation region structure, and a second isolation region structure are formed on the surface of the well region 202. The gate serves as a gate 206 of a control transistor. Source and drain regions are provided in the well region 202 on both sides of the gate. The control transistors are either NMOS transistors or both PMOS transistors.

[0072] The first isolation region structure is filled with an insulating material. The first isolation structure includes an insulating trench 402 and an insulating material filled in the insulating trench 402. The first isolation region structure is Figure 3 The isolation area STI203 in the.

[0073] The second isolation region structure includes an isolation trench 401 . An insulating layer is formed on the sidewall of the isolation trench 401 , and the interior of the isolation trench 401 is filled with a conductive material 208 .

[0074] A power contact hole (i.e., anti-fuse power contact hole 209) is provided on the surface of the conductive material 208, a word line contact hole (i.e., control tube gate word line contact hole 210) is formed on the surface of the gate, and a bit line contact hole (i.e., control tube source-drain bit line contact hole 211) is provided in the drain region, the power contact hole is connected to the source region, the source region is connected to the bit line contact hole, and the gate is connected to the word line contact hole.

[0075] The thickness of the insulating layer is 2-5 nm and the material of the insulating layer includes silicon dioxide.

[0076] The conductive material 208 includes one of copper, tungsten, ruthenium, nickel, tantalum, polysilicon, or any combination thereof.

[0077] This embodiment utilizes the parasitic equivalent capacitor between MOS tubes to design a "1T1C" memory cell consisting of one transistor and one capacitor. Its area is equivalent to that of a single transistor, significantly reducing the size of the memory cell and adapting it to existing process flows. The memory designed based on this memory cell has a smaller area and competitive manufacturing costs. In addition, the dielectric layer of the equivalent capacitor of the anti-fuse device of this patent is made of only a single material, silicon dioxide, with good thickness uniformity, thereby improving the yield and reliability of the memory.

[0078] To realize the above idea, this embodiment also discloses an anti-fuse OTP memory, including:

[0079] The anti-fuse memory cell as described above.

[0080] The anti-fuse OTP memory also includes a memory array formed by arranging a plurality of the anti-fuse memory cells, wherein the memory array includes memory cells in the same row sharing a word line interconnected through a gate or a high-level metal; memory cells in the same column sharing a bit line connected to a metal layer through a contact hole; and memory cells in the same column, active regions of two adjacent cells are interconnected and share a contact hole connected to the bit line, and two adjacent cells share a second isolation region structure. According to the manufacturing scheme of the above-mentioned memory cells, this embodiment proposes a method for expanding it into a memory array. For the convenience of describing this embodiment as an NMOS array, it can also be designed as a PMOS array. In order to optimize the layout utilization of the memory array as much as possible, this embodiment connects adjacent memory cells in the same column in a "head-to-head" and "tail-to-tail" mode, that is, two adjacent memory cells share a source and drain region connected to the bit line, and two memory cells in the other direction share an STI, and the two side walls of the STI are anti-fuse devices of the two memory cells, such as Figures 9 to 11 The figure shows how to connect four memory cells in a row.

[0081] When the memory array is expanded in the row direction, the word line WL of the gate control tube is interconnected to the row decoding and word line driver module through the same root gate, or high-level metal interconnection is added every few columns according to the load and resistance conditions. The bit line BL is connected to the bit line driver module and the data reading module through column decoding. The anti-fuse power supply VPP can form a power supply network through high-level metal, and all memory cells are connected in parallel to the same VPP power supply (such as Figure 12 As shown); or according to the leakage of the memory cell, several columns of VPP form a VPP[i] that is selected by address decoding. During programming, only the VPP power supply of the address corresponding area is turned on to reduce the leakage of the entire memory array (as shown Figure 13 shown).

[0082] The programming and reading methods of the storage cells of this OTP memory are consistent with those of traditional OTP storage cells. Taking the gate control transistor as NMOS as an example, the P well of the gate control transistor is grounded, and the anti-fuse VPP is set to a high voltage:

[0083] For the storage cell that needs to be programmed, the gate WL of the selection control tube (that is, the control tube) is high and the drain BL is grounded. At this time, the selection control tube is turned on, so that the other end of the anti-fuse capacitor is also grounded. Some lattice defects in the thin layer of silicon dioxide form a weak leakage current. As time accumulates, the lattice defects near the charge path gradually increase, the leakage current also increases and forms positive feedback, and finally forms a large leakage current. The capacitor is broken down into an equivalent resistance device, and the stored data is programmed and flipped.

[0084] For a memory cell whose address is not selected, WL is low or BL is high. At this time, the other end of the anti-fuse capacitor is in a floating or high state. The leakage current passing through the thin layer of silicon dioxide is negligible, and the capacitor cannot be broken down and programmed.

[0085] In summary, the above embodiments provide a detailed description of the anti-fuse memory unit and its manufacturing method, and the different configurations of the fuse OTP memory. Of course, the above description is only a description of the preferred embodiment of the present invention, and is not any limitation to the scope of the present invention. The present invention includes but is not limited to the configurations listed in the above implementation. Those skilled in the art can draw inferences based on the contents of the above embodiments. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the scope of protection of the claims.

Claims

1. An antifuse memory cell, characterized in that: include: A well region is formed on the surface of the substrate, and a gate, a first isolation region structure, and a second isolation region structure are formed on the surface of the well region. The gate serves as the gate of the control transistor, and the well regions on both sides of the gate are provided with a source region and a drain region. The first isolation region structure is filled with an insulating material; The second isolation region structure includes an isolation trench, a sidewall of the isolation trench is formed with an insulating layer, and the interior of the isolation trench is filled with a conductive material; A power contact hole is provided on the surface of the conductive material, a word line contact hole is formed on the surface of the gate, a bit line contact hole is provided in the drain region, the power contact hole is connected to the source region, the source region is connected to the bit line contact hole, and the gate is connected to the word line contact hole.

2. The anti-fuse memory cell according to claim 1, wherein: The thickness of the insulating layer is 2-5 nm.

3. The anti-fuse memory cell according to claim 1, wherein: The conductive material includes one of copper, tungsten, ruthenium, nickel, tantalum, polysilicon, or any combination thereof.

4. The anti-fuse memory cell according to claim 1, wherein: The control tube is an NMOS tube or a PMOS tube.

5. A method for manufacturing an antifuse memory cell, characterized in that: include: Providing a substrate, wherein an isolation trench and an insulation trench are formed on a surface of the substrate; forming an insulating layer on sidewalls of the isolation trench and the insulation trench; Filling the isolation trench with the insulating layer with a conductive material; The insulating trench is filled with insulating material.

6. The method for manufacturing an antifuse memory cell according to claim 5, wherein: The thickness of the insulating layer is 2-5 nm.

7. The method for manufacturing an anti-fuse memory cell according to claim 5, wherein: The conductive material includes one of copper, tungsten, ruthenium, nickel, tantalum, polysilicon, or any combination thereof.

8. The method for manufacturing an anti-fuse memory cell according to claim 5, wherein: The method further includes: After the insulating trench is filled with insulating material, a control tube connected in series with the anti-fuse device is manufactured on the substrate.

9. An anti-fuse OTP memory, characterized in that: include: The antifuse memory cell according to any one of claims 1 to 4.

10. The anti-fuse OTP memory according to claim 9, wherein: Also included is a memory array formed by arranging a plurality of said antifuse memory cells, wherein the memory array comprises memory cells in a same row sharing a word line and interconnected via gates or high-level metal; Memory cells in the same column share a bit line, which is connected to the metal layer through contact holes; In the same column of memory cells, the active regions of two adjacent cells are interconnected and share a contact hole to connect to the bit line, and the two adjacent cells share a second isolation region structure.

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