Semiconductor device

Abstract

A semiconductor device according to an embodiment of the present disclosure includes: a substrate including a cell region and a peripheral circuit region; a vertical structure extending in a direction perpendicular to an upper surface of the substrate at the cell region, the vertical structure including bit lines and source lines spaced apart in a first direction parallel to the upper surface of the substrate; a word line extending in a first direction at one side of the vertical structure; a channel layer between the bit line and the word line and between the source line and the word line, the channel layer being connected between the bit line and the source line; a ferroelectric layer between the word line and the channel layer; a control circuit on the substrate at the peripheral circuit region; a source line connection wiring connected to the source line and the control circuit; and a bit line connection wiring connected to the bit line and the control circuit. The source line connection wiring and the bit line connection wiring intersect on a plane.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0042052, filed on March 27, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device. Background Art

[0004] With the development of autonomous vehicles, humanoid robots, artificial intelligence mobile phones, etc., semiconductor devices capable of performing artificial neural network calculations are being developed. An example of a semiconductor device capable of performing artificial neural network calculations may be a neural processing unit (NPU). The NPU may be a computing device that can perform calculations by exchanging data with a memory device. The power consumption of the computing device exchanging data with the memory device is inevitable. Therefore, in order to reduce the electrical power consumed in data transmission, research is being conducted on neuromorphic elements that can perform artificial neural network calculations within a memory device. Summary of the Invention

[0005] Some example embodiments provide a semiconductor device that is capable of performing deep neural network (DNN) calculations with ultra-low electric power and in which memory cells are stacked in a three-dimensional form to be highly integrated.

[0006] A semiconductor device according to some example embodiments includes: a substrate including a cell region and a peripheral circuit region; a vertical structure extending in a direction perpendicular to an upper surface of the substrate at the cell region, the vertical structure including a bit line and a source line spaced apart in a first direction parallel to the upper surface of the substrate; a word line extending in the first direction at one side of the vertical structure;

[0007] A channel layer is located between the bit line and the word line and between the source line and the word line, and the channel layer is connected between the bit line and the source line; a ferroelectric layer is located between the word line and the channel layer; a control circuit is located on the substrate in the peripheral circuit region; a source line connection wiring is connected to the source line and the control circuit; and a bit line connection wiring is connected to the bit line and the control circuit. The source line connection wiring and the bit line connection wiring intersect in a plane.

[0008] According to some example embodiments, a semiconductor device includes a substrate including a cell region and a peripheral circuit region; a vertical structure extending in a direction perpendicular to an upper surface of the substrate at the cell region, the vertical structure including a bit line and a source line spaced apart in a first direction parallel to the upper surface of the substrate; a word line extending in a first direction at one side of the vertical structure; a channel layer located between the bit line and the word line and between the source line and the word line, the channel layer connecting the bit line and the source line; a ferroelectric layer located between the word line and the channel layer; a control circuit located on the substrate at the peripheral circuit region; and a source line connection wiring and a bit line connection wiring, the source line connection wiring and the bit line connection wiring extending in a direction parallel to the upper surface of the substrate, the source line connection wiring and the bit line connection wiring being stacked above the vertical structure. The source line connection wiring extends in the first direction, and the bit line connection wiring extends in a second direction orthogonal to the first direction.

[0009] According to some example embodiments, a semiconductor device includes: a substrate including a cell region and a peripheral circuit region; a vertical structure extending in a direction perpendicular to an upper surface of the substrate at the cell region, the vertical structure including a bit line and a source line spaced apart in a first direction parallel to the upper surface of the substrate; a word line extending in a first direction at one side of the vertical structure; a channel layer located between the bit line and the word line and between the source line and the word line, the channel layer being connected between the bit line and the source line; a ferroelectric layer located between the word line and the channel layer; a control circuit located on the substrate at the peripheral circuit region; an analog-to-digital converter located on the substrate and connected to the control circuit; a source line connection wiring above the vertical structure and connected to the source line and the control circuit; and a bit line connection wiring above the vertical structure and connected to the bit line and the analog-to-digital converter. The source line connection wiring and the bit line connection wiring are located in different layers, one of the source line connection wiring and the bit line connection wiring extends in a direction parallel to the word line, and the other of the source line connection wiring and the bit line connection wiring extends in a direction intersecting the word line.

[0010] According to some example embodiments, a semiconductor device may perform deep neural network (DNN) calculations with ultra-low electric power without exchanging data with a separate computing device.

[0011] According to some example embodiments, a semiconductor device may implement a highly integrated memory device capable of performing DNN calculations with ultra-low electric power. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a perspective view of a semiconductor device according to some example embodiments.

[0013] Figure 2 It shows Figure 1A block diagram of the signal flow between components of a semiconductor device.

[0014] Figure 3 yes Figure 1 A plan view of a semiconductor device.

[0015] Figure 4 It is along Figure 3 A cross-sectional view taken along line AA'.

[0016] Figure 5 It is along Figure 3 A cross-sectional view taken along line BB'.

[0017] Figure 6 is a block diagram illustrating a signal flow between components of a semiconductor device according to some example embodiments.

[0018] Figure 7 yes Figure 6 A plan view of a semiconductor device.

[0019] Figure 8 It is along Figure 7 A cross-sectional view taken along line AA'.

[0020] Figure 9 、 Figure 11 、 Figure 13 、 Figure 15 、 Figure 17 、 Figure 19 、 Figure 21 and Figure 23 are plan views illustrating a method for manufacturing a semiconductor device according to some example embodiments.

[0021] Figure 10 、 Figure 12 、 Figure 14 、 Figure 16 、 Figure 18 、 Figure 20 、 Figure 22 and Figure 24 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some example embodiments. DETAILED DESCRIPTION

[0022] Some example embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings so that those skilled in the art can easily implement the example embodiments. The present disclosure can be modified in various different ways without departing from the spirit or scope of the present disclosure.

[0023] In order to clearly describe the present disclosure, parts or portions irrelevant to the description are omitted, and the same or similar constituent elements are denoted by the same reference numerals throughout the specification.

[0024] In addition, in the drawings, the size and thickness of each element are arbitrarily shown for the sake of convenience of description, and the present disclosure is not necessarily limited to those shown in the drawings. In the drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for the sake of clarity. In the drawings, the thickness of some layers and regions are exaggerated for the sake of convenience of description.

[0025] It will be understood that when an element such as a layer, film, region, area, or substrate is referred to as being "on" or "over" another element, it can be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. Furthermore, in this specification, the terms "on" or "above" mean disposed above or below a target portion, and do not necessarily mean disposed on the upper side of the target portion based on the direction of gravity.

[0026] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising”, will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0027] Furthermore, throughout the specification, the phrase “in a plan view” or “on a plane” means viewing a target portion from the top, and the phrase “in a cross-sectional view” or “on a cross section” means viewing a cross section formed by vertically cutting the target portion from the side.

[0028] In the following, reference will be made to Figures 1 to 5 A semiconductor device 100 according to some example embodiments is described.

[0029] Figure 1 is a perspective view of a semiconductor device according to some example embodiments. Figure 2 It shows Figure 1 A block diagram of the signal flow between components of a semiconductor device. Figure 3 yes Figure 1 A plan view of a semiconductor device. Figure 4 It is along Figure 3 A cross-sectional view taken along line AA'. Figure 5 It is along Figure 3 For ease of description, the cross-sectional view is taken along the line BB'. Figure 3 Some insulating layers of the semiconductor device 100 are omitted from illustration.

[0030] Reference Figures 1 to 5 The semiconductor device 100 according to some example embodiments may include a substrate 110, a cell array structure CAS, an analog-to-digital converter ADC, and a control circuit CU. The cell array structure CAS, the analog-to-digital converter ADC, and the control circuit CU may be disposed above or on the substrate 110. The analog-to-digital converter ADC may be connected between the cell array structure CAS and the control circuit CU.

[0031] The substrate 110 may be a semiconductor substrate made of silicon, germanium, and / or silicon germanium. The substrate 110 may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate having an epitaxial thin film obtained by performing selective epitaxial growth (SEG).

[0032] The cell array structure CAS may be provided at the cell region CR of the substrate 110, and the analog-to-digital converter ADC and the control circuit CU may be provided at the peripheral circuit region PR of the substrate 110. In plan view, the peripheral circuit region PR may be provided adjacent to the cell region CR. The control circuit CU may be provided adjacent to the cell array structure CAS in plan view. The analog-to-digital converter ADC may be provided adjacent to the cell array structure CAS in plan view. For example, the analog-to-digital converter ADC may be provided between the cell array structure CAS and the control circuit CU in plan view, but the present disclosure is not limited thereto.

[0033] The cell array structure CAS may include a plurality of memory cells MC that may store data. The cell array structure CAS may have a structure in which a plurality of layers are stacked on an upper surface of a substrate 110. The memory cells MC may be arranged in an array form at each layer of the cell array structure CAS.

[0034] The analog-to-digital converter ADC and the control circuit CU may be circuit patterns formed on the substrate 110. The analog-to-digital converter ADC may be a circuit pattern configured to convert an analog signal into a digital signal. The control circuit CU may be a circuit pattern configured to control the cell array structure CAS. The control circuit CU may control the cell array structure CAS to write data into the plurality of memory cells MC in the cell array structure CAS and read data stored in the plurality of memory cells MC.

[0035] According to some example embodiments, the control circuit CU may control the cell array structure CAS to perform calculations (or operations) based on data stored in a plurality of memory cells MC. According to some example embodiments, the control circuit CU may perform deep neural network (DNN) calculations by controlling input signals input to the cell array structure CAS. Each layer of the cell array structure CAS may correspond to a plurality of hidden layers of the deep neural network. The weight values ​​of each hidden layer of the deep neural network may be stored in the memory cells MC of each layer of the cell array structure CAS, respectively. The control circuit CU may perform calculations on each hidden layer by inputting an input signal to each layer of the cell array structure CAS to obtain an output signal. The control circuit CU may perform calculations on multiple hidden layers by inputting the output signal of the previous layer as the input signal of the next layer. The output signal output from the last layer of the cell array structure CAS may correspond to the final calculation result of the deep neural network for the input signal input to the first layer of the cell array structure CAS.

[0036] In some example embodiments, the control circuit CU may input an input signal (input) to the cell array structure CAS based on an initial input signal (Initialinput) received from the outside. For example, the input signal (input) input to the cell array structure CAS may be a voltage. The control circuit CU may input a layer control signal (layer control) to each layer of the cell array structure CAS, and the layer control signal (layer control) turns on / off the transistors of the memory cells constituting each layer. The analog-to-digital converter ADC may convert an output signal (output) output from the cell array structure CAS from an analog signal to a digital signal. For example, the output signal (output) output from the cell array structure CAS may be a current. The control circuit CU may receive an output signal (output') of the cell array structure CAS converted into a digital signal from the analog-to-digital converter ADC. The control circuit CU may output a final output signal (Final output) based on the output signal (output') of the cell array structure CAS received from the analog-to-digital converter ADC.

[0037] although Figure 2 Two analog-to-digital converters ADC are shown, but the present disclosure is not limited thereto. The number of the analog-to-digital converters ADC may be variously changed in response to the number of output signals output from the cell array structure CAS.

[0038] According to some example embodiments, the analog-to-digital converter ADC may include a converter transistor TRC. The control circuit CU may include a control transistor TRCT. Figure 1 and Figure 5In , the converter transistor TRC may correspond to the analog-to-digital converter ADC, and the control transistor TRCT may correspond to the control circuit CU. Figure 1 and Figure 5 In the figure, for the convenience of description, one converter transistor TRC and one control transistor TRCT are shown, but the present disclosure is not limited thereto. Each of the analog-to-digital converter ADC and the control circuit CU may further include more transistors or circuit elements other than transistors.

[0039] According to some example embodiments, the cell array structure CAS may include a vertical structure VS including a bit line BL and a source line SL, a word line structure WLS including a word line WL, and a ferroelectric layer 131 and a channel layer 133 disposed between the vertical structure VS and the word line structure WLS. According to some example embodiments, the cell array structure CAS may further include a gate insulating layer 132 located between the ferroelectric layer 131 and the channel layer 133.

[0040] According to some example embodiments, the vertical structure VS may include a bit line BL and a source line SL extending in a third direction DR3 perpendicular to the upper surface of the substrate 110. The bit line BL and the source line SL may have a columnar shape extending in the third direction DR3. The bit line BL and the source line SL may be spaced apart in a first direction DR1 parallel to the upper surface of the substrate 110. A channel layer 133 and an insulating pattern 150, which will be described later, may be provided between the bit line BL and the source line SL.

[0041] Each of the bit line BL and the source line SL may include a conductive material. For example, each of the bit line BL and the source line SL may include at least one selected from a doped semiconductor material (e.g., doped silicon or doped germanium), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), a metal (e.g., tungsten, titanium, or tantalum), and / or a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, or titanium silicide), but the present disclosure is not limited thereto.

[0042] The word line structure WLS may be provided at one side of the vertical structure VS. The word line structure WLS may include a word line WL extending in a first direction DR1 parallel to the upper surface of the substrate 110. The word line WL may include a conductive material. For example, the word line WL may include at least one selected from a doped semiconductor material, a conductive metal nitride, a metal, and a metal semiconductor compound, but the present disclosure is not limited thereto.

[0043] The word line structure WLS may include a plurality of word lines WL1, WL2, and WL3 stacked in a third direction DR3 perpendicular to the upper surface of the substrate 110. Each of the plurality of word lines WL1, WL2, and WL3 may extend in a first direction DR1 parallel to the upper surface of the substrate 110.

[0044] According to some example embodiments, each of a plurality of layers of the cell array structure CAS may be defined by a word line WL. Each layer of the cell array structure CAS may include a plurality of word lines WL1, WL2, and WL3.

[0045] According to some example embodiments, each of the plurality of memory cells MC of the cell array structure CAS may include a source line SL, a bit line BL, a word line WL, and a ferroelectric layer 131, a gate insulating layer 132, and a channel layer 133 disposed therebetween.

[0046] According to some example embodiments, an on / off signal may be applied to a word line WL, and an input signal may be applied to a source line SL. According to some example embodiments, an output signal may be output from a bit line BL. Memory cells MC of a layer of the cell array structure CAS corresponding to the word line WL to which the on signal is applied may be turned on. A voltage may be applied between the bit line BL and the source line SL of each of the turned-on memory cells MC.

[0047] The channel layer 133 may be disposed between the word line WL and the bit line BL, and between the word line WL and the source line SL. The channel layer 133 may cover the side surfaces of the bit line BL and the source line SL and may extend in a third direction DR3 perpendicular to the upper surface of the substrate 110. The channel layer 133 may extend in a plane along a first direction DR1 from the side surface of the bit line BL to the side surface of the source line SL. The channel layer 133 may protrude between the bit line BL and the source line SL in a second direction DR2 parallel to the upper surface of the substrate 110. The channel layer 133 may connect the bit line BL and the source line SL. The second direction DR2 may be a direction intersecting the first direction DR1, and for example, the second direction DR2 may be orthogonal to the first direction DR1.

[0048] The channel layer 133 may include at least one of a semiconductor material, an amorphous oxide semiconductor material, and a two-dimensional material. In some example embodiments, the channel layer 133 may include at least one selected from polycrystalline silicon, doped silicon (Si), silicon germanium (SiGe), and / or a semiconductor formed by selective epitaxial growth (SEG). The channel layer 133 may have a single-layer or multi-layer structure.

[0049] In some example embodiments, the channel layer 133 may include an amorphous oxide semiconductor material, and for example, the channel layer 133 may include a compound of at least two metals selected from zinc (Zn), indium (In), gallium (Ga), and tin (Sn), and oxygen (O). For example, the channel layer 133 may include at least one selected from indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), Sn-IGZO, IWO, CuS2, CuSe2, WSe2, IZO, ZTO, and / or YZO, but the present disclosure is not limited thereto.

[0050] In some example embodiments, the channel layer 133 may include a two-dimensional material. For example, the channel layer 133 may include metal chalcogenide, transition metal chalcogenide, graphene, or phosphorene.

[0051] According to some example embodiments, if a gate turn-on signal is applied to the word line WL of the memory cell MC and predetermined or alternatively desired voltages are respectively applied to the bit line BL and the source line SL, current may flow from the source line SL to the bit line BL through the channel layer 133 of the memory cell MC.

[0052] The ferroelectric layer 131 may be disposed between the channel layer 133 and the word line WL. According to some example embodiments, the ferroelectric layer 131 may extend along the first direction DR1. The thickness of the ferroelectric layer 131 on a plane (or the width along the second direction DR2) may not be constant. On a plane, a portion of the ferroelectric layer 131 that overlaps with the channel layer 133 in the second direction DR2 may be thicker than a portion of the ferroelectric layer 131 that does not overlap with the channel layer 133 in the second direction DR2.

[0053] According to some example embodiments, the ferroelectric layer 131 may include a horizontal portion 131_H parallel to an upper surface of the substrate 110, and vertical portions 131_V1 and 131_V2 extending from the horizontal portion 131_H in a third direction DR3 perpendicular to the upper surface of the substrate 110. The vertical portions 131_V1 and 131_V2 may include a first vertical portion 131_V1 and a second vertical portion 131_V2 spaced apart in a second direction DR2.

[0054] The ferroelectric layer 131 may include a ferroelectric material. In some example embodiments, the ferroelectric material may include an Hf compound. For example, the Hf compound may be an Hf-based oxide. The Hf-based oxide may also include at least one impurity selected from Zr, Si, Al, Y, Gd, La, Sc, and / or Sr. For example, the ferroelectric material may include HfO2, HfZnO, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or a combination thereof. The ferroelectric layer 131 may have an orthorhombic phase. The ferroelectric layer 131 may include a single layer, a multilayer in which two or more types of ferroelectric layers are stacked, or a multilayer in which a ferroelectric layer and a dielectric material layer are stacked.

[0055] According to some example embodiments, the ferroelectric layer 131 may have various polarization states according to a voltage applied between the bit line BL and the source line SL and the word line WL. According to some example embodiments, a current value flowing from the source line SL to the bit line BL through the channel layer 133 may be determined based on the polarization state of the ferroelectric layer 131.

[0056] According to some example embodiments, a gate insulating layer 132 may be disposed between the channel layer 133 and the ferroelectric layer 131. The gate insulating layer 132 may have a shape corresponding to the outline of the ferroelectric layer 131. The gate insulating layer 132 may be disposed between the vertical portions 131_V1 and 131_V2 of the ferroelectric layer 131 and the channel layer 133. The gate insulating layer 132 may be disposed between the horizontal portion 131_H of the ferroelectric layer 131 and the channel layer 133. The gate insulating layer 132 may be disposed between the horizontal portion 131_H of the ferroelectric layer 131 and the lower surface of the bit line BL and the source line SL. The gate insulating layer 132 may be disposed between the horizontal portion 131_H of the ferroelectric layer 131 and the lower surface of the insulating pattern 150, which will be described later. The gate insulating layer 132 may extend along the second direction DR2 between the first vertical portion 131_V1 and the second vertical portion 131_V2 of the ferroelectric layer 131. The thickness of the gate insulating layer 132 may be thinner than the thicknesses of the ferroelectric layer 131 and the channel layer 133 .

[0057] For example, the gate insulating layer 132 may include a silicon oxide layer, a silicon oxynitride layer, a high dielectric layer having a higher dielectric constant than the silicon oxide layer, or a combination thereof. For example, the high dielectric layer may include metal oxide or metal oxynitride.

[0058] According to some example embodiments, the cell array structure CAS may include a first vertical structure VS1 and a second vertical structure VS2 spaced apart in a second direction DR2. The first vertical structure VS1 may include a first bit line BL1 and a first source line SL1. The second vertical structure VS2 may include a second bit line BL2 and a second source line SL2. The first bit line BL1 may face the second bit line BL2 in the second direction DR2, and the first source line SL1 may face the second source line SL2 in the second direction DR2.

[0059] The ferroelectric layer 131 may surround the first and second vertical structures VS1 and VS2. The first and second vertical structures VS1 and VS2 may be disposed above the horizontal portion 131_H of the ferroelectric layer 131. The first and second vertical structures VS1 and VS2 may be disposed between the first and second vertical portions 131_V1 and 131_V2 of the ferroelectric layer 131.

[0060] The channel layer 133 may be disposed between the first vertical structure VS1 and the first vertical portion 131_V1 of the ferroelectric layer 131, and may be disposed between the second vertical structure VS2 and the second vertical portion 131_V2 of the ferroelectric layer 131. The channel layer 133 may extend over the horizontal portion 131_H of the ferroelectric layer 131 from between the first source line SL1 and the first bit line BL1 to between the second source line SL2 and the second bit line BL2.

[0061] According to some example embodiments, the cell array structure CAS may include a third vertical structure VS3 spaced apart from the first vertical structure VS1 in the first direction DR1. The cell array structure CAS may include a fourth vertical structure VS4 spaced apart from the second vertical structure VS2 in the first direction DR1. The third vertical structure VS3 and the fourth vertical structure VS4 may be separated in the second direction DR2.

[0062] The third vertical structure VS3 may include a third bit line BL3 and a third source line SL3. The fourth vertical structure VS4 may include a fourth bit line BL4 and a fourth source line SL4. The third bit line BL3 may face the fourth bit line BL4 in the second direction DR2, and the third source line SL3 may face the fourth source line SL4 in the second direction DR2.

[0063] The first source line SL1, the first bit line BL1, the third source line SL3, and the third bit line BL3 may be arranged along the first direction DR1. The second source line SL2, the second bit line BL2, the fourth source line SL4, and the fourth bit line BL4 may be arranged along the first direction DR1. That is, the source lines SL and the bit lines BL may be alternately arranged along the first direction DR1.

[0064] The ferroelectric layer 131 may surround the third and fourth vertical structures VS3 and VS4. The third and fourth vertical structures VS3 and VS4 may be disposed above the horizontal portion 131_H of the ferroelectric layer 131. The third and fourth vertical structures VS3 and VS4 may be disposed between the first and second vertical portions 131_V1 and 131_V2 of the ferroelectric layer 131.

[0065] The ferroelectric layer 131 may extend along the first direction DR1 at one side of each of the first vertical structure VS1 and the third vertical structure VS3. The ferroelectric layer 131 may extend along the first direction DR1 at one side of each of the second vertical structure VS2 and the fourth vertical structure VS4. Each of the one side of each of the first vertical structure VS1 and the third vertical structure VS3 and the one side of each of the second vertical structure VS2 and the fourth vertical structure VS4 may be a side along the second direction DR2. For example, the first vertical portion 131_V1 of the ferroelectric layer 131 may extend along the first direction DR1 from the one side of each of the first vertical structure VS1 and the third vertical structure VS3, and the second vertical portion 131_V2 of the ferroelectric layer 131 may extend along the first direction DR1 from the one side of each of the second vertical structure VS2 and the fourth vertical structure VS4.

[0066] The channel layer 133 may be disposed between the third vertical structure VS3 and the first vertical portion 131_V1 of the ferroelectric layer 131 , and between the fourth vertical structure VS4 and the second vertical portion 131_V2 of the ferroelectric layer 131 .

[0067] The cell array structure CAS may include a plurality of channel layers 133_1 and 133_2. The plurality of channel layers 133_1 and 133_2 may include a first channel layer 133_1 disposed between the first and second vertical structures VS1 and VS2 and the ferroelectric layer 131, and a second channel layer 133_2 disposed between the third and fourth vertical structures VS3 and VS4 and the ferroelectric layer 131. The first channel layer 133_1 and the second channel layer 133_2 may be spaced apart in a first direction DR1.

[0068] The insulating pattern 150 may be disposed above the horizontal portion 131_H of the ferroelectric layer 131. The gate insulating layer 132 may be disposed between the horizontal portion 131_H of the ferroelectric layer 131 and the insulating pattern 150. The insulating pattern 150 may be disposed between the first vertical portion 131_V1 and the second vertical portion 131_V2 of the ferroelectric layer 131. The insulating pattern 150 may cover the side surface and the upper surface of the channel layer 133 between the first vertical portion 131_V1 and the second vertical portion 131_V2 of the ferroelectric layer 131.

[0069] The plurality of channel layers 133_1 and 133_2 may be spaced apart along the first direction DR1 between the first vertical portion 131_V1 and the second vertical portion 131_V2 of the ferroelectric layer 131 by the insulating pattern 150. The plurality of vertical structures VS1, VS2, VS3, and VS4 may be spaced apart along the first vertical portion 131_V1 and the second vertical portion 131_V2 of the ferroelectric layer 131 by the insulating pattern 150. The insulating pattern 150 may be provided between the first and second bit lines BL1 and BL2 facing each other along the second direction DR2, and between the first and second source lines SL1 and SL2 facing each other along the second direction DR2. The insulating pattern 150 may be provided between the third and fourth bit lines BL3 and BL4 facing each other along the second direction DR2, and between the third and fourth source lines SL3 and SL4 facing each other along the second direction DR2. The insulating pattern 150 may be provided between the first and third source lines BL1 and SL3 facing each other along the first direction DR1. The insulating pattern 150 may be disposed between the second bit line BL2 and the fourth source line SL4 facing each other in the first direction DR1 .

[0070] For example, the first vertical structure VS1 and the second vertical structure VS2 may be spaced apart along the second direction DR2 between the first vertical portion 131_V1 and the second vertical portion 131_V2 of the ferroelectric layer 131 by the insulating pattern 150. The third vertical structure VS3 and the fourth vertical structure VS4 may be spaced apart along the second direction DR2 between the first vertical portion 131_V1 and the second vertical portion 131_V2 of the ferroelectric layer 131 by the insulating pattern 150.

[0071] For example, the first vertical structure VS1 and the third vertical structure VS3 may be spaced apart along the first direction DR1 between the first vertical portion 131_V1 and the second vertical portion 131_V2 of the ferroelectric layer 131 by the insulating pattern 150. The second vertical structure VS2 and the fourth vertical structure VS4 may be spaced apart along the first direction DR1 between the first vertical portion 131_V1 and the second vertical portion 131_V2 of the ferroelectric layer 131 by the insulating pattern 150.

[0072] For example, the insulating pattern 150 may include at least one of silicon oxide, silicon nitride, and / or silicon oxynitride, but the present disclosure is not limited thereto.

[0073] The cell array structure CAS may include a plurality of word line structures WLS. Each of the plurality of word line structures WLS may be shared by a plurality of vertical structures arranged along a first direction. For example, the plurality of word line structures WLS may include a first word line structure shared by a first vertical structure VS1 and a third vertical structure VS3, and a second word line structure shared by a second vertical structure VS2 and a fourth vertical structure VS4. The first word line structure may be disposed on one side of the first vertical portion 131_V1 of the ferroelectric layer 131, and the second word line structure may be disposed on one side of the second vertical portion 131_V2 of the ferroelectric layer 131.

[0074] The first word line structure and the second word line structure may be disposed on opposite sides of the surfaces of the first vertical portion 131_V1 and the second vertical portion 131_V2 of the ferroelectric layer 131 facing each other. For example, the first word line structure may be adjacent to the outer surface of the first vertical portion 131_V1, and the second word line structure may be adjacent to the outer surface of the second vertical portion 131_V2. The first channel layer 133_1 may be disposed between the first word line structure and the first vertical structure VS1, and between the second word line structure and the second vertical structure VS2. The second channel layer 133_2 may be disposed between the first word line structure and the third vertical structure VS3, and between the second word line structure and the fourth vertical structure VS4. The first vertical portion 131_V1 of the ferroelectric layer 131 may be disposed between the first word line structure and the first channel layer 133_1, and between the first word line structure and the second channel layer 133_2. The second vertical portion 131_V2 of the ferroelectric layer 131 may be disposed between the first word line structure and the first channel layer 133_1 , and between the second word line structure and the second channel layer 133_2 .

[0075] According to some example embodiments, a plurality of vertical structures VS1, VS2, VS3, and VS4 and a plurality of channel layers 133_1 and 133_2 may be disposed inside the ferroelectric layer 131 surrounded by a horizontal portion 131_H of the ferroelectric layer 131 and first and second vertical portions 131_V1 and 131_V2 extending from the horizontal portion 131_H in a third direction DR3. A plurality of word line structures WLS may be disposed outside the ferroelectric layer 131.

[0076] According to some example embodiments, the cell array structure CAS may include a plurality of ferroelectric layers 131. A plurality of vertical structures VS1, VS2, VS3, and VS4 and a plurality of channel layers 133_1 and 133_2 may be disposed inside each of the plurality of ferroelectric layers 131. A plurality of word line structures WLS may be disposed outside each of the plurality of ferroelectric layers 131.

[0077] According to some example embodiments, the cell insulating layer 140 may surround the cell array structure CAS. The cell insulating layer 140 may fill an external space of the plurality of ferroelectric layers 131. The cell insulating layer 140 may surround the plurality of word line structures WLS outside the plurality of ferroelectric layers 131. The cell insulating layer 140 may cover the upper surface of the substrate 110 disposed outside the cell array structure CAS.

[0078] The bit line connection wiring 170 and the source line connection wiring 190 may be disposed above the cell array structure CAS and the cell insulating layer 140. According to some example embodiments, the bit line connection wiring 170 and the source line connection wiring 190 may be stacked along a third direction DR3 perpendicular to the upper surface of the substrate 110. The bit line connection wiring 170 and the source line connection wiring 190 may be disposed at different layers. According to some example embodiments, the source line connection wiring 190 may be stacked above the bit line connection wiring 170, but the present disclosure is not limited thereto, and the bit line connection wiring 170 may be stacked above the source line connection wiring 190.

[0079] According to some example embodiments, the bit line connection wiring 170 and the source line connection wiring 190 may extend in a direction parallel to the upper surface of the substrate 110 and may extend in directions intersecting each other on a plane. According to some example embodiments, the bit line connection wiring 170 may extend in the second direction DR2, and the source line connection wiring 190 may extend in the first direction DR1, but the present disclosure is not limited thereto.

[0080] According to some example embodiments, a first interlayer insulating layer 160 may be disposed on the cell array structure CAS and the cell insulating layer 140. The first interlayer insulating layer 160 may cover the upper surface of the cell array structure CAS and the upper surface of the cell insulating layer 140. A plurality of bit line connection wirings 170 extending in the second direction DR2 may be disposed on the first interlayer insulating layer 160. Each of the plurality of bit line connection wirings 170 may pass over the upper surface of a plurality of bit lines BL of the cell array structure CAS, the plurality of bit lines BL being spaced apart and disposed along the second direction DR2. For example, the plurality of bit line connection wirings 170 may include a first bit line connection wiring 170_1 passing over the upper surfaces of the first and second bit lines BL1 and BL2, and a second bit line connection wiring 170_2 passing over the upper surfaces of the third and fourth bit lines BL3 and BL4. The first interlayer insulating layer 160 may also be disposed between the plurality of bit line connection wirings 170.

[0081] A second interlayer insulating layer 180 may be provided on the plurality of bit line connection wirings 170 and the first interlayer insulating layer 160. The second interlayer insulating layer 180 may cover the upper surfaces of the plurality of bit line connection wirings 170 and the first interlayer insulating layer 160. A plurality of source line connection wirings 190 extending in the first direction DR1 may be provided on the second interlayer insulating layer 180. The bit line connection wirings 170 and the source line connection wirings 190 may be spaced apart from each other in a third direction DR3 perpendicular to the upper surface of the substrate 110. According to some example embodiments, the plurality of bit line connection wirings 170 and the plurality of source line connection wirings 190 may be separated in the third direction DR3 by the second interlayer insulating layer 180.

[0082] Each of the plurality of source line connection wirings 190 may pass over the upper surface of the plurality of source lines SL along the cell array structure CAS, the plurality of source lines SL being spaced apart and arranged in the first direction DR1. For example, the plurality of source line connection wirings 190 may include a first source line connection wiring 190_1 passing over the upper surfaces of the first source line SL1 and the third source line SL3, and a second source line connection wiring 190_2 passing over the upper surfaces of the second source line SL2 and the fourth source line SL4. A second interlayer insulating layer 180 may also be provided between the plurality of source line connection wirings 190.

[0083] According to some example embodiments, each of the first interlayer insulating layer 160 and the second interlayer insulating layer 180 may be made of a single layer or a multilayer. For example, each of the first interlayer insulating layer 160 and the second interlayer insulating layer 180 may include at least one of a silicon oxide layer, a silicon nitride layer, and / or a silicon oxynitride layer. Figure 1 and Figure 4 , the boundary between the first interlayer insulating layer 160 and the second interlayer insulating layer 180 is not distinguished, but the present disclosure is not limited thereto. For example, the boundary between the first interlayer insulating layer 160 and the second interlayer insulating layer 180 may be distinguished.

[0084] According to some example embodiments, the bit line connection wiring 170 may be connected to a plurality of bit lines BL spaced apart and arranged along the second direction DR2 through a plurality of bit line contacts 162 penetrating the first interlayer insulating layer 160. The bit line connection wiring 170 may connect the plurality of bit lines BL spaced apart and arranged along the second direction DR2. For example, the first bit line connection wiring 170_1 may connect the first bit line BL1 to the second bit line BL2. The second bit line connection wiring 170_2 may connect the third bit line BL3 to the fourth bit line BL4.

[0085] According to some example embodiments, a source line connection wiring 190 may be connected to a plurality of source lines SL spaced apart and arranged along a first direction DR1 via a plurality of source line contacts 166 that penetrate the first interlayer insulating layer 160 and the second interlayer insulating layer 180. The source line connection wiring 190 may connect the plurality of source lines SL spaced apart and arranged along the first direction DR1. For example, a first source line connection wiring 190_1 may connect the first source line SL1 and the third source line SL3. A second source line connection wiring 190_2 may connect the second source line SL2 and the fourth source line SL4.

[0086] According to some example embodiments, the bit line connection wiring 170 and the source line connection wiring 190 may connect the cell array structure CAS and the control circuit CU. The bit line connection wiring 170 and the source line connection wiring 190 may be connected to the control circuit CU through a through-hole 164 that penetrates the cell insulation layer 140. Each of the bit line connection wiring 170, the source line connection wiring 190, the bit line contact 162, the source line contact 166, and the through-hole 164 may include a conductive material.

[0087] Although not shown in the drawings, the source line connection wiring 190 may be connected to the control circuit CU through a via that penetrates the second interlayer insulating layer 180, the first interlayer insulating layer 160, and the cell insulating layer 140. The control circuit CU may transmit an input signal to the source line connection wiring 190 through the via. The source line connection wiring 190 may transmit an input signal to a plurality of source lines SL connected to the source line connection wiring 190 through the source line contact 166.

[0088] According to some example embodiments, the bit line connection wiring 170 may be connected to the analog-to-digital converter ADC connected between the cell array structure CAS and the control circuit CU. The bit line connection wiring 170 may be connected to the analog-to-digital converter ADC through the through-hole 164. Figure 1 and Figure 4 The via 164 can penetrate the first interlayer insulating layer 160 and the cell insulating layer 140 to connect the bit line connection wiring 170 to the converter transistor TRC. Output signals output from the plurality of bit lines BL can be transmitted to the bit line connection wiring 170 connected to the plurality of bit lines BL through the bit line contact 162. The output signal can be transmitted from the bit line connection wiring 170 to the analog-to-digital converter ADC through the via 164. The analog-to-digital converter ADC can receive the output signal from the bit line connection wiring 170 through the via 164. The analog-to-digital converter ADC can convert the output signal from an analog signal to a digital signal. The analog-to-digital converter ADC can transmit the converted output signal to the control circuit CU.

[0089] The converter transistor TRC and the control transistor TRCT may be electrically connected. According to some example embodiments, the converter transistor TRC and the control transistor TRCT may form a single circuit pattern, but the present disclosure is not limited thereto. According to some example embodiments, the semiconductor device 100 may further include a wiring layer connecting the converter transistor TRC and the control transistor TRCT in the peripheral circuit region PR.

[0090] Reference Figure 2 , the semiconductor device 100 may include a plurality of analog-to-digital converters ADC. Each of the plurality of analog-to-digital converters ADC may be connected to each of the plurality of bit line connection wirings 170. The control circuit CU may be connected to each of the plurality of analog-to-digital converters ADC. The control circuit CU may input an input signal to the cell array structure CAS based on the output signals (output') transmitted from the plurality of analog-to-digital converters ADC, or may output a final output signal (Final output).

[0091] In the above-described example embodiments, the cell array structure CAS is above or on the substrate 110, and the analog-to-digital converter ADC and the control circuit CU are arranged next to the cell array structure CAS, but the present disclosure is not limited to this. According to some example embodiments, in the semiconductor device 100, the analog-to-digital converter ADC and the control circuit CU and the insulating layer covering the analog-to-digital converter ADC and the control circuit CU may be arranged above or on the substrate 110, and the cell array structure CAS may be arranged above or on the insulating layer. This arrangement structure may be referred to as a cell on periphery (COP) structure. In the COP structure, the through-piece 164 may be connected to the analog-to-digital converter ADC or the control circuit CU by further penetrating the insulating layer covering the analog-to-digital converter ADC and the control circuit CU.

[0092] According to some example embodiments, the semiconductor device 100 may include a cell array structure CAS in which a plurality of memory cells including a ferroelectric layer 131 are stacked in a three-dimensional form, a control circuit CU, and a source line connection wiring 190 and a bit line connection wiring 170 connecting the cell array structure CAS and the control circuit CU and extending in directions intersecting each other. Therefore, the semiconductor device 100 may implement a deep neural network (DNN) in hardware.

[0093] According to some example embodiments, the semiconductor device 100 may apply an on / off signal to a word line WL in each of the multiple layers of the cell array structure CAS to turn on the memory cells MC in any one of the multiple layers and turn off the memory cells MC in the remaining layers of the multiple layers. Furthermore, an output signal may be obtained from the bit line BL of the turned-on memory cell MC based on an input signal input to the source line SL of the turned-on memory cell MC and the polarization state of the ferroelectric layer 131 of the turned-on memory cell MC. In this case, the multiple layers of the cell array structure CAS may correspond to the multiple hidden layers of a DNN, and the polarization state of the ferroelectric layer 131 may correspond to a weight value used in calculations for each hidden layer. According to some example embodiments, the source line connection wiring 190 that inputs an input signal to the source line SL and the bit line connection wiring 170 that outputs an output signal from the bit line BL may extend in a direction perpendicular to each other. Therefore, each of the output signals corresponding to the input signals input to the source lines SL can be output from each of the bit lines BL corresponding to the source lines SL, and the output signals output from the bit lines BL can be combined via the bit line connection wiring 170 for transmission to the analog-to-digital converter ADC and the control circuit CU. The semiconductor device 100 can use the output signals output from the memory cells MC of the previous layer as input signals for the memory cells MC of the next layer. The semiconductor device 100 can perform DNN calculations by repeating the above operation for all layers of the cell array structure CAS.

[0094] According to some example embodiments, the semiconductor device 100 may perform DNN calculations with ultra-low electric power based on data stored in and input to the plurality of memory cells MC without exchanging data with a separate computing device. According to some example embodiments, the semiconductor device 100 may implement a highly integrated or high-density memory device capable of performing DNN calculations with ultra-low electric power by stacking a plurality of memory cells MC including the ferroelectric layer 131 in a direction perpendicular to the upper surface of the substrate 110.

[0095] In the following, reference will be made to Figures 6 to 8 A semiconductor device 101 according to some example embodiments is described.

[0096] Figure 6 is a block diagram illustrating a signal flow between components of a semiconductor device according to some example embodiments. Figure 7 yes Figure 6 A plan view of a semiconductor device. Figure 8 It is along Figure 7 A cross-sectional view taken along line AA'.

[0097] Figure 6 Can be corresponding to Figure 2, Figure 7 Can be corresponding to Figure 3 , and Figure 8 Can be corresponding to Figure 4 Schematic diagram of . Figure 1 The structure of the cell array structure CAS shown in FIG can also be applied to Figures 6 to 8 semiconductor device 101.

[0098] The following will focus on Figures 6 to 8 The semiconductor device 101 and Figures 1 to 5 to describe the differences between the semiconductor device 100 Figures 6 to 8 The semiconductor device 101 will be briefly described or omitted for reference. Figures 6 to 8 The semiconductor device 101 described above with reference to Figures 1 to 5 The content described can be applied equally to the content. Figures 6 to 8 The components of the semiconductor device 101 are Figures 1 to 5 The same components of the semiconductor device 100 may be denoted by the same reference numerals.

[0099] Reference Figures 6 to 8 According to some example embodiments, a semiconductor device 101 may include a plurality of cell blocks BLK1 to BLKn, a control circuit CU, and a summing circuit ADCs. The plurality of cell blocks BLK1 to BLKn may include n cell blocks, where n is a natural number. Each of the plurality of cell blocks BLK1 to BLKn may include a cell array structure CAS, an analog-to-digital converter ADC, a bit line connection wiring 170 connecting the cell array structure CAS to the analog-to-digital converter ADC, and a source line connection wiring 190 connecting the cell array structure CAS to the control circuit CU.

[0100] According to some example embodiments, the summing circuit ADCs may be a circuit pattern configured to sum digital signals converted by the analog-to-digital converter ADC of each of the plurality of unit blocks BLK1 to BLKn. The summing circuit ADCs may be connected between the analog-to-digital converter ADC of each of the plurality of unit blocks BLK1 to BLKn and the control circuit CU.

[0101] The control circuit CU can input an input signal (input) to the cell array structure CAS of each of the multiple cell blocks BLK1 to BLKn based on an initial input signal (Initial input) received from the outside. The control circuit CU can input a layer control signal (layer control) to each layer of the cell array structure CAS of each of the multiple cell blocks BLK1 to BLKn. The layer control signal (layer control) turns on / off the transistors constituting the memory cells of each layer. The analog-to-digital converter ADC of each of the multiple cell blocks BLK1 to BLKn can convert an output signal (output) output from the cell array structure CAS from an analog signal to a digital signal. The control circuit CU can receive an output signal (output') from each of the multiple cell blocks BLK1 to BLKn, which is converted into a digital signal from the analog-to-digital converter ADC of each of the multiple cell blocks BLK1 to BLKn. The control circuit CU can transmit the output signal (output') received from the analog-to-digital converter ADC of each of the multiple cell blocks BLK1 to BLKn to the summing circuit ADCs. The summing circuit ADCs may transmit an output signal (output") which is a sum of output signals (output') of the plurality of unit blocks BLK1 to BLKn to the control circuit CU. The control circuit CU may output a final output signal (Final output) based on the output signal (output") received from the summing circuit ADCs.

[0102] In some example embodiments, the summing circuits ADCs may be omitted. In other words, each of the analog-to-digital converters ADC of the plurality of unit blocks BLK1 to BLKn may be directly connected to the control circuit CU. The control circuit CU may output a final output signal (Final output) based on the output signal (output') received from the analog-to-digital converter ADC of each of the plurality of unit blocks BLK1 to BLKn.

[0103] According to some example embodiments, the summing circuit ADCs may include a summing transistor TRS. Figure 8 In the embodiment, the summing transistor TRS may correspond to the summing circuit ADCs. Although for ease of description, Figure 8 One summing transistor TRS is shown in FIG. 1 , but the present disclosure is not limited thereto, and the summing circuit ADCs may also include more transistors or circuit elements other than transistors.

[0104] Hereinafter, description will be focused on some example embodiments in which the semiconductor apparatus 100 includes the summing circuit ADCs, but the present disclosure is not limited thereto, and the following description may be equally or similarly applied to some example embodiments in which the summing circuit ADCs are omitted.

[0105] According to some example embodiments, the converter transistor TRC, the summing transistor TRS, and the control transistor TRCT of each of the plurality of unit blocks BLK1 to BLKn may be disposed on or over the substrate 110. According to some example embodiments, a peripheral circuit insulating layer 120 covering the converter transistor TRC, the summing transistor TRS, and the control transistor TRCT may be disposed on the substrate 110.

[0106] According to some example embodiments, a wiring layer 122 and a lower contact 124 may be provided within the peripheral circuit insulating layer 120. The wiring layer 122 may include wirings connecting the converter transistor TRC, the summing transistor TRS, and the control transistor TRCT of each of the plurality of cell blocks BLK1 to BLKn. Figure 8 1 and 2. The wiring layer 122 is shown as a single layer in FIG. 2, but the present disclosure is not limited thereto and the wiring layer 122 may be formed of a plurality of layers. In this case, the plurality of layers may be spaced apart from each other in the third direction DR3 perpendicular to the upper surface of the substrate 110 by the peripheral circuit insulating layer 120.

[0107] Lower contacts 124 may penetrate peripheral circuit insulation layer 120 to connect wiring layer 122 to converter transistor TRC, summing transistor TRS, and control transistor TRCT. Wiring layer 122 and lower contacts 124 may include conductive materials. Converter transistor TRC, summing transistor TRS, and control transistor TRCT of each of the plurality of cell blocks BLK1 to BLKn may be electrically connected via wiring layer 122 and lower contacts 124.

[0108] According to some example embodiments, the cell array structure CAS of each of the plurality of cell blocks BLK1 to BLKn may be disposed on the peripheral circuit insulating layer 120. Figure 1 The structure of the cell array structure CAS shown in FIG. 2 may be similarly applied to the cell array structure CAS of each of the plurality of cell blocks BLK1 to BLkn.

[0109] According to some example embodiments, a cell insulating layer 140 surrounding the cell array structure CAS of each of the plurality of cell blocks BLK1 to BLKn may be disposed on the peripheral circuit insulating layer 120. The cell insulating layer 140 may cover an upper surface of the peripheral circuit insulating layer 120 disposed outside the plurality of cell blocks BLK1 to BLKn.

[0110] According to some example embodiments, a bit line connection wiring 170 and a source line connection wiring 190 may be stacked above the cell array structure CAS and the cell insulation layer 140 of each of the plurality of cell blocks BLK1 to BLKn. A first interlayer insulation layer 160 may be disposed above the cell array structure CAS and the cell insulation layer 140 of each of the plurality of cell blocks BLK1 to BLKn, and a plurality of bit line connection wirings 170 extending in the second direction DR2 may be disposed above the first interlayer insulation layer 160. For example, the plurality of bit line connection wirings 170 may include a first bit line connection wiring 170_1 connecting a first bit line BL1 and a second bit line BL2 spaced apart from each other in the second direction DR2, and a second bit line connection wiring 170_2 connecting a third bit line BL3 and a fourth bit line BL4 spaced apart from each other in the second direction DR2. The bit line connection wiring 170 may be connected to the bit lines BL via bit line contacts 162 penetrating the first interlayer insulation layer 160. A first interlayer insulating layer 160 may be disposed between the plurality of bit line connection wirings 170 of each of the plurality of cell blocks BLK1 to BLKn.

[0111] According to some example embodiments, a second interlayer insulating layer 180 may be disposed over the plurality of bit line connection wirings 170 and the first interlayer insulating layer 160 of each of the plurality of cell blocks BLK1 to BLKn, and a plurality of source line connection wirings 190 extending in the first direction DR1 may be disposed over the second interlayer insulating layer 180. For example, the plurality of source line connection wirings 190 may include a first source line connection wiring 190_1 connecting a first source line SL1 and a third source line SL3 spaced apart from each other in the first direction DR1, and a second source line connection wiring 190_2 connecting a second source line SL2 and a fourth source line SL4 spaced apart from each other in the first direction DR1. The source line connection wirings 190 may be connected by Figure 5 The source line contact 166 penetrating the second interlayer insulating layer 180 and the first interlayer insulating layer 160 is connected to the source line SL. The second interlayer insulating layer 180 may be provided between the plurality of source line connection wirings 190 of each of the plurality of cell blocks BLK1 to BLKn.

[0112] According to some example embodiments, the source line connection wiring 190 of each of the plurality of cell blocks BLK1 to BLKn is not Figure 8Instead, it may be connected to the control transistor TRCT of each of the plurality of cell blocks BLK1 to BLKn through a via. The via connecting the source line connection wiring 190 and the control transistor TRCT may penetrate the second interlayer insulating layer 180, the first interlayer insulating layer 160, the cell insulating layer 140, and the peripheral circuit insulating layer 120. The control circuit CU may transmit an input signal to the source line connection wiring 190 of each of the plurality of cell blocks BLK1 to BLKn through the via.

[0113] According to some example embodiments, the bit line connection wiring 170 of each of the plurality of cell blocks BLK1 to BLKn may be connected to the converter transistor TRC of each of the plurality of cell blocks BLK1 to BLKn through the through-via 164. The through-via 164 may connect the bit line connection wiring 170 to the analog-to-digital converter ADC by penetrating the first interlayer insulating layer 160, the cell insulating layer 140, and the peripheral circuit insulating layer 120. The analog-to-digital converter ADC of each of the plurality of cell blocks BLK1 to BLKn may convert an output signal transmitted from the bit line connection wiring 170 of each of the plurality of cell blocks BLK1 to BLKn from an analog signal to a digital signal through the through-via 164.

[0114] According to some example embodiments, a converted output signal (output′) output from the analog-to-digital converter ADC of each of the plurality of unit blocks BLK1 to BLKn may be transmitted to the summing circuit ADCs through the wiring layer 122 and the lower contact 124. The summing circuit ADCs may sum the output signals of the plurality of unit blocks BLK1 to BLKn. According to some example embodiments, a summed output signal (output″) output from the summing circuit ADCs may be transmitted to the control circuit CU through the wiring layer 122 and the lower contact 124.

[0115] According to some example embodiments, the control circuit CU may input an input signal to the cell array structure CAS of each of the plurality of cell blocks BLK1 to BLKn, or may output a final output signal (Final output) based on a converted output signal (output′) output from the analog-to-digital converter ADC of each of the plurality of cell blocks BLK1 to BLKn or a summed output signal (output”) output from the summing circuits ADCs.

[0116] According to some example embodiments, the semiconductor device 101 may perform DNN calculations with ultra-low electric power based on data stored in and input to the plurality of memory cells MC without exchanging data with a separate computing device. According to some example embodiments, the semiconductor device 100 may implement a highly integrated or high-density memory device capable of performing DNN calculations with ultra-low electric power by stacking a plurality of memory cells MC including the ferroelectric layer 131 in a direction perpendicular to the upper surface of the substrate 110.

[0117] For example, as the number of parameters used in DNN calculations increases, the number of memory cells MC included in the cell array structure CAS of the semiconductor device 101 may increase. As the number of memory cells MC increases, the length of the bit line connection wiring 170 and the source line connection wiring 190 connecting the cell array structure CAS and the control circuit CU may increase. If the length of the wiring increases, the signal transmitted through the wiring may be attenuated.

[0118] The semiconductor device 101 according to some example embodiments may include a plurality of unit blocks BLK1 to BLKn, each including a unit array structure CAS divided into a plurality of units on a plane, and may include an analog-to-digital converter ADC within each unit block BLK. Therefore, the semiconductor device 101 may convert analog signals output in units of blocks into digital signals, sum the converted digital signals, and transmit the summed digital signals to the control circuit CU to perform more accurate DNN calculations.

[0119] In the following, reference will be made to Figures 9 to 24 Describes methods for manufacturing according to some example embodiments Figure 1 Method for manufacturing a semiconductor device 100.

[0120] Figure 9 、 Figure 11 、 Figure 13 、 Figure 15 、 Figure 17 、 Figure 19 、 Figure 21 and Figure 23 are plan views illustrating a method for manufacturing a semiconductor device according to some example embodiments. Figure 10 、 Figure 12 、 Figure 14 、 Figure 16 、 Figure 18 、 Figure 20 、 Figure 22 and Figure 24 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some example embodiments. Figure 10 、 Figure 12 、 Figure 14 、 Figure 16 、 Figure 18 、 Figure 20 、 Figure 22 and Figure 24 Along Figure 9 、 Figure 11 、 Figure 13 、 Figure 15 、 Figure 17 、 Figure 19 、 Figure 21 and Figure 23 A cross-sectional view taken along line AA'.

[0121] Reference Figure 9 and Figure 10 , a converter transistor TRC and a control transistor TRCT may be formed on a substrate 110. The converter transistor TRC may be Figure 2 The control transistor TRCT can be Figure 2 The converter transistor TRC and the control transistor TRCT may be electrically connected.

[0122] The substrate 110 may include a cell region CR and a peripheral circuit region PR. The peripheral circuit region PR may be disposed adjacent to the cell region CR. The converter transistor TRC and the control transistor TRCT may be formed in the peripheral circuit region PR of the substrate 110.

[0123] Reference Figure 11 and Figure 12 , a mold structure MS may be formed on the substrate 110. Figure 9 A mold structure MS is formed at the cell region CR of the substrate 110. The mold structure MS may include a plurality of first insulating layers ILD1 and a plurality of second insulating layers ILD2 stacked in a third direction DR3 perpendicular to the upper surface of the substrate 110. The first insulating layers ILD1 and the second insulating layers ILD2 may include different insulating materials having etching selectivity. For example, the first insulating layer ILD1 may be a silicon oxide layer, and the second insulating layer ILD2 may be a silicon nitride layer, but the present disclosure is not limited thereto.

[0124] The first insulating layer ILD1 may be Figure 9 The cell region CR extends to Figure 9 The peripheral circuit area PR. Figure 9 In the peripheral circuit region PR, the first insulating layer ILD1 may cover the converter transistor TRC, the control transistor TRCT, and an upper surface of the substrate 110 .

[0125] Next, a trench T penetrating the mold structure MS may be formed. For example, the mold structure MS may be anisotropically etched to form a trench T penetrating the mold structure MS along the third direction DR3. The trench T may have a linear shape extending in a first direction DR1 parallel to the upper surface of the substrate 110. Both side surfaces of the trench T may face each other in a second direction DR2 intersecting (e.g., perpendicular) to the first direction DR1. The side surfaces of the plurality of first insulating layers ILD1 and the plurality of second insulating layers ILD2 may be exposed through the trench T.

[0126] Reference Figure 13 and Figure 14 , a ferroelectric material layer 131_L, a gate insulating material layer 132_L, and a channel material layer 133_L may be sequentially formed in the trench T.

[0127] The ferroelectric material layer 131_L may be formed by a deposition process, such as atomic layer deposition (ALD) or chemical vapor deposition (CVD), to conformally cover the lower surface and inner surface of the trench T. The ferroelectric material layer 131_L may cover the upper surface of the substrate 110. The ferroelectric material layer 131_L may cover the side surfaces of the plurality of first insulating layers ILD1 and the plurality of second insulating layers ILD2 exposed by the trench T.

[0128] The ferroelectric material layer 131_L may include a ferroelectric material. In some example embodiments, the ferroelectric material layer 131_L may include an Hf compound. For example, the ferroelectric material may include HfO2, HfZnO, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or a combination thereof.

[0129] The gate insulating material layer 132_L may be formed by a deposition process such as atomic layer deposition (ALD) or chemical vapor deposition (CVD) to conformally cover the ferroelectric material layer 131_L. For example, the gate insulating material layer 132_L may include silicon oxide, silicon oxynitride, a high dielectric constant material having a dielectric constant higher than that of silicon oxide, or a combination thereof.

[0130] The channel material layer 133_L may be formed by a deposition process, such as atomic layer deposition (ALD) or chemical vapor deposition (CVD), to conformally cover the gate insulating material layer 132_L. The channel material layer 133_L may include at least one of a semiconductor material, an amorphous oxide semiconductor material, and a two-dimensional material. For example, the channel material layer 133_L may include IGZO.

[0131] According to some example embodiments, a ferroelectric material layer 131_L may be deposited to cover the upper surface of the first insulating layer ILD1 that is farthest from the upper surface of the substrate 110. Subsequently, a gate insulating material layer 132_L and a channel material layer 133_L may be sequentially deposited on the ferroelectric material layer 131_L. Subsequently, portions of the ferroelectric material layer 131_L, the gate insulating material layer 132_L, and the channel material layer 133_L that are disposed at a level higher than the level of the upper surface of the first insulating layer ILD1 may be removed by a chemical mechanical polishing (CMP) process. That is, the upper surfaces of the ferroelectric material layer 131_L, the gate insulating material layer 132_L, and the channel material layer 133_L may be disposed at substantially the same level as the upper surface of the first insulating layer ILD1 that is farthest from the upper surface of the substrate 110.

[0132] Each of the ferroelectric material layer 131_L, the gate insulating material layer 132_L and the channel material layer 133_L may include a horizontal portion covering the bottom surface of the trench T and parallel to the upper surface of the substrate 110 and vertical portions extending from the horizontal portion along the third direction DR3 and facing each other in the second direction DR2 of the trench T.

[0133] Reference Figure 15 and Figure 16 , a plurality of channel layers 133 may be formed by patterning the channel material layer 133_L.

[0134] According to some example embodiments, the channel material layer 133_L extending in the first direction DR1 may be cut by an anisotropic etching process to be divided into a plurality of channel layers 133 spaced apart along the first direction DR1. In the etching process, the gate insulating material layer 132_L may also be cut together with the channel material layer 133_L.

[0135] During the etching process, portions of the vertical portions of the ferroelectric material layer 131_L that face each other in the second direction DR2 may be removed. Therefore, the thickness of each of the vertical portions of the ferroelectric layer 131 on a plane (e.g., the width along the second direction DR2) may not be constant. According to some example embodiments, a portion of the ferroelectric layer 131 that overlaps with the channel layer 133 in the second direction DR2 may be thicker than a portion of the ferroelectric layer 131 that does not overlap with the channel layer 133 in the second direction DR2.

[0136] Next, an insulating pattern 150 may be formed to fill a remaining space of the trench T. The insulating pattern 150 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0137] According to some example embodiments, an insulating material layer including at least one of silicon oxide, silicon nitride, and silicon oxynitride may be deposited to fill the remaining space of the trench T. The insulating material layer may fill the remaining space of the trench T and may cover the upper surface of the first insulating layer ILD1 farthest from the upper surface of the substrate 110, the channel layer 133, the gate insulating layer 132, and the ferroelectric layer 131. Subsequently, a portion of the insulating material layer disposed at a level higher than the level of the upper surface of the first insulating layer ILD1 farthest from the upper surface of the substrate 110, the channel layer 133, the gate insulating layer 132, and the ferroelectric layer 131 may be removed by a chemical mechanical polishing (CMP) process. The upper surface of the insulating pattern 150 may be disposed at substantially the same level as the upper surface of the first insulating layer ILD1 farthest from the upper surface of the substrate 110, the channel layer 133, the gate insulating layer 132, and the ferroelectric layer 131.

[0138] The insulating pattern 150 may have a columnar shape extending in the third direction DR3. The insulating pattern 150 may be disposed between vertical portions of the ferroelectric layer 131. The insulating pattern 150 may cover side surfaces of the plurality of gate insulating layers 132 and the plurality of channel layers 133 spaced apart in the first direction DR1. The plurality of channel layers 133 spaced apart in the first direction DR1 by the insulating pattern 150 may be insulated.

[0139] Reference Figure 17 and Figure 18 Each of the plurality of vertical structures VS including a source line SL and a bit line BL may be formed. The source line SL and the bit line BL may have a pillar shape that penetrates the channel layer 133 and the insulating pattern 150 along the third direction DR3. The source line SL and the bit line BL may be spaced apart in the first direction DR1. The channel layer 133 may protrude in the second direction DR2 between the source line SL and the bit line BL.

[0140] Each of the source line SL and the bit line BL may include a conductive material. For example, each of the source line SL and the bit line BL may include at least one selected from a doped semiconductor material, a conductive metal nitride, a metal, and a metal semiconductor compound.

[0141] According to some example embodiments, the plurality of vertical structures VS may include a first vertical structure VS1 and a second vertical structure VS2 spaced apart along a second direction DR2 between vertical portions of the ferroelectric layer 131. A first bit line BL1 of the first vertical structure VS1 and a second bit line BL2 of the second vertical structure VS2 may face each other in the second direction DR2. A first source line SL1 of the first vertical structure VS1 and a second source line SL2 of the second vertical structure VS2 may face each other in the second direction DR2.

[0142] According to some example embodiments, the plurality of vertical structures VS may include a third vertical structure VS3 spaced apart from the first vertical structure VS1 in a first direction DR1 and a fourth vertical structure VS4 spaced apart from the second vertical structure VS2 in the first direction DR1. A first source line SL1 and a first bit line BL1 of the first vertical structure VS1 and a third source line SL3 and a third bit line BL3 of the third vertical structure VS3 may be arranged along the first direction DR1. A second source line SL2 and a second bit line BL2 of the second vertical structure VS2 and a fourth source line SL4 and a fourth bit line BL4 of the fourth vertical structure VS4 may be arranged along the first direction DR1.

[0143] Reference Figure 19 and Figure 20 A word line cut trench WCT may be formed between the ferroelectric layers 131 along the third direction DR3, penetrating the first insulating layers ILD1 and the second insulating layers ILD2. The word line cut trench WCT may have a linear shape extending in the first direction DR1. Side surfaces of the first insulating layers ILD1 and the second insulating layers ILD2 may be exposed through the word line cut trench WCT.

[0144] Subsequently, the plurality of second insulating layers ILD2 may be replaced with a plurality of word lines WL1, WL2, and WL3. According to some example embodiments, the plurality of second insulating layers ILD2 may be selectively removed by providing an etchant having a high etch selectivity relative to the second insulating layer ILD2 of the first insulating layer ILD1 and the second insulating layer ILD2 through the word line cutting trench WCT. The plurality of word lines WL1, WL2, and WL3 may be formed by filling the region where the plurality of second insulating layers ILD2 are removed with a conductive material. A word line structure WLS may be formed on one side of each of the vertical portions of the ferroelectric layer 131, wherein the plurality of word lines WL1, WL2, and WL3 are stacked in the third direction DR3. For example, the plurality of word lines WL1, WL2, and WL3 may include at least one selected from a doped semiconductor material, a conductive metal nitride, a metal, and a metal semiconductor compound.

[0145] Can be achieved through Figures 12 to 20 The process shown forms a cell array structure CAS. The cell array structure CAS may include a plurality of ferroelectric layers 131 spaced apart and arranged along the second direction DR2. The cell array structure CAS may include a plurality of gate insulating layers 132, a plurality of channel layers 133, a plurality of vertical structures VS1, VS2, VS3, and VS4, each surrounded by the plurality of ferroelectric layers 131, and an insulating pattern 150. The cell array structure CAS may include a word line structure WLS adjacent to an outer portion of each of the plurality of ferroelectric layers 131.

[0146] Next, an insulating material layer may be formed within the word line cut trench WCT. According to some example embodiments, the insulating material layer filling the word line cut trench WCT may include the same insulating material as the first insulating layer ILD1. Therefore, the insulating material layer filling the word line cut trench WCT and the first insulating layer ILD1 disposed between the plurality of word lines WL1, WL2, and WL3 may form an integral cell insulating layer 140. The cell insulating layer 140 may surround the cell array structure CAS. The cell insulating layer 140 may cover the converter transistor TRC and the control transistor TRCT disposed on the substrate 110 outside the cell array structure CAS.

[0147] Reference Figure 21 and Figure 22 , a first interlayer insulating layer 160 and a plurality of bit line connection wirings 170_1 and 170_2 extending in the second direction DR2 may be formed above or over the cell array structure CAS and the cell insulating layer 140 .

[0148] According to some example embodiments, an insulating material layer may be deposited by a deposition process such as chemical vapor deposition (CVD) or physical vapor deposition (PVD), and a plurality of contact holes may be formed penetrating the insulating material layer along the third direction DR3. The upper surface of the bit line BL may be exposed through the contact holes.

[0149] Subsequently, a conductive material layer may be deposited to fill the plurality of contact holes. The conductive material layer may fill the plurality of contact holes and may cover the upper surface of the insulating material layer. When the conductive material layer is filled in the plurality of contact holes, a plurality of bit line contacts 162 may be formed.

[0150] Next, the conductive material layer may be patterned to form a plurality of bit line connection wirings 170_1 and 170_2 having a line shape passing through contact holes spaced apart along the second direction DR2. The plurality of bit line connection wirings 170_1 and 170_2 and the plurality of bit lines BL may be connected through a plurality of bit line contacts 162. According to some example embodiments, the plurality of bit line connection wirings 170_1 and 170_2 may include a first bit line connection wiring 170_1 connecting a first bit line BL1 and a second bit line BL2 spaced apart from each other along the second direction DR2, and a second bit line connection wiring 170_2 connecting a third bit line BL3 and a fourth bit line BL4 spaced apart from each other along the second direction DR2.

[0151] Next, an insulating material layer may be further deposited to form a first interlayer insulating layer 160. The first interlayer insulating layer 160 may surround side surfaces of the plurality of bit line contacts 162 and may be disposed between the plurality of bit line connection wirings 170_1 and 170_2.

[0152] According to some example embodiments, a through-hole 164 may be formed that penetrates the cell insulating layer 140 to connect each of the plurality of bit line connection wirings 170_1 and 170_2 to the converter transistor TRC. For example, a through-hole may be formed that penetrates each of the plurality of bit line connection wirings 170_1 and 170_2, the first interlayer insulating layer 160, and the cell insulating layer 140, and the through-hole 164 may be formed by depositing a conductive material layer within the through-hole. Each of the plurality of bit line connection wirings 170_1 and 170_2 may be connected to the converter transistor TRC of each of the plurality of analog-to-digital converters through the through-hole 164.

[0153] Reference Figure 23 and Figure 24 A second interlayer insulating layer 180 and a plurality of source line connection wirings 190_1 and 190_2 extending in the first direction DR1 may be formed above or over the plurality of bit line connection wirings 170_1 and 170_2 and the first interlayer insulating layer 160 .

[0154] According to some example embodiments, an insulating material layer may be deposited by a deposition process such as chemical vapor deposition (CVD) or physical vapor deposition (PVD), and a plurality of contact holes may be formed penetrating the insulating material layer along the third direction DR3 . The upper surface of the source line SL may be exposed through the contact holes.

[0155] Subsequently, a conductive material layer may be deposited to fill the plurality of contact holes. The conductive material layer may fill the plurality of contact holes and may cover the upper surface of the insulating material layer. When the conductive material layer is filled in the plurality of contact holes, a plurality of source line contacts may be formed.

[0156] Next, the conductive material layer may be patterned to form a plurality of source line connection wirings 190_1 and 190_2 having a line shape passing through contact holes spaced apart along the first direction DR1. The plurality of source line connection wirings 190_1 and 190_2 and the plurality of source lines SL may be connected via a plurality of source line contacts. According to some example embodiments, the plurality of source line connection wirings 190_1 and 190_2 may include a first source line connection wiring 190_1 connecting a first source line SL1 and a third source line SL3 spaced apart from each other along the first direction DR1, and a second source line connection wiring 190_2 connecting a second source line SL2 and a fourth source line SL4 spaced apart from each other along the first direction DR1.

[0157] Subsequently, an insulating material layer may be further deposited to form a second interlayer insulating layer 180. The second interlayer insulating layer 180 may surround side surfaces of the plurality of source line contacts and may be disposed between the plurality of source line connection wirings 190_1 and 190_2.

[0158] According to some example embodiments, a via may be formed that penetrates the cell insulating layer 140 to connect each of the plurality of source line connection wirings 190_1 and 190_2 to the control transistor TRCT. For example, a via may be formed that penetrates each of the plurality of source line connection wirings 190_1 and 190_2, the second interlayer insulating layer 180, the first interlayer insulating layer 160, and the cell insulating layer 140, and the via may be formed by depositing a conductive material layer within the via. Each of the plurality of source line connection wirings 190_1 and 190_2 may be connected to the control transistor TRCT of the control circuit through the via.

[0159] Can be achieved through Figures 9 to 24 The semiconductor device 100 according to some example embodiments is formed using the process shown in FIG. The semiconductor device 100 may include a cell array structure CAS and a control transistor TRCT of a control circuit CU of the cell array structure CAS. The semiconductor device 100 may include a converter transistor TRC of an analog-to-digital converter ADC connected between the cell array structure CAS and the control circuit CU. The semiconductor device 100 may include a plurality of bit line connection wirings 170_1 and 170_2 and a plurality of source line connection wirings 190_1 and 190_2. Each of the plurality of bit line connection wirings 170_1 and 170_2 may connect bit lines BL spaced apart in a second direction DR2 of the cell array structure CAS to the converter transistor TRC. Each of the plurality of source line connection wirings 190_1 and 190_2 may connect source lines SL spaced apart in a first direction DR1 of the cell array structure CAS to the control transistor TRCT.

[0160] While the disclosure has been described in connection with what are presently considered to be some example embodiments, it is to be understood that the disclosure is not limited to the disclosed example embodiments, but on the contrary, the disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A semiconductor device comprising: a substrate including a cell region and a peripheral circuit region; a vertical structure extending in a direction perpendicular to an upper surface of the substrate at the cell region, the vertical structure including a bit line and a source line spaced apart in a first direction parallel to the upper surface of the substrate; a word line extending along the first direction at one side of the vertical structure; a channel layer located between the bit line and the word line and between the source line and the word line, the channel layer being connected between the bit line and the source line; a ferroelectric layer located between the word line and the channel layer; a control circuit located on the substrate at the peripheral circuit region; a source line connection wiring connected to the source line and the control circuit; as well as a bit line connection wiring connected to the bit line and the control circuit, The source line connection wiring and the bit line connection wiring intersect in a plane.

2. The semiconductor device according to claim 1, wherein The source line connection wiring and the bit line connection wiring are separated by an interlayer insulating layer in a direction perpendicular to an upper surface of the substrate.

3. The semiconductor device according to claim 1 , further comprising: an analog-to-digital converter located on the substrate and connected between the bit line and the control circuit, The bit line connection wiring is connected to the analog-to-digital converter.

4. The semiconductor device according to claim 3, further comprising: a cell array structure comprising the vertical structure and a word line structure, wherein the word line structure comprises a plurality of word lines stacked in a direction perpendicular to an upper surface of the substrate, the ferroelectric layer and the channel layer located between the vertical structure and the word line structure; a cell insulating layer surrounding the cell array structure; as well as A through-hole penetrates the cell insulating layer to connect the bit line connection wiring to the analog-to-digital converter.

5. The semiconductor device according to claim 4, wherein The control circuit, the analog-to-digital converter, and a peripheral circuit insulation layer covering the analog-to-digital converter and the control circuit are located on the substrate. The cell array structure and the cell insulating layer are located on the peripheral circuit insulating layer, The bit line connection wiring and the source line connection wiring are stacked above the cell array structure and the cell insulating layer, and The through-hole further penetrates the peripheral circuit insulating layer.

6. The semiconductor device according to claim 5, further comprising: Multiple unit blocks; as well as Summing circuit, wherein each of the plurality of cell blocks comprises the cell array structure and the analog-to-digital converter connected to the cell array structure, and The summing circuit is connected between the analog-to-digital converter of each of the plurality of unit blocks and the control circuit.

7. The semiconductor device according to claim 1, wherein The ferroelectric layer includes a horizontal portion parallel to the upper surface of the substrate, the ferroelectric layer includes a first vertical portion and a second vertical portion, and the first vertical portion and the second vertical portion are perpendicular to the upper surface of the substrate and spaced apart in a second direction intersecting the first direction, and A plurality of vertical structures are located between the first vertical portion and the second vertical portion.

8. The semiconductor device according to claim 7, wherein The plurality of vertical structures include a first vertical structure and a second vertical structure spaced apart in the second direction, The first source line of the first vertical structure and the second source line of the second vertical structure face each other in the second direction, The first bit line of the first vertical structure and the second bit line of the second vertical structure face each other in the second direction, and The bit line connection wiring connects the first bit line and the second bit line.

9. The semiconductor device according to claim 8, wherein The plurality of vertical structures further include a third vertical structure spaced apart from the first vertical structure in the first direction and a fourth vertical structure spaced apart from the second vertical structure in the first direction, The first source line of the first vertical structure and the third source line of the third vertical structure are parallel in the first direction, The second source line of the second vertical structure and the fourth source line of the fourth vertical structure are parallel in the first direction, and The source line connection wiring includes a first source line connection wiring connecting the first source line and the third source line, and a second source line connection wiring connecting the second source line and the fourth source line.

10. The semiconductor device according to claim 9, further comprising: Multiple word line structures, wherein each of the plurality of word line structures comprises a plurality of word lines stacked in a direction perpendicular to the upper surface of the substrate, The plurality of word line structures include a first word line structure located at one side of the first vertical portion of the ferroelectric layer and a second word line structure located at one side of the second vertical portion of the ferroelectric layer, and The first word line structure and the second word line structure are located on opposite side surfaces of the first vertical portion and the second vertical portion, the side surfaces being spaced apart in the second direction.

11. The semiconductor device according to claim 10, further comprising: Multiple channel layers, Wherein, the plurality of channel layers include: a first channel layer located between the first word line structure and the first vertical structure and between the second word line structure and the second vertical structure, and a second channel layer located between the first word line structure and the third vertical structure and between the second word line structure and the fourth vertical structure, and The first channel layer and the second channel layer are spaced apart in the first direction.

12. The semiconductor device according to claim 11, wherein The first vertical portion of the ferroelectric layer is located between the first word line structure and the first channel layer and between the first word line structure and the second channel layer, and The second vertical portion of the ferroelectric layer is located between the second word line structure and the first channel layer and between the second word line structure and the second channel layer.

13. A semiconductor device comprising: a substrate including a cell region and a peripheral circuit region; a vertical structure extending in a direction perpendicular to an upper surface of the substrate at the cell region, the vertical structure including a bit line and a source line spaced apart in a first direction parallel to the upper surface of the substrate; a word line extending along the first direction at one side of the vertical structure; a channel layer located between the bit line and the word line and between the source line and the word line, the channel layer being connected between the bit line and the source line; a ferroelectric layer located between the word line and the channel layer; a control circuit located on the substrate at the peripheral circuit region; as well as a source line connection wiring and a bit line connection wiring, the source line connection wiring and the bit line connection wiring extending in a direction parallel to the upper surface of the substrate, the source line connection wiring and the bit line connection wiring being stacked above the vertical structure, The source line connection wiring extends in the first direction, and the bit line connection wiring extends in a second direction orthogonal to the first direction.

14. The semiconductor device according to claim 13, wherein The source line connection wiring and the bit line connection wiring are separated by an interlayer insulating layer in a direction perpendicular to an upper surface of the substrate.

15. The semiconductor device according to claim 13, further comprising: an analog-to-digital converter located on the substrate and connected between the bit line and the control circuit, The bit line connection wiring is connected to the analog-to-digital converter.

16. The semiconductor device according to claim 13, wherein The ferroelectric layer includes a horizontal portion parallel to the upper surface of the substrate, a first vertical portion and a second vertical portion perpendicular to the upper surface of the substrate, the first vertical portion and the second vertical portion are spaced apart in the second direction, and A plurality of vertical structures are located between the first vertical portion and the second vertical portion.

17. The semiconductor device according to claim 16, wherein The plurality of vertical structures include a first vertical structure and a second vertical structure spaced apart in the second direction, The first source line of the first vertical structure and the second source line of the second vertical structure face each other in the second direction, The first bit line of the first vertical structure and the second bit line of the second vertical structure face each other in the second direction, and The bit line connection wiring extends in the second direction over the first vertical structure and the second vertical structure and connects the first bit line and the second bit line.

18. The semiconductor device according to claim 17, wherein The plurality of vertical structures further include a third vertical structure spaced apart from the first vertical structure in the first direction and a fourth vertical structure spaced apart from the second vertical structure in the first direction, The first source line of the first vertical structure and the third source line of the third vertical structure are parallel in the first direction, The second source line of the second vertical structure and the fourth source line of the fourth vertical structure are parallel in the first direction, and The source line connection wiring includes a first source line connection wiring connecting the first source line and the third source line, and a second source line connection wiring connecting the second source line and the fourth source line.

19. A semiconductor device comprising: a substrate including a cell region and a peripheral circuit region; a vertical structure extending in a direction perpendicular to an upper surface of the substrate at the cell region, the vertical structure including a bit line and a source line spaced apart in a first direction parallel to the upper surface of the substrate; a word line extending along the first direction at one side of the vertical structure; a channel layer located between the bit line and the word line and between the source line and the word line, the channel layer being connected between the bit line and the source line; a ferroelectric layer located between the word line and the channel layer; a control circuit located on the substrate at the peripheral circuit region; an analog-to-digital converter located on the substrate and connected to the control circuit; a source line connection wiring above the vertical structure and connected to the source line and the control circuit; as well as a bit line connection wiring above the vertical structure and connected to the bit line and the analog-to-digital converter, The source line connection wiring and the bit line connection wiring are located in different layers, one of the source line connection wiring and the bit line connection wiring extends in a direction parallel to the word line, and the other of the source line connection wiring and the bit line connection wiring extends in a direction crossing the word line.

20. The semiconductor device according to claim 19, wherein The source line connection wiring and the bit line connection wiring are spaced apart in a direction perpendicular to an upper surface of the substrate.

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