A metallic capacitor structure and its fabrication method

Abstract

This invention provides a metal capacitor structure and its fabrication method. A TixOy transition layer is grown in situ at the interface between the first electrode and the insulating layer using plasma technology, successfully solving the problem of high interface roughness. Furthermore, the bandgap of TixOy is greater than that of titanium nitride. The transition layer hinders carrier migration across the interface, thereby suppressing leakage current at the interface and improving the withstand voltage of the insulating layer. The formation of a first oxide layer on the surface of the insulating layer using plasma technology reduces interface defects, avoids abnormal charge accumulation, and reduces the concentration of localized strong electric fields that lead to early breakdown, fundamentally delaying the occurrence of breakdown. The active Si atoms in the silicon-rich oxide layer can capture plasma charges, making the silicon-rich oxide layer a charge neutralization layer. This prevents the accumulation of charges generated during the plasma process on the insulating layer and their migration and accumulation into the insulating layer, further enhancing the overall breakdown resistance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a metal capacitor structure and its fabrication method. Background Technology

[0002] Capacitors are used in semiconductor integrated circuits as charge storage, coupling, and filtering devices. Among them, the metal-insulator-metal (MIM) capacitor structure is widely used in analog and radio frequency (RF) circuits due to its advantages such as low parasitic resistance, stable frequency characteristics, and the ability to be directly formed using the interconnect layers of the device. The requirements for the parasitic resistance of metal capacitors vary depending on the application. For example, in RF circuit applications, due to the high frequency (GHz), the capacitive reactance is low, and the parasitic resistance of the entire metal capacitor is high, so it is necessary to minimize the parasitic resistance of the metal capacitor. However, for low-frequency analog circuits, such as panel driver chips, when the metal capacitor is used as a charge pump, the breakdown voltage (BV) becomes a critical parameter restricting the reliability of the device. A higher breakdown voltage (usually at least 25V) can effectively ensure the stability of the dielectric layer under long-term high-voltage stress and avoid the failure risk caused by time-dependent dielectric breakdown (TDDB).

[0003] Figure 1 The diagram shown is a cross-sectional view of a metal capacitor structure in the prior art. (See attached diagram.) Figure 1 The metal capacitor structure includes a substrate and a capacitor structure formed on the substrate. From bottom to top, the capacitor structure includes a barrier layer, a lower electrode, a capacitor insulating layer, an upper electrode, and an anti-reflection layer stacked on the substrate. Part of the upper electrode is removed by photolithography and selective etching, and the anti-reflection layer covers the capacitor insulating layer. Then, part of the lower electrode is removed by photolithography and selective etching. On the one hand, the multiple patterning steps expose the capacitor insulating layer to the plasma environment, easily leading to surface defects and increased interface state density, weakening the insulation strength of the capacitor insulating layer. On the other hand, as... Figure 2 The TEM image of the prior art metal capacitor structure shown reveals that the surface roughness of the lower electrode is high, resulting in non-uniform coverage of the capacitor insulation layer. This leads to a significantly higher actual electric field strength at weak points compared to the theoretical value, easily inducing early breakdown. Furthermore, when this metal capacitor structure is applied to the manufacture of semiconductor devices, breakdown voltage tests show that the breakdown voltage of the metal capacitor structure is only 17.7V, far below the conventional requirement of 25V, thus greatly reducing the reliability of the semiconductor device.

[0004] Therefore, there is a need to provide a metal capacitor structure and its fabrication method to solve the problem of low breakdown voltage in metal capacitor structures. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a metal capacitor structure and its preparation method, so as to solve the problem of low breakdown voltage of metal capacitor structures in the prior art and the resulting reduction in device reliability.

[0006] To achieve the above and other related objectives, the present invention provides a method for preparing a metal capacitor structure, the method comprising:

[0007] A substrate is provided, and an etch barrier layer and a first electrode are sequentially fabricated on the substrate;

[0008] The surface of the first electrode plate is oxidized using a first plasma to form a transition layer on the first electrode plate;

[0009] An insulating layer is deposited on the transition layer, and the surface of the insulating layer is oxidized using a first plasma to form a first oxide layer on the insulating layer;

[0010] A second electrode plate and a first anti-reflection layer are formed on the first oxide layer. The second electrode plate is partially etched based on the first anti-reflection layer as a mask layer to expose the insulating layer, and the first anti-reflection layer is removed.

[0011] The surface of the second electrode plate and the insulating layer are oxidized using a second plasma to form a second oxide layer on the second electrode plate and a third oxide layer on the insulating layer.

[0012] A silicon-rich oxide layer and a second anti-reflection layer are sequentially formed on the second oxide layer and the third oxide layer, wherein the silicon-rich oxide layer covers the second oxide layer and the third oxide layer, and the second anti-reflection layer covers the silicon-rich oxide layer;

[0013] The first electrode plate is etched to remove a portion of it.

[0014] Optionally, the first plasma is oxygen, and the second plasma is nitrous oxide gas.

[0015] Optionally, the process temperature for oxidizing the surface of the first electrode plate using the first plasma is set to 200°C to 420°C, and the process temperature for oxidizing the surface of the insulating layer using the first plasma is set to 200°C to 420°C.

[0016] Optionally, the oxidation treatment time of the first electrode plate using the first plasma is 10~200s, and the oxidation treatment time of the insulating layer using the first plasma is 10~200s.

[0017] Optionally, the process temperature for oxidizing the surface of the second electrode plate and the insulating layer using the second plasma is set to 300°C to 420°C, and the oxidation time for oxidizing the surface of the second electrode plate and the insulating layer using the second plasma is 10 to 200 seconds.

[0018] Optionally, the width of the second electrode plate after partial etching is smaller than the width of the first electrode plate after etching.

[0019] Optionally, the thickness of the silicon-rich oxide layer is 100~300 Å.

[0020] Optionally, the materials of the first electrode and the second electrode include titanium nitride.

[0021] Optionally, the insulating layer may be made of silicon nitride.

[0022] The present invention also provides a metal capacitor structure, which is manufactured using the metal capacitor structure preparation method described above.

[0023] As described above, this invention provides a metal capacitor structure and its fabrication method, which has the following beneficial effects: A TixOy transition layer is grown in situ at the interface between the first electrode and the insulating layer using plasma technology. This transition layer successfully solves the problem of high interface roughness in traditional processes. Furthermore, the band gap of TixOy is larger than that of titanium nitride, making the transition layer an effective charge barrier that significantly hinders carrier migration across the interface, thereby efficiently suppressing leakage current at the interface and improving the withstand voltage of the insulating layer. This invention applies plasma technology to the oxidation treatment of the insulating layer surface to form a first oxide layer, thus improving the interface roughness of the insulating layer surface. The significant reduction in surface defects, pinholes, or uneven areas prevents abnormal charge accumulation, resulting in a more balanced voltage distribution during device operation. This significantly reduces the concentration of localized strong electric fields that could lead to early breakdown, fundamentally delaying the occurrence of breakdown. The excess active Si atoms in the silicon-rich oxide layer can capture plasma charges generated during the plasma process, allowing the silicon-rich oxide layer to act as a charge neutralization layer. This actively consumes and prevents the accumulation of charges generated during the plasma process on the insulating layer and their migration and accumulation into the insulating layer, further enhancing the overall breakdown resistance. Breakdown voltage tests on the metal capacitor structure show a breakdown voltage of 27 V. A high breakdown voltage is one of the most crucial indicators for evaluating the stable operation of capacitors under high-voltage environments. Its substantial improvement means that the device's ability to withstand abnormal voltage stress without failure under complex operating conditions (such as high temperature, high humidity, and high bias voltage) is greatly enhanced. This not only significantly reduces the risk of accidental failure due to voltage overload during application but also provides a solid foundation for ensuring the long-term, stable, and reliable operation of the device, significantly extending its service life. Attached Figure Description

[0024] Figure 1 The diagram shown is a cross-sectional view of a metal capacitor structure in the prior art.

[0025] Figure 2 The image shown is a TEM image of a metal capacitor structure in the prior art.

[0026] Figure 3 The diagram shows a flow chart of the method for preparing the metal capacitor structure of the present invention.

[0027] Figure 4 The diagram shows a cross-sectional structure of the present invention after an etching barrier layer and a first electrode plate are formed on a substrate.

[0028] Figure 5 The diagram shows a cross-sectional structure after the transition layer is formed according to the present invention.

[0029] Figure 6 The diagram shows a cross-sectional structure after the formation of the insulating layer and the first oxide layer according to the present invention.

[0030] Figure 7 The diagram shows a cross-sectional structure of the second electrode plate and the first anti-reflective layer after the present invention is formed.

[0031] Figure 8 The diagram shows a cross-sectional structure of the second electrode plate after partial etching according to the present invention.

[0032] Figure 9 The diagram shows a cross-sectional structure after the formation of the second oxide layer and the third oxide layer in this invention.

[0033] Figure 10 The diagram shows a cross-sectional structure after the formation of the silicon-rich oxide layer and the second anti-reflection layer according to the present invention.

[0034] Figure 11 The diagram shows a cross-sectional structure of the first electrode plate after partial etching according to the present invention.

[0035] Component designation explanation

[0036] 11. Substrate; 12. Barrier layer; 13. Lower electrode; 14. Capacitor insulating layer; 15. Upper electrode; 16. Anti-reflection layer; 101. Substrate; 1011. Dielectric layer; 1012. Metal via; 102. Etching barrier layer; 103. First electrode; 104. Transition layer; 105. Insulating layer; 106. First oxide layer; 107. Second electrode; 108. First anti-reflection layer; 109. Second oxide layer; 110. Third oxide layer; 111. Silicon-rich oxide layer; 112. Second anti-reflection layer; S1~S7. Steps. Detailed Implementation

[0037] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0038] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0039] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, when a layer is referred to as “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0040] Please see Figures 3 to 11 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0041] Example 1

[0042] This embodiment provides a method for fabricating a metal capacitor structure. Please refer to [link / reference]. Figure 3 The diagram shows the process flow of this preparation method, which includes the following steps:

[0043] S1: A substrate 101 is provided, and an etch barrier layer 102 and a first electrode plate 103 are sequentially formed on the substrate 101;

[0044] S2: The surface of the first electrode plate 103 is oxidized using a first plasma to form a transition layer 104 on the first electrode plate 103;

[0045] S3: An insulating layer 105 is deposited on the transition layer 104, and the surface of the insulating layer 105 is oxidized using a first plasma to form a first oxide layer 106 on the insulating layer 105.

[0046] S4: A second electrode 107 and a first anti-reflection layer 108 are formed on the first oxide layer 106. The second electrode 107 is partially etched based on the first anti-reflection layer 108 as a mask layer to expose the insulating layer 105, and the first anti-reflection layer 108 is removed.

[0047] S5: The surface of the second electrode plate 107 and the insulating layer 105 are oxidized using a second plasma to form a second oxide layer 109 on the second electrode plate 107 and a third oxide layer 110 on the insulating layer 105.

[0048] S6: A silicon-rich oxide layer 111 and a second anti-reflection layer 112 are sequentially formed on the second oxide layer 109 and the third oxide layer 110, wherein the silicon-rich oxide layer 111 covers the second oxide layer 109 and the third oxide layer 110, and the second anti-reflection layer 112 covers the silicon-rich oxide layer 111.

[0049] S7: Etch the first electrode plate 103 to remove a portion of the first electrode plate 103.

[0050] The preparation method of the metal capacitor structure of this embodiment will be described in detail below with reference to the specific accompanying drawings.

[0051] like Figure 4 As shown, in step S1, a substrate 101 is provided, and an etch barrier layer 102 and a first electrode 103 are sequentially fabricated on the substrate 101. Optionally, the substrate 101 may include a silicon substrate 101, a germanium substrate 101, a silicon-germanium substrate 101, or an insulating substrate 101, such as a silicon-on-insulator (SOI) substrate 101 or a silicon-on-glass (SOG) substrate 101, etc. Before performing subsequent processes, the substrate 101 can be cleaned, for example, by sequentially cleaning with an organic solvent such as acetone and deionized water to remove contaminants from the surface of the substrate 101, followed by drying; or by first removing the natural oxide layer on the surface of the substrate 101 with a diluted acid solution, then cleaning with deionized water, and finally drying; or by performing multiple cleanings using the aforementioned cleaning methods. It should be noted that in this embodiment, as... Figure 4 The diagram shows a cross-sectional view of the substrate 101. In this embodiment, the substrate 101 is a copper-containing structure fabricated using a damascus process. The substrate 101 includes a dielectric layer 1011 and metal vias 1012, wherein the metal vias 1012 are formed in the dielectric layer 1011. Specifically, the dielectric layer 1011 can be a single layer or a stack of one or more dielectric materials. The dielectric material can include silicon oxide, or materials with high dielectric constants, such as silicon nitride (SiN), silicon oxynitride (SiON), hafnium oxide (HfO2), aluminum oxide (Al2O3), titanium oxide (TiO2), or ferroelectric materials. As an example, the dielectric material used to form the dielectric layer 1011 includes any one of silicon nitride (SiN), silicon oxide, or silicon oxynitride. Preferably, the material of the metal vias 1012 includes one or more of titanium, copper, or aluminum.

[0052] Furthermore, an etch barrier layer 102 and a first electrode 103 are sequentially formed on the substrate 101. The etch barrier layer 102 covers the surface of the substrate 101, preventing damage to the substrate 101 during subsequent etching of the first electrode 103. The etch barrier layer 102 can be formed using a chemical vapor deposition process or a thermal oxidation process. The material forming the etch barrier layer 102 includes nitrogen-doped silicon carbide or silicon nitride. The first electrode 103 (e.g., including a tantalum nitride or titanium nitride layer) can also be formed on the etch barrier layer 102 using a sputtering process. Preferably, in this embodiment, the first electrode 103 is made of titanium nitride. Figure 5 As shown, in step S2, the surface of the first electrode plate 103 is oxidized using a first plasma to form a transition layer 104 on the first electrode plate 103.

[0053] As an example, the first plasma is oxygen, and the process temperature for oxidizing the surface of the first electrode plate 103 using the first plasma is set to be 200℃~420℃, and the oxidation time for oxidizing the surface of the first electrode plate 103 using the first plasma is 10~200s.

[0054] Specifically, the substrate 101 is placed in the reaction chamber of a plasma processing apparatus, and a gas mixture of first plasma is introduced. The flow rate of the first plasma can be 1000 sccm to 20000 sccm, and the first plasma can be oxygen (O2). The first plasma is used to oxidize the surface of the first electrode 103 for 10 to 200 seconds to oxidize the titanium nitride layer on the surface of the first electrode 103 to TixOy, thereby forming a transition layer 104 on the first electrode 103. In one embodiment, the first plasma can be used to oxidize the titanium nitride layer on the surface of the first electrode 103, and the corresponding process temperature can be set to 200°C to 420°C. Figure 5 As shown, TixOy serves as the transition layer 104, with a smoother surface, which solves the problem of high surface roughness of the first electrode plate 103. Furthermore, the band gap of TixOy is greater than that of titanium nitride, making the transition layer 104 an effective charge barrier, thereby efficiently suppressing leakage current at the interface and improving the withstand voltage capability of the subsequently formed insulating layer 105.

[0055] like Figure 6 As shown, step S3 is performed, an insulating layer 105 is deposited on the transition layer 104, and the surface of the insulating layer 105 is oxidized using a first plasma to form a first oxide layer 106 on the insulating layer 105.

[0056] As an example, the first plasma is oxygen, and the process temperature for oxidizing the surface of the insulating layer 105 using the first plasma is set to be 200℃~420℃, and the oxidation time for oxidizing the surface of the insulating layer 105 using the first plasma is 10~200s.

[0057] Specifically, the insulating layer 105 can be formed using a chemical vapor deposition process. The material of the insulating layer 105 includes either silicon nitride or silicon oxide. In this embodiment, silicon nitride with a high dielectric constant is preferred. After forming the insulating layer 105, the substrate 101 is placed back into the reaction chamber of a plasma process apparatus, and a gas mixture of the first plasma is introduced. The flow rate of the first plasma can be 1000 sccm to 20000 sccm, and the first plasma can be oxygen (O2). The oxidation treatment of the surface of the first electrode plate 103 using the first plasma is performed for 10 to 200 seconds to oxidize the silicon nitride layer on the surface of the insulating layer 105 to SixOyNz, thereby forming a first oxide layer 106 on the insulating layer 105. In one embodiment, while the first plasma is used to oxidize the silicon nitride layer on the surface of the insulating layer 105, the corresponding process temperature can be set to 200°C to 420°C. Figure 6 As shown, SixOyNz, as the first oxide layer 106, has better uniformity than pure silicon nitride, which greatly reduces interface defects or uneven areas on the surface of the insulating layer 105. This can avoid abnormal charge accumulation, reduce local electric field concentration, and make the voltage distribution more balanced when the device is working, thus fundamentally delaying the occurrence of breakdown.

[0058] like Figure 7 and Figure 8 As shown, in step S4, a second electrode 107 and a first anti-reflection layer 108 are formed on the first oxide layer 106. The second electrode 107 is partially etched based on the first anti-reflection layer 108 as a mask layer to expose the insulating layer 105, and the first anti-reflection layer 108 is removed.

[0059] Specifically, the second electrode 107 can be formed by physical vapor deposition. The material used to form the second electrode 107 includes tantalum nitride or titanium nitride layers, etc. Preferably, in this embodiment, the material of the second electrode 107 is the same as that of the first electrode 103, which is titanium nitride.

[0060] Specifically, such as Figure 7As shown, after the second electrode plate 107 is formed, a first anti-reflection layer 108 needs to be formed on the surface of the second electrode plate 107. For example, the first anti-reflection layer 108 is formed on the surface of the second electrode plate 107 by an epitaxial process or a deposition process. The first anti-reflection layer 108 can effectively reduce light reflection and reduce or even eliminate the standing wave effect.

[0061] Specifically, such as Figure 8 As shown, photoresist is coated on top of the first anti-reflective layer 108. A patterning process is then performed on the second electrode plate 107 using the first anti-reflective layer 108 as a mask. The patterning process includes, but is not limited to, exposure, development, and etching steps. After the patterning process, part of the second electrode plate 107 is etched away to expose the insulating layer 105. Furthermore, because the first anti-reflective layer 108 is formed on the surface of the second electrode plate 107, the standing wave effect during exposure can be effectively prevented during the patterning process, resulting in a more uniform sidewall morphology of the etched portion of the second electrode plate 107. Furthermore, after the second electrode 107 is partially etched, the photoresist coated on the top of the first antireflective layer 108 needs to be removed through ashing, acid washing, and drying processes. During this process, the first antireflective layer 108 is easily damaged, causing its physical or optical properties to deteriorate. Therefore, after the photoresist is removed, the first antireflective layer 108 also needs to be removed through processes such as plasma dry etching. In other embodiments, the first antireflective layer 108 can also be removed by wet etching processes according to the different etching ratios of the first antireflective layer 108 and the second electrode 107 in the chemical solution.

[0062] like Figure 9 As shown, in step S5, the surface of the second electrode plate 107 and the insulating layer 105 are oxidized using a second plasma to form a second oxide layer 109 on the second electrode plate 107 and a third oxide layer 110 on the insulating layer 105.

[0063] As an example, the second plasma is nitrous oxide gas. The process temperature for oxidizing the surface of the second electrode plate 107 and the insulating layer 105 using the second plasma is set to 300°C to 420°C, and the oxidation time for oxidizing the surface of the second electrode plate 107 and the insulating layer 105 using the second plasma is 10 to 200 seconds.

[0064] Specifically, the substrate 101 is placed back into the reaction chamber of the plasma-enhanced chemical vapor deposition (PECVD) apparatus, and a gas mixture of the second plasma is introduced. The flow rate of the second plasma can be 1000 sccm to 20000 sccm, and the second plasma can be nitrous oxide (N2O). The oxidation treatment of the surfaces of the second electrode 107 and the insulating layer 105 using the second plasma is performed for 10 to 200 seconds, thereby oxidizing the titanium nitride layer on the surface of the second electrode 107 to TixOy, thereby forming a second oxide layer 109 on the second electrode 107, and oxidizing the silicon nitride layer on the surface of the insulating layer 105 to SixOyNz, thereby forming a third oxide layer 110 on the insulating layer 105. The second oxide layer 109 has a smoother surface, which solves the problem of high surface roughness of the second electrode plate 107. The band gap of TixOy is larger than that of titanium nitride, making the second oxide layer 109 an effective charge barrier, thereby effectively suppressing leakage current at the interface and improving the withstand voltage of the metal capacitor structure. SixOyNz, as the third oxide layer 110, has better surface uniformity than the insulating layer 105 formed by pure silicon nitride, which greatly reduces interface defects or non-uniformity on the surface of the insulating layer 105. This can avoid abnormal charge accumulation, reduce local electric field concentration, and fundamentally delay the possibility of metal capacitor breakdown.

[0065] like Figure 10 As shown, in step S6, a silicon-rich oxide layer 111 and a second anti-reflection layer 112 are sequentially formed on the second oxide layer 109 and the third oxide layer 110, wherein the silicon-rich oxide layer 111 covers the second oxide layer 109 and the third oxide layer 110, and the second anti-reflection layer 112 covers the silicon-rich oxide layer 111.

[0066] Specifically, the process of depositing silicon-rich oxide layers 111 on the second oxide layer 109 and the third oxide layer 110 may include using atomic layer deposition (ALD), molecular beam epitaxy (MBE), or chemical vapor deposition (CVD). In some embodiments, the thickness of the silicon-rich oxide layer 111 is 100~300 Å. As a type of oxide layer, the silicon-rich silicon oxide layer (SRO) has good adhesion, which allows the second oxide layer 109 and the third oxide layer 110 to adhere stably together with the subsequently formed second antireflective layer 112, thereby improving the stability between the material layers. In addition, the material in the silicon-rich oxide layer 111 refers to non-stoichiometric silicon oxide (SiOx) material, whose silicon-to-oxygen ratio is greater than the stoichiometric silicon-to-oxygen ratio of about 1:2. The excess active Si atoms can capture the plasma charge in the plasma process, so that the silicon-rich oxide layer 111 can act as a charge neutralization layer, actively consuming and blocking the accumulation of charge generated in the plasma process on the insulating layer 105 and the migration and accumulation into the insulating layer 105, further enhancing the overall breakdown resistance of the metal capacitor structure.

[0067] Specifically, a second anti-reflective layer 112 is deposited on the silicon-rich oxide layer 111 using the same materials and growth method as when the first anti-reflective layer 108 was formed, such that the second anti-reflective layer 112 has the same properties as the first anti-reflective layer 108 before photolithography.

[0068] like Figure 11 As shown, step S7 is performed to etch the first electrode plate 103 to remove a portion of the first electrode plate 103.

[0069] Specifically, such as Figure 11 As shown, the first electrode plate 103 is etched using the second anti-reflection layer 112 as a mask layer. The etching barrier layer 102 serves as the endpoint of the etching process, and all material layers above the etching barrier layer 102 are etched away. Since the second anti-reflection layer 112 is formed on the surface of the second electrode plate 107, the standing wave effect can be effectively prevented during the etching process. This also makes the sidewall morphology of the first electrode plate 103 and the etched portions of each material layer more uniform. Furthermore, the width of the first electrode plate 103 after etching is greater than the width of the second electrode plate 107 after partial etching, ultimately forming a metal capacitor structure.

[0070] In other embodiments, the present invention also provides a metal capacitor structure, wherein the metal capacitor structure can be directly prepared using the above-described method for preparing metal capacitor structures. Therefore, the specific materials and parameters of the metal capacitor structure can be found in the above description and will not be repeated here. Of course, the metal capacitor structure can also be prepared using other preparation processes as needed.

[0071] In summary, this invention provides a metal capacitor structure and its fabrication method. A TixOy transition layer is grown in situ at the interface between the first electrode and the insulating layer using plasma technology. This transition layer successfully solves the problem of high interface roughness in traditional processes. Furthermore, the band gap of TixOy is larger than that of titanium nitride, making the transition layer an effective charge barrier that significantly hinders carrier migration across the interface. This effectively suppresses leakage current at the interface and improves the withstand voltage of the insulating layer. This invention applies plasma technology to the oxidation treatment of the insulating layer surface to form a first oxide layer, thus reducing interface defects on the insulating layer surface. The significant reduction in pinholes or uneven areas prevents abnormal charge accumulation, resulting in a more balanced voltage distribution during operation. This significantly reduces the concentration of localized strong electric fields that could lead to early breakdown, fundamentally delaying its occurrence. Excess active Si atoms in the silicon-rich oxide layer can capture plasma charges generated during the plasma process, acting as a charge neutralization layer. This actively consumes and prevents the accumulation of charges generated during the plasma process on the insulating layer and their migration and accumulation into the insulating layer, further enhancing the overall breakdown resistance. Breakdown voltage tests on the metal capacitor structure show a breakdown voltage of 27 V. A high breakdown voltage is one of the most crucial indicators for evaluating the stable operation of capacitors under high-voltage environments. Its substantial improvement means a significantly enhanced ability to withstand abnormal voltage stress under complex conditions (such as high temperature, high humidity, and high bias) without failure. This not only greatly reduces the risk of accidental failure due to voltage overload during application but also provides a solid foundation for ensuring long-term, stable, and reliable operation of the device, significantly extending its service life. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0072] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a metal capacitor structure, characterized in that, The preparation method includes: A substrate is provided, and an etch barrier layer and a first electrode are sequentially fabricated on the substrate; The surface of the first electrode plate is oxidized using a first plasma to form a transition layer on the first electrode plate; An insulating layer is deposited on the transition layer, and the surface of the insulating layer is oxidized using a first plasma to form a first oxide layer on the insulating layer; A second electrode plate and a first anti-reflection layer are formed on the first oxide layer. The second electrode plate is partially etched based on the first anti-reflection layer as a mask layer to expose the insulating layer, and the first anti-reflection layer is removed. The surface of the second electrode plate and the insulating layer are oxidized using a second plasma to form a second oxide layer on the second electrode plate and a third oxide layer on the insulating layer. A silicon-rich oxide layer and a second anti-reflection layer are sequentially formed on the second oxide layer and the third oxide layer, wherein the silicon-rich oxide layer covers the second oxide layer and the third oxide layer, and the second anti-reflection layer covers the silicon-rich oxide layer; The first electrode plate is etched to remove a portion of it.

2. The method for preparing the metal capacitor structure according to claim 1, characterized in that: The first plasma is oxygen, and the second plasma is nitrous oxide gas.

3. The method for preparing the metal capacitor structure according to claim 1, characterized in that: The process temperature set for oxidizing the surface of the first electrode plate using the first plasma is 200℃~420℃, and the process temperature set for oxidizing the surface of the insulating layer using the first plasma is 200℃~420℃.

4. The method for preparing the metal capacitor structure according to claim 1, characterized in that: The oxidation treatment time of the first electrode plate surface using the first plasma is 10~200s, and the oxidation treatment time of the insulating layer surface using the first plasma is 10~200s.

5. The method for preparing the metal capacitor structure according to claim 1, characterized in that: The process temperature for oxidizing the surface of the second electrode plate and the insulating layer using the second plasma is set to 300℃~420℃, and the oxidation time for oxidizing the surface of the second electrode plate and the insulating layer using the second plasma is 10~200s.

6. The method for preparing the metal capacitor structure according to claim 1, characterized in that, The width of the second electrode plate after partial etching is smaller than the width of the first electrode plate after etching.

7. The method for preparing the metal capacitor structure according to claim 1, characterized in that, The thickness of the silicon-rich oxide layer is 100~300 Å.

8. The method for preparing the metal capacitor structure according to any one of claims 1 to 7, characterized in that, The first electrode and the second electrode are made of titanium nitride.

9. The method for preparing the metal capacitor structure according to any one of claims 1 to 7, characterized in that, The insulating layer is made of silicon nitride.

10. A metal capacitor structure, characterized in that, The metal capacitor structure is manufactured using the method for preparing a metal capacitor structure as described in any one of claims 1 to 9.

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