Power semiconductor device

Abstract

The invention discloses a power semiconductor device, which comprises a semiconductor substrate, a first buffer layer, a post-processing layer, a second buffer layer and a third buffer layer, the device comprises a barrier layer, a passivation layer, a first anode contact hole, a first anode, a dielectric layer, a second anode contact hole, a second anode, a cathode contact hole, a cathode, a protection layer, an anode opening, anode conduction metal, a cathode opening, cathode conduction metal and a field plate layer. According to the invention, the problem that leakage current exists between the buffer layer and the semiconductor substrate interface when one buffer layer is provided is solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power semiconductor device. Background Art

[0002] Semiconductor devices are fabricated using metal-contact semiconductor layers. Compared to traditional semiconductor diodes, they feature extremely short reverse recovery times. Consequently, they are widely used in circuits such as switching power supplies, inverters, and drives. Gallium nitride (GaN) is a third-generation wide-bandgap semiconductor material. Its large bandgap, high electron saturation velocity, high breakdown electric field, high thermal conductivity, corrosion resistance, and radiation resistance make it an ideal material for short-wavelength optoelectronic devices and high-voltage, high-frequency, and high-power devices. In summary, semiconductor devices fabricated using GaN combine the advantages of the aforementioned semiconductor devices and GaN materials, offering fast switching speeds, high field strengths, and excellent thermal performance. They hold great promise for development in the power rectifier market.

[0003] However, the lattice mismatch between the substrate and barrier layer in conventional semiconductor device structures leads to numerous defects in the barrier layer, which in turn affects the performance and lifespan of the semiconductor device. Existing technologies often form a buffer layer between the semiconductor substrate and the barrier layer to partially offset the effects of the lattice mismatch. However, a single buffer layer has limited effectiveness and cannot completely offset the effects of the lattice mismatch. Furthermore, leakage current can occur at the interface between the buffer layer and the semiconductor substrate, which in turn fails to fully improve the performance and lifespan of the semiconductor device. Summary of the Invention

[0004] The purpose of the present invention is to provide a power semiconductor device, which solves the problem of leakage current between the buffer layer and the semiconductor substrate interface when the buffer layer is a single layer by growing multiple buffer layers and post-processing layers through PVD.

[0005] To solve the above technical problems, the present invention is achieved through the following technical solutions:

[0006] The present invention provides a power semiconductor device, comprising:

[0007] semiconductor substrates;

[0008] a first buffer layer, disposed on the semiconductor substrate;

[0009] a post-treatment layer, which is arranged on a side of the first buffer layer away from the semiconductor substrate, and the post-treatment layer is an aluminum oxide layer;

[0010] a second buffer layer, which is disposed on a side of the post-treatment layer away from the first buffer layer, and the second buffer layer is a gallium nitride layer or an aluminum gallium nitride layer;

[0011] a third buffer layer, disposed on the second buffer layer, and the third buffer layer is a gallium nitride layer;

[0012] a barrier layer, disposed on the third buffer layer;

[0013] a passivation layer, disposed on a side of the barrier layer away from the second buffer layer;

[0014] a first anode contact hole, which penetrates the passivation layer and extends into the barrier layer;

[0015] a first anode disposed in the first anode contact hole;

[0016] a dielectric layer, disposed on a side of the passivation layer away from the barrier layer and between the first anode and the barrier layer;

[0017] a second anode contact hole, which penetrates the dielectric layer and the passivation layer and extends into the barrier layer;

[0018] a second anode disposed in the second anode contact hole;

[0019] a cathode contact hole, which penetrates the dielectric layer and the passivation layer;

[0020] a cathode, which is disposed on the dielectric layer and in the cathode contact hole;

[0021] a protective layer, disposed on the first anode, the second anode, the cathode, and the dielectric layer;

[0022] an anode opening penetrating through the protective layer to expose the first anode and the second anode;

[0023] an anode conductive metal, disposed on a side of the protective layer away from the dielectric layer, and connected to the first anode and the second anode;

[0024] a cathode opening penetrating through the protective layer to expose the cathode;

[0025] a cathode conductive metal disposed on a side of the protective layer away from the dielectric layer, and connected to the cathode;

[0026] A field plate layer is provided on the protection layer, wherein the field plate layer is connected to the anode conductive metal, wherein the anode conductive metal, the cathode conductive metal and the field plate layer are formed simultaneously.

[0027] In one embodiment of the present invention, the first anode and the second anode include a first metal layer and a second metal layer, wherein the first metal layer is arranged on a side of the dielectric layer away from the passivation layer, and extends into the first anode contact hole and the second anode contact hole to cover the dielectric layer at the bottom of the first anode contact hole and the bottom of the second anode contact hole, and the second metal layer is arranged on the first metal layer and fills the first anode contact hole and the second anode contact hole.

[0028] In one embodiment of the present invention, the first anode and the second anode are composed of a first number of stacked metal layers, and the cathode is composed of a second number of stacked metal layers, and the first number is greater than the second number.

[0029] In one embodiment of the present invention, the first buffer layer is an aluminum nitride layer.

[0030] In one embodiment of the present invention, the thickness of the first buffer layer is 10-300 nm.

[0031] In one embodiment of the present invention, the post-treatment layer is an aluminum oxide layer.

[0032] In one embodiment of the present invention, the thickness of the post-treatment layer is 0.5-2 nm.

[0033] The present invention grows a first buffer layer and a post-treatment layer by PVD to obtain a first buffer layer of good quality, which facilitates the subsequent preparation and application of gallium nitride-based semiconductor devices. When the buffer layer is a multi-layer structure, the lattice constants of different layers gradually change. The lattice constant near the surface of the semiconductor substrate is closest to the lattice constant of the semiconductor substrate, and the lattice constant of the top layer is closest to the lattice constant of the barrier layer formed subsequently. This can reduce the lattice defects in the buffer layer caused by the lattice constant of the semiconductor substrate, reduce the interface state at the interface between the buffer layer and the semiconductor substrate, and reduce the interface leakage current at the interface. The present invention increases the anode area by providing a dielectric layer, greatly reducing reverse leakage, and this dielectric layer can be formed simultaneously with the gate dielectric layer of the GaN HEMT (High Electron Mobility Transistor), which is compatible with the CMOS process line. In addition, the present invention expands the depletion region of the semiconductor device by adding an anode conductive metal, a cathode conductive metal and a field plate layer structure, thereby improving the withstand voltage performance of the semiconductor device.

[0034] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1-1 This is a schematic structural diagram of a gallium nitride epitaxial layer of the present invention;

[0037] Figure 1-2 for Figure 1-1 Flow chart of the method for preparing the gallium nitride epitaxial layer;

[0038] Figure 2-1 Schematic diagram of the structure of another gallium nitride epitaxial layer of the present invention;

[0039] Figure 2-2 for Figure 2-1 Flow chart of the method for preparing the gallium nitride epitaxial layer;

[0040] Figure 3-1 Schematic diagram of the structure of another gallium nitride epitaxial layer of the present invention;

[0041] Figure 3-2 for Figure 3-1 Flow chart of the method for preparing the gallium nitride epitaxial layer;

[0042] Figure 4-1 Schematic diagram of the structure of another gallium nitride epitaxial layer of the present invention;

[0043] Figure 4-2 for Figure 4-1 Flow chart of the method for preparing the gallium nitride epitaxial layer;

[0044] Figure 5-1 To adopt Figure 1-1 A schematic structural diagram of a semiconductor device obtained by growing a gallium nitride epitaxial layer;

[0045] Figure 5-2 for Figure 5-1 Flow chart of the method for preparing a semiconductor device;

[0046] Figure 6-1 To adopt Figure 1-1 A schematic structural diagram of another semiconductor device obtained by forming a gallium nitride epitaxial layer;

[0047] Figure 6-2 for Figure 6-1 Flow chart of the method for preparing a semiconductor device;

[0048] Figure 7-1 To adopt Figure 2-1 A schematic structural diagram of a semiconductor device obtained by growing a gallium nitride epitaxial layer;

[0049] Figure 7-2 for Figure 7-1 Flow chart of the method for preparing a semiconductor device;

[0050] Figure 8-1 To adopt Figure 2-1 A schematic structural diagram of another semiconductor device obtained by forming a gallium nitride epitaxial layer;

[0051] Figure 8-2 for Figure 8-1 Flow chart of the method for preparing a semiconductor device;

[0052] Figure 9-1 To adopt Figure 3-1 A schematic structural diagram of a semiconductor device obtained by growing a gallium nitride epitaxial layer;

[0053] Figure 9-2 for Figure 9-1 Flow chart of the method for preparing a semiconductor device;

[0054] Figure 10-1 To adopt Figure 3-1 A schematic structural diagram of another semiconductor device obtained by forming a gallium nitride epitaxial layer;

[0055] Figure 10-2 for Figure 10-1 Flow chart of the method for preparing a semiconductor device;

[0056] Figure 11-1 To adopt Figure 4-1 A schematic structural diagram of a semiconductor device obtained by growing a gallium nitride epitaxial layer;

[0057] Figure 11-2 for Figure 11-1 Flowchart of the method for preparing a semiconductor device. DETAILED DESCRIPTION

[0058] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0059] Gallium nitride materials have low heat generation rate and high breakdown electric field, and are important materials for the development of high-temperature, high-power electronic devices and high-frequency microwave devices. Gallium nitride materials can be used to prepare new devices such as metal field effect transistors (MESFETs), heterojunction field effect transistors (HFETs), and modulation doped field effect transistors (MODFETs). The modulation doped AlGaN / GaN structure has high electron mobility (2000cm2 / v·s), high saturation velocity (1×107cm / s), and low dielectric constant make it a preferred material for making microwave devices. GaN has a wide band gap (3.4eV) and is used as a substrate made of materials such as sapphire and silicon carbide, which has good heat dissipation performance and is conducive to the operation of devices under high-power conditions.

[0060] The gallium nitride epitaxial layer and semiconductor device provided by the present invention can be applied to power semiconductor devices and radio frequency semiconductor devices.

[0061] See also Figure 1-1 As shown, the present invention provides a gallium nitride epitaxial layer, comprising: a semiconductor substrate 1100, a buffer layer 1101, and a barrier layer 1102. The buffer layer 1101 is disposed on the semiconductor substrate 1100, and the barrier layer 1102 is disposed on a side of the buffer layer 1101 away from the semiconductor substrate 1100. The material of the semiconductor substrate 1100 is, for example, one of sapphire, silicon carbide, silicon, zinc oxide, lithium aluminate, aluminum nitride, or gallium nitride, and the material of the buffer layer 1101 can be one or more of aluminum oxide, hafnium oxide, titanium oxide, titanium nitride, aluminum nitride, aluminum gallium nitride, or gallium nitride. When the buffer layer 1101 has a multi-layer structure, the lattice constants of different layers gradually change. The lattice constant near the surface of the semiconductor substrate 1100 is closest to that of the semiconductor substrate 1100, while the lattice constant of the top layer is closest to that of the subsequently formed barrier layer 1102. This reduces lattice defects in the buffer layer caused by the lattice constant of the semiconductor substrate 1100, reduces interface states at the interface between the buffer layer and the semiconductor substrate 1100, and reduces interface leakage current at the interface. The barrier layer 1102 can be made of, for example, aluminum gallium nitride or gallium nitride.

[0062] Please also refer to Figure 1-2 As shown, the method for preparing the gallium nitride epitaxial layer of this embodiment includes at least the following steps:

[0063] In step S1100 , a buffer layer 1101 is grown on a semiconductor substrate 1100 by using an epitaxial growth process. In step S1101 , a barrier layer 1102 is then grown on the buffer layer 1101 by using an epitaxial growth process.

[0064] See also Figure 2-1 As shown, in other embodiments of the present invention, a gallium nitride epitaxial layer may further include: a semiconductor substrate 1200 , a first buffer layer 1201 , a second buffer layer 1202 , a third buffer layer 1203 and a barrier layer 1204 .

[0065] The first buffer layer 1201 is disposed on a semiconductor substrate 1200. The second buffer layer 1202 is disposed on a side of the first buffer layer 1201 away from the semiconductor substrate 1200, and the third buffer layer 1203 is disposed on a side of the second buffer layer 1202 away from the first buffer layer 1201. The barrier layer 1204 is disposed on a side of the third buffer layer 1203 away from the second buffer layer 1202. Based on the above embodiment, in this embodiment, the first buffer layer 1201 can be, for example, an aluminum nitride layer, with a thickness of, for example, 10 nm to 300 nm. The second buffer layer 1202 can be, for example, a gallium nitride or aluminum gallium nitride layer. The third buffer layer 1203 can be, for example, a gallium nitride layer. The materials used for the first buffer layer 1201, the second buffer layer 1202, and the third buffer layer 1203 can be adaptively selected based on the materials of the semiconductor substrate and the barrier layers.

[0066] Please also refer to Figure 2-2 As shown, the method for preparing the gallium nitride epitaxial layer of this embodiment includes at least the following steps:

[0067] In step S1200, a first buffer layer 1201, such as an aluminum nitride buffer layer, is grown on a semiconductor substrate 1200, such as a silicon substrate or a silicon carbide substrate, using an epitaxial growth process. In step S1201, a second buffer layer 1202, such as a gallium nitride buffer layer, is grown on the first buffer layer 1201 using an epitaxial growth process. In step S1202, a third buffer layer 1203, such as an aluminum gallium nitride buffer layer, is grown on the second buffer layer 1202 using an epitaxial growth process. In step S1203, an aluminum gallium nitride barrier layer 1204 is grown on the third buffer layer 1203 using an epitaxial growth process.

[0068] See also Figure 3-1 As shown, in other embodiments of the present invention, a gallium nitride epitaxial layer may further include: a semiconductor substrate 1300 , a first buffer layer 1301 , a post-treatment layer 1302 , a second buffer layer 1303 , and a barrier layer 1304 .

[0069] The first buffer layer 1301 is disposed on a semiconductor substrate 1300, the post-treatment layer 1302 is disposed on a side of the first buffer layer 1301 away from the semiconductor substrate 1300, the second buffer layer 1303 is disposed on a side of the post-treatment layer 1302 away from the first buffer layer 1301, and the barrier layer 1304 is disposed on a side of the second buffer layer 1303 away from the post-treatment layer 1302. The material of the semiconductor substrate 1300 is, for example, sapphire, silicon carbide, silicon, zinc oxide, lithium aluminate, aluminum nitride, or gallium nitride. The first buffer layer 1301 can be, for example, an aluminum nitride layer, and the thickness of the first buffer layer 1301 is, for example, 10 nm to 300 nm. The post-treatment layer 1302 can be, for example, a thin layer of aluminum oxide (Al2O3), and the thickness of the post-treatment layer 1302 is 0.5 nm to 2 nm. The second buffer layer 1303 can be, for example, a gallium nitride layer or an aluminum gallium nitride layer. The barrier layer 1304 is made of, for example, a gallium nitride layer or an aluminum gallium nitride layer. The present invention grows the first buffer layer 1301 and the post-treatment layer 1302 by PVD to obtain a first buffer layer 1301 of good quality, facilitating the subsequent preparation and application of gallium nitride-based semiconductor devices.

[0070] Please also refer to Figure 3-2 As shown, a method for preparing a gallium nitride epitaxial wafer according to this embodiment includes the following steps:

[0071] In step S1301, the material of the semiconductor substrate 1300 is, for example, one of sapphire, silicon carbide, silicon, zinc oxide, lithium aluminate, aluminum nitride or gallium nitride. The oxide layer on the surface of the semiconductor substrate 1300 is removed by treating with a hydrofluoric acid solution, and then a first buffer layer 1301, such as a single-layer aluminum nitride buffer layer, is deposited by a PVD process, with a thickness range of, for example, 10-50 nm. Specifically, an epitaxial-grade semiconductor substrate 1300 (for example, a Si substrate is used here) is placed on a tray made of SiC material, the tray is placed in a PVD sputtering machine, and transferred to the deposition chamber of the machine. After the semiconductor substrate 1300 is placed in, the deposition chamber is evacuated, and the semiconductor substrate 1300 is heated and heated at the same time. The background vacuum is evacuated to, for example, below 10 -5 -10 -7When the temperature reaches 400°C to 600°C, the semiconductor substrate 1300 is baked for a time of 1 to 10 minutes. After the semiconductor substrate 1300 is baked, Ar, N2, and O2 are introduced, with the Ar:N2 flow ratio being, for example, 10:2 to 1:1, and the O2 flow being, for example, 0-5% of the sum of the Ar and N2 flows. The total gas flow rate is preferably such that the PVD deposition chamber pressure is maintained at 2 to 8 mTorr. Simultaneously, the heating temperature of the semiconductor substrate 1300 is set to the deposition temperature, preferably within the deposition temperature range of 400 to 600°C. After the reaction gases are introduced and the deposition temperature is allowed to stabilize for 10 to 60 seconds, the sputtering power supply is turned on to sputter the Al target, thereby depositing an O-doped AlN crystalline thin film on the semiconductor substrate 1300. The sputtering power can be set, for example, to 10 kW to 10 kW depending on the required deposition rate, and the sputtering time can be set, for example, to 10 to 1000 seconds depending on the thickness.

[0072] In step S1302, further, an ALD process is used to prepare a post-treatment layer 1302, such as an Al2O3 layer. The ALD chamber is evacuated to, for example, 0.05MPa-0.5MPa, the temperature is raised to, for example, 100°C, the precursors are trimethylaluminum and high-purity water, the deposition thickness is, for example, 0.5-2nm, and the deposition time is, for example, 3-25min.

[0073] In step S1303, further, a second buffer layer 1303, such as a gallium nitride buffer layer, is prepared on the post-treatment layer 1302. The preparation of the gallium nitride buffer layer can be achieved by a two-step method. In the first step, the temperature is controlled to, for example, 450°C to 600°C and the pressure is, for example, 200-500 torr to grow a gallium nitride nucleation layer, and then the temperature is increased to 950°C to 1200°C to grow gallium nitride three-dimensional and two-dimensional coating layers. The nucleation layer and subsequent three-dimensional and two-dimensional gallium nitride are collectively referred to as a gallium nitride buffer layer.

[0074] In step S1304, the last step is to grow a barrier layer 1304, such as a gallium nitride barrier layer 1304. The temperature can be controlled to be, for example, 950°C to 1100°C, and the pressure can be controlled to be, for example, 70 torr to 200 torr. The gallium nitride barrier layer 1304 is grown on the gallium nitride buffer layer. The gallium nitride barrier layer 1304 has a thickness of, for example, 50-500 nm.

[0075] After the epitaxy is completed, the gallium nitride epitaxial layer is obtained by cooling the film.

[0076] Temperature and pressure control refers to controlling the temperature and pressure in the reaction chamber where the epitaxial wafers are grown, specifically the reaction chamber of the metal organic chemical vapor deposition (MOCVD) equipment. This is achieved using trimethylgallium or triethylgallium as the gallium source, high-purity ammonia as the nitrogen source, trimethylindium as the indium source, trimethylaluminum as the aluminum source, silane as the silicon source, tetramethylgermanium as the germanium source, and bismuthocene magnesium as the magnesium source.

[0077] See also Figure 4-1 As shown, in other embodiments of the present invention, a gallium nitride epitaxial layer may further include: a semiconductor substrate 1400 , a first buffer layer 1401 , a nano buffer layer 1402 , a second buffer layer 1403 , and a barrier layer 1404 .

[0078] The first buffer layer 1401 is disposed on the semiconductor substrate 1400. The first buffer layer 1401 can be, for example, an aluminum nitride layer, and the thickness of the first buffer layer 1401 can be, for example, 10 nm to 300 nm. The nanobuffer layer 1402 is disposed on the side of the first buffer layer 1401 away from the semiconductor substrate 1400. The second buffer layer 1403 is disposed on the side of the nanobuffer layer 1402 away from the first buffer layer 1401. The second buffer layer 1403 can be, for example, a gallium nitride or aluminum gallium nitride layer. The barrier layer 1400 is disposed on the side of the second buffer layer 1403 away from the nanobuffer layer 1402. The nanobuffer layer 1402 can be, for example, gallium nitride nanocrystals or aluminum gallium nitride nanocrystals.

[0079] Please also refer to Figure 4-2 As shown, this embodiment also provides a method for preparing a gallium nitride-based epitaxial wafer, comprising the following steps: in step S1401, growing a first buffer layer 1401 on a semiconductor substrate; in step S1402, forming a nanobuffer layer 1402, such as a gallium nitride nanobuffer layer 1402, on the first buffer layer using a molecular beam epitaxy process. In an ultra-high vacuum system, the substrate and several molecular beam source furnaces are placed, and various elements constituting the compound, such as Ga, N, and dopant substances, are placed in different injection furnaces for heating and cracking and ionization in different source furnaces. The molecules or atoms are ejected onto the heated substrate surface at a certain thermal motion speed and a certain proportional intensity beam. These molecules or atoms interact with the surface, and a single crystal thin film grows. The growth rate of the single crystal thin film is, for example, 0.01-1 μm / h, and the growth temperature is, for example, 500-600°C. In step S1403, a second buffer layer 1403, such as a gallium nitride buffer layer, is further formed on the nanobuffer layer 1402 using a PVD process. The gallium nitride buffer layer can also be formed using the two-step method described in the above embodiment. In step S1404, a barrier layer 1404 is grown on the second buffer layer 1402. After the epitaxial growth is completed, the gallium nitride epitaxial wafer layer is obtained by cooling the substrate.

[0080] See also Figure 5-1 As shown, the present invention also provides a semiconductor device based on a gallium nitride epitaxial layer, for example, including: a semiconductor substrate 1100, a buffer layer 1101, a barrier layer 1102, a passivation layer 103, an anode 104, a cathode 107, a protective layer 108, a field plate layer 109, an anode conductive metal 110 and a cathode conductive metal 111.

[0081] See also Figure 5-1 As shown, a buffer layer 1101 is disposed on a semiconductor substrate 1100, a barrier layer 1102 is disposed on a side of the buffer layer 1101 away from the semiconductor substrate 1100, and a passivation layer 103 is disposed on a side of the barrier layer 1102 away from the buffer layer 1101. An anode 104 penetrates the passivation layer 1103 and extends into the barrier layer 1102, and a cathode 107 penetrates the passivation layer 1103 and connects to the barrier layer 1102. A protective layer 108 is disposed on the anode 104 and the cathode 107. A field plate layer 109 is disposed on the protective layer 108 and is located between the anode 104 and the cathode 107. An anode conduction metal 110 is disposed on the field plate layer 109 and is in communication with the anode 104, and a cathode conduction metal 111 is disposed on the field plate layer 109 and is in communication with the cathode 107. The anode 104 and cathode 107 may comprise a multi-layer metal structure, including but not limited to a titanium metal layer, an aluminum metal layer, a titanium metal layer, and a titanium nitride metal layer. The protective layer 108 may be, for example, a PETEOS oxide layer. The anode conductive metal 110 and cathode conductive metal 111 may be formed simultaneously with the field plate layer 109 and may be composed of, for example, aluminum silicon copper (AlSiCu).

[0082] In this embodiment, the provision of buffer layer 1101 reduces lattice defects in barrier layer 1102 caused by the lattice constant of semiconductor substrate 1100, thereby reducing interface states at the interface between barrier layer 1102 and semiconductor substrate 1100 and reducing interface leakage current at the interface. The structure of anode conductive metal 110, cathode conductive metal 111, and field plate layer 109 balances the electric field distribution, reduces the electric field strength of the main Schottky junction, and thus improves the withstand voltage of the semiconductor device.

[0083] Please also refer to Figure 5-2 As shown, the present invention also provides a method for preparing a semiconductor device, and the specific steps are as follows:

[0084] In step S101 , an epitaxial growth process is used to grow, for example, an aluminum gallium nitride barrier layer 1102 on, for example, a silicon substrate or a silicon carbide substrate.

[0085] In step S102 , a passivation layer 103 , such as silicon nitride, is deposited on the aluminum gallium nitride barrier layer 1102 using, but not limited to, a chemical vapor deposition process.

[0086] In step S103, the silicon nitride passivation layer 103 and the aluminum gallium nitride barrier layer 1102 are patterned to form an anode 104 and a cathode 107. The anode 104 and the cathode 107 penetrate the silicon nitride passivation layer 103 and extend into the aluminum gallium nitride barrier layer 1102. More specifically, the steps of patterning the silicon nitride passivation layer 103 and the aluminum gallium nitride barrier layer 1102 to obtain the anode 104 include, for example, coating the silicon nitride passivation layer 103 with photoresist, exposing and developing the photoresist to obtain a patterned photoresist layer, then etching the silicon nitride passivation layer 103 and the aluminum gallium nitride barrier layer 1102 using the patterned photoresist layer as a mask to define the anode region AZ and the cathode region, and then depositing and patterning a first metal to obtain a first metal layer within the anode region AZ. More specifically, the specific steps for obtaining the first metal layer located in the anode area AZ may be: using but not limited to a magnetron sputtering coating process to deposit metal to form the first metal layer, the material of the first metal layer may be one of titanium nitride and titanium, applying photoresist on the first metal layer, and then exposing and developing the photoresist to obtain a patterned photoresist layer, and then etching the first metal layer using the patterned photoresist layer as a mask to remove the first metal layer outside the anode area AZ shown in the figure, so as to obtain the first metal layer located in the anode area AZ.

[0087] In step S104, a second metal is deposited and patterned on the first metal layer in the anode area AZ and in the cathode area to obtain a second metal layer and a cathode 107. More specifically, the specific steps for obtaining the anode 104 and the cathode 107 may be: a titanium metal layer, a metal aluminum layer, a metal titanium layer and a metal titanium nitride layer are sequentially deposited on the passivation layer 103, the first metal layer in the anode area AZ and the cathode area using, but not limited to, an electron beam evaporation metal process to form a second metal layer, that is, the second metal layer is a stacked multi-layer metal structure, including but not limited to a titanium metal layer, a metal aluminum layer, a metal titanium layer and a metal titanium nitride layer; and then the second metal layer is subjected to a photolithography and etching process to form the second metal layer of the anode 104 and the cathode 107. More specifically, the anode 104 includes the first metal layer and the second metal layer located in the anode area AZ.

[0088] In step S105, a protective layer 108 is formed on the passivation layer 103, the anode 104, and the cathode 107. More specifically, the protective layer 108 is, for example, a PETEOS (Plasma Enhanced Tetraethylorthosilicate) oxide layer. The specific steps for forming the protective layer 108, for example, the PETEOS oxide layer, may be as follows: a silicon dioxide film, i.e., the protective layer 108, is formed on the passivation layer 103, the anode 104, and the cathode 107 using ethyl orthosilicate as a raw material by microwave plasma chemical vapor deposition. A photoresist is then applied to the protective layer 108, and the photoresist is then exposed and developed to obtain a patterned photoresist layer. The protective layer 108 is then etched using the patterned photoresist layer as a mask until the anode 104 and the cathode 107 are exposed, and the remaining patterned photoresist layer is removed.

[0089] In steps S106 and S107, a third metal layer is formed on the protective layer 108 and on the exposed anode 104 and cathode 107, and the third metal layer is patterned to form a field plate layer 109. An anode conduction metal 110 is formed on the exposed anode 104, and a cathode conduction metal 111 is formed on the exposed cathode 107. More specifically, the steps of forming the anode conduction metal 110, the cathode conduction metal 111, and the field plate layer 109 are as follows: a third metal layer is deposited on the protective layer 108 using, but not limited to, an electron beam evaporation process. The material of the third metal layer is, for example, copper aluminum silicon (AlSiCu). The third metal layer is then subjected to photolithography (resist coating, exposure, and development) and etching processes to form the anode conduction metal 110, the cathode conduction metal 111, and the field plate layer 109. The field plate layer 109 is located between the anode conductive metal 110 and the cathode conductive metal 111 and outside the anode region AZ and is connected to the anode conductive metal 110 .

[0090] In summary, this embodiment provides a method for fabricating a semiconductor device. By providing a buffer layer 1101, lattice defects in the barrier layer 1102 caused by the lattice constant of the semiconductor substrate 1100 are reduced, thereby reducing interface states at the interface between the barrier layer 1102 and the semiconductor substrate 1100 and reducing interface leakage current at the interface. By providing an anode conductive metal 110, a cathode conductive metal 111, and a field plate, the depletion region of the semiconductor device is expanded, the electric field distribution is balanced, and the electric field strength of the main Schottky junction is reduced, thereby improving the withstand voltage of the semiconductor device.

[0091] See also Figure 6-1As shown, the present invention also provides a semiconductor device based on a gallium nitride epitaxial layer, for example, comprising: a semiconductor substrate 1100, a buffer layer 1101, a barrier layer 1102, a passivation layer 203, a first anode 204, a dielectric layer 205, a second anode 206, a cathode 207, a protective layer 208, a field plate layer 209, an anode conduction metal 210, and a cathode conduction metal 211. The buffer layer 1101 is disposed on the semiconductor substrate 1100, the barrier layer 1102 is disposed on a side of the buffer layer 1101 away from the semiconductor substrate 1100, and the passivation layer 203 is disposed on a side of the barrier layer 1102 away from the semiconductor substrate 1100. The first anode 204 penetrates the passivation layer 203 and extends into the barrier layer 1102. The dielectric layer 205 is disposed on a side of the passivation layer 203 away from the barrier layer 1102 and between the first anode 204 and the barrier layer 1102. The second anode 206 penetrates the dielectric layer 205 and the passivation layer 203 and extends into the barrier layer 1102. The cathode 207 is disposed on the dielectric layer 205 and penetrates the dielectric layer 205 and the passivation layer 203. The protective layer 208 is disposed on the first anode 204, the second anode 206, the cathode 207, and the dielectric layer 205. The field plate layer 209, the anode conductive metal 210, and the cathode conductive metal 211 are disposed on the protective layer 208. The field plate layer 209 is located between the anode conductive metal 210 and the cathode conductive metal 211, and the field plate layer 209 is connected to the anode conductive metal 210. Based on the above embodiment, in this embodiment, the material of the dielectric layer 205 is, for example, one of silicon nitride, silicon oxide, and tetraethyl orthosilicate. The first anode 204 and the second anode 206 are provided with a first metal layer and a second metal layer having a multilayer structure. The material of the first metal layer can be a titanium metal layer or a titanium nitride metal layer, wherein the second metal layer can include, but is not limited to, a titanium metal layer, a metal aluminum layer, a metal titanium layer, and a metal titanium nitride layer stacked in sequence. The cathode 207 includes a second metal layer. The second metal layer of the cathode 207 and the second metal layer of the anode can be formed simultaneously and both have a multilayer metal structure. In other words, the first anode 204 and the second anode 206 are composed of a first number of stacked metal layers, and the cathode 207 is composed of a second number of stacked metal layers, where the first number is greater than the second number.

[0092] See also Figure 6-1 As shown, in this embodiment, the provision of a buffer layer 1101 reduces lattice defects in the barrier layer 1102 due to the lattice constant of the semiconductor substrate 1100, thereby reducing interface states at the interface between the barrier layer 1102 and the semiconductor substrate 1100 and reducing interface leakage current at the interface. Forming a dielectric layer 205 on the passivation layer 203 greatly increases the anode area and reduces reverse leakage. Furthermore, the provision of an anode conductive metal 210, a cathode conductive metal 211, and a field plate layer 209 structure balances the electric field distribution, reduces the electric field strength of the main Schottky junction, and thereby improves the withstand voltage of the semiconductor device.

[0093] Please also refer to Figure 6-2 As shown, the present invention also provides a method for preparing a semiconductor device, the specific steps of which include:

[0094] In step S201 , a buffer layer 1101 and an aluminum gallium nitride barrier layer 1102 are grown on a silicon substrate or a silicon carbide substrate using an epitaxial growth process.

[0095] In step S202 , a silicon nitride passivation layer 203 is deposited on the aluminum gallium nitride barrier layer 1102 using, but not limited to, a chemical vapor deposition process.

[0096] In steps S203, S204, and S205, the silicon nitride passivation layer 203 and the aluminum gallium nitride barrier layer 1102 are patterned to form a first anode 204, a dielectric layer 205 is formed on the silicon nitride passivation layer 203 and within the first anode 204, and the dielectric layer 205, the silicon nitride passivation layer 203, and the aluminum gallium nitride barrier layer 1102 are patterned to form a second anode 206 that penetrates the dielectric layer 205, the silicon nitride passivation layer 203, and extends into the aluminum gallium nitride barrier layer 1102. More specifically, the material of the dielectric layer 205 is, for example, one of silicon nitride, silicon oxide, and tetraethyl orthosilicate, and the steps of patterning the dielectric layer 205, the silicon nitride passivation layer 203, and the aluminum gallium nitride barrier layer 1102 to form the second anode 206 penetrating the dielectric layer 205, the silicon nitride passivation layer 203, and extending into the aluminum gallium nitride barrier layer 1102 include, for example: coating a photoresist on the dielectric layer 205, exposing and developing the photoresist to obtain a patterned photoresist layer, and then etching the dielectric layer 205, the silicon nitride passivation layer 203, and the aluminum gallium nitride barrier layer 1102 using the patterned photoresist layer as a mask to form the second anode 206. A first metal layer is formed on the dielectric layer 205 and within the second anode 206, and the first metal layer is patterned to obtain the first metal layer located within the first anode 204 and the second anode 206. More specifically, the specific steps for obtaining the first metal layer located within the first anode 204 and the second anode 206 may be: depositing metal in the second anode 206 region and on the dielectric layer 205 using, but not limited to, a magnetron sputtering coating process to form the first metal layer, the material of the first metal layer may be one of titanium nitride and titanium, applying photoresist on the first metal layer, then exposing and developing the photoresist to obtain a patterned photoresist layer, and then etching the first metal layer using the patterned photoresist layer as a mask to remove the first metal layer outside the first anode 204 and the second anode 206 to obtain the first metal layer located within the first anode 204 and the second anode 206.

[0097] In step S206, the dielectric layer 205 and the silicon nitride passivation layer 203 are patterned to form a cathode 207 region extending through the dielectric layer 205 and the silicon nitride passivation layer 203. More specifically, the steps of patterning the dielectric layer 205 and the silicon nitride passivation layer 203 to form the cathode 207 region extending through the dielectric layer 205 and the silicon nitride passivation layer 203 can include: applying photoresist on the dielectric layer 205, then exposing and developing the photoresist to obtain a patterned photoresist layer; then etching the dielectric layer 205 and the silicon nitride passivation layer 203 using the patterned photoresist layer as a mask until the surface of the aluminum gallium nitride barrier layer 1102 is exposed to form the cathode 207 region; and removing the remaining patterned photoresist layer. A second metal layer is formed on the dielectric layer 205 and the first metal layer located within the first anode 204 and the second anode 206, as well as in the cathode 207 region, and patterning the second metal layer to obtain the second metal layer of the anode and the cathode 207. More specifically, the specific steps for obtaining a complete anode and cathode 207 may be: in the dielectric layer 205, the first metal layer located in the first anode 204 and the second anode 206, and the cathode 207 area, a titanium metal layer, a metal aluminum layer, a metal titanium layer and a metal titanium nitride layer are sequentially deposited using, but not limited to, an electron beam evaporation metal process to form a second metal layer, that is, the second metal layer is a stacked multi-layer metal structure, including but not limited to a titanium metal layer, a metal aluminum layer, a metal titanium layer and a metal titanium nitride layer, and then the second metal layer is subjected to a photolithography and etching process to form the second metal layer of the anode and the cathode 207. More specifically, the anode includes the first metal layer and the second metal layer located in the first anode 204 and the second anode 206.

[0098] In step S207, a protective layer 208 is formed on the dielectric layer 205 and the anode and cathode 207. More specifically, the protective layer 208 is, for example, a PETEOS (Plasma Enhanced Tetraethy lorthosilicate) oxide layer. The specific steps for forming the protective layer 208, for example, a PETEOS oxide layer, may be as follows: a silicon dioxide film is formed on the dielectric layer 205, the first anode 204, the second anode 206, and the cathode 207 using ethyl orthosilicate as a raw material, for example, by microwave plasma chemical vapor deposition (PCVD).

[0099] In step 208, the protective layer 208 is patterned to expose the first anode 204, the second anode 206, and the cathode 207. More specifically, the steps of exposing the first anode 204, the second anode 206, and the cathode 207 can be as follows: a photoresist is coated on the protective layer 208, and then the photoresist is exposed and developed to obtain a patterned photoresist layer. Then, the protective layer 208 is etched using the patterned photoresist layer as a mask until the first anode 204, the second anode 206, and the cathode 207 are exposed, and the remaining patterned photoresist layer is removed.

[0100] In step S209, a third metal layer is formed on the protective layer 208 and the exposed first anode 204, second anode 206, and cathode 207, and the third metal layer is patterned to form a field plate layer 209. An anode conduction metal 210 is formed on the exposed first anode 204 and second anode 206, and a cathode conduction metal 211 is formed on the exposed cathode 207. More specifically, the steps of forming the anode conduction metal 210, cathode conduction metal 211, and field plate are as follows: a third metal layer is deposited on the protective layer 208 using, but not limited to, an electron beam evaporation process. The material of the third metal layer is, for example, aluminum silicon copper (AlSiCu); and the third metal layer is then subjected to photolithography (resist coating, exposure, and development) and etching processes to form the anode conduction metal 210, cathode conduction metal 211, and field plate layer 209. The field plate layer 209 is located between the anode conductive metal 210 and the cathode conductive metal 211 and outside the anode region AZ and is connected to the anode conductive metal 210 .

[0101] See also Figure 7-1As shown, the present invention also provides a semiconductor device based on a gallium nitride epitaxial layer, comprising: a semiconductor substrate 1100, a buffer layer 1101, a barrier layer 1102, a passivation layer 303, a first anode contact hole 313, a dielectric layer 305, a second anode contact hole 314, a first anode 304, a second anode 306, a cathode contact hole 315, a cathode 307, a protective layer 308, an anode opening 316, a cathode opening 317, an anode conduction metal 310, a cathode conduction metal 311, and a field plate layer 309. The buffer layer 312 is disposed on the semiconductor substrate 1100. The barrier layer 1102 is disposed on a side of the buffer layer 1101 away from the semiconductor substrate 1100. The passivation layer 303 is disposed on a side of the barrier layer 1102 away from the buffer layer 1101. The first anode contact hole 313 penetrates the passivation layer 303 and extends into the barrier layer 1102. The dielectric layer 305 is disposed on a side of the passivation layer 303 away from the barrier layer 1102 and within the first anode contact hole 313. The second anode contact hole 314 penetrates the dielectric layer 305 and the passivation layer 303 and extends into the barrier layer 1102. The first anode 304 and the second anode 306 are disposed within the first anode contact hole 313 and the second anode contact hole 314. The first anode 304 and the second anode 306 include a first metal layer and a second metal layer. The first metal layer is disposed on a side of the dielectric layer 305 away from the passivation layer 303 and extends into the first anode contact hole 313 and the second anode contact hole 314 to cover the bottom of the dielectric layer 305 and the second anode contact hole 314. The second metal layer is disposed on the first metal layer and fills the first anode contact hole 313 and the second anode contact hole 314. A cathode contact hole 315 penetrates the dielectric layer 305 and the passivation layer 303. The cathode 307 is disposed on the dielectric layer 305 and fills the cathode contact hole 315. A protective layer 308 is disposed on the first anode 304, the second anode 306, the cathode 307, and the dielectric layer 305. An anode opening 316 penetrates the protective layer 308 to expose the first anode 304 and the second anode 306. A cathode opening 317 penetrates the protective layer 308 to expose the cathode 307. An anode conductive metal 310 is disposed on a side of the protective layer 308 away from the dielectric layer 305, and the anode conductive metal 310 fills the anode conductive metal opening 316. A cathode conductive metal 311 is disposed on a side of the protective layer 308 away from the dielectric layer 305, and the cathode conductive metal 311 fills the cathode conductive metal opening 317. A field plate layer 309 is disposed on the protective layer 308 and is located in the region between the anode conductive metal 310 and the cathode conductive metal 311, and is connected to the anode conductive metal 310. The anode conductive metal 310, the cathode conductive metal 311, and the field plate layer 309 can be formed simultaneously, for example, in the same photolithography and etching process.Based on the above embodiment, the first anode contact hole 313 and the second anode contact hole 314 of this embodiment are, for example, strip-shaped grooves. The material of the first metal layer contained in the first anode 304 and the second anode 306 can be a titanium metal layer or a titanium nitride metal layer. The second metal layer contained in the first anode 304 and the second anode 306 is a multilayer structure, which may include but is not limited to a titanium metal layer, a metal aluminum layer, a metal titanium layer, and a metal titanium nitride layer stacked in sequence. The cathode 307 and the second metal layer are formed simultaneously, for example, in the same electron beam evaporation process, and both are multilayer metal structures. In other words, the first anode 304 and the second anode 306 are composed of a first number of stacked metal layers, and the cathode 307 is composed of a second number of stacked metal layers, and the first number is greater than the second number.

[0102] In this embodiment, the semiconductor device significantly increases the anode area and reduces reverse leakage by forming a dielectric layer 305 on the passivation layer 303. Furthermore, the provision of an anode conductive metal 310, a cathode conductive metal 311, and a field plate structure balances the electric field distribution, reduces the electric field strength of the main Schottky junction, and thereby improves the withstand voltage of the semiconductor device.

[0103] Please also refer to Figure 7-2 As shown, the present invention also provides a method for preparing a semiconductor device, the method comprising the following steps:

[0104] In step S301 , a gallium nitride layer, for example, is grown on a silicon substrate or a silicon carbide substrate using an epitaxial growth process, and then an aluminum gallium nitride layer, for example, is grown on the gallium nitride layer using an epitaxial growth process.

[0105] In step S302 , a silicon nitride passivation layer 303 is deposited on the aluminum gallium nitride layer using, but not limited to, a chemical vapor deposition process.

[0106] In step S303, the silicon nitride passivation layer 303 and the aluminum gallium nitride layer are patterned to form a first anode contact hole 313. The first anode contact hole 313 penetrates the silicon nitride passivation layer 303 and extends into the aluminum gallium nitride layer. More specifically, the steps of patterning the silicon nitride passivation layer 303 and the aluminum gallium nitride layer to form the first anode contact hole 313 include, for example, coating the silicon nitride passivation layer 303 with photoresist, exposing and developing the photoresist to obtain a patterned photoresist layer, and then etching the silicon nitride passivation layer 303 and the aluminum gallium nitride layer using the patterned photoresist layer as a mask to form the first anode contact hole 313. The first anode contact hole 313 is a stripe-shaped groove.

[0107] In step S304, a dielectric layer 305 is formed on the silicon nitride passivation layer 303 and in the first anode contact hole 313, and the dielectric layer 305, the silicon nitride passivation layer 303 and the aluminum gallium nitride layer are patterned to form a second anode contact hole 314 that penetrates the dielectric layer 305, the silicon nitride passivation layer 303 and extends into the aluminum gallium nitride layer. More specifically, the dielectric layer 305 is made of, for example, silicon nitride, silicon oxide, and tetraethyl orthosilicate. Patterning the dielectric layer 305, silicon nitride passivation layer 303, and aluminum gallium nitride layer to form a second anode contact hole 314 that penetrates the dielectric layer 305, the silicon nitride passivation layer 303, and extends into the aluminum gallium nitride layer includes, for example, applying photoresist on the dielectric layer 305, exposing and developing the photoresist to obtain a patterned photoresist layer, and then etching the dielectric layer 305, the silicon nitride passivation layer 303, and the aluminum gallium nitride layer using the patterned photoresist layer as a mask to form the second anode contact hole 314. The area where the first anode contact hole 313 and the second anode contact hole 314 are located constitutes the anode area AZ, and the first anode 304 and the second anode 306 fill the first anode contact hole 313 and the second anode contact hole 314, respectively.

[0108] In step S305, a first metal layer is formed on the dielectric layer 305 and in the second anode contact hole 314, and the first metal layer is patterned to obtain the first metal layer located in the anode area AZ. More specifically, the specific steps for obtaining the first metal layer located in the anode area AZ may include: depositing metal in the second anode contact hole 314 and on the dielectric layer 305 using, but not limited to, a magnetron sputtering coating process to form the first metal layer, wherein the material of the first metal layer may be one of titanium nitride and titanium; applying a photoresist on the first metal layer, then exposing and developing the photoresist to obtain a patterned photoresist layer; and then etching the first metal layer using the patterned photoresist layer as a mask to remove the first metal layer outside the anode area AZ, thereby obtaining the first metal layer located in the anode area AZ.

[0109] In step S306, the dielectric layer 305 and the silicon nitride passivation layer 303 are patterned to form a cathode contact hole 315 penetrating the dielectric layer 305 and the silicon nitride passivation layer 303. More specifically, the steps of patterning the dielectric layer 305 and the silicon nitride passivation layer 303 to form the cathode contact hole 315 penetrating the dielectric layer 305 and the silicon nitride passivation layer 303 may include: coating a photoresist on the dielectric layer 305, then exposing and developing the photoresist to obtain a patterned photoresist layer, then etching the dielectric layer 305 and the silicon nitride passivation layer 303 using the patterned photoresist layer as a mask until the surface of the aluminum gallium nitride layer is exposed to form the cathode contact hole 315, and then removing the remaining patterned photoresist layer.

[0110] In step S307, a second metal layer is formed on the dielectric layer 305 and the first metal layer located in the anode area AZ and in the cathode contact hole 315, and the second metal layer is patterned to obtain a second metal layer of the first anode 304 and the second anode 306 and a cathode 307, wherein the cathode 307 fills the cathode contact hole 315. More specifically, the specific steps for obtaining the first anode 304, the second anode 306 and the cathode 307 may be: a titanium metal layer, a metal aluminum layer, a metal titanium layer and a metal titanium nitride layer are sequentially deposited in the dielectric layer 305, the first metal layer located in the anode area AZ and the cathode contact hole 315 using, but not limited to, an electron beam evaporation metal process to form a second metal layer, that is, the second metal layer is a stacked multi-layer metal structure, including but not limited to a titanium metal layer, a metal aluminum layer, a metal titanium layer and a metal titanium nitride layer, and then the second metal layer is subjected to a photolithography and etching process to form the first anode 304, the second metal layer of the second anode 306 and the cathode 307. More specifically, the first anode 304 and the second anode 306 include the first metal layer and the second metal layer located in the anode area AZ.

[0111] In step S308 , a protection layer 308 is formed on the dielectric layer 305 , the first anode 304 , the second anode 306 , and the cathode 307 .

[0112] In step S309, the protective layer 308 is patterned to form anode openings 316 and cathode openings 317 penetrating the protective layer 308 to expose the first anode 304, the second anode 306, and the cathode 307, respectively. More specifically, the steps of patterning the protective layer 308 to form the anode openings 316 and cathode openings 317 penetrating the protective layer 308 may include: coating a photoresist on the protective layer 308, then exposing and developing the photoresist to obtain a patterned photoresist layer, then etching the protective layer 308 using the patterned photoresist layer as a mask until the first anode 304, the second anode 306, and the cathode 307 are exposed, thereby forming the anode openings 316 and cathode openings 317, and removing the remaining patterned photoresist layer.

[0113] In step S310, a third metal layer is formed on the protective layer 308 and within the anode opening 316 and the cathode opening 317. The third metal layer is then patterned to form a field plate layer 309, an anode conduction metal 310 filling the anode opening 316, and a cathode conduction metal 311 filling the cathode opening 317. More specifically, the steps of forming the anode conduction metal 310, the cathode conduction metal 311, and the field plate are as follows: a third metal layer is deposited on the protective layer 308 using, but not limited to, an electron beam evaporation process. The third metal layer material is, for example, copper aluminum silicon (AlSiCu). The third metal layer is then subjected to photolithography (resist coating, exposure, and development) and etching processes to form the anode conduction metal 310, the cathode conduction metal 311, and the field plate. The field plate layer 309 is located in the region between the anode conduction metal 310 and the cathode conduction metal 311, as well as outside the anode region AZ and connected to the anode conduction metal 310.

[0114] In summary, this embodiment provides a method for fabricating a semiconductor device. By depositing a layer of dielectric material on the surface of the silicon nitride passivation layer 303 and within the first anode contact hole 313 to form a dielectric layer 305, the anode area is increased, significantly reducing reverse leakage. This dielectric layer can be formed simultaneously with the gate dielectric layer of the GaN HEMT, making it compatible with CMOS process lines. Furthermore, by providing the anode conduction metal 310, cathode conduction metal 311, and field plate layer 309, the depletion region of the semiconductor device is expanded, the electric field distribution is balanced, and the electric field strength of the main Schottky junction is reduced, thereby improving the withstand voltage of the semiconductor device.

[0115] See also Figure 8-1 As shown, the present invention also provides a semiconductor device based on a gallium nitride epitaxial layer, for example, including: a semiconductor substrate 1200, a first buffer layer 1201, a second buffer layer 1202, a third buffer layer 1203, a barrier layer 1204, a passivation layer 503, a first anode contact hole 513, a first anode 504, a dielectric layer 505, a second anode contact hole 514, a second anode 506, a cathode contact hole 515, a cathode 507, a protective layer 508, a field plate layer 509, an anode opening 516, an anode conduction metal 510, a cathode opening 517 and a cathode conduction metal 511.

[0116] See also Figure 8-1 As shown, the semiconductor device in this embodiment is applied Figure 2-1 The gallium nitride epitaxial layer in the embodiment is used as a substrate, and the semiconductor device described in the previous embodiment is prepared thereon.

[0117] Please also refer to Figure 8-2 As shown, this embodiment also provides a method for preparing a semiconductor device, the specific steps of which include:

[0118] In step S501, prepare Figure 2-1 GaN epitaxial layer.

[0119] In steps S502-S510, Figure 2-1 The GaN epitaxial layer is Figure 7-2 In steps S302-S310, a semiconductor device is prepared.

[0120] See also Figure 9-1 As shown, the present invention also provides a semiconductor device based on a gallium nitride epitaxial layer, for example, including: a semiconductor substrate 1300, a first buffer layer 1301, a post-processing layer 1302, a second buffer layer 1303, a barrier layer 1304, a passivation layer 603, a first anode contact hole 613, a first anode 604, a dielectric layer 605, a second anode contact hole 614, a second anode 606, a cathode contact hole 617, a cathode 607, a protective layer 608, a field plate layer 609, an anode opening 616, an anode conduction metal 610, a cathode opening 617 and a cathode conduction metal 611.

[0121] See also Figure 9-1 As shown, the semiconductor device in this embodiment is applied Figure 3-1 The gallium nitride epitaxial layer in the embodiment is used as a substrate, and the semiconductor device described in the previous embodiment is prepared thereon.

[0122] Please also refer to Figure 9-2 As shown, this embodiment also provides a method for preparing a semiconductor device, which includes the following steps:

[0123] In steps S601-S604, on the semiconductor substrate 1300, a Figure 3-1 The gallium nitride epitaxial layer is shown.

[0124] In steps S605-S613, Figure 3-1 The gallium nitride epitaxial layer shown is Figure 7-2 In steps S302-S310, a semiconductor device is prepared.

[0125] See also Figure 10-1 As shown, the present invention also provides a semiconductor device based on a gallium nitride epitaxial layer, including: a semiconductor substrate 1300, a first buffer layer 1301, a post-treatment layer 1302, a second buffer layer 1303, a barrier layer 1304, a dielectric layer 705, a source 704, a drain 706 and a gate 707.

[0126] See also Figure 10-1As shown, a first buffer layer 1301 is disposed on a semiconductor substrate 1300, a post-treatment layer 1302 is disposed on a side of the first buffer layer 1301 away from the semiconductor substrate 1300, a second buffer layer 1303 is disposed on a side of the post-treatment layer 1302 away from the first buffer layer 1301, and a barrier layer 1304 is disposed on a side of the second buffer layer 1303 away from the post-treatment layer 1302. The barrier layer 1304 has a wider bandgap than the second buffer layer 1303 and induces a 2D electron gas (2DEG) in the channel. A dielectric layer 705 is disposed on a side of the barrier layer 1304 away from the second buffer layer 1303. The source 704, drain 706 and gate 707 are arranged in the dielectric layer 705. The source 704, drain 706 and gate 707 respectively penetrate the dielectric layer 705 and are connected to the barrier layer 1304, and a portion of them protrudes from the top of the dielectric layer 705. The gate 707 extends into the barrier layer 1304 and reaches the bottom of the barrier layer 1304. The gate 707 has a conical structure, and the ratio of the upper and lower sides of the cone is 1:2-1:4.

[0127] See also Figure 10-1 As shown, based on the above embodiment, in this embodiment, the source electrode 704 and the drain electrode 706 are composed of a third metal layer, which includes a first titanium metal layer, an aluminum metal layer, a second titanium metal layer, and a titanium nitride layer in sequence. The gate electrode 707 is composed of a fourth metal layer, which is a nickel-gold alloy.

[0128] Please also refer to Figure 10-2 As shown, this embodiment also provides a method for preparing a semiconductor device, and the specific steps are as follows:

[0129] In step 701, a semiconductor substrate 1300 is prepared as follows Figure 3-1 The gallium nitride epitaxial layer is shown.

[0130] In step 702, a layer of hafnium oxide (HfO2) may be deposited on the surface of the GaN-based epitaxial wafer using plasma enhanced chemical vapor deposition to form a dielectric layer 705. The thickness of the hafnium oxide may be, for example, 2000 angstroms.

[0131] In step 703 , the dielectric layer 705 is dry-etched to form a source 704 contact hole and a drain 706 contact hole that are oppositely disposed.

[0132] In step 704, a first metal is deposited within the source 704 contact hole and the drain 706 contact hole, as well as on the surface of the dielectric layer 705. Specifically, a magnetron sputtering process can be used to sequentially deposit a first titanium metal layer, an aluminum metal layer, a second titanium metal layer, and a titanium nitride layer within the source 704 contact hole and the drain 706 contact hole, as well as on the surface of the dielectric layer 705, to form the first metal layer. The thickness of the first titanium metal layer can be, for example, 200 angstroms, the thickness of the aluminum metal layer can be, for example, 1200 angstroms, the thickness of the second titanium metal layer can be, for example, 200 angstroms, and the thickness of the titanium nitride layer can be, for example, 200 angstroms. The first metal is then photolithographically etched to expose a portion of the surface of the dielectric layer 705. The photolithographic process includes resist coating, exposure, and development. Thus, the first metal layer above the source 704 contact hole constitutes the source 704 of the device, and the first metal layer above the drain 706 contact hole constitutes the drain 706 of the device.

[0133] In step 705, the exposed portion of the dielectric layer 705 and the gallium nitride layer are dry-etched to form a contact hole for gate 707. The gate 707 contact hole completely penetrates the dielectric layer 705 and the gallium nitride layer to the bottom of the gallium nitride layer. Gate 707 has a tapered structure with a top-to-bottom ratio of 1:2 to 1:4.

[0134] In step 706, a silicon nitride layer is deposited in the contact hole of gate 707 using a magnetron sputtering process. The silicon nitride layer is no higher than the contact hole of gate 707. Then, Ni / Au is deposited as a second metal on the silicon nitride layer and on the outer edge of the contact hole of gate 707. The Ni / Au metal thickness ratio is 0.01-0.04 μm / 0.08-0.4 μm, thereby forming gate 707. Therefore, gate 707 is a composite structure composed of multiple materials.

[0135] See also Figure 11-1 As shown, the present invention also provides a semiconductor device based on a gallium nitride epitaxial layer, for example, including: a semiconductor substrate 1400, a first buffer layer 1401, a nano buffer layer 1402, a second buffer layer 1403, a barrier layer 1404, a passivation layer 803, a first anode contact hole 813, a first anode 804, a dielectric layer 805, a second anode contact hole 814, a second anode 806, a cathode contact hole 815, a cathode 807, a protective layer 808, a field plate layer 809, an anode opening 816, an anode conduction metal 810, a cathode opening 817 and a cathode conduction metal 811.

[0136] See also Figure 11-1 As shown, the semiconductor device in this embodiment is applied Figure 4-1 The gallium nitride epitaxial layer in the embodiment is used as a substrate, and the semiconductor device described in the previous embodiment is prepared thereon.

[0137] See also Figure 11-1 As shown, in other embodiments, a nano buffer layer 1402 can be simultaneously set between the semiconductor substrate 1400 and the buffer layer, between multiple buffer layers, and between the buffer layer and the barrier layer 1404. The nano buffer layer 1402 provides a nucleation point for the growth of subsequent growth layers, which is beneficial to improving the film formation quality of subsequent growth layers.

[0138] Please also refer to Figure 11-2 As shown, the present invention also provides a method for preparing a semiconductor device, comprising the following steps:

[0139] In steps S801-S804, prepare Figure 4-1 GaN epitaxial layer.

[0140] In steps S805-S813, Figure 4-1 The gallium nitride epitaxial layer shown is Figure 7-2 In steps S302-S310, a semiconductor device is prepared.

[0141] The preferred embodiments of the present invention disclosed above are intended only to help illustrate the present invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the present invention to the specific embodiments described. Obviously, many modifications and variations are possible based on the content of this specification. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better understand and utilize the present invention. The present invention is limited only by the claims and their full scope and equivalents.

[0142] The preferred embodiments of the present invention disclosed above are intended only to help illustrate the present invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the present invention to the specific embodiments described. Obviously, many modifications and variations are possible based on the content of this specification. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better understand and utilize the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A power semiconductor device, characterized in that: It includes: semiconductor substrates; a first buffer layer, disposed on the semiconductor substrate; a post-treatment layer, which is arranged on a side of the first buffer layer away from the semiconductor substrate, and the post-treatment layer is an aluminum oxide layer; a second buffer layer, which is disposed on a side of the post-treatment layer away from the first buffer layer, and the second buffer layer is a gallium nitride layer or an aluminum gallium nitride layer; a third buffer layer, disposed on the second buffer layer, and the third buffer layer is a gallium nitride layer; a barrier layer, disposed on the third buffer layer; a passivation layer, disposed on a side of the barrier layer away from the second buffer layer; a first anode contact hole, which penetrates the passivation layer and extends into the barrier layer; a first anode disposed in the first anode contact hole; a dielectric layer, disposed on a side of the passivation layer away from the barrier layer and between the first anode and the barrier layer; a second anode contact hole, which penetrates the dielectric layer and the passivation layer and extends into the barrier layer; a second anode disposed in the second anode contact hole; a cathode contact hole, which penetrates the dielectric layer and the passivation layer; a cathode, which is disposed on the dielectric layer and in the cathode contact hole; a protective layer, disposed on the first anode, the second anode, the cathode, and the dielectric layer; an anode opening penetrating through the protective layer to expose the first anode and the second anode; an anode conductive metal, disposed on a side of the protective layer away from the dielectric layer, and connected to the first anode and the second anode; a cathode opening penetrating through the protective layer to expose the cathode; a cathode conductive metal disposed on a side of the protective layer away from the dielectric layer, and connected to the cathode; A field plate layer is provided on the protection layer, wherein the field plate layer is connected to the anode conductive metal, wherein the anode conductive metal, the cathode conductive metal and the field plate layer are formed simultaneously.

2. A power semiconductor device according to claim 1, characterized in that: The first anode and the second anode include a first metal layer and a second metal layer, wherein the first metal layer is arranged on a side of the dielectric layer away from the passivation layer, and extends into the first anode contact hole and the second anode contact hole to cover the dielectric layer located at the bottom of the first anode contact hole and the bottom of the second anode contact hole, and the second metal layer is arranged on the first metal layer and fills the first anode contact hole and the second anode contact hole.

3. A power semiconductor device according to claim 1, characterized in that: The first anode and the second anode are formed by stacking a first number of metal layers, and the cathode is formed by stacking a second number of metal layers, and the first number is greater than the second number.

4. A power semiconductor device according to claim 1, characterized in that: The thickness of the first buffer layer is 10-300 nm.

5. The power semiconductor device according to claim 1, characterized in that: The thickness of the post-treatment layer is 0.5-2 nm.

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