Power device and manufacturing method thereof, and electronic device

Abstract

The application discloses a power device and a preparation method thereof and electronic equipment, and relates to the technical field of electronic components. The power device comprises a semiconductor substrate and a two-dimensional metal material layer on the surface of the semiconductor substrate. In the application, the two-dimensional metal material layer is in contact with the semiconductor substrate to form an electrode contact. Since the two-dimensional layered metal material forming the two-dimensional metal material layer has an atomically flat surface without dangling bonds, the two-dimensional layered metal material can provide a uniform and low-wrinkle surface for the interface between the metal and the semiconductor substrate, which is beneficial to improving the contact quality, reducing the influence of the rough surface of the semiconductor substrate, improving the transport efficiency of the carriers, and further improving the performance of the semiconductor power device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronic components, and particularly relates to a power device and a preparation method thereof, and an electronic device. BACKGROUND

[0002] At present, a semiconductor power device includes a semiconductor substrate and a metal electrode arranged on the semiconductor substrate; the semiconductor substrate serves as a main part and bears the function of regulating current and voltage, and the metal electrode is needed for connecting the device with external components. At present, the existing semiconductor power device is usually prepared by depositing metal (such as traditional metals such as Ni, Cr, Al and Ti) on the surface of the semiconductor substrate, but the contact quality is low, thereby resulting in an undesirable performance of the semiconductor power device. SUMMARY

[0003] In view of the above, the present application provides a power device and a preparation method thereof, and an electronic device, aiming at improving the problem that the low interface contact quality of the existing metal layer and the semiconductor substrate leads to an undesirable performance of the semiconductor power device.

[0004] In the first aspect, an embodiment of the present application provides a power device, which includes a semiconductor substrate and a two-dimensional metal material layer arranged on at least one side surface of the semiconductor substrate.

[0005] In some embodiments of the present application, the material of the two-dimensional metal material layer includes at least one of telluride and stannide;

[0006] And / or, the power device includes a semiconductor power device.

[0007] In some embodiments of the present application, the material of the two-dimensional metal material layer includes at least one of Td phase ditungsten telluride, 1T' phase dimolybdenum telluride, 1T phase dipatinum telluride and 1T' phase distannum platinum.

[0008] In some embodiments of the present application, the thickness of the two-dimensional metal material layer is greater than or equal to 9 nm.

[0009] In some embodiments of the present application, the thickness of the two-dimensional metal material layer is 9 nm to 51 nm.

[0010] In some embodiments of the present application, the thickness of the two-dimensional metal material layer is 10 nm to 50 nm.

[0011] In some embodiments of the present application, the thickness of the two-dimensional metal material layer is 13 nm to 17 nm.

[0012] In some embodiments of the present application, the semiconductor substrate and the two-dimensional metal material layer have van der Waals force.

[0013] In some embodiments of the present application, the material of the semiconductor substrate comprises a wide bandgap semiconductor material.

[0014] In some embodiments of the present application, the wide bandgap semiconductor material comprises at least one of silicon carbide, gallium nitride, aluminum nitride, gallium oxide and diamond.

[0015] In some embodiments of the present application, the power device further comprises an electrode layer for connecting with external elements, the electrode layer being stacked on the side of the two-dimensional metal material layer away from the semiconductor substrate.

[0016] In some embodiments of the present application, the thickness of the electrode layer is 100-200 μm.

[0017] In some embodiments of the present application, the semiconductor substrate is provided with a doped region on the side close to the two-dimensional metal material layer.

[0018] In some embodiments of the present application, the doped region is an N-type doped region.

[0019] In some embodiments of the present application, the N-type doped region comprises nitrogen ions, and the concentration of nitrogen ions in the doped region is greater than or equal to 5 x 1018cm-3. 19 cm -3 .

[0020] In some embodiments of the present application, the doped region is a P-type doped region.

[0021] In some embodiments of the present application, the P-type doped region comprises boron ions, and the concentration of boron ions in the doped region is greater than or equal to 5 x 1018cm-3. 19 cm -3 .

[0022] The second aspect of the present application provides a method for preparing a power device, the method comprising:

[0023] providing a semiconductor substrate;

[0024] providing a two-dimensional metal material layer on at least one side surface of the semiconductor substrate to obtain a power device.

[0025] In some embodiments of the present application, one side of the semiconductor substrate is provided with a doped region, and the two-dimensional metal material layer is provided on the side of the semiconductor substrate provided with the doped region.

[0026] In some embodiments of the present application, the step of providing a two-dimensional metal material layer on at least one side surface of the semiconductor substrate comprises:

[0027] providing a bulk mother material of two-dimensional metal material;

[0028] The two-dimensional metal material layer is obtained by peeling the two-dimensional metal material from the bulk mother material by a micro-mechanical peeling method.

[0029] The obtained two-dimensional metal material layer is arranged on the semiconductor substrate.

[0030] In some embodiments of the present application, the step of arranging the two-dimensional metal material layer on at least one side surface of the semiconductor substrate comprises:

[0031] The two-dimensional metal material layer is prepared by a vapor deposition method.

[0032] The obtained two-dimensional metal material layer is arranged on the semiconductor substrate.

[0033] In some embodiments of the present application, the step of arranging the obtained two-dimensional metal material layer on the semiconductor substrate comprises:

[0034] An organic adhesive film is arranged on the two-dimensional metal material layer, the two-dimensional metal material layer is arranged on the surface of the semiconductor substrate through the organic adhesive film, and the organic adhesive film is removed.

[0035] In some embodiments of the present application, the step of removing the organic adhesive film comprises: placing the two-dimensional metal material layer and the semiconductor substrate connected by the organic adhesive film in an organic solvent and soaking at 50-80℃ for 10-20min.

[0036] In some embodiments of the present application, the preparation method further comprises: after removing the organic adhesive film, annealing the two-dimensional metal material layer and the semiconductor substrate arranged in layers at a temperature less than or equal to 200℃.

[0037] In some embodiments of the present application, after arranging the two-dimensional metal material layer on the semiconductor substrate and before obtaining the power device, the preparation method further comprises forming an electrode layer on the side of the two-dimensional metal material layer away from the semiconductor substrate by an evaporation deposition method.

[0038] The third aspect of the present application provides an electronic device comprising the power device or the power device prepared by the preparation method.

[0039] Advantages:

[0040] In the application, the two-dimensional metal material layer is in contact with the semiconductor substrate to form an electrode contact. The two-dimensional layered metal material forming the two-dimensional metal material layer has an atomically flat surface and no dangling bonds on the surface, which can provide a uniform and low-crease surface for the interface of the metal-semiconductor substrate, thereby improving the contact quality, reducing the influence of the rough surface of the semiconductor substrate, improving the transport efficiency of the carriers, and further improving the performance of the power device. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0042] Figure 1 is a structure schematic diagram of one embodiment of the semiconductor power device provided by the present application;

[0043] Figure 2 is a molecular structure schematic diagram of the two-dimensional layered metal material provided by the present application;

[0044] Figures 3-7 is an electrical curve of the semiconductor power device provided by the experimental example of the present application.

[0045] Reference signs:

[0046] 1, semiconductor substrate; 2, doped region; 3, two-dimensional metal material layer; 4, electrode layer. DETAILED DESCRIPTION

[0047] The experimental examples described in the present application are only some embodiments of the present application, not all embodiments, and all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application. In addition, it should be understood that the specific embodiments described herein are only for the purpose of illustration and explanation of the present application, and are not intended to limit the present application.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used in the specification of the present application are only for the purpose of describing the specific embodiments and are not intended to limit the present application. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0049] In the description of the present application, the term "comprising" means "including but not limited to".

[0050] In the present application, the association relationship of the associated objects is described by "and / or", which means that there can be three kinds of relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone. Wherein A and B can be singular or plural.

[0051] In the present application, "at least one" means one or more, and "multiple" means two or more. "One or more", "at least one of the following" or the like means any combination of these items, including any combination of single item or multiple items. For example, "at least one of a, b, or c", or "at least one of a, b, and c" can represent a, b, c, a-b (i.e. a and b), a-c, b-c, or a-b-c, where a, b, and c can be single or multiple.

[0052] Various embodiments of the present application can exist in the form of a range; it should be understood that the description in the form of a range is only for the convenience and brevity, and should not be understood as a hard limit on the scope of the present application; therefore, it should be considered that the described range has specifically disclosed all possible sub-ranges and single values within the range. For example, it should be considered that the range description from 1 to 6 has specifically disclosed sub-ranges, such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as single numbers within the described range, such as 1, 2, 3, 4, 5, and 6, regardless of the range. In addition, whenever a numerical range is indicated in this document, it refers to any cited number (fraction or integer) within the indicated range.

[0053] At present, the semiconductor power device includes a semiconductor substrate and a metal electrode arranged on the semiconductor substrate; wherein the semiconductor substrate serves as the main part and undertakes the function of regulating current and voltage, and the metal electrode is needed for the connection between the device and external elements. At present, the existing semiconductor power device is usually prepared by depositing metal (such as traditional metals such as Ni, Cr, Al, Ti, etc.) on the surface of the semiconductor substrate, but it has the problem of low contact quality, which leads to the unsatisfactory performance of the semiconductor power device.

[0054] In view of this, please refer to Figure 1 and Figure 2The embodiment of the present application provides a power device, and exemplarily, the power device is a semiconductor power device. The semiconductor power device comprises a semiconductor substrate 1 and a two-dimensional metal material layer 3 located on the surface of the semiconductor substrate 1, and the semiconductor substrate 1 and the two-dimensional metal material layer 3 are also understood to be laminated, and the two-dimensional metal material layer 3 is in direct contact with the semiconductor substrate 1. Exemplarily, one side of the semiconductor substrate 1 is provided with a doped region 2, and the two-dimensional metal material layer 3 is located on the side of the semiconductor substrate 1 provided with the doped region 2. In the present application, the electrode contact is formed by the contact between the two-dimensional metal material layer 3 and the semiconductor substrate 1. Since the two-dimensional layered metal material forming the two-dimensional metal material layer 3 has an atomically flat surface and no dangling bond on the surface, the two-dimensional layered metal material can provide a uniform and low-wrinkle surface for the interface of the metal-semiconductor substrate 1, which is beneficial to improve the contact quality, reduce the influence of the rough surface of the semiconductor substrate 1, improve the transport efficiency of the carriers, and further improve the performance of the semiconductor power device.

[0055] It should be noted that the two-dimensional layered metal material in the present application refers to a material with layered molecular structure and metallic properties, and a structural schematic diagram thereof is as shown in Figure 2 The two-dimensional layered metal material in the present application has strong conductivity.

[0056] In some embodiments of the present application, the semiconductor substrate and the two-dimensional metal material layer have van der Waals force. Exemplarily, the contact interface between the semiconductor substrate 1 and the two-dimensional metal material layer 3 is combined by van der Waals force. In this way, the stress concentration caused by the lattice mismatch between different materials can be ignored, the electrode contact is more stable, and the performance of the semiconductor power device in the present application is improved.

[0057] In some embodiments of the present application, the material of the two-dimensional metal material layer includes at least one of telluride and stannide. For example, the material of the two-dimensional metal material layer 3 includes at least one of Td phase di-tungsten telluride (Td-WTe2), 1T' phase di-molybdenum telluride (1T'-MoTe2), 1T phase di-platinum telluride (1T-PtTe2), and 1T' phase di-platinum stannide (1T'-PtSe2). It should be noted that Td phase indicates that the crystal structure of the material is orthorhombic phase; 1T phase indicates that the crystal structure of the material is trigonal phase; and 1T' phase indicates that the crystal structure of the material is monoclinic phase. It can be understood that these different two-dimensional layered metal materials exhibit different work functions, and thus different relative positions with the conduction band and valence band of the semiconductor substrate 1 (for example, SiC substrate), which can realize devices with different functions. For example, according to the functional requirements of the power device, the two-dimensional layered metal material can be used to match the positions of the conduction band and valence band of the semiconductor material to construct "ohmic contact" or "Schottky contact" electrode contact, which plays a decisive role in the on-state loss, switching efficiency and thermal stability of the power device.

[0058] In some embodiments of the present application, the thickness of the two-dimensional metal material layer is greater than or equal to 9 nm. For example, the thickness of the two-dimensional metal material layer 3 is 9 nm to 51 nm. Further, the thickness of the two-dimensional metal material layer is 10 nm to 50 nm. For example, the thickness of the two-dimensional metal material layer is 9 nm, 10 nm, 13 nm, 15 nm, 17 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 51 nm, and a range value between any two of the above values. For example, the thickness of the two-dimensional metal material layer is 13 nm to 17 nm. In this way, by setting the thickness of the two-dimensional metal material layer within a suitable range, the performance of the semiconductor power device can be further improved. The thickness of the two-dimensional metal material layer can be determined by optical microscopy or Raman spectroscopy, which is not limited herein.

[0059] For example, the two-dimensional layered metal material can be peeled off from the target substrate surface by a micromechanical peeling method, and then transferred to the semiconductor substrate 1 to form the two-dimensional metal material layer 3. In some other embodiments of the present application, the two-dimensional metal material layer 3 can also be prepared by a vapor deposition method. The vapor deposition method can be used to scale up the preparation of semiconductor power devices with two-dimensional layered metal electrode contact.

[0060] In some embodiments of the present application, the material for preparing the semiconductor substrate 1 comprises a wide bandgap semiconductor material. It should be noted that the wide bandgap semiconductor material refers to a semiconductor material with a large energy band gap, usually greater than 3 electron volts (eV). Due to its large energy band gap, these materials can work stably under high temperature, high voltage, high frequency and high power conditions, significantly improving the efficiency and reliability of the device. Compared with traditional silicon-based semiconductors, wide bandgap semiconductors also have obvious advantages in electron mobility, thermal conductivity and radiation resistance, and are widely used in high-power electronic devices, electric vehicles, photovoltaic systems, radio frequency and radar technology, energy conversion and power electronic equipment, etc.

[0061] Exemplarily, the wide bandgap semiconductor material comprises at least one of silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga2O3) and diamond. It should be noted that silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga2O3) and diamond are all wide bandgap semiconductor materials, and their band gap widths are 3.26 eV, 3.4 eV, 6.2 eV, 4.9 eV and 5.4 eV, respectively, so that the power device in the present application can be applied to high voltage, high power, high temperature and other application scenarios.

[0062] Exemplarily, the wide bandgap semiconductor material is SiC material, and the SiC epitaxial layer obtained by vapor deposition method can be doped with nitrogen or ammonia to realize N-type electron conduction during epitaxial growth. It can also be doped with trimethylaluminum to realize P-type hole conduction, which is the basis for realizing the design function of the power device.

[0063] In some embodiments of the present application, the semiconductor power device further comprises an electrode layer 4 for connecting with external elements, and the electrode layer 4 is arranged on the side of the two-dimensional metal material layer away from the semiconductor substrate 1. Exemplarily, the electrode layer 4 can be used as a wire to connect the semiconductor power device with an external power supply. Exemplarily, the electrode layer 4 can be a metal or metal alloy layer.

[0064] It should be noted that since the semiconductor power device in the present application comprises a two-dimensional metal material layer 3, the two-dimensional layered metal material has strong conductivity, so the two-dimensional metal material layer 3 prepared therefrom also has strong conductivity, so that the material for preparing the electrode layer 4 can be any kind of metal, without considering the problem of matching the work function of the metal material, which is conducive to reducing or avoiding the problem caused by the mismatching of the type selection of the metal material. Exemplarily, a low-cost metal is used as the electrode layer 4 arranged on the two-dimensional metal material layer. In some embodiments of the present application, the electrode layer 4 is deposited on the surface of the two-dimensional metal material layer by vapor deposition process such as evaporation deposition and magnetron sputtering.

[0065] In some embodiments of the present application, the thickness of the electrode layer 4 is 100 μm to 200 μm. Specifically, it can be 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, 160 μm, 170 μm, 180 μm, 190 μm, 200 μm. In this way, the electrode layer and the power device in the present application can have higher conductivity at almost the same manufacturing cost.

[0066] In some embodiments of the present application, the semiconductor power device includes at least one of a power diode, a power transistor, a field effect transistor (FET), a Schottky diode, etc., which can realize the control and regulation of electric energy through electric energy conversion, voltage and current regulation, switching control, etc.

[0067] In some embodiments of the present application, the doped region 2 is an N-type doped region. Further, the N-type doped region includes nitrogen ions, and the nitrogen ion concentration of the doped region is greater than or equal to 5 x 1018cm-3. 19 cm -3 That is, the number of injected N ions in the semiconductor substrate (e.g., SiC substrate) per cubic centimeter is greater than or equal to 5 x 1018cm-3. 19 In this way, the N ion concentration of the doped region 2 can be higher, the conductivity of the doped region 2 is higher, and the resistance of the electrode contact formed by the subsequent contact of the metal electrode is lower, which is beneficial to improve the performance of the power device.

[0068] For example, the ion implantation method is used to implant nitrogen ions into the specified region of the semiconductor substrate. The effect of N ion implantation and doping is to improve the conductivity of the semiconductor material, so that the originally semiconductive region becomes conductive, which is used to build an electrode with low contact resistance.

[0069] In some embodiments of the present application, the doped region is a P-type doped region. Further, the P-type doped region includes boron ions, and the boron ion concentration of the doped region is greater than or equal to 5 x 1018cm-3. 19 cm -3 .

[0070] The present application also provides a preparation method of a semiconductor power device, which is used to prepare the semiconductor power device described above.

[0071] In some embodiments of the present application, the preparation method includes the following steps:

[0072] providing a semiconductor substrate 1;

[0073] The semiconductor power device is obtained by laminating a two-dimensional metal material layer on at least one side surface of the semiconductor substrate 1. In the present application, the electrode contact is formed by contacting the two-dimensional metal material layer with the semiconductor substrate 1. Since the two-dimensional layered metal material forming the two-dimensional metal material layer has an atomically flat surface and no dangling bonds on the surface, the two-dimensional metal material layer can provide a uniform and low-crease surface for the interface between the metal and the semiconductor substrate 1, which is conducive to improving the contact quality, reducing the influence of the surface roughness of the semiconductor substrate 1, improving the transport efficiency of the carriers, and further improving the performance of the semiconductor power device.

[0074] In some embodiments of the present application, the semiconductor substrate 1 and the two-dimensional metal material layer 3 have van der Waals forces. Illustratively, the contact interface between the semiconductor substrate 1 and the two-dimensional metal material layer 3 is combined by van der Waals forces. In this embodiment, the stress concentration caused by the lattice mismatch between different materials can be ignored by combining the contact interface between the semiconductor substrate 1 and the two-dimensional metal material layer by van der Waals forces, so that the electrode contact is more stable, thereby improving the performance of the semiconductor power device in the present application.

[0075] In some embodiments of the present application, the thickness of the electrode layer is 100 μm to 200 μm. Specifically, the thickness of the electrode layer can be 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, 160 μm, 170 μm, 180 μm, 190 μm, 200 μm. In this way, the electrode layer and the power device in the present application can have higher conductivity under the condition that the preparation cost is almost similar.

[0076] In some embodiments of the present application, the material of the semiconductor substrate 1 includes at least one of silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga2O3), and diamond. It should be noted that silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), gallium oxide (Ga2O3), and diamond are all wide-bandgap semiconductor materials, and their bandgap widths are 3.26 eV, 3.4 eV, 6.2 eV, 4.9 eV, and 5.4 eV, respectively. In this way, the power device in the present application can be applied to high-voltage, high-power, high-temperature, and other application scenarios.

[0077] Taking SiC as an example of the material of the semiconductor substrate 1, the steps of providing the semiconductor substrate 1 include: providing a SiC substrate, growing an N-type conductive SiC epitaxial layer on the SiC substrate by chemical vapor deposition to obtain a SiC epitaxial wafer. Then, nitrogen ions are injected into the SiC epitaxial wafer by ion implantation to form a doped region 2, thereby obtaining a semiconductor substrate 1 with a doped region 2.

[0078] In some embodiments of the present application, one side of the semiconductor substrate is provided with a doped region, and the two-dimensional metal material layer is arranged on the side of the semiconductor substrate provided with the doped region. Further, the doped region 2 is an N-type high-doped region, and the N ion concentration of the doped region 2 is greater than or equal to 5×1018cm-3. 19 cm -3 In this way, the N ion concentration of the doped region 2 can be higher, the conductivity of the doped region 2 is higher, and the resistance of the electrode contact formed by the subsequent contact of the metal electrode is lower, which is beneficial to improve the performance of the power device.

[0079] In some embodiments of the present application, the step of arranging the two-dimensional metal material layer on at least one side surface of the semiconductor substrate 1 comprises: providing a block-shaped master batch of two-dimensional layered metal material; using a micro-mechanical peeling method to peel the two-dimensional layered metal material from the block-shaped master batch to obtain a two-dimensional metal material layer; and arranging the obtained two-dimensional metal material layer on the semiconductor substrate 1. In this embodiment, the two-dimensional metal material layer is arranged on the semiconductor substrate, so that the advantages of the atomically flat surface of the two-dimensional metal material layer can be fully utilized. Specifically, (1) the two-dimensional layered metal material has an atomically flat surface, and the surface has no dangling bond, which can provide a uniform and low-wrinkle surface for the metal-semiconductor interface, reduce the influence of the surface roughness of the wide-bandgap semiconductor material, and improve the transport efficiency of the carriers. (2) The layered structure of the two-dimensional layered metal material means that the contact interface with the wide-bandgap semiconductor material is combined by van der Waals force, and the stress concentration caused by the lattice mismatch between different materials can be ignored, which is beneficial to make the electrode contact more stable.

[0080] Further, the two-dimensional metal material layer and the semiconductor substrate 1 arranged in layers are subjected to annealing treatment. Specifically, the annealing temperature is less than or equal to 200°C. Further, the annealing treatment is carried out in an inert atmosphere (for example, an argon atmosphere), and the annealing time is 60 min-120 min. It should be noted that in the prior art, after the traditional metal material (for example, Ni, Cr, Al, Ti, etc.) is directly deposited on the surface of the semiconductor substrate 1, high-temperature annealing treatment is required to make the metal and the semiconductor substrate react at the interface to form an alloy electrode. The annealing temperature in this process is greater than 900°C, and the high temperature used for annealing will affect the quality and reliability of the device gate oxide. The two-dimensional layered metal material electrode can be prepared by micro-mechanical peeling and physical transfer. This technical process has no high-temperature (≤200 ℃) treatment process, which is beneficial to reduce the degradation of the quality of the power device gate oxide layer caused by high temperature.

[0081] For example, the bulk materials of two-dimensional layered metal materials include, but are not limited to, Td-WTe2 or 1T'-PtSe2 bulk materials. It is understood that these different two-dimensional layered metal materials exhibit different work functions, thus resulting in different relative positional relationships with the conduction band and valence band of the semiconductor substrate 1 (e.g., SiC substrate), enabling devices with different functions. For example, according to the functional requirements of power devices, the conduction band and valence band positions of semiconductor materials can be matched using two-dimensional layered metal materials to construct either "ohmic contacts" or "Schottky contacts," which play a decisive role in the conduction loss, switching efficiency, and thermal stability of power devices.

[0082] In some embodiments of this application, the thickness of the two-dimensional metal material layer is greater than or equal to 9 nm. For example, the thickness of the two-dimensional metal material layer 3 is 9 nm to 51 nm. Further, the thickness of the two-dimensional metal material layer is 10 nm to 50 nm. Exemplarily, the thickness of the two-dimensional metal material layer is 9 nm, 10 nm, 13 nm, 15 nm, 17 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 51 nm, and any two of the above values. For another example, the thickness of the two-dimensional metal material layer is 13 nm to 17 nm. Thus, by setting the thickness of the two-dimensional metal material layer within a suitable range, it is beneficial to further improve the performance of semiconductor power devices. The thickness of the two-dimensional metal material layer can be determined using optical microscopy or Raman spectroscopy, and is not limited here.

[0083] Furthermore, the step of depositing the obtained two-dimensional metal material layer on the semiconductor substrate includes: depositing an organic adhesive film on the obtained two-dimensional metal material layer, then using the organic adhesive film to transfer the two-dimensional metal material layer to the surface of the semiconductor substrate 1, and then removing the organic adhesive film to obtain a semiconductor substrate with a two-dimensional metal material layer, such as a power device. This simplifies the fabrication process and reduces fabrication costs.

[0084] For example, the step of forming an adhesive film on the obtained two-dimensional metal material layer includes coating the surface of the two-dimensional metal material layer with an adhesive liquid, and then drying the adhesive liquid to form an adhesive film. For example, the adhesive film can be made of PPC material, and the specific drying conditions are: baking on a hot plate at 70°C to 90°C for 20 to 50 seconds, and the thickness of the resulting adhesive film is 100 μm to 200 μm.

[0085] For example, the two-dimensional metal material layer and the semiconductor substrate connected by the organic adhesive film are placed in an organic solvent and immersed at 50°C to 80°C for 10-20 minutes. In this embodiment, the adhesive film is completely removed by placing the semi-finished product with the adhesive film in acetone solvent, taking advantage of the good solubility of acetone solution for organic matter, and immersing it at 50°C to 80°C for 10-20 minutes.

[0086] In some other embodiments of this application, the step of stacking a two-dimensional metal material layer on the side of the semiconductor substrate 1 where the doped region 2 is provided can also be: preparing the two-dimensional metal material layer by vapor deposition, and then transferring the prepared two-dimensional metal material layer onto the semiconductor substrate 1. It should be noted that the step of depositing the prepared two-dimensional metal material layer onto the semiconductor substrate 1 can be referred to the foregoing description. The specific process of preparing the two-dimensional metal material layer by vapor deposition is not a major improvement of this application and will not be elaborated here.

[0087] In some embodiments of this application, after the two-dimensional metal material layer is deposited on the semiconductor substrate and before the power device is obtained, the fabrication method further includes forming an electrode layer on the side of the two-dimensional metal material layer facing away from the semiconductor substrate using an evaporation deposition method. Further, after the two-dimensional metal material layer is stacked on the side of the semiconductor substrate 1 where the doped region 2 is provided, the fabrication method further includes depositing an electrode layer 4 on the side of the two-dimensional metal material layer facing away from the semiconductor substrate 1. Further, the thickness of the electrode layer 4 is 100 μm to 200 μm. Exemplarily, metal Al is deposited on the surface of the two-dimensional layered metal material as the electrode layer 4 using an evaporation deposition method.

[0088] This application also provides an electronic device, which includes the aforementioned power device or a power device prepared by the aforementioned preparation method. Exemplarily, the electronic device includes, but is not limited to, a display, a power adapter, an LED light, a solar panel, a motor driver, etc.

[0089] To facilitate understanding, the technical solution of this application will be further explained below with specific experimental examples and test results.

[0090] Example 1

[0091] Step 1: Provide a SiC substrate and grow an N-type conductive SiC epitaxial layer on the substrate using chemical vapor deposition to obtain a SiC epitaxial wafer.

[0092] Step 2: Nitrogen ions are implanted into a designated area of ​​the SiC epitaxial wafer using ion implantation. The concentration of implanted nitrogen ions is 5 × 10⁻⁶. 19 cm -3 This forms a SiC epitaxial material with a highly doped N-type region.

[0093] Step 3: Cut the obtained SiC epitaxial material with N-type highly doped region into the required size to obtain SiC semiconductor substrate for later use.

[0094] Step 4: Provide a two-dimensional metal material in bulk form (Td-WTe2 bulk material) and a target substrate. Use a micromechanical peeling method to obtain a two-dimensional metal material layer: Place the Td-WTe2 bulk material on a blue film tape, tear the tape ten times to obtain the material of the corresponding thickness, slowly attach the side of the blue film tape with the material attached to the corresponding target substrate for 10 minutes, and then slowly separate the tape from the substrate to complete the transfer and placement of the two-dimensional metal material on the target substrate, resulting in a Td-WTe2 two-dimensional metal material layer with a thickness of 10 nm.

[0095] Step 5: Coat the surface of the obtained two-dimensional metal material layer with an organic adhesive film and dry it. The organic adhesive film is made of PPC material, and the specific drying conditions are: bake on a hot plate at 90℃ for 20 seconds, and the thickness of the obtained organic adhesive film is 150μm.

[0096] Step 6: Transferring the two-dimensional metal material layer to the surface of the SiC semiconductor substrate with the N-type highly doped region using an organic adhesive film: Slowly separate the PPC film from the target substrate, transfer the micromechanically exfoliated two-dimensional metal Td-WTe2 material layer onto the PPC film, and slowly attach it to the surface of the provided SiC semiconductor substrate with the N-type doped region. Then, place the sample with the PPC film in acetone and immerse it at 80 °C for 15 min to remove the PPC film and obtain the Td-WTe2 / SiC structure.

[0097] Step 7: Anneal the obtained Td-WTe2 / SiC structure at 200 °C for 90 min in an argon atmosphere.

[0098] Step 8: Deposit Al metal on the surface of the two-dimensional metal material layer using the evaporation deposition method to form an electrode layer with a thickness of 200 μm, thereby obtaining a two-dimensional layered metal material Al / Td-WTe2 / SiC electrode contact structure, and test its surface roughness and specific contact resistance.

[0099] Step 9: Fabricate the Al / Td-WTe2 / SiC electrode contact structure obtained by the above method into a power device, and perform electrical characteristic tests on the power device.

[0100] Examples 2-5

[0101] The difference between it and Example 1 is that the thickness of the Td-WTe2 material layer (i.e., the two-dimensional metal material layer) is different.

[0102] Example 6

[0103] The difference between this and Example 2 is that the Td-WTe2 two-dimensional metal material layer is replaced with a 1T'-PtSe2 two-dimensional metal material layer.

[0104] Example 7

[0105] The difference between this and Example 2 is that the Td-WTe2 two-dimensional metal material layer is replaced with a 1T'-MoTe2 two-dimensional metal material layer.

[0106] Example 8

[0107] The difference between this and Example 2 is that the Td-WTe2 two-dimensional metal material layer is replaced with a 1T'-1T-PtTe2 two-dimensional metal material layer.

[0108] Example 9

[0109] The difference between this example and Example 2 is that the semiconductor substrate is made of GaN.

[0110] Example 10

[0111] The difference between this and Example 2 is that the semiconductor substrate is made of diamond.

[0112] Example 11

[0113] The difference between this example and Example 2 is that the semiconductor substrate is made of Ga2O3.

[0114] Example 12

[0115] The difference between this example and Example 2 is that the semiconductor substrate is made of AlN.

[0116] Example 13

[0117] The difference between this and Example 2 is that the thickness of the electrode layer is 100 nm.

[0118] Example 14

[0119] The difference between this and Example 2 is that the thickness of the electrode layer is 150 nm.

[0120] Example 15

[0121] The difference between this example and Example 6 is that boron ions are implanted into a designated area of ​​the SiC epitaxial wafer using ion implantation, and the concentration of implanted boron ions is 5 × 10⁻⁶. 19 cm -3 This forms a SiC epitaxial material with a highly doped P-type region.

[0122] Comparative Example 1

[0123] The difference between it and Example 1 is that a nickel layer is used instead of a two-dimensional metal material layer.

[0124] Test methods

[0125] 1. Thickness of two-dimensional metal material layer and electrode layer: The thickness of the two-dimensional layered metal material layer and electrode layer was measured using atomic force microscopy (AFM).

[0126] 2. Surface roughness test: The surface roughness of the electrode contact structure was tested using an atomic force microscope (AFM), with a scanning area of ​​5×5μm. 2 .

[0127] 3. Specific contact resistance test: The specific contact resistance of the two-dimensional layered metal / wide bandgap semiconductor electrode contact structure is tested using the transmission line model (TLM) method.

[0128] 4. Semiconductor power device performance testing: The electrical characteristics of the manufactured power devices are tested according to IEC60747-8 standard, and the current-voltage characteristic curve of the sample under test is tested using a probe test station.

[0129] The above experimental examples underwent relevant performance tests, and the test results are shown in Table 1.

[0130] Table 1

[0131]

[0132] Examples 1 to 15 differ from Comparative Example 1 in that Comparative Example 1 does not include the two-dimensional metallic material layer described in this application, as shown in Table 1. Figures 3 to 7 The test results show that the electrode contact structure with a two-dimensional metal material layer in this application has a lower surface roughness Ra, a lower specific contact resistance, and better electrical characteristics of the semiconductor power device.

[0133] The difference between Examples 1 to 5 lies in the thickness of the two-dimensional metal material layer. The thicknesses of the two-dimensional metal material layers in Examples 1 to 5 are 10 nm, 15 nm, 50 nm, 9 nm, and 51 nm, respectively. After depositing Al metal to obtain Al / Td-WTe2 / Si, the surface roughness is 0.31 nm, 0.14 nm, 0.25 nm, 0.48 nm, and 0.45 nm, respectively. That is, as the thickness of the two-dimensional metal material layer increases, the surface roughness first decreases and then increases. This is because the high temperature conditions cause a certain degree of damage to the surface of the two-dimensional layered material Td-WTe2. The thinner the Td-WTe2, the greater the degree of damage, thus resulting in a rougher surface after metal deposition. When the thickness of Td-WTe2 increases to about 15 nm, the unique layered, atomically flat, inert surface of the two-dimensional layered metal material plays a significant role, further reducing the surface roughness. When the thickness of the two-dimensional metal material layer is further increased, for example, when the thickness of the two-dimensional metal material layer is greater than 50 nm, such as the 51 nm thickness shown in Example 5, the specific contact resistance increases to 6.9 Ω·cm. 2 The possible reason is that current micromechanical exfoliation methods for preparing Td-WTe2 materials, when used to prepare materials exceeding a certain thickness, indicate insufficient exfoliation of the Td-WTe2 bulk material. Insufficient exfoliation results in significant fluctuations in surface roughness, leading to higher surface roughness in Al / Td-WTe2 / Si and consequently higher specific contact resistance at the electrode contacts. Therefore, when the Td-WTe2 material thickness is around 13-17 nm, Al / Td-WTe2 / SiC exhibits lower surface roughness and lower specific contact resistance.

[0134] Comparative Example 1 shows the test results of a traditional metallic Ni electrode contact. Ion implantation damages the SiC material surface, resulting in a rougher surface and thus a higher specific contact resistance. In contrast, although very thin Td-WTe2 materials are also affected by poor roughness, the unique layered, atomically flat, inert surface of the two-dimensional material, along with the van der Waals interactions with the SiC substrate surface, significantly reduces the influence of the SiC substrate surface on the electrode contact structure, enabling it to provide superior surface finish and specific contact resistance.

[0135] Furthermore, since the work function (4.1 eV) of the two-dimensional layered metallic material Td-WTe2 is close to that of the conduction band of SiC material, the power devices constructed in Examples 1-5 and Comparative Example 1 exhibit near-ohmic contact electrical characteristics, such as... Figure 3 As shown.

[0136] The difference between Example 6 and Example 2 lies in the two-dimensional layered metal material. Other two-dimensional layered metal materials with different work functions can be used. In Example 6, the two-dimensional layered metal material is 1T'-PtSe2. Since the work function of 1T'-PtSe2 is 4.9 eV, it forms a Schottky contact after contacting the SiC phase. The power device fabricated with the Al / 1T'-PtSe2 / SiC electrode contact will exhibit the rectifying electrical characteristics of a Schottky diode, such as... Figure 4 As shown.

[0137] The difference between Examples 7 and 8 and Example 2 lies in the different two-dimensional layered metal materials. Since the work functions of 1T'-MoTe2 and 1T'-1T-PtTe2 are closer to the conduction band of SiC, they form ohmic contacts when in contact with SiC. The resulting power devices exhibit near-linear electrical characteristics, such as... Figure 5 As shown.

[0138] The difference between Examples 9 to 12 and Example 1 lies in the semiconductor substrate material. The method of using two-dimensional layered metal materials for electrode contacts is not only applicable to SiC semiconductor materials but also to other wide-bandgap semiconductor materials. Examples 9 to 12 respectively present GaN, diamond, Ga2O3, and AlN power devices based on two-dimensional layered metal material Td-WTe2 electrode contacts. The surface roughness of the prepared electrode contacts is good, at 0.13 nm, 0.19 nm, 0.23 nm, and 0.30 nm, respectively; correspondingly, the specific contact resistances are 3.9 Ω·cm², 4.4 Ω·cm², 4.6 Ω·cm², and 5.0 Ω·cm², respectively. Furthermore, based on the work function of Td-WTe2 material and the positional relationship between the bands of various wide-bandgap semiconductor materials, the prepared power devices exhibit different electrical characteristics, such as… Figure 5 As shown, devices fabricated with Td-WTe2 materials in conjunction with GaN and diamond exhibit good near-ohmic contact electrical transport characteristics, while devices fabricated with Td-WTe2 materials in conjunction with Ga2O3 and AlN exhibit the rectifying electrical characteristics of Schottky diodes, such as... Figure 6 As shown.

[0139] The difference between Examples 13 and 14 and Example 2 lies in the thickness of the metal electrode layer used, which is 100 μm and 150 μm, respectively. The fabricated power devices all exhibited good ohmic contact electrical transport characteristics, such as... Figure 7 As shown.

[0140] The difference between Example 15 and Example 6 lies in the type of ion implantation doping used on the semiconductor SiC substrate. B ions are used to form a highly doped P-type region with a doping concentration of 5 × 10⁻⁶. 19 cm-3 When using a two-dimensional layered metallic material with a high work function, 1T'-PtSe2, as the electrode contact for the P-type doped region, the work function of 1T'-PtSe2 is closer to that of SiC's valence band. This facilitates the electrical transport of hole carriers, resulting in power devices exhibiting near-ohmic contact electrical transport characteristics. Figure 7 As shown.

[0141] The technical solutions provided by the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A power device, characterized by, The power device comprises a semiconductor substrate and a two-dimensional metal material layer on at least one side surface of the semiconductor substrate. The two-dimensional metal material layer comprises at least one of Td phase tungsten ditelluride, 1T' phase molybdenum ditelluride, 1T phase platinum ditelluride and 1T' phase platinum diselenide. The thickness of the two-dimensional metal material layer is 9-51 nm.

2. The power device of claim 1, wherein, The power device comprises a semiconductor power device.

3. The power device of claim 1, wherein, The thickness of the two-dimensional metal material layer is 10-50 nm.

4. The power device of claim 3, wherein, The thickness of the two-dimensional metal material layer is 13-17 nm.

5. A power device according to any one of claims 1 to 4, c h a r a c t e r i z e d in that The semiconductor substrate and the two-dimensional metal material layer have van der Waals force.

6. The power device according to any one of claims 1 to 4, wherein The semiconductor substrate comprises a wide bandgap semiconductor material.

7. The power device of claim 6, wherein, The wide bandgap semiconductor material comprises at least one of silicon carbide, gallium nitride, aluminum nitride, gallium oxide and diamond.

8. The power device of claim 1, wherein, The power device further comprises an electrode layer for connecting with external elements, which is stacked on the side of the two-dimensional metal material layer away from the semiconductor substrate.

9. The power device of claim 8, wherein, The thickness of the electrode layer is 100-200 μm.

10. The power device of claim 1, wherein, The semiconductor substrate is provided with a doped region on the side close to the two-dimensional metal material layer.

11. The power device of claim 10, wherein, The doped region is an N-type doped region.

12. The power device of claim 11, wherein, The N-type doped region includes nitrogen ions, and the nitrogen ion concentration of the doped region is greater than or equal to 5 x 1018cm-3. 19 cm -3 .

13. The power device of claim 10, wherein, The doped region is a P-type doped region.

14. The power device of claim 13, wherein, The P-type doped region includes boron ions, and the boron ion concentration of the doped region is greater than or equal to 5 x 1018cm-3. 19 cm -3 .

15. A method of manufacturing a power device as claimed in any one of claims 1 to 14, characterized in that The preparation method comprises: providing a semiconductor substrate; providing a two-dimensional metal material layer on at least one side surface of the semiconductor substrate to obtain a power device.

16. The method of producing a power device according to Claim 15, wherein One side of the semiconductor substrate is provided with a doped region, and the two-dimensional metal material layer is provided on the side of the semiconductor substrate provided with the doped region.

17. The method of producing a power device according to Claim 16, wherein The step of providing a two-dimensional metal material layer on at least one side surface of the semiconductor substrate comprises: providing a bulk two-dimensional metal material; adopting a micromechanical exfoliation method to exfoliate the two-dimensional metal material from the bulk two-dimensional metal material to obtain the two-dimensional metal material layer; providing the obtained two-dimensional metal material layer on the semiconductor substrate.

18. The method of producing a power device according to Claim 17, wherein The step of providing a two-dimensional metal material layer on at least one side surface of the semiconductor substrate comprises: adopting a vapor deposition method to prepare the two-dimensional metal material layer; providing the obtained two-dimensional metal material layer on the semiconductor substrate.

19. The production method according to claim 17 or 18, wherein The step of providing the obtained two-dimensional metal material layer on the semiconductor substrate comprises: providing an organic adhesive film on the two-dimensional metal material layer, providing the two-dimensional metal material layer on the surface of the semiconductor substrate through the organic adhesive film, and removing the organic adhesive film.

20. The production method according to claim 19, wherein The step of removing the organic adhesive film comprises: placing the two-dimensional metal material layer and the semiconductor substrate connected through the organic adhesive film in an organic solvent and soaking at 50-80°C for 10-20 min.

21. The production method according to claim 20, wherein The preparation method further comprises: after removing the organic adhesive film, annealing the stacked two-dimensional metal material layer and semiconductor substrate at a temperature less than or equal to 200°C.

22. The preparation method according to claim 15, characterized in that, After providing the two-dimensional metal material layer on the semiconductor substrate and before obtaining the power device, the preparation method further comprises forming an electrode layer on the side of the two-dimensional metal material layer away from the semiconductor substrate by using an evaporation deposition method.

23. An electronic device, comprising: The electronic device comprises the power device according to any one of claims 1 to 14 or the power device prepared by the preparation method according to any one of claims 15 to 21.

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