A semiconductor integrated device and a method for manufacturing the same

Abstract

The application discloses a semiconductor integrated device and a preparation method thereof. The preparation method comprises the following steps: providing a substrate, and sequentially forming a channel layer and a barrier layer on the substrate, wherein the substrate comprises at least two device partitions, and the at least two device partitions comprise a first device partition and a second device partition; forming a first p-type cap layer located in the first device partition and a second p-type cap layer located in the second device partition on a side of the barrier layer away from the channel layer; forming a passivation layer on a side of the first p-type cap layer and the second p-type cap layer away from the barrier layer; etching the passivation layer to form a first through hole opposite to the first p-type cap layer; performing hydrogen treatment on the first p-type cap layer through the first through hole; and forming a first gate located in the first device partition on a side of the passivation layer away from the barrier layer, wherein the first gate is in contact with the first p-type cap layer through the first through hole. The preparation method can perform hydrogen treatment on the first p-type cap layer and improve the stability of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor integrated device and a preparation method thereof. BACKGROUND

[0002] In the development history of semiconductor power switching devices, the third generation of wide bandgap semiconductor materials have attracted widespread attention due to their superior physical properties. These materials, especially gallium nitride (GaN), have shown great potential in high-performance power conversion and modulation due to their high electron mobility, wide bandgap width, high critical breakdown field strength, and electron saturation drift speed. These characteristics of GaN materials provide significant advantages in designing high-performance power switching devices, especially in the production of high electron mobility transistors (HEMTs).

[0003] GaN monolithic integration refers to the realization of a complete functional system including logic gate circuits, drive circuits, and power switches on the same GaN wafer. This integration method takes full advantage of the high electron mobility, high breakdown field strength, and high temperature resistance of GaN materials, providing a revolutionary solution for the next generation of high-frequency, high-power density electronic systems. This all-GaN integrated system will exhibit outstanding performance advantages, with switching speeds up to 10 times that of silicon-based devices, operating temperature ranges extending to 300℃, power density increasing by 5-10 times, and excellent radiation resistance, making it particularly suitable for high-end application fields such as aerospace, 5G / 6G communication base stations, and new energy vehicles. With breakthroughs in manufacturing technology and continuous optimization of processes, all-GaN monolithic integrated systems are expected to revolutionize computing systems in extreme environments and high-frequency power conversion applications.

[0004] In the prior art, when preparing an integrated device control circuit, an etching method is often used to form two types of gate structures with inconsistent threshold values, such as forming a MISHEMT device by etching a p-GaN layer. This structure formed by etching cannot avoid the etching damage caused by the etching process, including physical damage, chemical damage, and ultraviolet damage, which forms a high-density interface state at the interface after etching, affecting the stability of the device at high frequencies. SUMMARY

[0005] The present application provides a semiconductor integrated device and a preparation method thereof. The preparation method of the semiconductor integrated device can only target the first p-type cap layer for hydrogen treatment through the first via, without affecting the surface state of the barrier layer, and can ensure the quality of the first p-type cap layer, reduce etching damage, and improve the stability of the device.

[0006] To achieve the above-mentioned purpose, the present application provides the following technical solutions:

[0007] A method for manufacturing a semiconductor integrated device, comprising:

[0008] forming a channel layer and a barrier layer successively on a substrate, the substrate comprising at least two device partitions, the at least two device partitions comprising a first device partition and a second device partition;

[0009] forming a first p-type cap layer in the first device partition and a second p-type cap layer in the second device partition on a side of the barrier layer facing away from the channel layer;

[0010] forming a passivation layer on a side of the first and second p-type cap layers facing away from the barrier layer;

[0011] etching the passivation layer to form a first via hole opposite to the first p-type cap layer, a projection of the first via hole on the substrate being located within a projection of the first p-type cap layer on the substrate;

[0012] performing hydrogen treatment on the first p-type cap layer through the first via hole;

[0013] forming a first gate in the first device partition on a side of the passivation layer facing away from the barrier layer, the first gate being in Schottky contact with the first p-type cap layer in the first device partition through the first via hole.

[0014] Optionally, forming a first p-type cap layer in the first device partition and a second p-type cap layer in the second device partition on a side of the barrier layer facing away from the channel layer comprises:

[0015] forming a layer of p-type semiconductor material on the side of the barrier layer facing away from the channel layer;

[0016] forming a gate metal layer on a side of the layer of p-type semiconductor material facing away from the barrier layer;

[0017] etching the gate metal layer to form a second gate in the second device partition;

[0018] etching the layer of p-type semiconductor material to form the first and second p-type cap layers, the second gate being in Schottky contact with the second p-type cap layer in the second device partition.

[0019] Optionally, after forming a first gate in the first device partition on a side of the passivation layer facing away from the barrier layer, the method further comprises:

[0020] etching the passivation layer to form a second via hole opposite to the second p-type cap layer, a projection of the second via hole on the substrate being located within a projection of the second p-type cap layer on the substrate;

[0021] forming a second gate in the second device partition on a side of the passivation layer away from the barrier layer, the second gate being in Schottky contact with the second p-type cap layer in the second device partition where the second gate is located through the second via hole.

[0022] Optionally, forming a passivation layer on a side of the first p-type cap layer and the second p-type cap layer away from the barrier layer, comprising:

[0023] forming a first passivation layer on a side of the first p-type cap layer and the second p-type cap layer away from the barrier layer;

[0024] etching the first passivation layer and the barrier layer to form a first recess and a second recess in the first device partition, and to form a third recess and a fourth recess in the second device partition, the first recess and the second recess being arranged on two sides of the first p-type cap layer, and the third recess and the fourth recess being arranged on two sides of the second p-type cap layer;

[0025] forming a source-drain metal layer on a side of the first passivation layer away from the barrier layer, and etching the source-drain metal layer to form a first source at the first recess, a first drain at the second recess, a second source at the third recess, and a second drain at the fourth recess;

[0026] performing a heat treatment on the first source, the first drain, the second source, and the second drain, the first source, the first drain, the second source, and the second drain being in ohmic contact with the barrier layer and the channel layer at an interface therebetween;

[0027] forming a second passivation layer on a side of the first passivation layer away from the barrier layer, the second passivation layer and the first passivation layer constituting the passivation layer.

[0028] Optionally, after forming the first passivation layer on a side of the first p-type cap layer and the second p-type cap layer away from the barrier layer, comprising:

[0029] forming a device isolation structure between two adjacent device partitions, the device isolation structure being configured to insulate the channel layer and the barrier layer on the two adjacent device partitions from each other.

[0030] The present application also provides a semiconductor integrated device, which is manufactured by using any of the above-mentioned semiconductor integrated device manufacturing methods, comprising:

[0031] a substrate comprising at least two device regions, the at least two device regions comprising a first device region and a second device region;

[0032] a channel layer located on a side of the substrate;

[0033] a barrier layer located on a side of the channel layer facing away from the substrate;

[0034] a first p-type cap layer and a second p-type cap layer located on a side of the barrier layer facing away from the channel layer, the first p-type cap layer being located within the first device region, the second p-type cap layer being located within the second device region, a hydrogen content in the first p-type cap layer being greater than a hydrogen content in the second p-type cap layer;

[0035] a passivation layer located on a side of the first and second p-type cap layers facing away from the barrier layer, the passivation layer having a first via opposite the first p-type cap layer, a footprint of the first via on the substrate being located within a footprint of the first p-type cap layer on the substrate;

[0036] a first gate located on a side of the passivation layer facing away from the barrier layer and within the first device region, the first gate being in Schottky contact with the first p-type cap layer within the first device region through the first via.

[0037] Optionally, further comprising a second gate located between the passivation layer and the second p-type cap layer, and the second gate being located within the second device region, the second gate being in Schottky contact with the second p-type cap layer within the second device region.

[0038] Optionally, the passivation layer further has a second via opposite the second p-type cap layer, a footprint of the second via on the substrate being located within a footprint of the second p-type cap layer on the substrate;

[0039] Further comprising a second gate located on a side of the passivation layer facing away from the barrier layer and within the second device region, the second gate being in Schottky contact with the second p-type cap layer within the second device region through the second via.

[0040] Optionally, the passivation layer comprises a first passivation layer and a second passivation layer;

[0041] the first passivation layer being located on a side of the first and second p-type cap layers facing away from the barrier layer;

[0042] the second passivation layer being located on a side of the first passivation layer facing away from the barrier layer;

[0043] A first source, a first drain, a second source and a second drain are further included between the second passivation layer and the channel layer, the first source, the first drain, the second source and the second drain penetrating through the first passivation layer and the barrier layer, and the barrier layer being in ohmic connection with the first source, the first drain, the second source and the second drain at the interface between the barrier layer and the channel layer;

[0044] The first source and the first drain are located in the first device partition and are arranged on the two sides of the first p-type cap layer respectively;

[0045] The second source and the second drain are located in the second device partition and are arranged on the two sides of the second p-type cap layer respectively.

[0046] Optionally, a device isolation structure is further included between two adjacent device partitions.

[0047] The device isolation structure is used to insulate the channel layer and the barrier layer on two adjacent device partitions.

[0048] The application provides a semiconductor integrated device and a preparation method thereof. In the preparation method, after a first p-type cap layer and a second p-type cap layer are formed on one side of a barrier layer away from a channel layer, a passivation layer is formed, then the passivation layer is etched to form a first through hole opposite to the first p-type cap layer, then the first p-type cap layer is subjected to hydrogen treatment through the first through hole, and then a first gate is directly formed on the side of the passivation layer away from the barrier layer, and the first gate is in Schottky contact with the first p-type cap layer through the first through hole. Compared with the related art, in the above preparation method, the first p-type cap layer and the second p-type cap layer are simultaneously formed on the barrier layer, and the first p-type cap layer is only subjected to targeted hydrogen treatment through the first through hole, so that the etching damage to the barrier layer is reduced, the hydrogen treatment is not needed for the barrier layer, the surface state of the barrier layer is not affected, after the hydrogen treatment of the first p-type cap layer, no other film layer needs to be deposited and etched, and the first gate in contact with the first p-type cap layer is directly formed, so that the time interval and the manufacturing steps between the hydrogen treatment and the formation of the first gate are reduced, the H ions in the first p-type cap layer after the hydrogen treatment are prevented from diffusing out, the manufacturing quality of the first p-type cap layer is ensured, the etching damage to the first p-type cap layer is reduced, and the stability of the device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0049] Figure 1 FIG. 1 is a structural schematic diagram of a gallium nitride monolithic integrated device in the related art;

[0050] Figure 2 FIG. 2 is a structural schematic diagram of another integrated device in the related art;

[0051] Figure 3 A flow chart of a preparation method of a semiconductor integrated device provided by an embodiment of the present application is shown in FIG. 1.

[0052] Figures 4 to 17 A preparation schematic diagram of a semiconductor integrated device provided by an embodiment of the present application is shown in FIG. 2.

[0053] Figure 18 A structure schematic diagram of a semiconductor integrated device provided by an embodiment of the present application is shown in FIG. 3.

[0054] Figure 19 A structure schematic diagram of a semiconductor integrated device provided by an embodiment of the present application is shown in FIG. 4.

[0055] Figure 20 A structure schematic diagram of a semiconductor integrated device provided by an embodiment of the present application is shown in FIG. 5.

[0056] Figure 21 A transfer characteristic curve diagram of a second semiconductor device provided by an embodiment of the present application is shown in FIG. 6.

[0057] Figure 22 A transfer characteristic curve diagram of a first semiconductor device provided by an embodiment of the present application is shown in FIG. 7.

[0058] Figure 23 A threshold voltage distribution diagram provided by an embodiment of the present application is shown in FIG. 8.

[0059] Icon:

[0060] 1-substrate; E1-first device partition; E2-second device partition; 2-channel layer; 21-first channel layer; 22-second channel layer; 3-barrier layer; 31-first barrier layer; 32-second barrier layer; 41-first p-type cap layer; 42-second p-type cap layer; 5-gate metal layer; 51-second gate; 6-passivation layer; 61-first passivation layer; 62-second passivation layer; 601-first via hole; 7-first gate; 81-first source; 82-first drain; 83-second source; 84-second drain; 9-planar layer; 101-first electrode; 102-second electrode; 103-third electrode; 104-connection part; H1-first semiconductor device; H2-second semiconductor device; J-photoresist; X-device isolation structure. DETAILED DESCRIPTION

[0061] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0062] In the related art, Figure 1 is a schematic diagram of a structure of a gallium nitride monolithic integrated device integrating an E-mode device A and a D-mode device B, which specifically includes a substrate 011, a GaN layer 012, an AlGaN layer 013, a p-GaN layer 014, a source-drain metal layer, a gate metal layer, a gate dielectric layer, and the like.

[0063] The gate metal layer includes a first gate 015 in the E-mode device and a second gate 016 in the D-mode device. The second gate 016 in the D-mode device is physically damaged, chemically damaged, and ultraviolet damaged during etching of the p-GaN layer 014, which causes a high interface state at the second gate, and the fast switching of charge causes instability of the overall integrated device. In addition, the gate dielectric layer 017 has interface states with the AlGaN layer 013 and defects such as in-growth traps, which cause carrier trapping / emission and other device degradation problems when a gate voltage is applied.

[0064] Another integrated device structure in the related art can be as shown in Figure 2 . Figure 2 The integrated device in the structure includes a substrate 021, a GaN layer 022, an AlGaN layer 023, a p-GaN layer, a first passivation layer 028, a second passivation layer 029, and a gate metal layer. The p-GaN layer is etched to form a first p-GaN gate 024 and a second p-GaN gate 025, and the gate metal layer is etched to form a first gate 026 and a second gate 027. In this structure, etching of the p-GaN layer does not affect the interface between the second p-GaN gate 025 and the AlGaN layer 023, and no gate dielectric layer is provided.

[0065] However, etching to form the first passivation layer 028 exposes a portion of the AlGaN layer 023 and the second p-GaN gate 025. The etching process is accompanied by damage to the interface between the AlGaN layer 023 and the second p-GaN gate 025. In addition, after etching the first passivation layer 028, the exposed AlGaN layer 023 and the second p-GaN gate 025 are subjected to in-situ plasma hydrogen treatment. The hydroxyl groups on the surface after hydrogen treatment will form H2O with H plasma and hang on the interface surface in the form of H bonds. The trimethylaluminum (TMA) used in the subsequent deposition (ALD) film needs to react with the hydroxyl groups to form Al-O bonds. The low hydroxyl concentration on the surface makes it easy for TMA to accumulate on the surface of the AlGaN layer 023 by physical adsorption, which will affect its overall surface state and lead to device instability. In addition, after hydrogen treatment of the second p-GaN gate 025, multiple layers of film need to be deposited. After etching these multiple layers of film, the second gate 027 that contacts the second p-GaN gate 025 is formed. Thus, there are many steps between hydrogen treatment of the second p-GaN gate 025 and the formation of the second gate 027. After hydrogen treatment, H ions in the second p-GaN gate 025 are prone to escape outward, affecting the quality of the second p-GaN gate 025.

[0066] To address the aforementioned technical problems, this invention provides a method for fabricating a semiconductor integrated device, such as... Figure 3 As shown, it includes:

[0067] S301: A channel layer and a barrier layer are sequentially formed on a substrate, the substrate including at least two device partitions, the at least two device partitions including a first device partition and a second device partition.

[0068] like Figure 4 As shown, a channel layer 2 and a barrier layer 3 are sequentially formed on a substrate 1. The barrier layer 3 and the channel layer 2 form a heterostructure. A two-dimensional electron gas (2DEG) is generated at the interface between the barrier layer 3 and the channel layer 2. The substrate 1 has a first device partition E1 and a second device partition E2. The number of first device partitions E1 can be at least one, and the specific number of second device partitions E2 can be at least one. The number of first device partitions E1 and second device partitions E2 is not limited here and depends on the actual situation.

[0069] S302: A first p-type cap layer located within a first device partition and a second p-type cap layer located within a second device partition are formed on the side of the barrier layer away from the channel layer; as shown Figure 5 As shown, a first p-type cap layer 41 and a second p-type cap layer 42 are formed on the barrier layer 3. Each first device partition E1 may have a first p-type cap layer 41, and each second device partition E2 may have a second p-type cap layer 42.

[0070] S303: forming a passivation layer on the side of the first p-type cap layer and the second p-type cap layer away from the barrier layer; as shown in Figure 6 The passivation layer 6 is formed on the first p-type cap layer 41 and the second p-type cap layer 42.

[0071] S304: etching the passivation layer to form a first via hole opposite to the first p-type cap layer, the orthographic projection of the first via hole on the substrate is located within the orthographic projection of the first p-type cap layer on the substrate.

[0072] S305: hydrogen treatment is performed on the first p-type cap layer through the first via hole; as shown in Figure 7 The first via hole 601 is formed on the passivation layer 6, and the first p-type cap layer 41 is subjected to hydrogen treatment through the first via hole 601. The hydrogen content in the first p-type cap layer 41 is greater than that in the second p-type cap layer 42 after the hydrogen treatment.

[0073] S306: forming a first gate in the first device partition on the side of the passivation layer away from the barrier layer, the first gate is in Schottky contact with the first p-type cap layer in the first device partition where the first gate is located through the first via hole; as shown in Figure 8 A first metal layer can be formed on the passivation layer 6, and the first gate 7 is formed on the side of the passivation layer 6 away from the barrier layer 3 by etching the first metal layer. Each first device partition E1 can have one first gate 7, and the first gate 7 is in contact with the first p-type cap layer 41 in the first device partition where the first gate 7 is located.

[0074] The preparation method of the semiconductor integrated device provided in the embodiment of the present application comprises the following steps: forming a first p-type cap layer 41 and a second p-type cap layer 42 on one side of a barrier layer 3 away from a channel layer 2, then forming a passivation layer 6, and then etching the passivation layer 6 to form a first through hole 601 opposite to the first p-type cap layer 41, and then performing hydrogen treatment on the first p-type cap layer 41 through the first through hole 601, and then forming a first gate 7 on one side of the passivation layer 6 away from the barrier layer 3, and the first gate 7 is in Schottky contact with the first p-type cap layer 41 through the first through hole 601. Compared with the related art, in the preparation method, the first p-type cap layer 41 and the second p-type cap layer 42 are simultaneously formed on the barrier layer 3, and the hydrogen treatment is only performed on the first p-type cap layer 41 through the first through hole 601, so that the etching damage to the barrier layer 3 is reduced, and the hydrogen treatment is not needed to be performed on the barrier layer 3, so that the surface state of the barrier layer 3 is not affected. In addition, after the hydrogen treatment is performed on the first p-type cap layer 41, no other film layer needs to be deposited and etched, and the first gate 7 in contact with the first p-type cap layer 41 is directly formed, so that the time interval and the manufacturing steps between the hydrogen treatment and the formation of the first gate 7 are reduced, the H ions in the first p-type cap layer 41 after the hydrogen treatment are prevented from diffusing out, the manufacturing quality of the first p-type cap layer 41 is ensured, the etching damage to the first p-type cap layer 41 is reduced, and the stability of the device is improved.

[0075] In the embodiment of the present application, the material of the channel layer 2 can be a III-V compound, for example, the material of the channel layer 2 is GaN; the material of the barrier layer 3 is a III-V compound, for example, the material of the barrier layer 3 can be AlGaN; the materials of the first p-type cap layer 41 and the second p-type cap layer 42 are p-type III-V compounds, for example, the materials of the first p-type cap layer 41 and the second p-type cap layer 42 can be p-GaN, and the p-type GaN uses Mg as a dopant. Alternatively, the materials of the channel layer 2, the barrier layer 3, and the first p-type cap layer 41 and the second p-type cap layer 42 can also be other materials, which are not limited herein and are determined according to actual conditions.

[0076] Specifically, one semiconductor device can be formed on each device partition of the substrate 1, and the semiconductor integrated device can comprise a first semiconductor device formed on the first device partition E1 and a second semiconductor device formed on the second device partition E2; wherein the first semiconductor device can comprise the above-mentioned channel layer 2, barrier layer 3, first p-type cap layer 41 and first gate 7 located on the first device partition E1, and the second semiconductor device can comprise the above-mentioned channel layer 2, barrier layer 3 and second p-type cap layer 42 located on the second device partition E2. Since the first p-type cap layer 41 is subjected to hydrogen treatment, and the second p-type cap layer 42 is not subjected to hydrogen treatment, the threshold voltage of the first semiconductor device can be different from the threshold voltage of the second semiconductor device.

[0077] Specifically, in the case that no voltage is applied to the second p-type cap layer 42 of the second semiconductor device, the second p-type cap layer 42 can absorb the two-dimensional electron gas generated at the interface between the barrier layer 3 and the channel layer 2, so that the second semiconductor device is an enhancement-mode (E-mode) device; and the first p-type cap layer 41 of the first semiconductor device is subjected to hydrogen treatment, so that hydrogen elements enter the first p-type cap layer 41, the hydrogen elements and the Mg doping in the first p-type cap layer form Mg-H bonds, thereby causing the material of the first p-type cap layer 41 to be deactivated, achieving the effect of negatively shifting the threshold voltage of the first semiconductor device, and after the hydrogen content in the first p-type cap layer reaches a certain concentration, the first semiconductor device can be a depletion-mode (D-mode) device.

[0078] In the embodiment of the present application, before the channel layer 2 and the barrier layer 3 are sequentially formed on the substrate 1 in step S301, the nucleation layer and the buffer layer are sequentially formed on the substrate 1. Specifically, in step S301, the substrate 1 has a nucleation layer, a buffer layer, a channel layer 2 and a barrier layer 3 sequentially stacked thereon. Among them, the nucleation layer provides a surface suitable for the growth of subsequent materials, which helps to form a high-quality crystal structure, and the buffer layer can alleviate the lattice mismatch between the substrate 1 and the channel layer 2, reduce stress and defects, and the buffered material can be AlGaN.

[0079] In the embodiment of the present application, the first p-type cap layer located in the first device partition and the second p-type cap layer located in the second device partition are formed on the side of the barrier layer away from the channel layer in step S302, and the specific steps can include:

[0080] S3021: Forming a whole layer of p-type semiconductor material layer 4 on the side of the barrier layer 3 away from the channel layer 2.

[0081] S3022: Forming a gate metal layer 5 on the side of the p-type semiconductor material layer 4 away from the barrier layer 3, as shown in Figure 9 .

[0082] S3023: Etching the gate metal layer 5 to form a second gate 51 located in the second device partition E2, as shown in Figure 10 .

[0083] Specifically, the gate metal layer 5 is etched by a low-damage etching method to form the second gate 51, and each second device partition E2 can have one second gate 51, which can reduce the etching damage to the p-type semiconductor material layer and improve the stability of the device. Among them, the low-damage etching method can be: etching 90% of the thickness direction of the gate metal layer 5 by dry etching, and then etching the remaining 10% of the thickness direction of the gate metal layer 5 by wet etching, to avoid the etching damage to the p-type semiconductor material layer caused by dry etching.

[0084] S3024: etching the p-type semiconductor material layer 4 to form the first p-type cap layer 41 and the second p-type cap layer 42, and the second gate 51 is in Schottky contact with the second p-type cap layer 42 in the second device partition E2 where the second gate is located.

[0085] As shown in Figure 11 , a layer of photoresist J can be formed on the side of the p-type semiconductor material layer 4 away from the barrier layer 3, the patterns of the first p-type cap layer 41 and the second p-type cap layer 42 are formed by etching with the photoresist J as a mask, and then the photoresist J is removed.

[0086] In the above preparation method, the p-type semiconductor material layer 4 and the gate metal layer 5 are sequentially formed on the side of the barrier layer 3 away from the channel layer 2, the first p-type cap layer 41, the second p-type cap layer 42 and the second gate 51 in Schottky contact with the second p-type cap layer 42 are formed by etching, and the manufacturing method is simple and saves manufacturing steps.

[0087] In the embodiment of the present application, the second gate can also be formed after the first gate 7 is formed, depending on the actual situation. That is, after the first gate in the first device partition is formed on the side of the passivation layer away from the barrier layer, the specific steps can include:

[0088] S3071: etching the passivation layer 6 to form a second through hole opposite to the second p-type cap layer 42, and the orthographic projection of the second through hole on the substrate 1 is located within the orthographic projection of the second p-type cap layer 42 on the substrate 1;

[0089] S3072: forming the second gate in the second device partition E2 on the side of the passivation layer 6 away from the barrier layer 3, and the second gate is in Schottky contact with the second p-type cap layer 42 in the second device partition E2 where the second gate is located through the second through hole. For example, a second metal layer is formed on the side of the passivation layer 6 away from the barrier layer 3, and the second gate is formed by etching the second metal layer on the side of the passivation layer 6 away from the barrier layer 3. The second gate corresponds to the second device partition one by one.

[0090] In the above preparation method, the second gate is formed after the first gate 7 is formed, and the first p-type cap layer 41 can not be etched and damaged when the second gate is manufactured, which can ensure the stability of the whole semiconductor device.

[0091] In the embodiment of the present application, the passivation layer is formed on the side of the first p-type cap layer and the second p-type cap layer away from the barrier layer in step S303, and the specific steps can include:

[0092] S3031: forming a first passivation layer 61 on the side of the first p-type cap layer 41 and the second p-type cap layer 42 away from the barrier layer 3, as shown in Figure 12

[0093] ​S3032: Etching the first passivation layer 61 and the barrier layer 3 to form a first recess and a second recess in the first device partition E1, and to form a third recess and a fourth recess in the second device partition E2, the first recess and the second recess being arranged on two sides of the first p-type cap layer, and the third recess and the fourth recess being arranged on two sides of the second p-type cap layer.

[0094] S3033: Forming a source-drain metal layer on the side of the first passivation layer 61 away from the barrier layer 3, and etching the source-drain metal layer to form a first source 81 at the first recess, a first drain 82 at the second recess, a second source 83 at the third recess, and a second drain 84 at the fourth recess, as shown in Figure 13 .

[0095] S3034: Heat treating the first source 81, the first drain 82, the second source 83, and the second drain 84, so that the first source 81, the first drain 82, the second source 83, and the second drain 84 are ohmic connected to the interface between the barrier layer 3 and the channel layer 2.

[0096] S3035: Forming a second passivation layer 62 on the side of the first passivation layer 61 away from the barrier layer 3, the second passivation layer 62 and the first passivation layer 61 forming the passivation layer 6, as shown in Figure 14 .

[0097] In the above preparation method, the first passivation layer 61 is first formed on the side of the first p-type cap layer 41 and the second p-type cap layer 42 away from the barrier layer 3, and then the first source 81, the first drain 82, the second source 83, and the second drain 84 are formed, so as to protect the first p-type cap layer and the second p-type cap layer from being damaged by etching. Furthermore, the second passivation layer 62 is formed after the first source 81, the first drain 82, the second source 83, and the second drain 84 are formed, so that the second passivation layer 62 can protect the first source 81, the first drain 82, the second source 83, and the second drain 84, thereby improving the stability of the device. Each first device partition E1 has a group of first sources 81 and first drains 82, and each second device partition E2 has a group of second sources 83 and second drains 84.

[0098] In the embodiment of the application, after the first passivation layer is formed on the side of the first p-type cap layer and the second p-type cap layer away from the barrier layer in step S3031, the method can further include: forming a device isolation structure X between adjacent two device partitions, the device isolation structure X being used to insulate the channel layer 2 and the barrier layer 3 on the adjacent two device partitions.

[0099] The device isolation structure X can make the channel layer 2, the barrier layer 3, the first p-type cap layer 41, the first source electrode 81, the first drain electrode 82 and the first gate electrode 7 in the first device partition E1 form a first semiconductor device, and the channel layer 2, the barrier layer 3, the second p-type cap layer 42, the second source electrode 83, the second drain electrode 84 and the second gate electrode 51 in the second device partition E2 form a second semiconductor device, as shown in Figure 15 and Figure 16 .

[0100] In the manufacturing method, the device isolation structure X is formed between the two adjacent device partitions, and the device isolation structure X can make the channel layer 2 and the barrier layer 3 on the two adjacent device partitions be insulated, and further make the two adjacent semiconductor devices be insulated. The two adjacent semiconductor devices can be of the same structure or different structure, which is not limited here and is determined according to the actual situation.

[0101] In addition, in the manufacturing method, the at least two semiconductor devices can be formed by the film layer same-layer manufacturing method, which can save manufacturing steps and manufacturing cost.

[0102] Specifically, as shown in Figure 17 , the channel layer 2, the barrier layer 3, the first p-type cap layer 41, the first source electrode 81, the first drain electrode 82 and the first gate electrode 7 in the first device partition E1 can form a first semiconductor device H1, and the threshold voltage of the first semiconductor device H1 can be negative, so that the first semiconductor device H1 is a depletion type device; the channel layer 2, the barrier layer 3, the second p-type cap layer 42, the second source electrode 83, the second drain electrode 84 and the second gate electrode 51 in the second device partition E2 can form a second semiconductor device H2, and the threshold voltage of the second semiconductor device H2 can be positive, so that the second semiconductor device H2 is an enhancement type device; since the device isolation structure X is arranged between the first semiconductor device H1 and the second semiconductor device H2, the first semiconductor device H1 and the second semiconductor device H2 can be insulated and do not affect each other, thereby improving the device stability.

[0103] In the embodiment of the application, the device isolation structure X can be an ion implantation region formed on the channel layer 2, the barrier layer 3 and the first passivation layer 61, as shown in Figure 15 and Figure 16 , which is simple in structure and easy to manufacture; or the device isolation structure X can also be a groove formed by etching the channel layer 2, the barrier layer 3 and the first passivation layer 61, as shown in Figure 17 , which is simple in structure and easy to manufacture.

[0104] The aforementioned device isolation structure X is formed after the formation of the first passivation layer 61, and can protect the barrier layer 3, the first p-type cap layer 41, and the second p-type cap layer 42. Specifically, the device isolation structure X can be fabricated after the formation of the first passivation layer 61 and before etching the first passivation layer 61, such as... Figure 15 and Figure 16 As shown; or the device isolation structure X can be fabricated after the formation of the second passivation layer 62 and before the etching of the passivation layer 6, as shown. Figure 6 As shown; or, the device isolation structure X can be fabricated after the first gate 7 is formed, as shown. Figure 17 As shown. There are no restrictions on the step in which the device isolation structure X is fabricated; it can be determined based on the specific circumstances.

[0105] Specifically, the device isolation structure X can also make other epitaxial film layers on two adjacent device partitions insulated from each other. For example, it can separate the nucleation layer and the buffer layer on two adjacent device partitions so that the nucleation layer and the buffer layer on two adjacent device partitions are insulated from each other.

[0106] In this embodiment of the application, after forming the first gate located within the first device partition on the side of the passivation layer away from the barrier layer, step S306 may specifically include:

[0107] S3081: A planarization layer 9 is formed on the side of the first gate 7 away from the passivation layer 6;

[0108] S3082: An electrode layer is formed on the side of the planarization layer 9 opposite to the first gate 7. The electrode layer includes a connection portion 104. The first semiconductor device H1 and the second semiconductor device H2 are connected through the connection portion 104 to form a semiconductor integrated device, such as... Figure 19 As shown.

[0109] In the above manufacturing method, the electrode layer can connect at least one first semiconductor device H1 and at least one second semiconductor device H2 to achieve the integration of at least two semiconductor devices. The operation is simple and easy to manufacture.

[0110] Specifically, such as Figure 18As shown in the figure, the semiconductor integrated device can include a first semiconductor device H1 and a second semiconductor device H2, the first semiconductor device H1 is a depletion mode device, and the second semiconductor device H2 is an enhancement mode device; the electrode layer can include a first electrode 101, a second electrode 102, a third electrode 103, and a connecting portion 104, the first electrode 101 can be ohmically connected with a first drain 82 of the first semiconductor device H1, the second electrode 102 can be ohmically connected with a second source 83 of the second semiconductor device H2, the third electrode 103 is ohmically connected with a second gate 51 of the second semiconductor device H2, and a first source 81 and a first gate 7 of the first semiconductor device H1 and a second drain 84 of the second semiconductor device H2 are connected through the connecting portion 104, so as to realize the integration of the first semiconductor device H1 and the second semiconductor device H2.

[0111] Specifically, after the hydrogen treatment of the first p-type cap layer 41 through the first via hole 601 in step S305, the second p-type cap layer 42 in the second semiconductor device H2 can have a lower intrinsic hydrogen concentration, such as 1*10 18 The device with this structure has a positive threshold voltage; the hydrogen treatment of the first p-type cap layer 41 in the first semiconductor device H1 can increase the hydrogen concentration to more than 1*10 19 The size of the Mg-H bond can cause the threshold voltage of the first semiconductor device H1 to be negative. The integration of the above two devices with positive and negative threshold voltages can form a complete functional system including logic gate circuits, drive circuits, and power switches.

[0112] The application also provides a semiconductor integrated device made by any of the preparation methods of the semiconductor integrated device provided in the above technical solutions, such as Figure 19 and Figure 20 As shown in the figure, the semiconductor integrated device can include:

[0113] a substrate 1, the substrate 1 includes at least two device partitions, and the at least two device partitions include a first device partition E1 and a second device partition E2;

[0114] a channel layer 2 located on one side of the substrate 1;

[0115] a barrier layer 3 located on a side of the channel layer 2 away from the substrate 1, and a two-dimensional electron gas is formed at the interface between the barrier layer 3 and the channel layer 2;

[0116] a first p-type cap layer 41 and a second p-type cap layer 42 located on a side of the barrier layer 3 away from the channel layer 2, the first p-type cap layer 41 is located in the first device partition E1, the second p-type cap layer 42 is located in the second device partition E2, and the hydrogen content in the first p-type cap layer 41 is greater than the hydrogen content in the second p-type cap layer 42;

[0117] The passivation layer 6 is located on the side of the first p-type cap layer 41 and the second p-type cap layer 42 away from the barrier layer 3, and has a first through hole opposite to the first p-type cap layer 41, and a normal projection of the first through hole on the substrate 1 is located within a normal projection of the first p-type cap layer 41 on the substrate 1.

[0118] The first gate 7 is located on the side of the passivation layer 6 away from the barrier layer 3 and in the first device partition E1, and the first gate 7 is in Schottky contact with the first p-type cap layer 41 in the first device partition E1 through the first through hole.

[0119] In the semiconductor integrated device provided by the embodiment of the present application, after the first p-type cap layer 41 and the second p-type cap layer 42 are formed on the side of the barrier layer 3 away from the channel layer 2, the passivation layer 6 is formed, then the passivation layer 6 is etched to form the first through hole 601 opposite to the first p-type cap layer 41, then the first p-type cap layer 41 is treated by hydrogen through the first through hole 601, and then the first gate 7 is directly formed on the side of the passivation layer 6 away from the barrier layer 3, and the first gate 7 is in Schottky contact with the first p-type cap layer 41 through the first through hole 601. Compared with the related art, in the preparation method, the first p-type cap layer 41 and the second p-type cap layer 42 are simultaneously formed on the barrier layer 3, and the first p-type cap layer 41 is treated by hydrogen through the first through hole 601, which can reduce the etching damage to the barrier layer 3, and the barrier layer 3 does not need to be treated by hydrogen, so that the surface state of the barrier layer 3 is not affected. In addition, after the first p-type cap layer 41 is treated by hydrogen, other film layers do not need to be deposited and etched, and the first gate 7 in contact with the first p-type cap layer 41 is directly formed, which can reduce the time interval and the preparation steps between the two steps of hydrogen treatment and first gate 7 formation, can avoid the diffusion of H ions in the first p-type cap layer 41 after hydrogen treatment, and thus can ensure the preparation quality of the first p-type cap layer 41, reduce the etching damage to the first p-type cap layer 41, and improve the stability of the device.

[0120] In the embodiment of the present application, the second gate 51 is located between the passivation layer 6 and the second p-type cap layer 42, and the second gate 51 is located in the second device partition E2, and the second gate 51 is in Schottky contact with the second p-type cap layer 42 in the second device partition E2.

[0121] Optionally, the second gate can not be arranged between the passivation layer 6 and the second p-type cap layer 42, but arranged on the side of the passivation layer 6 away from the barrier layer 3.

[0122] Specifically, the passivation layer also has a second via opposite to the second p-type cap layer 42, and the orthogonal projection of the second via on the substrate is located within the orthogonal projection of the second p-type cap layer 42 on the substrate; the semiconductor integrated device also includes a second gate located on the side of the passivation layer away from the barrier layer 3, and the second gate is located in the second device partition E2, and the second gate makes Schottky contact with the second p-type cap layer 42 in the second device partition E2 through the second via.

[0123] In this embodiment of the invention, the passivation layer 6 includes a first passivation layer 61 and a second passivation layer 62; the first passivation layer 61 is located on the side of the first p-type cap layer 41 and the second p-type cap layer 42 that are away from the barrier layer 3; the second passivation layer 62 is located on the side of the first passivation layer 61 that is away from the barrier layer 3.

[0124] Specifically, the semiconductor integrated device also includes a first source 81, a first drain 82, a second source 83, and a second drain 84 located between the second passivation layer 62 and the channel layer 2. The first source 81, the first drain 82, the second source 83, and the second drain 84 penetrate the first passivation layer 61 and the barrier layer 3. The interface between the barrier layer 3 and the channel layer 2 is ohmically connected to the first source 81, the first drain 82, the second source 83, and the second drain 84. The first source 81 and the first drain 82 are located within the first device partition E1 and are spaced apart on both sides of the first p-type cap layer 41. The second source 83 and the second drain 84 are located within the second device partition E2 and are spaced apart on both sides of the second p-type cap layer 42.

[0125] In this embodiment of the invention, the semiconductor integrated device further includes a device isolation structure X located between two adjacent device partitions; the device isolation structure X is used to ensure that the channel layer 2 and the barrier layer 3 on the two adjacent device partitions are insulated from each other.

[0126] Specifically, the device isolation structure X can be an ion implantation region formed on at least the channel layer 2, the barrier layer 3, and the first passivation layer 61; or, the device isolation structure X can be a trench formed by etching at least the channel layer 2, the barrier layer 3, and the first passivation layer 61.

[0127] Specifically, such as Figure 20 As shown, the device isolation structure X can isolate the channel layer 2 into a first channel layer 21 located in the first device partition E1 and a second channel layer 22 located in the second device partition E2, which are insulated from each other. The first channel layer 21 and the second channel layer 22 are insulated from each other. The device isolation structure X can also isolate the barrier layer 3 into a first barrier layer 31 located in the first device partition E1 and a second barrier layer 32 located in the second device partition E2, which are insulated from each other.

[0128] The first channel layer 21, the first barrier layer 31, the first p-type cap layer 41, the first source 81, the first drain 82 and the first gate 7 located in the first device partition E1 form a first semiconductor device, and the threshold voltage of the first semiconductor device can be negative; the second channel layer 22, the second barrier layer 32, the second p-type cap layer 42, the second source 83, the second drain 84 and the second gate 51 located in the second device partition E2 form a second semiconductor device, and the threshold voltage of the second semiconductor device can be positive.

[0129] As shown in the embodiment of the present application, Figure 20 The semiconductor integrated device further includes a planar layer 9 and an electrode layer, the planar layer 9 is located on the side of the first gate 7 away from the passivation layer 6, and the electrode layer is located on the side of the planar layer 9 away from the first gate 7, the electrode layer includes a first electrode 101, a second electrode 102, a third electrode 103 and a connecting part 104, the first electrode 101 can be ohmically connected with the first drain 82 of the first semiconductor device H1, the second electrode 102 can be ohmically connected with the second source 83 of the second semiconductor device H2, the third electrode 103 is ohmically connected with the second gate 51 of the second semiconductor device H2, and the first source 81 and the first gate 7 of the first semiconductor device H1 and the second drain 84 of the second semiconductor are connected through the connecting part 104, so as to realize the integration of the first semiconductor device H1 and the second semiconductor device H2.

[0130] In actual application, the characteristics of the semiconductor integrated device provided by the embodiment of the present application are detected, as shown in Figure 21 , which is a transfer characteristic curve diagram of the second semiconductor device H2, as shown in Figure 22 , which is a transfer characteristic curve diagram of the first semiconductor device H1, as shown in Figure 23 , which is the threshold voltage distribution of the first semiconductor device H1 and the second semiconductor device H2, wherein the threshold voltage V th is the current of the device ds The voltage that makes the device open when reaching 0.1 mA / mm. As can be seen from Figures 21 to 23 , the threshold voltage of the first semiconductor device H1 is negative, and the distribution range is between-2.83 and-2.07 V, and the threshold voltage of the second semiconductor device H2 is positive, and the distribution range is between 1.22 and 1.44 V.

[0131] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application belong to the scope of the claims of the present application and the equivalent technology thereof, the present application also intends to include these modifications and variations.

Claims

1. A method of manufacturing a semiconductor integrated device, characterized by, The method comprises the following steps: forming a channel layer and a barrier layer on a substrate in sequence, the substrate comprising at least two device partitions, the at least two device partitions comprising a first device partition and a second device partition; forming a first p-type cap layer in the first device partition and a second p-type cap layer in the second device partition on a side of the barrier layer away from the channel layer; forming a passivation layer on a side of the first p-type cap layer and the second p-type cap layer away from the barrier layer after forming the first p-type cap layer and the second p-type cap layer; etching the passivation layer to form a first via hole opposite to the first p-type cap layer, a projection of the first via hole on the substrate being located within a projection of the first p-type cap layer on the substrate; performing hydrogen treatment on the first p-type cap layer through the first via hole; forming a first gate in the first device partition and extending into the first via hole on a side of the passivation layer away from the barrier layer after performing hydrogen treatment on the first p-type cap layer, the first gate being in Schottky contact with the first p-type cap layer in the first device partition through the first via hole; forming a passivation layer on a side of the first p-type cap layer and the second p-type cap layer away from the barrier layer comprises: forming a first passivation layer on a side of the first p-type cap layer and the second p-type cap layer away from the barrier layer; etching the first passivation layer and the barrier layer to form a first recess and a second recess in the first device partition and to form a third recess and a fourth recess in the second device partition, the first recess and the second recess being arranged on two sides of the first p-type cap layer, and the third recess and the fourth recess being arranged on two sides of the second p-type cap layer; forming a source-drain metal layer on a side of the first passivation layer away from the barrier layer, and etching the source-drain metal layer to form a first source at the first recess, a first drain at the second recess, a second source at the third recess, and a second drain at the fourth recess; performing heat treatment on the first source, the first drain, the second source, and the second drain, the first source, the first drain, the second source, and the second drain being in ohmic contact with interfaces of the barrier layer and the channel layer; forming a second passivation layer on a side of the first passivation layer away from the barrier layer, the second passivation layer and the first passivation layer forming the passivation layer.

2. The production method according to claim 1, characterized by, forming a first p-type cap layer in the first device partition and a second p-type cap layer in the second device partition on a side of the barrier layer away from the channel layer comprises: forming an integral p-type semiconductor material layer on a side of the barrier layer away from the channel layer; forming a gate metal layer on a side of the p-type semiconductor material layer away from the barrier layer; etching the gate metal layer to form a second gate in the second device partition; etching the p-type semiconductor material layer to form the first p-type cap layer and the second p-type cap layer, the second gate being in Schottky contact with the second p-type cap layer in the second device partition.

3. The preparation method according to claim 1, characterized in that, forming a first gate in the first device partition on a side of the passivation layer away from the barrier layer, the first gate being in Schottky contact with the first p-type cap layer in the first device partition through the first via; etching the passivation layer to form a second via opposite the second p-type cap layer, a footprint of the second via on the substrate being within a footprint of the second p-type cap layer on the substrate; forming a second gate in the second device partition on a side of the passivation layer away from the barrier layer, the second gate being in Schottky contact with the second p-type cap layer in the second device partition through the second via.

4. The production method according to claim 1, characterized by, forming a first passivation layer on a side of the first and second p-type cap layers away from the barrier layer, the first passivation layer having a first via opposite the first p-type cap layer, a footprint of the first via on the substrate being within a footprint of the first p-type cap layer on the substrate; forming a device isolation structure between adjacent two of the device partitions, the device isolation structure being configured to insulate both the channel layer and the barrier layer on the adjacent two of the device partitions.

5. A semiconductor integrated device, characterized by comprising: a semiconductor integrated device fabricated by using a method as claimed in any one of claims 1-4, comprising: a substrate, the substrate comprising at least two device partitions, the at least two device partitions comprising a first device partition and a second device partition; a channel layer on a side of the substrate; a barrier layer on a side of the channel layer away from the substrate; first and second p-type cap layers on a side of the barrier layer away from the channel layer, the first p-type cap layer being in the first device partition, the second p-type cap layer being in the second device partition, a hydrogen content in the first p-type cap layer being greater than a hydrogen content in the second p-type cap layer; a passivation layer on a side of the first and second p-type cap layers away from the barrier layer, the passivation layer having a first via opposite the first p-type cap layer, a footprint of the first via on the substrate being within a footprint of the first p-type cap layer on the substrate; a first gate on a side of the passivation layer away from the barrier layer and in the first device partition, the first gate being in Schottky contact with the first p-type cap layer in the first device partition through the first via; the passivation layer comprising first and second passivation layers; the first passivation layer being on a side of the first and second p-type cap layers away from the barrier layer; the second passivation layer being on a side of the first passivation layer away from the barrier layer; further comprising first and second sources and first and second drains between the second passivation layer and the channel layer, the first and second sources and the first and second drains penetrating through the first passivation layer and the barrier layer, the barrier layer being in ohmic connection with the first and second sources and the first and second drains at an interface between the barrier layer and the channel layer; the first source and the first drain being in the first device partition and being disposed on two sides of the first p-type cap layer respectively; the second source and the second drain being in the second device partition and being disposed on two sides of the second p-type cap layer respectively.

6. The semiconductor integrated device according to claim 5, wherein A second gate is further included between the passivation layer and the second p-type cap layer, and the second gate is located in the second device region, and the second gate is in Schottky contact with the second p-type cap layer in the second device region where the second gate is located.

7. The semiconductor integrated device according to claim 5, wherein The passivation layer further has a second via hole opposite to the second p-type cap layer, and a projection of the second via hole on the substrate is located within a projection of the second p-type cap layer on the substrate; A second gate is further included on a side of the passivation layer away from the barrier layer, and the second gate is located in the second device region, and the second gate is in Schottky contact with the second p-type cap layer in the second device region where the second gate is located through the second via hole.

8. The semiconductor integrated device according to claim 5, wherein A device isolation structure is further included between two adjacent device regions. The device isolation structure is configured to insulate both the channel layer and the barrier layer on two adjacent device regions.

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