Backside gate cut formation

Abstract

The invention discloses backside gate cut formation, and provides a technique for forming an integrated circuit having adjacent pairs of semiconductor devices separated by a dielectric wall formed from a backside of a structure. Adjacent semiconductor devices each include a semiconductor region extending between a source region and a drain region and a gate structure extending over the semiconductor region of the adjacent semiconductor device. A dielectric wall may be present between each pair of adjacent semiconductor devices, thereby interrupting the gate structure. Each dielectric wall may be formed as a series of parallel lines throughout the integrated circuit, for example from the backside of the structure. A conductive link may extend through a given dielectric wall to electrically connect adjacent gate electrodes together. Other conductive links may also extend through dielectric walls in the source / drain trenches to connect adjacent source or drain contacts.

Description

Background Art

[0001] As integrated circuits scale down in size, numerous challenges arise. For example, reducing the size of memory and logic cells becomes increasingly difficult. Certain aspects of photolithography can impose physical limitations on how precisely certain structures can be aligned. Due to the high complexity of integrated circuit layouts, any etching process performed on the multiple materials on a given die creates potential points of failure for the device. Therefore, numerous significant challenges remain in the creation of such high-density semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure 1A and Figure 1B 1 is a diagram showing a gate trench of an integrated circuit according to an embodiment of the present disclosure ( Figure 1A ) and source / drain trenches ( Figure 1B ) having a series of dielectric walls formed from the back side of the structure.

[0003] Figure 2A and Figure 2B is a cross-sectional view illustrating a stage in an exemplary process for forming an integrated circuit having a series of dielectric walls formed from the backside of the structure according to an embodiment of the present disclosure.

[0004] Figure 3A and Figure 3B is a cross-sectional view illustrating another stage in an exemplary process for forming an integrated circuit having a series of dielectric walls formed from the backside of the structure according to an embodiment of the present disclosure.

[0005] Figure 4A and Figure 4B is a cross-sectional view illustrating another stage in an exemplary process for forming an integrated circuit having a series of dielectric walls formed from the backside of the structure according to an embodiment of the present disclosure.

[0006] Figure 5A and Figure 5B is a cross-sectional view illustrating another stage in an exemplary process for forming an integrated circuit having a series of dielectric walls formed from the backside of the structure according to an embodiment of the present disclosure.

[0007] Figure 6A and Figure 6B is a cross-sectional view illustrating another stage in an exemplary process for forming an integrated circuit having a series of dielectric walls formed from the backside of the structure according to an embodiment of the present disclosure.

[0008] Figure 7A and Figure 7Bis a cross-sectional view illustrating another stage in an exemplary process for forming an integrated circuit having a series of dielectric walls formed from the backside of the structure according to an embodiment of the present disclosure.

[0009] Figure 8A and Figure 8B is a cross-sectional view illustrating another stage in an exemplary process for forming an integrated circuit having a series of dielectric walls formed from the backside of the structure according to an embodiment of the present disclosure.

[0010] Figure 9A and Figure 9B is a cross-sectional view illustrating another stage in an exemplary process for forming an integrated circuit having a series of dielectric walls formed from the backside of the structure according to an embodiment of the present disclosure.

[0011] Figure 10A and Figure 10B is a cross-sectional view illustrating another stage in an exemplary process for forming an integrated circuit having a series of dielectric walls formed from the backside of the structure according to an embodiment of the present disclosure.

[0012] Figure 11A and Figure 11B is a cross-sectional view illustrating another stage in an exemplary process for forming an integrated circuit having a series of dielectric walls formed from the backside of the structure according to an embodiment of the present disclosure.

[0013] Figure 12A and Figure 12B is a cross-sectional view illustrating another stage in an exemplary process for forming an integrated circuit having a series of dielectric walls formed from the backside of the structure according to an embodiment of the present disclosure.

[0014] Figure 13A and Figure 13B is a cross-sectional view illustrating another stage in an exemplary process for forming an integrated circuit having a series of dielectric walls formed from the backside of the structure according to an embodiment of the present disclosure.

[0015] Figure 14A and Figure 14B is a cross-sectional view illustrating another stage in an exemplary process for forming an integrated circuit having a series of dielectric walls formed from the backside of the structure according to an embodiment of the present disclosure.

[0016] Figure 15A and Figure 15B is a cross-sectional view illustrating another stage in an exemplary process for forming an integrated circuit having a series of dielectric walls formed from the backside of the structure according to an embodiment of the present disclosure.

[0017] Figure 16A and Figure 16B is a cross-sectional view illustrating another stage in an exemplary process for forming an integrated circuit having a series of dielectric walls formed from the backside of the structure according to an embodiment of the present disclosure.

[0018] Figure 17A and Figure 17B is a cross-sectional view illustrating another stage in an exemplary process for forming an integrated circuit having a series of dielectric walls formed from the backside of the structure according to an embodiment of the present disclosure.

[0019] Figure 18A and Figure 18B is a cross-sectional view illustrating another stage in an exemplary process for forming an integrated circuit having a series of dielectric walls formed from the backside of the structure according to an embodiment of the present disclosure.

[0020] Figure 19A and Figure 19B is a cross-sectional view illustrating another stage in an exemplary process for forming an integrated circuit having a series of dielectric walls formed from the backside of the structure according to an embodiment of the present disclosure.

[0021] Figure 20A and Figure 20B is a cross-sectional view illustrating another stage in an exemplary process for forming an integrated circuit having a series of dielectric walls formed from the backside of the structure according to an embodiment of the present disclosure.

[0022] Figure 21 A cross-sectional view of a chip package containing one or more semiconductor dies according to some embodiments of the present disclosure is shown.

[0023] Figure 22 is a flow chart of a fabrication process for a semiconductor device having a series of dielectric walls formed from the backside of the structure according to an embodiment of the present disclosure.

[0024] Figure 23 A computing system including one or more integrated circuits as described herein is shown according to an embodiment of the present disclosure.

[0025] Although the following detailed description will be made with reference to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent in light of this disclosure. As will be further understood, the drawings are not necessarily drawn to scale or intended to limit the disclosure to the particular configurations shown. For example, although some of the figures generally indicate perfectly straight lines, right angles, and smooth surfaces, actual implementations of integrated circuit structures may have less than perfect straight lines and right angles (e.g., some features may have tapered sidewalls and / or rounded corners), and some features may have surface topologies or otherwise be non-smooth, given the practical limitations of the processing equipment and techniques used. DETAILED DESCRIPTION

[0026] Provided herein is a technique for forming an integrated circuit having adjacent pairs of semiconductor devices separated by a dielectric wall formed from the back side of the structure. The technique can be used in any number of integrated circuit applications and is particularly useful for logic and memory cells, such as those using finFETs or gate-all-around transistors (e.g., ribbon FETs and nanowire FETs). In one example, adjacent semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending above the semiconductor region of the adjacent semiconductor device. A dielectric wall (e.g., a gate cut) can be present between each pair of adjacent semiconductor devices, thereby interrupting the gate structure and isolating the gate of one semiconductor device from the gate of another semiconductor device. Multiple such dielectric walls can be formed, for example, from the back side of the structure as a series of parallel lines across the entire integrated circuit, or in one or more regions of the integrated circuit. In one embodiment, a conductive link can extend through a given dielectric wall to electrically connect adjacent gate electrodes together. Because the dielectric wall is formed from the back side, such a conductive link is formed along the bottom of the gate trench rather than along the top of the gate trench. Other conductive links may also be formed through the dielectric walls in the source / drain trenches to connect adjacent source or drain contacts.Many variations and embodiments will be apparent in light of this disclosure.

[0027] General Overview

[0028] As mentioned above, there are still many challenges in integrated circuit manufacturing that cannot be ignored. In more detail, a dielectric wall is sometimes provided between two adjacent semiconductor devices to isolate the first and second parts of the gate structure across each of the adjacent semiconductor devices. Therefore, the dielectric wall can be used to isolate the gates of the two devices from each other. Forming this specifically positioned structure may require many relatively complex mask and etching processes and may damage the integrity of the integrated circuit. Some dielectric walls can extend beyond a single gate trench to isolate multiple pairs of adjacent devices in different gate trenches. Electrically connecting the gates on either side of a given wall can be achieved using a conductive bridge that passes through the wall. However, the additional mask and etching processes used to form such a conductive bridge may cause damage to other positive-side transistor elements.

[0029] Therefore, and in accordance with embodiments of the present disclosure, techniques are provided herein for forming a grid of dielectric walls (e.g., a series of parallel dielectric walls) across an entire integrated circuit (or a portion thereof) from the back side of the structure rather than from the front side. According to some such examples, forming a dielectric wall between each device pair allows for a more simplified mask and etch process to form the dielectric wall from a variety of material types (e.g., the dielectric wall can be formed after forming the metal gate). Furthermore, the back side fabrication process of the dielectric wall allows for the formation of a conductive bridge (e.g., for linking adjacent gate electrodes in a gate trench or for linking adjacent source / source contacts in a source / drain trench) through selected dielectric walls without damaging other front side transistor structures. According to some embodiments, the dielectric wall between a given pair of adjacent devices can be etched back from the back side of the structure, and the back side recess can be plugged with a conductive material to bridge the gap between adjacent gate structures of adjacent devices. In this way, the conductive bridge is formed at or near the bottom of the gate trench, rather than at or near the top.

[0030] According to an embodiment, an integrated circuit includes: a first semiconductor device having a first semiconductor region extending in a first direction from a first source or drain region and a first gate electrode surrounding the first semiconductor region; and a second semiconductor device having a second semiconductor region extending in the first direction from a second source or drain region and a second gate electrode surrounding the second semiconductor region. The second semiconductor device is spaced apart from the first semiconductor device in a second direction different from the first direction. The integrated circuit also includes: a dielectric structure (one or more dielectric layers) located below the first gate electrode and the second gate electrode; a dielectric wall extending in the first direction between the first gate electrode and the second gate electrode and extending in a third direction along at least the entire height of the first gate electrode and the second gate electrode; and a conductive bridge extending through a bottom portion of the dielectric wall in the second direction and contacting the first gate electrode and the second gate electrode. According to an embodiment, the conductive bridge is located on the top surface of the dielectric structure.

[0031] According to another embodiment, an integrated circuit includes: a first semiconductor device having a first semiconductor region extending in a first direction from a first source or drain region and a first gate electrode surrounding the first semiconductor region; and a second semiconductor device having a second semiconductor region extending in the first direction from a second source or drain region and a second gate electrode surrounding the second semiconductor region. The second semiconductor device is spaced apart from the first semiconductor device in a second direction different from the first direction. The integrated circuit also includes: a first topside contact on a top surface of the first source or drain region and a second topside contact on a top surface of the second source or drain region; a first bottom contact on a bottom surface of the first source or drain region and a second bottom contact on a bottom surface of the second source or drain region; a dielectric wall extending in the first direction between the first gate electrode and the second gate electrode and between the first source or drain region and the second source or drain region; a first conductive bridge extending in a second direction through a bottom portion of the dielectric wall and contacting the first and second bottom contacts; and a second conductive bridge extending in the second direction through a top portion of the dielectric wall and contacting the first and second topside contacts.

[0032] According to another embodiment, an electronic device includes a chip package having one or more dies. At least one of the one or more dies includes: a first semiconductor region extending in a first direction from a first source or drain region; a second semiconductor region extending in a second direction from a second source or drain region, wherein the second semiconductor region is spaced apart from the first semiconductor region in a second direction different from the first direction; a gate electrode surrounding each of the first and second semiconductor regions; a dielectric structure (one or more dielectric layers) below the gate electrode; and a dielectric wall between the first and second semiconductor regions. A portion of the gate electrode extends through a bottom portion of the dielectric wall in the second direction, such that the portion of the gate electrode is located on a top surface of the dielectric structure.

[0033] According to another embodiment, a method of forming an integrated circuit includes: forming a first fin including a first semiconductor material and a second fin including a second semiconductor material, the first fin and the second fin extending above a substrate, and each fin extending parallel to each other in a first direction; forming a first source or drain region at an end of the first fin, and forming a second source or drain region at an end of the second fin; forming a gate electrode, which extends over the first fin and the second fin in a second direction different from the first direction; removing the substrate from the back side of the integrated circuit; after removing the substrate, forming a recess between the first semiconductor material and the second semiconductor material from the back side through the entire thickness of the gate electrode, the recess further extending in the first direction between the first source or drain region and the second source or drain region; forming a dielectric material within the recess; recessing a portion of the dielectric material between the first semiconductor material and the second semiconductor material; forming a conductive material on the dielectric material, the conductive material being within the recess and contacting the gate electrode; and forming a dielectric layer on the conductive material.

[0034] The technology can be used for any type of non-planar transistor, including finFETs (sometimes called double-gate transistors or tri-gate transistors), or nanowire, nanosheet, and nanoribbon transistors (sometimes called gate-all-around transistors), to name a few examples. The source and drain regions can be epitaxial regions deposited, for example, during the etching and replacement source / drain formation process. The type of dopant in the source and drain regions will depend on the polarity of the corresponding transistor. The source and drain regions can be any epitaxial diffusion regions. The gate structure can be implemented using a gate-first process or a gate-last process (sometimes called a removed metal gate or RMG process). Any number of semiconductor materials can be used to form the transistors, such as Group IV materials (e.g., silicon, germanium, silicon germanium) or Group III-V materials (e.g., gallium arsenide, indium gallium arsenide).

[0035] The techniques and structures provided herein can be inspected using tools such as electron microscopy, including scanning / transmission electron microscopy (SEM / TEM), scanning transmission electron microscopy, nanobeam electron diffraction (NBD or NBED), and reflection electron microscopy (REM), to name a few suitable exemplary analytical tools; compositional mapping; x-ray crystallography or diffraction (XRD); energy dispersive x-ray spectroscopy (EDX); secondary ion mass spectrometry; time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) technology; 3D tomography; or high-resolution physical or chemical analysis. For example, in some exemplary embodiments, such tools can indicate the presence of one or more gate links or conductive bridges at or near the bottom of a gate trench between each adjacent pair of semiconductor devices of a given integrated circuit or between gate structures of one or more adjacent semiconductor devices. In some other examples, a conductive bridge can be observed extending through the dielectric wall between adjacent source / drain contacts within a source / drain trench. Such a conductive bridge may form a connection between the top side source / drain contacts, the back side source / source contacts, or both the top side and back side source / drain contacts of a given adjacent pair of source or drain regions.Many configurations and variations will be apparent in light of this disclosure.

[0036] It should be readily understood that the meaning of "above" and "over" in this disclosure should be interpreted in the broadest sense, such that "above" and "over" not only mean "directly on something," but also include being on something with an intermediate feature or layer therebetween. In addition, for ease of description, spatially relative terms (e.g., "under," "below," "lower," "above," "upper," "top," "bottom," etc.) may be used herein to describe the relationship of one element or feature to another element or feature shown in the figures. In addition to the orientations shown in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0037] As used herein, the term "layer" refers to a portion of a material including an area with a thickness. A monolayer is a layer consisting of a single layer of atoms of a given material. A layer may extend over the entire underlying or overlying structure, or may have a smaller range than the range of the underlying or overlying structure. In addition, a layer may be a region of a homogeneous or heterogeneous continuous structure, wherein the layer has a thickness smaller than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A layer may conform to a given surface (whether flat or curved) and have a relatively uniform thickness across the entire layer. A structure may include one or more layers. In some cases, one or more layers of a given structure may all be materials of the same electrical type (e.g., dielectric material, conductive material, or semiconductor material), although other exemplary structures may have a hybrid structure (a mixture of dielectric and conductive materials, such as a gate structure). In some cases, one or more layers of a given structure may be materials of the same electrical type but different in composition (e.g., a low-k dielectric material in a first layer and a high-k dielectric material in a second layer). The layers of a given structure may be arranged in a vertical manner (one layer stacked on top of another layer) and / or a horizontal manner (one layer laterally adjacent to another layer).

[0038] As used herein, "compositionally different" or "substantially different in composition" refers to two materials having different chemical compositions. This compositional difference can be, for example, due to an element in one material that is not in the other (e.g., SiGe is compositionally different from silicon), or due to one material having all of the same elements as the second material but at least one of these elements being intentionally provided in a different concentration in one material relative to the other (e.g., SiGe with 70 atomic percent germanium is compositionally different from SiGe with 25 atomic percent germanium). In addition to this chemical composition diversity, the materials can also have different dopants (e.g., gallium and magnesium), or have the same dopants but in different concentrations. In other embodiments, compositionally different materials can also refer to two materials having different crystal orientations. For example, (110) silicon is compositionally distinct from or different from (100) silicon. For example, blanket wafer layer transfer can be used to achieve stacks of different orientations. If two materials are elementally different, then one of the materials has an element that is not present in the other.

[0039] Architecture

[0040] Figure 1A and Figure 1B 1 shows gate trenches of a plurality of semiconductor devices 101a-101d according to some embodiments. Figure 1A ) and adjacent source / drain trenches ( Figure 1B ). Each of the semiconductor devices 101a-101d can be a non-planar metal oxide semiconductor (MOS) transistor, such as a tri-gate or gate all around (GAA) transistor, although other transistor topologies and types can also benefit from the techniques provided herein. The examples herein describe semiconductor devices having a GAA structure (e.g., having nanoribbons, nanowires, or nanosheets extending between source and drain regions).

[0041] As shown, semiconductor devices 101a-101d are formed on a base dielectric structure 102. Any number of semiconductor devices can be formed on or above base dielectric structure 102, but four are used here as an example. According to some embodiments, base dielectric structure 102 represents any number of dielectric layers on the backside of a semiconductor device that can be formed after removing the substrate from the backside of the structure. In some cases, dielectric structure 102 is a single layer of dielectric material. In other exemplary cases, dielectric structure 102 includes two or more different depositions of dielectric material, where each deposition can be the same dielectric material or a different dielectric material. In some such cases, seams can be seen between the same (or different) dielectric materials deposited at different times. The substrate can be, for example, a bulk substrate including a Group IV semiconductor material (e.g., silicon, germanium, or silicon germanium), a Group III-V semiconductor material (e.g., gallium arsenide, indium gallium arsenide, or indium phosphide), and / or any other suitable material on which transistors can be formed. Alternatively, the substrate can be a semiconductor-on-insulator substrate having the desired semiconductor layer above a buried insulator layer (e.g., silicon above silicon dioxide). Alternatively, the substrate can be a multilayer substrate or superlattice suitable for forming nanowires or nanoribbons (e.g., alternating layers of silicon and SiGe, or alternating layers of indium gallium arsenide and indium phosphide). Any number of substrates can be used. As described above, the substrate can be removed from the back side and replaced by one or more backside interconnect layers (including base dielectric structure 102) to provide backside power and signal routing. Base dielectric structure 102 can include any suitable dielectric material, such as silicon dioxide.

[0042] Each semiconductor device includes one or more nanoribbons 104 extending in a first direction (inside / outside of the page) between epitaxial source or drain regions 106. A gate structure comprising a gate electrode 107 and a gate dielectric 108 extends over the one or more nanoribbons 104 in a second direction (from left to right on the page, orthogonal to the first direction) to form a transistor gate. It should be noted that the one or more nanoribbons 104 of each device can also be fins in a tri-gate transistor design.

[0043] The semiconductor material used in each semiconductor device can be formed from a semiconductor substrate (which can subsequently be removed as discussed in more detail herein). As described above, one or more semiconductor regions of the device can include fins, which can be, for example, intrinsic to (formed from) the substrate itself, such as silicon fins etched from a bulk silicon substrate. Alternatively, the fins can be formed from material deposited on an underlying substrate. In one such exemplary case, a blanket layer of silicon germanium (SiGe) can be deposited on a silicon substrate and then patterned and etched to form a plurality of SiGe fins extending from the substrate. In further embodiments, the fins include alternating layers of material (e.g., alternating layers of silicon and SiGe) that facilitate the formation of nanowires and nanoribbons (e.g., nanoribbon 104 shown) during a gate formation process in which one type of alternating layer is selectively etched away to release another type of alternating layer in the channel region so that a gate all-around process can then be performed. Again, the alternating layers can be blanket deposited and then etched into fins or deposited in fin-shaped trenches.

[0044] Source or drain regions 106 may be formed at the ends of one or more nanoribbons 104 in each device and thus may be aligned with each other along the second direction within a common source / drain trench, e.g. Figure 1B As shown. Note that Figure 1B A source or drain region 106 is shown at a first end of the nanoribbon 104, and a similar source or drain region will be formed at the opposite end of the nanoribbon 104 in another source / drain trench on the other side of the gate trench. According to some embodiments, the source or drain region 106 is an epitaxial region provided at the end of the semiconductor region during an etching and replacement process. Any semiconductor material suitable for the source or drain region (e.g., Group IV and Group III-V semiconductor materials) can be used. The source or drain region 106 can include multiple layers, such as a liner and a capping layer, to increase contact resistance. In any such case, depending on the polarity of the transistor, the composition and doping of the source or drain region 106 can be the same or different. Any number of source or drain configurations and materials can be used.

[0045] As described above, the gate structure extends in the second direction over one or more nanoribbons 104 of various devices and includes both a gate electrode 107 and a gate dielectric 108. The gate electrode 107 can comprise any sufficiently conductive material, such as a metal, a metal alloy, or doped polysilicon. In some embodiments, the gate electrode 107 comprises one or more work function metals surrounding one or more semiconductor regions. In some embodiments, a p-channel device comprises a work function metal comprising titanium surrounding one or more semiconductor regions, while an n-channel device comprises a work function metal comprising tungsten surrounding one or more semiconductor regions. The gate electrode 107 can also include a fill metal or other conductive material (e.g., tungsten, ruthenium, molybdenum, or cobalt) surrounding the work function metal to provide a complete gate electrode structure. The gate dielectric 108 represents any number of dielectric layers present between the one or more nanoribbons 104 and the gate electrode 107. In some embodiments, a gate cap 110 extends over the gate electrode 107 along the top portion of the gate trench. The gate cap 110 can be any suitable dielectric material, such as silicon nitride or silicon oxynitride.

[0046] In some embodiments, one or more topside contacts 112 are provided to make electrical connections to the underlying source or drain regions 106. The topside contacts 112 can comprise any suitable conductive material, such as tungsten, ruthenium, molybdenum, or cobalt, to name a few examples. In the illustrated example, each source or drain region 106 includes a corresponding topside contact 112. However, in some embodiments, one or more source or drain regions 106 do not include a topside contact 112 and can instead have a dielectric material on their top surface. Similarly, any number of the source or drain regions 106 can include a backside contact 114 to make electrical connections below the corresponding source or drain region 106. The backside contact 114 can comprise any suitable conductive material, such as tungsten, ruthenium, molybdenum, or cobalt, to name a few examples. Any number of the source or drain regions 106 can also not have a backside contact and can instead have a dielectric plug 116 on the bottom surface of the source or drain region. The dielectric plug 116 may include any suitable dielectric material, such as silicon dioxide.

[0047] According to some embodiments, each gate structure is separated along the second direction by a different dielectric wall 118, which acts as a dielectric barrier between the gate structures. The dielectric wall 118 effectively isolates the gate structures from each other to form an electrically separated gate for each semiconductor device. In the example shown, three dielectric walls 118 are formed. The dielectric wall 118 can be formed of a sufficiently insulating material (e.g., a dielectric material). Exemplary materials for the dielectric wall 118 include silicon nitride, silicon oxide, or silicon oxynitride. In some embodiments, the dielectric wall 118 includes a dielectric liner and a dielectric filler on the dielectric liner. The dielectric liner can be a high-k dielectric material, such as silicon nitride, and the dielectric filler can be a low-k dielectric material, such as silicon dioxide or a flowable oxide. According to some embodiments, each dielectric wall 118 has a maximum width between about 10 nm and about 20 nm.

[0048] According to some embodiments, dielectric walls 118 extend across the gate trenches in a first direction (along the length of nanoribbon 104) and further extend along the source / drain trenches to isolate adjacent source or drain regions 106 from each other, as shown in FIG. Figure 1B As described above, the dielectric wall 118 separates all of the gate structures from each other along the second direction. In some applications, it may be necessary to connect two adjacent gate structures. Therefore, according to an embodiment, a gate link (e.g., a conductive bridge) 120 is connected between adjacent gate electrodes 107 below a given dielectric wall 118. The gate link 120 can be any suitable conductive material and can include the same conductive material as the gate electrode 107 (e.g., tungsten, ruthenium, molybdenum, or cobalt). According to some embodiments, only a portion of the dielectric wall 118 that extends across the gate trench is recessed from the back side to form the gate link 120. As described above, the gate link 120 is formed from the back side of the structure and is therefore located at the bottom of the gate trench. In some embodiments, the gate link 120 is located on the top surface of the base dielectric structure 102 that extends below the semiconductor device. In some embodiments, an imaginary plane extending along the first and second directions intersects the gate link 120 and the bottom-most nanoribbon 104 of each of the semiconductor devices 101a-101d. Figure 1A In the example shown, two gate links 120 are provided to connect the gates of each of the semiconductor devices 101 b , 101 c , and 101 d .

[0049] In a similar manner to the gate links 120, other conductive structures may be provided within the source / drain trenches to connect between adjacent source / drain contacts. According to some embodiments, two adjacent positive side contacts 112 may be connected using a positive side contact link 122 (e.g., a conductive bridge) extending above a given dielectric wall 118. The positive side contact link 122 may be any suitable conductive material and may include the same conductive material as the positive side contacts 112. Figure 1B In the example shown, positive side contact link 122 is used to connect positive side source / drain contacts of semiconductor devices 101 a and 101 b , and to connect positive side source / drain contacts of semiconductor devices 101 c and 101 d .

[0050] According to some embodiments, two adjacent backside contacts 114 may be connected using a backside contact link 124 (e.g., a conductive bridge) extending below a given dielectric wall 118. The backside contact link 124 may be any suitable conductive material and may include the same conductive material as the backside contacts 114. Figure 1B In the example shown, backside contact link 124 is used to connect backside source / drain contacts of semiconductor devices 101 c and 101 d .

[0051] It should be noted that gate link 120, front-side contact link 122, and back-side contact link 124 may exist only within their respective gate trenches or source / drain trenches, such that they do not extend further in the first direction to short the gate electrode to the source / drain contact. For example, according to some embodiments, gate link 120 between the gates of semiconductor devices 101 c and 101 d is electrically isolated from back-side contact link 124 between the back-side contacts of semiconductor devices 101 c and 101 d. According to some embodiments, a seam may exist between any of gate link 120, front-side contact link 122, and back-side contact link 124 and the adjacent conductive material of gate electrode 107, front-side contact 112, or back-side contact 114. In some examples, the seam may not be visible, such that the connector appears to be a continuous metal extending above or below a given dielectric wall 118.

[0052] Manufacturing method

[0053] Figures 2A-20A and Figure 2B-Figure 20B are cross-sectional views collectively illustrating an exemplary process for forming an integrated circuit constructed with a series of dielectric walls formed from the backside of the structure, according to an embodiment of the present disclosure. Figures 2A-20A shows a cutaway cross-sectional view of a gate trench of an integrated circuit, and Figure 2B-Figure 20BA cross-sectional view of a source / drain trench adjacent to a gate trench taken in the same direction is shown. Each figure shows an exemplary structure resulting from the process flow up to that point in time, so the depicted structure evolves as the process flow continues, ultimately forming Figure 20A and Figure 20B The structures shown are respectively Figure 1A and Figure 1B The architecture shown is similar to that shown. Such a structure may be part of an overall integrated circuit (e.g., such as a processor or memory chip) that includes, for example, digital logic cells and / or memory cells and analog mixed signal circuits. Thus, the integrated circuit structure shown may be part of a larger integrated circuit that includes other integrated circuits not shown. Exemplary materials and process parameters are given, but as will be understood, the present disclosure is not intended to be limited to any particular such materials or parameters. Figures sharing the same number (e.g., Figure 2A and Figure 2B ) shows different views of the structure at the same point in time during the process flow.

[0054] Figure 2A and Figure 2B A parallel cross-sectional view taken through a stack of alternating semiconductor layers on a semiconductor substrate 201 is shown. Figure 2A is taken from a portion of the stack that will eventually become the gate trench, and Figure 2B The section is taken from a portion of the stack that will eventually become source / drain trenches adjacent to and parallel to the gate trench. Alternating material layers can be deposited on a substrate 201 that includes sacrificial layers 202 alternating with semiconductor layers 204. The alternating layers are used to form a GAA transistor structure. Any number of alternating semiconductor layers 204 and sacrificial layers 202 can be deposited on the substrate 201.

[0055] For example, substrate 201 can be a bulk substrate comprising a Group IV semiconductor material (e.g., silicon, germanium, or silicon germanium), a Group III-V semiconductor material (e.g., gallium arsenide, indium gallium arsenide, or indium phosphide), and / or any other suitable material on which transistors can be formed. Alternatively, substrate 201 can be a semiconductor-on-insulator substrate having the desired semiconductor layer above a buried insulator layer (e.g., silicon above silicon dioxide). Alternatively, substrate 201 can be a multilayer substrate or superlattice suitable for forming nanowires or nanoribbons (e.g., alternating layers of silicon and SiGe, or alternating layers of indium gallium arsenide and indium phosphide). Any number of substrates can be used.

[0056] According to some embodiments, sacrificial layer 202 has a different material composition than semiconductor layer 204. In some embodiments, sacrificial layer 202 is silicon germanium (SiGe), while semiconductor layer 204 includes a semiconductor material suitable for use as a nanoribbon, such as silicon (Si), SiGe, germanium, or a III-V material such as indium phosphide (InP) or gallium arsenide (GaAs). In examples where SiGe is used in each of sacrificial layer 202 and semiconductor layer 204, the germanium concentration between sacrificial layer 202 and semiconductor layer 204 is different. For example, sacrificial layer 202 can include a higher germanium content than semiconductor layer 204. In some examples, semiconductor layer 204 can be doped with an n-type dopant (to create a p-channel transistor) or a p-type dopant (to create an n-channel transistor).

[0057] While the dimensions may vary from one exemplary embodiment to the next, the thickness of each sacrificial layer 202 may be between about 5 nm and about 20 nm. In some embodiments, the thickness of each sacrificial layer 202 is substantially the same (e.g., within 1-2 nm). The thickness of each semiconductor layer 204 may be about the same as the thickness of each sacrificial layer 202 (e.g., about 5-20 nm). Thickness herein refers to Figure 2A-2B Each of the sacrificial layer 202 and the semiconductor layer 204 can be deposited using any known or specialized material deposition technique, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0058] Figure 3A and Figure 3B and 3D respectively depict the process of forming a capping layer 301 and subsequently forming a fin under the capping layer 301 according to an embodiment. Figure 2A and Figure 2B . Capping layer 301 can be any suitable hard mask material, such as a carbon hard mask (CHM) or silicon nitride. Capping layer 301 is patterned into rows to form corresponding rows of fins from the alternating layer stack of sacrificial layer 202 and semiconductor layer 204. The rows of fins extend longitudinally in a first direction (e.g., into and out of the page of each cross-sectional view).

[0059] In accordance with some embodiments, the anisotropic etching process through the layer stack continues into at least a portion of substrate 201, wherein the unetched portion of substrate 201 beneath the fin forms a sub-fin region 302. The etched portion of substrate 201 may be filled with a dielectric filler 304, which acts as a shallow trench isolation (STI) between adjacent fins. Dielectric filler 304 may be any suitable dielectric material, such as silicon oxide, and may be recessed to a desired depth (in this exemplary case, down to around the upper surface of sub-fin region 302) as shown, thereby defining the active portion of the fin to be covered by the gate structure.

[0060] Figure 4A and Figure 4B respectively depicting the sacrificial gate 402 after formation according to some embodiments. Figure 3A and Figure 3B , the sacrificial gate 402 extends across the fin in a second direction different from the first direction. The sacrificial gate 402 may extend across the fin in a second direction orthogonal to the first direction. According to some embodiments, the sacrificial gate material is formed in parallel strips across the integrated circuit and is removed in all areas not protected by the gate mask layer. The sacrificial gate 402 may be any suitable material that can be selectively removed without damaging the semiconductor material of the fin. In some examples, the sacrificial gate 402 comprises polysilicon.

[0061] As shown in the cross-sectional view, the sacrificial gate 402 is Figure 4A The gate trench cross section in the fin extends across the fin, but along Figure 4B The source / drain trench cross section does not have a sacrificial gate 402. Figure 4B As shown, the sacrificial gate 402 (and any gate spacers formed on the sidewalls of the sacrificial gate 402) protects the underlying portion of the fin, while the exposed portion of the fin is etched away. According to some embodiments, both the semiconductor layer 204 and the sacrificial layer 202 are etched at substantially the same rate using an anisotropic RIE process. Figure 4B As shown, the RIE process removes both the fin and sub-fin 302 above substrate 201 . In some embodiments, the RIE process recesses sub-fin region 302 below the top surface of dielectric fill 304 .

[0062] According to some embodiments, the exposed portion of the sacrificial layer 202 along the edge of the gate spacer can be recessed, and the recess can be filled with an internal spacer material. The internal spacer material can be conformally deposited over the exposed ends of the fin and then etched back to fill the recess with the internal spacer while exposing the ends of the semiconductor layer 204.

[0063] Figure 5A and Figure 5B and FIG. 5 depicts the structure of the source / drain trenches after forming a sacrificial material 502 according to some embodiments. Figure 4A and Figure 4B . According to some embodiments, the source / drain trenches may be filled with a sacrificial material 502. The sacrificial material 502 may be any suitable material that can be subsequently easily removed without damaging any surrounding structures. In some examples, the sacrificial material 502 includes titanium nitride or aluminum oxide. After depositing the sacrificial material 502, it may be recessed to a final thickness such that the top surface of the sacrificial material 502 is substantially coplanar (e.g., within 2 nm) with the top surface of the dielectric filler 304.

[0064] According to some embodiments, sacrificial material 502 is located in areas where backside contact to the corresponding source or drain is required. It may be preferred that no backside contact to one or more source or drain regions is present. Therefore, according to some embodiments, one or more plugs of sacrificial material at the bottom of the source / drain trenches can be removed and replaced with dielectric plugs 504. Dielectric plugs 504 can be any suitable dielectric material, such as silicon dioxide. In some examples, dielectric plugs 504 have the same material composition as adjacent dielectric filler 304.

[0065] Figure 6A and Figure 6B Depicts forming source or drain regions 602 (extending into and out of) the ends of each fin, respectively, in accordance with some embodiments. Figure 6A After the page in Figure 5A and Figure 5B , a cross-sectional view of the structure shown in . In accordance with some embodiments, the source or drain regions 602 can be epitaxially grown from the exposed ends of the semiconductor layers 204 such that the materials grow together or otherwise merge toward the middle of the source / drain trenches between the fins. Note that the epitaxial growth on one semiconductor layer 204 can be fully or partially merged with the epitaxial growth on one or more other semiconductor layers 204 in the same vertical stack. The extent of any such merging can vary from one embodiment to the next. In the example of a PMOS device, a given source or drain region 602 can be a semiconductor material (e.g., a Group IV or Group III-V semiconductor material) having a higher dopant concentration of p-type dopants as compared to n-type dopants. In the example of an NMOS device, a given source or drain region 602 can be a semiconductor material (e.g., a Group IV or Group III-V semiconductor material) having a higher dopant concentration of n-type dopants as compared to p-type dopants. In accordance with some embodiments, the various source or drain regions 602 grown from different semiconductor devices can be aligned along the second direction, such as Figure 6BThe source or drain region 602 may be formed directly on the sacrificial material 502 and / or the dielectric plug 504 .

[0066] In accordance with some embodiments, a dielectric filler 604 is provided within the source / drain trenches and around the source or drain regions 602. In accordance with some embodiments, the dielectric filler 604 can extend between adjacent source or drain regions 602 along the second direction and can also extend upward and over each source or drain region 602. Thus, each source or drain region 602 can be isolated from any adjacent source or drain region 602 by the dielectric filler 604. The dielectric filler 604 can be any suitable dielectric material, although in some embodiments, the dielectric filler 602 includes the same dielectric material as the dielectric filler 304. In one example, both the dielectric filler 604 and the dielectric filler 304 include silicon dioxide. In accordance with some embodiments, the top surface of the dielectric filler 604 can be polished using, for example, chemical mechanical polishing (CMP). The top surface of the dielectric filler 604 can be polished until it is substantially coplanar with the top surface of the sacrificial gate 402.

[0067] Figure 7A and Figure 7B and FIG. 1 respectively depict the process of forming nanoribbons 702 from semiconductor layer 204 according to some embodiments. Figure 6A and Figure 6B , a cross-sectional view of the structure shown in . Depending on the size of the structure, the nanoribbon 702 can also be considered as a nanowire or nanosheet. The sacrificial gate 402 can be removed using any wet or dry isotropic process to expose the alternating layer stack of the fin in the trench that is left after removing the sacrificial gate 402. Once the sacrificial gate 402 is removed, the sacrificial layer 202 can also be removed using a selective isotropic etching process that removes the material of the sacrificial layer 202 but does not remove (or removes very little) the semiconductor layer 204 or any other exposed layer (e.g., an internal gate spacer). The sacrificial gate 402 and the sacrificial layer 202 can be removed together using the same isotropic etching process. At this point, the suspended (sometimes referred to as released) semiconductor layer 204 forms a nanoribbon 702 that extends in a first direction (into and out of the page) between the corresponding source or drain region 602 and the other source or drain regions on the opposite end of the nanoribbon 702.

[0068] Figure 8A and Figure 8B and FIG. 1 respectively depict the gate structure after forming the gate structure around the nanoribbon 702 in the gate trench according to some embodiments. Figure 7A and Figure 7B, a cross-sectional view of the structure shown in FIG. As described above, the gate structure includes a gate dielectric 802 and a gate electrode 804. The gate dielectric 802 can be conformally deposited around the nanoribbon 702 using any suitable deposition process, such as atomic layer deposition (ALD). The gate dielectric 802 can include any suitable dielectric, such as silicon dioxide and / or a high-k dielectric material. Examples of high-k dielectric materials include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to provide some examples. According to some embodiments, the gate dielectric 802 is hafnium oxide having a thickness between about 1 nm and about 5 nm. In some embodiments, the gate dielectric 802 can include one or more silicates, such as titanium silicate, tungsten silicate, niobium silicate, and other transition metal silicates. In some examples, the gate dielectric 802 can be a multilayer structure. For example, the gate dielectric 802 can include a first layer on the nanoribbon 702 and a second layer on the first layer. For example, the first layer can be an oxide of the semiconductor layer (e.g., silicon dioxide), and the second layer can be a high-k dielectric material (e.g., hafnium oxide). In some embodiments, when a high-k dielectric material is used, an annealing process can be performed on the gate dielectric 802 to improve its quality. In some embodiments, the high-k material can be nitrided to improve its aging resistance. The gate dielectric 802 can be formed on all exposed surfaces within the gate trench, including on the bottom of the gate trench (e.g., on the top surface of the sub-fin portion 302 and the dielectric filler 304).

[0069] The gate electrode 804 can be deposited on the gate dielectric 802 and can be any standard or dedicated conductive structure. In some embodiments, the gate electrode 804 includes doped polysilicon, a metal, or a metal alloy. Examples of suitable metals or metal alloys include aluminum, tungsten, cobalt, molybdenum, ruthenium, titanium, tantalum, copper, and their carbides and nitrides. For example, the gate electrode 804 may include one or more work function layers, resistance reduction layers, and / or barrier layers. For example, the work function layer may include a p-type work function material (e.g., titanium nitride) for a PMOS gate or an n-type work function material (e.g., titanium aluminum carbide) for an NMOS gate.

[0070] According to some embodiments, a top portion of gate electrode 804 is recessed within the gate trench, and the recess is filled with a dielectric material to form gate cap 806. Gate cap 806 may be any suitable dielectric material, such as silicon nitride.

[0071] In accordance with some embodiments, a topside conductive contact 808 is formed within the source / drain trenches and on the upper surface of the source or drain region 602. A top portion of the dielectric fill 604 can first be recessed until at least a top surface of the source or drain region 602 is exposed. The topside conductive contact 808 can then be formed within the recessed volume above the source or drain region 602. The topside conductive contact 808 can include any suitable conductive material, such as tungsten, ruthenium, cobalt, titanium, tantalum, molybdenum, or any alloy thereof. The top surface of the topside conductive contact 808 can be polished to be substantially coplanar with the top surface of the gate cap 806. Note that, as will be described in greater detail herein, the topside conductive contact 808 can be split into separate, isolated contacts above the corresponding source or drain region 602 using a dielectric wall.

[0072] Figure 9A and Figure 9B respectively depicting the back side after removing the substrate 201 according to some embodiments. Figure 10A and Figure 10B . The substrate 201 can be polished away via CMP or another grinding process to remove substrate material. According to some embodiments, the substrate 201 continues to be thinned, at least until the sacrificial material 502 is exposed from the backside of the source / drain trenches. In some examples, portions of the sub-fin region 302 and / or dielectric fill 304 can also be exposed from the backside of the gate trenches.

[0073] Figure 10A and Figure 10B and 1002 respectively depict the backside after removing the sub-fin region 302 and forming the base dielectric structure 1002 according to some embodiments. Figure 9A and Figure 9B . The exposed sub-fin region 302 can be removed using an appropriate isotropic semiconductor etching process or any other appropriate semiconductor etching process. The backside cavity left by removing the sub-fin region 302 can be filled with another dielectric material (e.g., the same dielectric material as the dielectric filler 304). Thus, the base dielectric structure 1002 can represent a combined dielectric structure of the dielectric filler 304 and the adjacent dielectric material. In some embodiments, after the dielectric etching process, the dielectric filler 304 is also removed from the back side, and a new dielectric layer is formed on the back side to form the base dielectric structure 1002. In any case, the newly deposited dielectric material on the back side of the structure can be polished to expose at least the bottom surface of the sacrificial material 502 and the dielectric plug 504 (if present).

[0074] Figure 11A and Figure 11Band 1102 respectively depict the back side contact portion 1102 after replacing the sacrificial material 502 according to some embodiments. Figure 10A and Figure 10B . The sacrificial material 502 can be selectively removed using any suitable isotropic etching process. The backside contact 1102 can include any of the same materials as the topside conductive contact 808 discussed above, and can be the same conductive material(s) as the topside conductive contact 808. The backside contact 1102 directly abuts the underside of the corresponding source or drain region 602. The bottom surface of the backside contact 1102 can be polished to be substantially coplanar with the bottom surface of the base dielectric structure 1002 and the dielectric plug 504 (if present).

[0075] Figure 12A and Figure 12B respectively depicting the back side trench recess 1202 after formation according to some embodiments. Figure 11A and Figure 11B , a cross-sectional view of the structure shown in FIG. According to some embodiments, a mask structure 1204 can be formed on the backside of the structure and photolithographically patterned to form trench openings through the mask structure 1202 at locations where backside trench recesses 1202 are to be formed. A RIE process can be used to etch through exposed material not protected by the mask structure 1204. According to some embodiments, the backside trench recesses 1202 are formed through the entire thickness of the base dielectric structure 1002 and through the entire thickness of the gate structure within the gate trench. Within the source / drain trenches, the backside trench recesses 1202 separate adjacent source or drain regions 602 while also etching through the conductive material of the topside conductive contacts 808 to isolate adjacent topside conductive contacts 808 above the corresponding source and drain regions 602. The backside trench recesses 1202 can have a high aspect ratio (e.g., an aspect ratio of 5:1 or higher, or 10:1 or higher).

[0076] Figure 13A and Figure 13B and FIG. 1 respectively depicts the steps after forming the dielectric liner 1302 according to some embodiments. Figure 12A and Figure 12B . A dielectric liner 1302 may be formed on all surfaces of the backside trench recess 1202. The dielectric liner 1302 may include any suitable dielectric material. In some examples, the dielectric liner 1302 includes a high-k dielectric material such as silicon nitride, aluminum oxide, or hafnium oxide. The dielectric liner 1302 may be deposited, for example, via CVD or ALD to provide a relatively thin (e.g., 1 nm to 6 nm thick) conformal layer.

[0077] Figure 14A and Figure 14Band respectively depict the following steps after forming the mask material 1402 according to some embodiments. Figure 13A and Figure 13B . A cross-sectional view of the structure shown in . Mask material 1402 can be any suitable sacrificial material that can be subsequently removed without damaging surrounding materials. In some examples, mask material 1402 is a carbon hard mask (CHM). Mask material 1402 can be formed within all backside trench recesses 1202 and on dielectric liner 1302. According to some embodiments, another backside mask structure 1404 is formed on the bottom surface of mask material 1402 and is patterned to provide openings through backside mask structure 1404 over areas where mask material 402 is to be removed. Backside mask structure 1404 can include any suitable hard mask material or photoresist that is selective to a subsequent etch that selectively removes unmasked portions of mask material 1402.

[0078] Figure 15A and Figure 15B and FIG. 1404 respectively depict the backside mask structure 1404 after removing the mask material 1402 from all areas not protected by the backside mask structure 1404, according to some embodiments. Figure 14A and Figure 14B In some examples, the mask material 1402 is removed from all portions of the backside trench recess 1202 within the gate trench (e.g., Figure 15A ), and may be removed from one or more portions of the backside trench recess 1202 within the source / drain trench (as shown in FIG. Figure 15B ). The exposed portions of the mask material 1402 may be removed using any suitable isotropic etching process. After removing the exposed portions of the mask material 1402, the backside mask structure 1404 may be removed (e.g., via an ashing process, if the mask structure 404 is a CHM).

[0079] Figure 16A and Figure 16B and 1402, respectively, after forming a dielectric filler 1602 within any exposed backside trench recess 1202 (eg, any recess not filled with mask material 1402), in accordance with some embodiments. Figure 15A and Figure 15B 1402 . Dielectric filler 1602 can be any suitable dielectric material. In some embodiments, dielectric filler 1602 is a normal-k or low-k dielectric material, such as silicon dioxide, porous silicon dioxide, or a flowable oxide. In some examples, the bottom surface of deposited dielectric filler 1602 is polished to be substantially coplanar with the bottom surface of mask material 1402.

[0080] Figure 17A and Figure 17Band 1702, respectively, after removing the mask material 1402 and forming the topside contact links 1702 within the backside trench recesses 1202, according to some embodiments. Figure 16A and Figure 16B . After removing the mask material 1402, the exposed portions of the dielectric liner 1302 (e.g., portions not covered by the dielectric filler 1602) are removed using any suitable isotropic etching process. Top side contact links 1702 can be formed at the top ends of the back side trench recesses 1202 and adjacent to the top side conductive contacts 808. Thus, the top side contact links 1702 provide an electrical connection between adjacent top side conductive contacts 808. The top side contact links 1702 can include any suitable conductive material, such as tungsten, or the same conductive material as the top side conductive contacts 808. According to some embodiments, the top side contact links 1702 are formed of a conductive material deposited within the back side trench recesses 1202 and recessed to a final thickness such that the bottom surface of the top side contact links 1702 is substantially coplanar with or above the bottom surface of the top side conductive contacts 808 (when such as Figure 17B In some other examples, the topside contact links 1702 are selectively grown from the exposed sides of the topside conductive contacts 808 at the top ends of the backside trench recesses 1202. Such selective growth can reduce the need for subsequent recess etching.

[0081] Figure 18A and Figure 18B and 1804, respectively, after forming another dielectric liner 1802 within the backside trench recess 1202 below the topside contact link 1702 and forming a dielectric filler 1804 on the dielectric liner 1804, according to some embodiments. Figure 17A and Figure 17B . The formation and properties of dielectric liner 1802 can be substantially the same as discussed above for dielectric liner 1302, and the formation and properties of dielectric filler 1804 can be substantially the same as discussed above for dielectric filler 1602. The bottom surface of dielectric filler 1804 can be polished to be substantially coplanar with the bottom surface of dielectric filler 1602. In accordance with some embodiments, a backside mask structure 1806 is formed on the bottom surfaces of dielectric filler 1602 and dielectric filler 1804 and is patterned to provide openings through backside mask structure 1806 over areas where backside conductive links are to be formed between adjacent gate structures or adjacent backside contacts. Backside mask structure 1806 can include any suitable hard mask material or photoresist.

[0082] Figure 19A and Figure 19B1 and 2 respectively depict the first backside recess 1902 through the gate trench and the second backside recess 1904 through the source / drain trench after forming the first backside recess 1902 through the gate trench and the second backside recess 1904 through the source / drain trench according to some embodiments. Figure 18A and Figure 18B , a cross-sectional view of the structure shown in . The RIE process can be used to etch away exposed material not protected by the backside mask structure 1806. In some examples, an isotropic etch can be performed to remove any portion of the dielectric liner 1302 within the first backside recess 1902 and / or any portion of the dielectric liner 1802 within the second backside recess 1904. According to some embodiments, the removal of the portion of the dielectric filler 1602 within the gate trench occurs at least until a bottom portion of the sidewall of the adjacent gate electrode 804 is exposed within the first backside recess 1902, for example Figure 19A In a similar manner, removal of portions of the dielectric fill 1804 within the source / drain trenches (and any other adjacent dielectric material) occurs until portions of the sidewalls of the adjacent backside conductive contact 1102 are exposed within the second backside recess 1904, e.g. Figure 19B In some embodiments, the second backside recess 1904 exposes sidewalls along the entire thickness of the adjacent backside conductive contact 1102 and may partially land on the source / drain region 602. After forming the first backside recess 1902 and the second backside recess 1904, the backside mask structure 1806 may be removed.

[0083] According to some embodiments, Figure 20A and Figure 20B 1902 and after forming a conductive gate link 2002 in the first backside recess 1902 and a backside contact link 2004 in the second backside recess 1904, respectively. Figure 19A and Figure 19B . Conductive gate link 2002 may include any suitable conductive material, such as tungsten or any of the conductive materials described above for gate electrode 804. In some examples, conductive gate link 2002 includes the same conductive material as gate electrode 804 (e.g., tungsten, ruthenium, molybdenum, titanium, tantalum, or cobalt). Backside contact link 2004 may include any suitable conductive material, such as tungsten or any of the materials described above for backside conductive contact 1102. In some examples, backside contact link 2004 includes the same conductive material as backside conductive contact 1102 (e.g., tungsten, ruthenium, molybdenum, titanium, tantalum, or cobalt).

[0084] Conductive material can be deposited within the first backside recess 1902 and the second backside recess 1904 and subsequently recessed to form the conductive gate link 2002 and the backside contact link 2004, respectively. In some examples, the conductive gate link 2002 has a bottom surface that is substantially coplanar with or within 5 nm of the bottom surface of the gate electrode 804. Similarly, in some examples, the backside contact link 2004 has a bottom surface that is substantially coplanar with or within 5 nm of the bottom surface of the backside conductive contact 1102. Other examples can be constructed differently, such as where the bottom surfaces of the gate electrode 804 and the backside conductive contact 1102 are lower than the bottom surfaces of the conductive gate link 2002 and the backside contact link 2004 (when a given integrated circuit structure such as Figure 20A-Figure 20B orientation shown).

[0085] According to some embodiments, dielectric filler 1602 and dielectric liner 1302 form dielectric walls within the gate trenches to separate adjacent gate structures and may extend into adjacent source / drain trenches to separate adjacent source or drain regions 602. Similarly, according to some embodiments, dielectric filler 1804 and dielectric liner 1802 form dielectric walls within the source / drain trenches to separate adjacent source or drain regions 602. Note that according to some examples, using top-side contact links 1702 and back-side contact links 2004 to connect between the top-side and back-side contacts of the same adjacent pair of source or drain regions 602 may reduce contact resistance to the source or drain regions 602.

[0086] According to some embodiments, the remaining portion of the first backside recess 1902 below the conductive gate link 2002 is filled with a dielectric filler 2006, and the remaining portion of the second backside recess 1904 below the backside contact link 2004 is filled with a dielectric filler 2008. Each of the dielectric filler 2006 and the dielectric filler 2008 can be any suitable dielectric material, such as silicon dioxide. In some embodiments, the bottom surfaces of the dielectric filler 2006 and the dielectric filler 2008 can be polished to be substantially coplanar with the bottom surface of the dielectric filler 1602 and / or the dielectric filler 1804. In some embodiments, after forming the dielectric filler 2006 and the dielectric filler 2008, the bottom of the structure is polished back until the bottom surface of the base dielectric structure 1002 is exposed.

[0087] Figure 21An exemplary embodiment of a chip package 2100 is shown. As shown, chip package 2100 includes one or more dies 2102. One or more dies 2102 may include at least one integrated circuit having a semiconductor device, such as any of the semiconductor devices disclosed herein. In some exemplary configurations, one or more dies 2102 may include any other circuitry for interfacing with other devices formed on the die or connected to chip package 2100.

[0088] As can be further seen, chip package 2100 includes a housing 2104 bonded to a package substrate 2106. Housing 2104 can be any standard or specialized housing and provides, for example, electromagnetic shielding and environmental protection for the components of chip package 2100. One or more dies 2102 can be conductively coupled to package substrate 2106 using connectors 2108, which can be implemented using any number of standard or specialized connection mechanisms, such as solder bumps, ball grid arrays (BGAs), pins, or wire bonds, to name a few. Package substrate 2106 can be any standard or specialized package substrate, but in some cases includes a dielectric material having conductive pathways (e.g., including conductive vias and lines) extending through the dielectric material between faces of package substrate 2106 or between different locations on each face. In some embodiments, package substrate 2106 can have a thickness of less than 1 mm (e.g., between 0.1 mm and 0.5 mm), but any number of package geometries can be used. Additional conductive contacts 2112 may be provided on the opposite side of the package substrate 2106 for conductive contact, for example, with a printed circuit board (PCB). One or more vias 2110 extend through the thickness of the package substrate 2106 to provide a conductive path between one or more connectors 2108 and one or more contacts 2112. For ease of illustration, the vias 2110 are shown as a single inline row through the package substrate 2106, but other configurations (e.g., inlays, dual inlays, through-silicon vias) may be used. In other embodiments, the vias 2110 are made from multiple smaller stacked vias or staggered at different locations throughout the package substrate 2106. In the illustrated embodiment, the contacts 2112 are solder balls (e.g., for bump-based connections or ball grid array arrangements), but any suitable package bonding mechanism (e.g., pins in a pin grid array arrangement, or pads in a pad grid array arrangement) may be used. In some embodiments, solder resist is provided between the contacts 2112 to prevent shorting.

[0089] In some embodiments, a molding material 2114 can be disposed around one or more dies 2102 included within the housing 2104 (e.g., as an underfill material between the die 2102 and the package substrate 2106, and as an overfill material between the die 2102 and the housing 2104). While the size and quality of the molding material 2114 can vary from one embodiment to the next, in some embodiments, the molding material 21114 has a thickness of less than 1 mm. Exemplary materials that can be used for the molding material 2114 include epoxy molding materials, as appropriate. In some cases, in addition to being electrically insulating, the molding material 2114 can also be thermally conductive.

[0090] Figure 22 is a flow chart of a method 2200 for forming at least a portion of an integrated circuit according to an embodiment. The various operations of the method 2200 may be performed in Figures 2A-20A and Figure 2B-Figure 20B . However, the correlation of the various operations of method 2200 with the specific components shown in the above figures is not intended to imply any structural and / or usage limitations. Instead, the above figures provide an exemplary embodiment of method 2200. Other operations may be performed before, during, or after any operation of method 2200. Other operations may be performed before, during, or after any operation of method 2200. For example, method 2200 does not explicitly describe the various processes performed to form a common transistor structure. Some operations of method 2200 may be performed in an order different from the order shown.

[0091] Method 2200 begins with operation 2202, wherein a plurality of parallel semiconductor fins comprising at least a first fin and a second fin are formed in accordance with some embodiments. The semiconductor material in the fins may be formed from a substrate such that the fins are an integral part of the substrate (e.g., etched from a bulk silicon substrate). Alternatively, the fins may be formed from a material deposited on an underlying substrate. In one such exemplary case, a blanket layer of silicon germanium (SiGe) may be deposited on a silicon substrate and then patterned and etched to form a plurality of SiGe fins extending from the substrate. In another such example, the fins include alternating layers of material (e.g., alternating layers of silicon and SiGe) that facilitate the formation of nanowires and nanoribbons during a gate formation process, wherein one type of alternating layer is selectively etched away to release another type of alternating layer within the channel region so that a gate all-around (GAA) process may be performed. The alternating layers may be blanket deposited and then etched into the fins, or deposited within fin-shaped trenches. The fins may further include a capping structure over each fin, the capping structure being used to define the position of the fin during, for example, an RIE process. The capping structure may be a dielectric material, such as silicon nitride.

[0092] According to some embodiments, a dielectric filler is formed around the sub-fin portion of the fin. In some embodiments, the dielectric filler extends between each pair of adjacent parallel fins and extends longitudinally in the same direction as the fins. In some embodiments, the anisotropic etching process that forms the fins also etches into a portion of the substrate and can form a dielectric filler within the recessed portion of the substrate. Thus, the dielectric filler acts as a shallow trench isolation (STI) between adjacent fins. The dielectric filler can be any suitable dielectric material, such as silicon dioxide.

[0093] Method 2200 continues with operation 2204, where a sacrificial gate and a spacer structure are formed over the fin. The sacrificial gate may be patterned using a gate mask layer in strips extending orthogonally over the fin (many gate mask layers and corresponding sacrificial gates may be formed parallel to each other (e.g., forming a cross-hatched pattern with the fin)). The gate mask layer may be any suitable hard mask material, such as CHM or silicon nitride. The sacrificial gate may be formed of any suitable material that may subsequently be selectively removed without damaging the semiconductor material of the fin. In one example, the sacrificial gate comprises polysilicon. The spacer structure may be deposited and then etched back such that the spacer structure remains primarily only on the sidewalls of any exposed structure, such as the sidewalls of the sacrificial gate. According to some embodiments, the spacer structure may be any suitable dielectric material, such as silicon nitride or silicon oxynitride.

[0094] Method 2200 continues with operation 2206, where a source or drain region is formed at the end of the semiconductor region of each fin. Any portion of the fin not protected by the sacrificial gate and spacer structure can be removed using, for example, an anisotropic etching process, after which the source or drain region is epitaxially grown from the exposed end of the semiconductor layer in the fin. In some exemplary embodiments, the source or drain region is an NMOS source or drain region (e.g., epitaxial silicon with n-type dopants) or a PMOS source or drain region (e.g., epitaxial SiGe with p-type dopants). Another dielectric filler can be formed near each source or drain region for additional electrical isolation between adjacent regions. The dielectric filler can also extend above the top surface of the source or drain region. In some embodiments, a topside conductive contact can be formed through the dielectric filler to contact one or more of the source or drain regions. In accordance with some embodiments, the internal gate spacer can be formed during source drain processing (e.g., after removing the exposed fins but before epitaxial growth of the source / drain regions, using a lateral etch process that selectively recesses the sacrificial material in the channel region and then fills the recess with the internal gate spacer material).

[0095] Method 2200 continues with operation 2208, where the sacrificial gate is removed and replaced by a gate structure. The sacrificial gate can be removed using an isotropic etching process that selectively removes all material from the sacrificial gate, thereby exposing the individual fins between the set of spacer structures. In the exemplary case of using a GAA transistor, any sacrificial layer within the exposed fins between the spacer structures can also be removed to release the nanoribbons, nanosheets, or nanowires of semiconductor material.

[0096] The gate structure may include both a gate dielectric and a gate electrode. According to some embodiments, the gate dielectric is first formed over the exposed semiconductor region between the spacer structures, after which the gate electrode is formed within the remaining portion of the trench between the spacer structures. The gate dielectric may include any number of dielectric layers deposited using a CVD process (e.g., ALD). The gate electrode may include any number of layers of conductive material, such as any metal, metal alloy, or polysilicon. The gate electrode may be deposited using electroplating, electroless plating, CVD, ALD, PECVD, or PVD, to name a few examples.

[0097] Method 2200 continues with operation 2210, where the substrate is removed from the backside to expose the underside of the dielectric filler surrounding the base of the fin. In some embodiments, the substrate is polished away via CMP or another grinding process to remove the substrate material. The substrate can be thinned at least until the bottom surface of the dielectric filler is exposed from the backside of the structure. In some examples, portions of the sub-fin region and / or any sacrificial material replacing the sub-fin region can also be exposed from the backside.

[0098] Method 2200 continues with operation 2212, wherein a backside trench recess is formed through at least the entire thickness of the gate structure between the semiconductor material of the first fin and the second fin. The backside trench recess can be formed using an RIE-based metal gate etching process that repeatedly etches through portions of the gate electrode while protecting the sidewalls of the recess from lateral etching to provide a final recess with a higher aspect ratio (e.g., an aspect ratio of 5:1 or higher, or 10:1 or higher). The trench recess can also extend along the first direction to separate two adjacent gate structures of adjacent devices from adjacent source or drain regions of the adjacent device.

[0099] Method 2200 continues with operation 2214, where one or more dielectric materials are formed within the backside trench recess to form a dielectric wall between adjacent gate structures. Because the dielectric wall is formed after the gate structure is formed, the gate dielectric of the gate structure does not extend over the entire sidewall surface of the dielectric wall within the gate trench. In other words, the dielectric wall directly contacts the gate electrode on either side of the dielectric wall (e.g., without a gate dielectric therebetween). In some examples, the dielectric wall comprises only silicon dioxide or silicon nitride. In some examples, the dielectric wall comprises a dielectric liner within the remaining volume of the backside trench recess and a dielectric filler on the dielectric liner. The dielectric liner may comprise a high-k dielectric material (e.g., a material having a dielectric constant higher than that of silicon oxide or higher than 3.9), while the dielectric filler may comprise a low-k dielectric material (e.g., a material having a dielectric constant equal to or lower than that of silicon oxide or lower than 3.9). In one example, the dielectric liner is silicon nitride and the dielectric filler is silicon dioxide.

[0100] Method 2200 continues with operation 2216, where a bottom portion of the dielectric wall is removed from the backside to form a backside cavity beneath the dielectric wall. A dielectric RIE process can be used to remove dielectric material from the backside of the dielectric wall while minimizing any removal of exposed gate electrode material. The recess can extend across the entire dielectric wall within the gate trench to expose the sidewalls of the gate electrodes of two adjacent gate structures.

[0101] Method 2200 continues with operation 2218, where a conductive material is deposited within the backside cavity to form a conductive gate link. The conductive gate link is formed directly on the lower surface of the dielectric wall and forms a conductive bridge between adjacent gate electrodes on either side of the dielectric wall. The conductive gate link can comprise any suitable conductive material and can include any of the conductive materials described above for gate electrodes, such as tungsten or molybdenum. Because the conductive gate link is formed from the backside of the structure, the conductive gate link extends along the bottom of the gate trench between adjacent gate electrodes.

[0102] Exemplary Systems

[0103] Figure 232300 is an exemplary computing system implemented using one or more integrated circuit structures as disclosed herein, according to some embodiments of the present disclosure. As can be seen, computing system 2300 houses a motherboard 2302. Motherboard 2302 may include multiple components, including but not limited to a processor 2304 and at least one communication chip 2306, each of which may be physically and electrically coupled to motherboard 2302 or otherwise integrated therein. As will be appreciated, motherboard 2302 may be, for example, any printed circuit board (PCB), whether a motherboard, a daughterboard mounted on a motherboard, or the sole board of system 2300.

[0104] Depending on its application, computing system 2300 may include one or more other components that may or may not be physically and electrically coupled to motherboard 2302. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a cryptographic processor, a chipset, an antenna, a display, a touch screen display, a touchpad controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (e.g., a hard drive, a compact disc (CD), a digital versatile disc (DVD), etc.). Any component included in computing system 2300 may include one or more integrated circuit structures or devices constructed according to exemplary embodiments (e.g., a module including an integrated circuit having a semiconductor device with a series of dielectric walls formed from the back side of the structure, as described herein). In some embodiments, multiple functions may be integrated into one or more chips (e.g., note that communication chip 2306 may be part of processor 2304 or otherwise integrated into processor 2304).

[0105] The communication chip 2306 implements wireless communication for transmitting data to and from the computing system 2300. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data through a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated devices do not contain any wires, although in some embodiments, they may not contain wires. The communication chip 2306 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher. The computing system 2300 may include multiple communication chips 2306. For example, the first communication chip 2306 can be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and the second communication chip 2306 can be dedicated to longer-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0106] The processor 2304 of the computing system 2300 includes an integrated circuit die packaged within the processor 2304. In some embodiments, as described herein, the integrated circuit die of the processor includes onboard circuitry implemented using one or more semiconductor devices. The term "processor" may refer to any device or portion of a device that processes electronic data, such as from registers and / or memory, to transform the electronic data into other electronic data that can be stored in registers and / or memory.

[0107] The communication chip 2306 may also include an integrated circuit die packaged within the communication chip 2306. According to some such exemplary embodiments, the integrated circuit die of the communication chip includes one or more semiconductor devices as described herein. As will be understood in light of this disclosure, it is noted that multi-standard wireless capabilities may be integrated directly into the processor 2304 (e.g., where the functionality of any chip 2306 is integrated into the processor 2304, rather than having a separate communication chip). It should also be noted that the processor 2304 may be a chipset with such wireless capabilities. In short, any number of processors 2304 and / or communication chips 2306 may be used. Likewise, any one chip or chipset may have multiple functionalities integrated therein.

[0108] In various embodiments, computing system 2300 can be a laptop, netbook, notebook computer, smartphone, tablet computer, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, digital video recorder, or any other electronic device as described herein that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques.

[0109] Other exemplary embodiments

[0110] The following examples relate to further embodiments, from which numerous arrangements and configurations will be apparent.

[0111] Example 1 is an integrated circuit comprising: a first semiconductor device having a first semiconductor region extending in a first direction from a first source or drain region and a first gate electrode surrounding the first semiconductor region; and a second semiconductor device having a second semiconductor region extending in the first direction from a second source or drain region and a second gate electrode surrounding the second semiconductor region. The second semiconductor device is spaced apart from the first semiconductor device in a second direction different from the first direction. The integrated circuit further comprises: a dielectric structure located below the first gate electrode and the second gate electrode; a dielectric wall extending in the first direction between the first gate electrode and the second gate electrode and extending in a third direction along at least the entire height of the first gate electrode and the second gate electrode; and a conductive bridge extending through a bottom portion of the dielectric wall in the second direction and contacting the first gate electrode and the second gate electrode. The conductive bridge is located on a top surface of the dielectric structure.

[0112] Example 2 includes the integrated circuit of Example 1, wherein the dielectric wall comprises a dielectric layer along one or more edges of the dielectric wall and a dielectric filler in a remaining volume of the dielectric wall.

[0113] Example 3 includes the integrated circuit of Example 2, wherein the dielectric layer comprises a high-k dielectric material.

[0114] Example 4 includes the integrated circuit of any of Examples 1-3, wherein the first semiconductor region includes a plurality of first semiconductor nanoribbons and the second semiconductor region includes a plurality of second semiconductor nanoribbons.

[0115] Embodiment 5 includes the integrated circuit of Example 4, wherein the plurality of first semiconductor nanoribbons and the plurality of second semiconductor nanoribbons include germanium, silicon, or a combination thereof.

[0116] Example 6 includes the integrated circuit of Example 4 or 5, wherein a plane extending along the first direction and along the second direction intersects the conductive bridge, at least one first semiconductor nanoribbon of the plurality of first semiconductor nanoribbons, and at least one second semiconductor nanoribbon of the plurality of second semiconductor nanoribbons.

[0117] Example 7 includes the integrated circuit of any of Examples 1-6, further comprising a first gate dielectric layer surrounding the first semiconductor region and a second gate dielectric layer surrounding the second semiconductor region, such that the first gate dielectric layer is located between the first semiconductor region and the first gate electrode, and the second gate dielectric layer is located between the second semiconductor region and the second gate electrode.

[0118] Example 8 includes the integrated circuit of Example 7, wherein the first gate dielectric layer and the second gate dielectric layer are not present on any sidewalls of the dielectric wall.

[0119] Example 9 includes the integrated circuit of any of Examples 1-8, wherein the dielectric wall extends along the first direction between the first source or drain region and the second source or drain region.

[0120] Example 10 includes the integrated circuit of Example 9, wherein the conductive bridge is a first conductive bridge, and the integrated circuit further comprises: a first contact located on a top surface of the first source or drain region; a second contact located on a top surface of the second source or drain region; and a second conductive bridge extending in the second direction through a top portion of the dielectric wall and contacting the first contact and the second contact.

[0121] Example 11 includes the integrated circuit of Example 10, further comprising: a third contact located on a bottom surface of the first source or drain region; a fourth contact located on a bottom surface of the second source or drain region; and a third conductive bridge extending in the second direction through a bottom portion of the dielectric wall and contacting the third contact and the fourth contact.

[0122] Example 12 includes the integrated circuit of Example 9, wherein the conductive bridge is a first conductive bridge, and the integrated circuit further comprises: a first contact located on a bottom surface of the first source or drain region; a second contact located on a bottom surface of the second source or drain region; and a second conductive bridge extending through a bottom portion of the dielectric wall in a second direction and contacting the first contact and the second contact.

[0123] Example 13 includes the integrated circuit of any of Examples 1-12, wherein the dielectric wall is a first dielectric wall, and the integrated circuit further comprises: a second dielectric wall extending in the first direction between the first semiconductor device and the third semiconductor device, the second dielectric wall extending through the entire thickness of the first gate electrode; and a third dielectric wall extending in the first direction between the second semiconductor device and the fourth semiconductor device, the third dielectric wall extending through the entire thickness of the second gate electrode.

[0124] Example 14 includes the integrated circuit of Example 13, wherein the conductive bridge is a first conductive bridge, and the integrated circuit further comprises: a second conductive bridge extending along the second direction through a bottom portion of the corresponding dielectric wall and contacting the first source or drain contact and the second source or drain contact; and / or a third conductive bridge extending along the second direction through a top portion of the corresponding dielectric wall and contacting the third source or drain contact and the fourth source or drain contact.

[0125] Example 15 is a printed circuit board comprising the integrated circuit of any one of Examples 1-14.

[0126] Example 16 is an electronic device comprising a chip package having one or more dies. At least one of the one or more dies comprises: a first semiconductor region extending in a first direction from a first source or drain region; a second semiconductor region extending in the first direction from the second source or drain region; a gate electrode surrounding each of the first and second semiconductor regions; a dielectric structure located below the gate electrode; and a dielectric wall located between the first and second semiconductor regions. The second semiconductor region is spaced apart from the first semiconductor region in a second direction different from the first direction. A portion of the gate electrode extends through a bottom portion of the dielectric wall in the second direction, such that the portion of the gate electrode is located on a top surface of the dielectric structure.

[0127] Example 17 includes the electronic device of Example 16, wherein the dielectric wall comprises a dielectric layer along one or more edges of the dielectric wall and a dielectric filler in a remaining volume of the dielectric wall.

[0128] Example 18 includes the electronic device of Example 17, wherein the dielectric layer comprises a high-k dielectric material.

[0129] Example 19 includes the electronic device of any of Examples 16-18, wherein the first semiconductor region includes a plurality of first semiconductor nanoribbons and the second semiconductor region includes a plurality of second semiconductor nanoribbons.

[0130] Example 20 includes the electronic device of Example 19, wherein the plurality of first semiconductor nanoribbons and the plurality of second semiconductor nanoribbons include germanium, silicon, or a combination thereof.

[0131] Example 21 includes the electronic device of Example 19 or 20, wherein a plane extending along the first direction and along the second direction intersects a portion of the gate electrode located on the top surface of the dielectric structure, at least one first semiconductor nanoribbon among the plurality of first semiconductor nanoribbons, and at least one second semiconductor nanoribbon among the plurality of second semiconductor nanoribbons.

[0132] Example 22 includes an electronic device of any of Examples 16-21, wherein at least one of the one or more dies further includes a gate dielectric layer surrounding the first semiconductor region and the second semiconductor region, such that the gate dielectric layer is located between the first semiconductor region and the gate electrode, and between the second semiconductor region and the gate electrode.

[0133] Example 23 includes the electronic device of Example 22, wherein the gate dielectric layer is not present on any sidewalls of the dielectric wall.

[0134] Example 24 includes the electronic device of any of Examples 16-23, wherein the dielectric wall extends along the first direction between the first source or drain region and the second source or drain region.

[0135] Example 25 includes the electronic device of Example 24, wherein at least one of the one or more tube cores further includes: a third contact portion located on the bottom surface of the first source or drain region; a fourth contact portion located on the bottom surface of the second source or drain region; and a conductive bridge extending along the second direction through the bottom portion of the dielectric wall and contacting the third contact portion and the fourth contact portion.

[0136] Example 26 includes the electronic device of Example 25, wherein the conductive bridge is a first conductive bridge, and at least one of the one or more tube cores further includes: a first contact portion located on a top surface of the first source or drain region; a second contact portion located on a top surface of the second source or drain region; and a second conductive bridge extending along a second direction through a top portion of the dielectric wall and contacting the first contact portion and the second contact portion.

[0137] Example 27 includes the electronic device of any of Examples 16-26, wherein the dielectric wall is a first dielectric wall, and at least one of the one or more dies further includes: a second dielectric wall extending in a first direction between the first semiconductor device and the third semiconductor device, the second dielectric wall extending through an entire thickness of the gate electrode, and a third dielectric wall extending in the first direction between the second semiconductor device and the fourth semiconductor device, the third dielectric wall extending through an entire thickness of the gate electrode.

[0138] Example 28 includes the electronic device of any of Examples 16-27, further comprising a printed circuit board, wherein the chip package is coupled to the printed circuit board.

[0139] Example 29 is a method of forming an integrated circuit. The method includes: forming a first fin and a second fin, the first fin comprising a first semiconductor material and the second fin comprising a second semiconductor material, the first fin and the second fin extending above a substrate, and each fin extending parallel to each other in a first direction; forming a first source or drain region at an end of the first fin and a second source or drain region at an end of the second fin; forming a gate electrode extending above the first fin and the second fin in a second direction different from the first direction; removing the substrate from a back side of the integrated circuit; after removing the substrate, forming a recess between the first semiconductor material and the second semiconductor material from the back side through the entire thickness of the gate electrode, the recess further extending in the first direction between the first source or drain region and the second source or drain region; forming a dielectric material within the recess; recessing a portion of the dielectric material between the first semiconductor material and the second semiconductor material; forming a conductive material on the dielectric material, the conductive material being within the recess and contacting the gate electrode; and forming a dielectric layer on the conductive material.

[0140] Example 30 includes the method of Example 29, further comprising: forming a gate dielectric layer surrounding the first semiconductor material and the second semiconductor material before forming the gate electrode.

[0141] Example 31 includes the method of Example 29 or 30, wherein forming the recess includes forming the recess through an entire thickness of the gate electrode.

[0142] Example 32 includes the method of any of Examples 29-31, wherein the conductive material is a first conductive material, and the method further includes: recessing another portion of the dielectric material between the first source or drain region and the second source or drain region; and forming a second conductive material on the dielectric material within the recess between the first source or drain region and the second source or drain region.

[0143] Example 33 is an integrated circuit comprising: a first semiconductor device having a first semiconductor region extending in a first direction from a first source or drain region and a first gate electrode surrounding the first semiconductor region; and a second semiconductor device having a second semiconductor region extending in the first direction from a second source or drain region and a second gate electrode surrounding the second semiconductor region. The second semiconductor device is spaced apart from the first semiconductor device in a second direction different from the first direction. The integrated circuit further comprises: a first contact on a top surface of the first source or drain region and a second contact on a top surface of the second source or drain region; a third contact on a bottom surface of the first source or drain region and a fourth contact on a bottom surface of the second source or drain region; a dielectric wall extending in the first direction between the first gate electrode and the second gate electrode and between the first source or drain region and the second source or drain region; a first conductive bridge extending in a second direction through a bottom portion of the dielectric wall and contacting the third contact and the fourth contact; and a second conductive bridge extending in the second direction through a top portion of the dielectric wall and contacting the first contact and the second contact.

[0144] Example 34 includes the integrated circuit of Example 33, wherein the dielectric wall comprises a dielectric layer along one or more edges of the dielectric wall and a dielectric filler in a remaining volume of the dielectric wall.

[0145] Example 35 includes the integrated circuit of Example 34, wherein the dielectric layer comprises a high-k dielectric material.

[0146] Example 36 includes the integrated circuit of any of Examples 33-35, wherein the first semiconductor region includes a plurality of first semiconductor nanoribbons and the second semiconductor region includes a plurality of second semiconductor nanoribbons.

[0147] Example 37 includes the integrated circuit of Example 36, wherein the plurality of first semiconductor nanoribbons and the plurality of second semiconductor nanoribbons include germanium, silicon, or a combination thereof.

[0148] Example 38 includes the integrated circuit of any of Examples 33-37, further comprising a gate dielectric layer surrounding the first semiconductor region and the second semiconductor region, such that the gate dielectric layer is located between the first semiconductor region and the first gate electrode and between the second semiconductor region and the second gate electrode.

[0149] Example 39 includes the integrated circuit of Example 38, wherein the gate dielectric layer is not present on any sidewalls of the dielectric wall.

[0150] Example 40 includes the integrated circuit of any of Examples 33-39, further comprising a third conductive bridge extending through a bottom portion of the dielectric wall in the second direction and contacting the first gate electrode and the second gate electrode.

[0151] Example 41 includes the integrated circuit of any of Examples 33-40, wherein the dielectric wall is a first dielectric wall, and the integrated circuit further includes: a second dielectric wall extending in a first direction between the first semiconductor device and the third semiconductor device, the second dielectric wall extending through an entire thickness of the first gate electrode; and a third dielectric wall extending in the first direction between the second semiconductor device and the fourth semiconductor device, the third dielectric wall extending through an entire thickness of the second gate electrode.

[0152] Example 42 is a printed circuit board comprising the integrated circuit of any one of Examples 33-41.

[0153] It will be understood that in some embodiments, the various components of the computing system 2300 can be combined or integrated in a system-on-chip (SoC) architecture. In some embodiments, the components can be hardware components, firmware components, software components, or any suitable combination of hardware, firmware, or software.

Claims

1. An integrated circuit comprising: a first semiconductor device having a first semiconductor region extending in a first direction from a first source or drain region and a first gate electrode surrounding the first semiconductor region; a second semiconductor device having a second semiconductor region extending from a second source or drain region in the first direction and a second gate electrode surrounding the second semiconductor region, the second semiconductor device being spaced apart from the first semiconductor device in a second direction different from the first direction; a dielectric structure located below the first gate electrode and the second gate electrode; a dielectric wall extending in the first direction between the first gate electrode and the second gate electrode and extending in a third direction along at least the entire height of the first gate electrode and the second gate electrode; as well as A conductive bridge extends along the second direction through a bottom portion of the dielectric wall and contacts the first gate electrode and the second gate electrode, wherein the conductive bridge is located on a top surface of the dielectric structure.

2. The integrated circuit according to claim 1, wherein: The dielectric wall includes a dielectric layer along one or more edges of the dielectric wall and a dielectric filler in the remaining volume of the dielectric wall.

3. The integrated circuit according to claim 2, wherein: The dielectric layer includes a high-k dielectric material.

4. The integrated circuit according to claim 1, wherein: The first semiconductor region includes a plurality of first semiconductor nanoribbons, and the second semiconductor region includes a plurality of second semiconductor nanoribbons.

5. The integrated circuit according to claim 4, wherein: A plane extending along the first direction and along the second direction intersects the conductive bridge, at least one first semiconductor nanoribbon of the plurality of first semiconductor nanoribbons, and at least one second semiconductor nanoribbon of the plurality of second semiconductor nanoribbons.

6. The integrated circuit according to claim 1 further includes a first gate dielectric layer surrounding the first semiconductor region and a second gate dielectric layer surrounding the second semiconductor region, such that the first gate dielectric layer is located between the first semiconductor region and the first gate electrode, and the second gate dielectric layer is located between the second semiconductor region and the second gate electrode.

7. The integrated circuit according to claim 6, wherein: The first gate dielectric layer and the second gate dielectric layer are not present on any sidewalls of the dielectric wall.

8. The integrated circuit according to claim 1, wherein: The dielectric wall extends along the first direction between the first source or drain region and the second source or drain region.

9. The integrated circuit according to claim 8, wherein: The conductive bridge is a first conductive bridge, and the integrated circuit further comprises: a first contact portion, the first contact portion being located on a top surface of the first source or drain region; a second contact located on a top surface of the second source or drain region; and A second conductive bridge extends along the second direction through a top portion of the dielectric wall and contacts the first contact and the second contact.

10. The integrated circuit of claim 9, further comprising: a third contact portion, the third contact portion being located on a bottom surface of the first source or drain region; a fourth contact portion, the fourth contact portion being located on a bottom surface of the second source or drain region; as well as A third conductive bridge extends along the second direction through a bottom portion of the dielectric wall and contacts the third contact and the fourth contact.

11. The integrated circuit according to claim 8, wherein: The conductive bridge is a first conductive bridge, and the integrated circuit further includes a first contact located on a bottom surface of the first source or drain region, a second contact located on a bottom surface of the second source or drain region, and a second conductive bridge extending through a bottom portion of the dielectric wall in the second direction and contacting the first contact and the second contact.

12. The integrated circuit according to any one of claims 1 to 11, wherein: The dielectric wall is a first dielectric wall, and the integrated circuit further includes: a second dielectric wall extending along the first direction between the first semiconductor device and the third semiconductor device, the second dielectric wall extending through the entire thickness of the first gate electrode; and a third dielectric wall extending along the first direction between the second semiconductor device and the fourth semiconductor device, the third dielectric wall extending through the entire thickness of the second gate electrode.

13. The integrated circuit according to claim 12, wherein: The conductive bridge is a first conductive bridge, and the integrated circuit further includes: a second conductive bridge extending along the second direction through a bottom portion of the corresponding dielectric wall and contacting the first source or drain contact and the second source or drain contact; and / or a third conductive bridge extending along the second direction through a top portion of the corresponding dielectric wall and contacting the third source or drain contact and the fourth source or drain contact.

14. A printed circuit board comprising the integrated circuit according to any one of claims 1 to 11.

15. An electronic device comprising: A chip package, the chip package comprising one or more dies, at least one of the one or more dies comprising: a first semiconductor region extending from the first source or drain region in a first direction; a second semiconductor region extending from a second source or drain region in the first direction, the second semiconductor region being spaced apart from the first semiconductor region in a second direction different from the first direction; a gate electrode surrounding each of the first semiconductor region and the second semiconductor region; a dielectric structure underlying the gate electrode; and a dielectric wall located between the first semiconductor region and the second semiconductor region, wherein a portion of the gate electrode extends through a bottom portion of the dielectric wall along the second direction such that the portion of the gate electrode is located on a top surface of the dielectric structure.

16. The electronic device according to claim 15, wherein: The dielectric wall includes a dielectric layer along one or more edges of the dielectric wall and a dielectric filler in the remaining volume of the dielectric wall.

17. The electronic device according to claim 15, wherein: The first semiconductor region includes a plurality of first semiconductor nanoribbons, and the second semiconductor region includes a plurality of second semiconductor nanoribbons.

18. The electronic device according to claim 17, wherein: A plane extending along the first direction and along the second direction intersects the portion of the gate electrode located on the top surface of the dielectric structure, at least one first semiconductor nanoribbon of the plurality of first semiconductor nanoribbons, and at least one second semiconductor nanoribbon of the plurality of second semiconductor nanoribbons.

19. The electronic device according to any one of claims 15 to 18, wherein: The dielectric wall extends along the first direction between the first source or drain region and the second source or drain region.

20. The electronic device according to any one of claims 15 to 18, wherein: The dielectric wall is a first dielectric wall, and the at least one of the one or more dies further comprises: a second dielectric wall extending along the first direction between the first semiconductor region and the third semiconductor region, the second dielectric wall extending through the entire thickness of the gate electrode; and A third dielectric wall extends between the second semiconductor region and the fourth semiconductor region along the first direction, and the third dielectric wall extends through the entire thickness of the gate electrode.

21. An integrated circuit comprising: a first semiconductor device having a first semiconductor region extending in a first direction from a first source or drain region and a first gate electrode surrounding the first semiconductor region; a second semiconductor device having a second semiconductor region extending from a second source or drain region in the first direction and a second gate electrode surrounding the second semiconductor region, the second semiconductor device being spaced apart from the first semiconductor device in a second direction different from the first direction; a first contact on a top surface of the first source or drain region and a second contact on a top surface of the second source or drain region; a third contact on a bottom surface of the first source or drain region and a fourth contact on a bottom surface of the second source or drain region; a dielectric wall extending along the first direction between the first gate electrode and the second gate electrode and between the first source or drain region and the second source or drain region; a first conductive bridge extending along the second direction through a bottom portion of the dielectric wall and contacting the third contact and the fourth contact; as well as A second conductive bridge extends along the second direction through a top portion of the dielectric wall and contacts the first contact and the second contact.

22. The integrated circuit of claim 21, wherein: The first semiconductor region includes a plurality of first semiconductor nanoribbons, and the second semiconductor region includes a plurality of second semiconductor nanoribbons.

23. The integrated circuit of claim 21 or 22, further comprising a gate dielectric layer surrounding the first semiconductor region and the second semiconductor region, such that the gate dielectric layer is located between the first semiconductor region and the first gate electrode and between the second semiconductor region and the second gate electrode.

24. The integrated circuit of claim 21 or 22, further comprising a third conductive bridge extending through a bottom portion of the dielectric wall along the second direction and contacting the first gate electrode and the second gate electrode.

25. An integrated circuit according to claim 21 or 22, wherein: The dielectric wall is a first dielectric wall, and the integrated circuit further comprises: a second dielectric wall extending along the first direction between the first semiconductor device and the third semiconductor device, the second dielectric wall extending through an entire thickness of the first gate electrode; and A third dielectric wall extends along the first direction between the second semiconductor device and the fourth semiconductor device, the third dielectric wall extending through an entire thickness of the second gate electrode.

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