Integrated circuit structure with uniform grid metal gate and trench contact cut-outs inserted with air gap structures

Abstract

Integrated circuit structures having uniform grid metal gates and trench contact cuts inserted with air gap structures are described. For example, an integrated circuit structure includes an insulating structure laterally between a first gate structure and a second gate structure, the insulating structure extends from a horizontal plane above a first vertical stack of fins or horizontal nanowires and a second stack of fins or horizontal nanowires to a horizontal plane below the first vertical stack of fins or horizontal nanowires and the second stack of fins or horizontal nanowires. The insulating structure includes a dielectric liner, a cavity within the dielectric liner, and a dielectric cap over the cavity. The dielectric liner is in contact with the first gate electrode and the second gate electrode.

Description

Background Art

[0001] Over the past few decades, feature scaling in integrated circuits has been the driving force behind the continued advancement of the semiconductor industry. Scaling to smaller and smaller features has enabled the density of functional units to be increased within the limited area of ​​a semiconductor chip. For example, shrinking transistor size allows for the integration of an increasing number of memory or logic devices on a chip, thereby facilitating the manufacture of products with increased capacity. However, the pursuit of greater capacity is not without its challenges. The need to optimize the performance of each device has become increasingly important.

[0002] In the manufacture of integrated circuit devices, as device sizes continue to shrink, multi-gate transistors (e.g., tri-gate transistors) have become more common. In conventional processes, tri-gate transistors are typically manufactured on bulk silicon substrates or silicon-on-insulator substrates. In some cases, bulk silicon substrates are preferred due to their lower cost and because they implement a less complex tri-gate manufacturing process. On the other hand, as microelectronic device sizes shrink to below 10 nanometer (nm) nodes, maintaining mobility improvements and short channel control poses a challenge in device manufacturing. Nanowires used to manufacture devices provide improved short channel control.

[0003] However, scaling multi-gate and nanowire transistors is not without consequences. As the size of these basic building blocks of microelectronic circuitry decreases, and as the number of basic building blocks fabricated in a given area increases, the constraints on the lithographic processes used to pattern these building blocks become overwhelming. Specifically, there can be a trade-off between the minimum size (critical dimension) of a feature patterned in a semiconductor stack and the spacing between these features. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figures 1A-1D Angled cross-sectional views representing various operations in a method of fabricating an integrated circuit structure having a uniform grid metal gate and trench contact cuts are illustrated in accordance with an embodiment of the present disclosure.

[0005] Figures 1E-1K Angled cross-sectional views representing various operations in a method of fabricating an integrated circuit structure having a uniform grid metal gate and trench contact cuts interposed with air gap structures are illustrated in accordance with an embodiment of the present disclosure.

[0006] Figure 2A A cross-sectional view of an integrated circuit structure having fins and pre-metal gate dielectric plugs according to an embodiment of the present disclosure is shown, and Figure 2B A cross-sectional view of an integrated circuit structure with fins and cut metal gate dielectric plugs according to an embodiment of the present disclosure is shown.

[0007] Figure 3AA cross-sectional view of an integrated circuit structure having nanowires and pre-metal gate dielectric plugs according to an embodiment of the present disclosure is shown, and Figure 3B A cross-sectional view of an integrated circuit structure with nanowires and cut metal gate dielectric plugs according to an embodiment of the present disclosure is shown.

[0008] Figure 4A A cross-sectional view of an integrated circuit structure having nanowires and pre-metal gate dielectric plugs according to an embodiment of the present disclosure is shown, and Figure 4B A cross-sectional view of an integrated circuit structure with nanowires and cut metal gate dielectric plugs according to an embodiment of the present disclosure is shown.

[0009] Figures 5A-5C Shown are plan views of comparative integrated circuit structures according to embodiments of the present disclosure.

[0010] Figures 6A-6C Cross-sectional views of comparative integrated circuit structures according to embodiments of the present disclosure are shown.

[0011] Figures 7A-7J Cross-sectional views are illustrated illustrating various operations in a method of fabricating a gate-all-around integrated circuit structure in accordance with an embodiment of the present disclosure.

[0012] Figure 8 A cross-sectional view of a non-planar integrated circuit structure taken along a gate line according to an embodiment of the present disclosure is shown.

[0013] Figure 9 Cross-sectional views through nanowires and fins are shown for a non-endcap architecture (left-hand side (a)) and a self-aligned gate endcap (SAGE) architecture (right-hand side (b)) according to embodiments of the present disclosure.

[0014] Figure 10 Cross-sectional views representing various operations in a method of fabricating a self-aligned gate end cap (SAGE) structure having a gate-all-around device are illustrated in accordance with an embodiment of the present disclosure.

[0015] Figure 11A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure is shown.

[0016] Figure 11B The image taken along the a-a' axis according to an embodiment of the present disclosure is shown. Figure 11A A cross-sectional source or drain view of a nanowire-based integrated circuit structure.

[0017] Figure 11C The image taken along the bb' axis according to an embodiment of the present disclosure is shown. Figure 11A Cross-sectional channel view of a nanowire-based integrated circuit structure.

[0018] Figure 12 A computing device according to one implementation of an embodiment of the present disclosure is shown.

[0019] Figure 13 An interposer including one or more embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0020] An integrated circuit structure having a uniform grid metal gate and a trench contact cutout with an air gap structure inserted therein, and a method of manufacturing an integrated circuit structure having a uniform grid metal gate and a trench contact cutout with an air gap structure inserted therein are described. In the following description, many specific details are set forth, such as specific integration and material schemes, in order to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure can be practiced without these specific details. In other cases, well-known features such as integrated circuit design layouts are not described in detail so as not to unnecessarily obscure the embodiments of the present disclosure. In addition, it should be appreciated that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0021] Certain terms may also be used in the following description for reference purposes only and are therefore not intended to be limiting. For example, terms such as "upper," "lower," "above," and "below" refer to directions in the accompanying drawings to which reference is being made. Terms such as "front," "rear," "back," and "side" describe the orientation and / or position of parts of a component within a consistent but arbitrary reference frame, which becomes clear by reference to the text and associated drawings describing the component in question. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar meaning.

[0022] Embodiments described herein may relate to front-end-of-the-line (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication, where devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically covers everything up to (but not including) the deposition of metal interconnect layers. After the final FEOL operations, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0023] The embodiments described herein may relate to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing where the devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring (e.g., one or more metallization layers) on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL portion of the manufacturing stage, contacts (pads), interconnects, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL.

[0024] The embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. Specifically, although FEOL processing scenarios may be used to illustrate exemplary processing schemes, such methods may also be applicable to BEOL processing. Similarly, although BEOL processing scenarios may be used to illustrate exemplary processing schemes, such methods may also be applicable to FEOL processing.

[0025] One or more embodiments described herein relate to integrated circuit structures fabricated to include a uniform grid of metal gates and trench contact plugs, which may include porous liner air gaps. One or more embodiments described herein relate to full-all-around gate devices fabricated using multiple common and extended metal gate notch (MGC) trench contact (TCN) notch plug structures. It should be appreciated that references herein to nanowires may refer to nanowires or nanoribbons unless otherwise stated. One or more embodiments described herein relate to FinFET structures fabricated using multiple common and extended metal gate notch (MGC) trench contact (TCN) notch plug structures.

[0026] To provide context, simplifying the trench contact and polysilicon cutting (gate cut) processes may be advantageous, for example, to improve device performance and reduce process variation.

[0027] According to one or more embodiments of the present disclosure, a metal gate process is performed and a trench contact process is performed without a plug. A single "infinite" long grid is then used to generate each possible trench contact plug and gate cut plug (as a unified dielectric cut plug). The resulting structure can be referred to as a pixel structure. The pixel structure can then be partially plug removed to effectively rejoin or reconnect the cut gate portion and / or rejoin the cut contact portion.

[0028] As an exemplary treatment scheme, Figures 1A-1DAngled cross-sectional views illustrating various operations in a method of fabricating an integrated circuit structure having a uniform grid metal gate and trench contact cuts are shown in accordance with an embodiment of the present disclosure. It will be appreciated that the described and illustrated embodiments may also be applicable to fin structures that replace a stack of nanowires, nanoribbons, or nanosheets (e.g., a fin structure on an underlying sub-fin structure).

[0029] refer to Figure 1A , shows a starting structure 100 prior to nanowire release and replacement gate processes. Starting structure 100 includes sub-fins 104 extending from a substrate 102, such as silicon sub-fins extending from a silicon substrate. Sub-fins 104 extend through shallow trench isolation (STI) structures 106, such as silicon oxide or silicon dioxide trench isolation structures. One or more stacks of horizontal nanowires 108 (e.g., stacks of horizontal silicon nanowires) are above corresponding sub-fins 104. At this stage, sacrificial interlayers 110, such as sacrificial silicon germanium interlayers, alternate with the horizontal nanowires 108 in the nanowire stacks. A sacrificial gate oxide 112 (e.g., a silicon oxide or silicon dioxide sacrificial gate oxide) is above the stacks of horizontal silicon nanowires 108. A sacrificial gate structure 114, such as a polysilicon sacrificial gate structure, is located above the sacrificial gate oxide 112 and above the channel region of the stacks of horizontal nanowires 108. As depicted, a hard mask layer 116, such as a silicon nitride hard mask layer, may be included over the sacrificial gate structure 114. A gate spacer-forming material 118 , such as silicon nitride gate spacer-forming material 118 , is included above and along the sides of the sacrificial gate structure 114 .

[0030] Reference again Figure 1A , epitaxial source or drain structures 120 (e.g., epitaxial silicon or epitaxial silicon germanium source or drain structures) are formed at the ends of the stack of horizontal nanowires 108 at locations between adjacent sacrificial gate structures 114. Internal gate spacers 126, such as internal silicon nitride internal gate spacers 126, can be formed by recessing the sacrificial interlayer 110 and depositing an internal gate spacer material before forming the epitaxial source or drain structures 120. The epitaxial source or drain structures 120 can be formed over a lower spacer recess filler 122 (e.g., silicon nitride spacer filler), which can be formed simultaneously with the internal gate spacers 126 and / or the gate spacer-forming material 118. A contact insulator structure 128 (e.g., a silicon oxide or silicon dioxide structure) is included over the epitaxial source or drain structures 120 and can occupy locations where conductive trench contacts will eventually be formed.

[0031] refer to Figure 1B, the starting structure 100 undergoes a replacement gate and nanowire release process flow. Specifically, the structure 100 is planarized and / or etched to expose the sacrificial gate structure 114. The planarization can remove the hard mask layer 116, form gate spacers 118A from the gate spacer forming material 118, and form a planarized contact insulator structure 128A. The sacrificial gate structure 114 and the sacrificial gate oxide 112 are then removed using a selective etch. The sacrificial interlayer 110 is then removed using a selective etch. A permanent gate dielectric structure 132, such as a gate dielectric structure comprising a high-k dielectric layer, is then formed in the resulting trenches and cavities (including around the channel region of each nanowire 108). A permanent gate electrode 134, such as a gate electrode comprising a metal, is formed over the permanent gate dielectric structure 132 (including in locations around the channel region of the nanowire 108). A gate insulating cap layer 136, such as a silicon nitride cap layer, can be formed over the resulting permanent gate electrode structure 134, such as by recessing the gate structure and backfilling with a dielectric.

[0032] refer to Figure 1C and Figure 1D , the pixel structure 149 is shown with a cross-sectional view of the exposed trench contact ( Figure 1C ) and a cross-sectional view of the exposed gate structure ( Figure 1D ). The pixel structure 149 is formed by first replacing the planarized contact insulator structure 128A with trench contact material. At this stage, the trench contact material is "infinite" along each trench contact, extending over all source / drain structures along a given trench contact line, effectively short-circuiting all trench contacts along a single trench contact line. Similarly, at this stage, the gate electrode material is "infinite" along each gate trench, extending over all nanowire stack channel regions along a given gate line, effectively short-circuiting all gates along a single gate line contact line. The gate insulating cap layer 136 may have been removed at this stage.

[0033] Subsequently, a non-selective cut is performed in a direction orthogonal to the gate and trench contact lines, which effectively cuts and isolates all trench contacts along a single trench contact line, and cuts and isolates all gate electrodes along a single gate line. The cut is then filled with a dielectric plug 148 extending through all trench contact lines and through all gate lines. The resulting "pixel" structure 149 includes a plurality of isolated / cut trench contact structures 140, which may include an insulating cap 142 thereon. The trench contact structure 140 may contact a silicide layer 146 on a corresponding epitaxial source or drain structure 120 at a location exposed by the etch stop layer 144. The resulting "pixel" structure 149 also includes a plurality of isolated / cut gate structures, for example, a structure including a cut gate dielectric 132A and a cut gate electrode 134A.

[0034] Reference again Figure 1C and 1D According to an embodiment of the present disclosure, an integrated circuit structure 149 includes a vertical stack of horizontal nanowires 108. A gate electrode 134A is located above the vertical stack of horizontal nanowires 108. A conductive trench contact 140 is adjacent to the gate electrode 134A. A dielectric sidewall spacer 118A is located between the gate electrode 134A and the conductive trench contact 140. A first dielectric cut plug structure 148 extends through the gate electrode 134A, through the dielectric sidewall spacer 118A, and through the conductive trench contact 140. A second dielectric cut plug structure 148 extends through the gate electrode 140, through the dielectric sidewall spacer 118A, and through the conductive trench contact 140. The second dielectric cut plug structure 148 is laterally spaced apart and parallel to the first dielectric cut plug structure 148.

[0035] It should be appreciated that the pixel structure 149 may then undergo: selective bonding / reconnection of some of the isolated / cut trench contact structures 140, and / or selective bonding / reconnection of some of the isolated / cut gate structures 132A / 134A. For example, one or more embodiments described herein relate to fabricating integrated circuit structures using trench contact (TCN) plug removal and / or metal gate cut (MGC) plug removal (e.g., as removal of selected portions of dielectric cut plug structures) to provide locations for conductive links or previously cut structures.

[0036] On the other hand, reducing the dielectric constant of the metal gate cut (MGC) fill material can significantly improve device performance.The embodiments described herein can be implemented to ensure the minimum possible dielectric constant of the MGC fill.

[0037] As an exemplary treatment scheme, Figures 1E-1K Angled cross-sectional views illustrating various operations in a method of fabricating an integrated circuit structure having a uniform grid metal gate and trench contact cuts with air gap structures inserted therein are shown in accordance with an embodiment of the present disclosure. It will be appreciated that the described and illustrated embodiments may also be applicable to fin structures (e.g., a fin structure on an underlying sub-fin structure) that replace a stack of nanowires, nanoribbons, or nanosheets.

[0038] refer to Figure 1E, shows the starting structure 150 after the replacement metal gate process and the trench contact metallization process. The starting structure 150 includes the sub-fins 152 in the trench isolation structure 153, the stack of nanowires 154 on the corresponding sub-fins in the sub-fins, the gate dielectric layer 156, the "infinite" gate electrode 158, the dielectric gate spacer 162, the "infinite" conductive trench contact 168 (which can enter or leave the page at the end of the nanowire stack on the epitaxial source or drain structure (not shown) and on the interlayer dielectric 167 between the source and drain regions), and the optional trench contact insulating cap layer 169.

[0039] refer to Figure 1F , Figure 1E The structure is subjected to a mask 170 and an etching process to form a cut 172. The cut 172 cuts the "infinite" gate electrode 158, the infinite "conductive trench contact structure 168", and the gate dielectric layer 156 to form a gate electrode 158A, a conductive trench contact structure 168A, a gate dielectric layer 156A, and a gate spacer portion 162A. A cut trench isolation structure portion 153A, an interlayer dielectric portion 167A, and a trench contact insulating cap layer portion 169A may also be formed.

[0040] refer to Figure 1G ,exist Figure 1F A dielectric gate plug liner forming material 174 is formed over the structure to line the cutout 172, forming a cutout 172A. In an embodiment, the dielectric gate plug liner forming material is composed of silicon nitride, silicon oxynitride, silicon carbide, or silicon oxide.

[0041] refer to Figure 1H A sacrificial material 176, such as a volatile material, is formed and recessed within the dielectric gate plug liner forming material 174 to fill the lower portion of the cutout 172A. A porous liner material 178, such as a porous low-k material, is then formed on the resulting structure.

[0042] refer to Figure 1I The sacrificial material 176 is removed, for example, by a volatilization process through the porous liner material 178, to form a cavity 180 within each cutout 172A. Each cavity 180 may be a volume devoid of solid material. Each cavity 180 may be an air gap.

[0043] refer to Figure 1J ,exist Figure 1I A dielectric capping layer 182 is formed over the structure. In one embodiment, the dielectric capping layer 182 is made of silicon nitride, silicon oxide, silicon oxynitride, or silicon carbide.

[0044] refer to Figure 1K , flattening Figure 1Jto form a planarized porous liner material 178A and a planarized dielectric cap layer 182A.

[0045] Reference again Figure 1K According to an embodiment of the present disclosure, the integrated circuit structure 190 includes a first vertical stack of horizontal nanowires 154 that is laterally spaced apart from a second vertical stack of horizontal nanowires 154. A first gate structure 156A / 158A is located above the first vertical stack of horizontal nanowires 154. The first gate structure 156A / 158A includes a first gate electrode 158A and a first gate dielectric 156A. A second gate structure 156A / 158A is located above the second vertical stack of horizontal nanowires 154. The second gate structure 156A / 158A includes a second gate electrode 158A and a second gate dielectric 156A. An insulating structure 174 / 180 / 178A / 182A is laterally located between the first gate structure 156A / 158A and the second gate structure 156A / 158A. Insulating structure 174 / 180 / 178A / 182A extends from a horizontal plane above the first vertical stack of horizontal nanowires 154 and the second stack of horizontal nanowires 154 to a horizontal plane below the first vertical stack of horizontal nanowires 154 and the second stack of horizontal nanowires 154. Insulating structure 174 / 180 / 178A / 182A includes a dielectric liner 174, a cavity 180 within dielectric liner 174, and a dielectric cap 182A or 182A / 178A over cavity 180. Dielectric liner 174 contacts first gate electrode 158A and second gate electrode 158A.

[0046] In an embodiment, the dielectric cap 182A or 182A / 178A of the insulating structure 174 / 180 / 178A / 182A has an uppermost surface at the same level as the uppermost surface of the first gate electrode 158A and the uppermost surface of the second gate electrode 158A. In an embodiment, the dielectric cap 182A or 182A / 178A is within the dielectric liner 174.

[0047] In an embodiment, the integrated circuit structure further includes a conductive trench contact (portion 168A) adjacent to the first and second gate structures 158A, and the insulating structure 174 / 180 / 178A / 182A extends through the conductive trench contact (e.g., between the pair of portions 168A). In an embodiment, the integrated circuit structure further includes a dielectric gate spacer (portion 162A) laterally located between the conductive trench contact (portion 168A) and the first and second gate structures 158A, and the insulating structure 174 / 180 / 178A / 182A extends through the dielectric gate spacer (e.g., between the pair of portions 162A).

[0048] On the other hand, to reduce cell height in future or scaled technology nodes, both gate endcap and gate cut dimensions need to shrink. The gate cut prior to gate metal fill can limit the effective endcap available for the work function, and metal fill capability in tighter spaces can become challenging. Defects can be worsened by any gate end-to-end misalignment, resulting in even less space for the endcap.

[0049] According to one or more embodiments of the present disclosure, the problems outlined above are solved, a metal gate cutting process is performed after the gate dielectric and work function metal deposition and patterning are completed, and the metal gate cutting process can be used in conjunction with the above Figures 1A-1D and the gate / contact plug process described in 1E-1K.

[0050] Advantages of implementing the methods described herein may include a so-called "plug-last" approach, resulting in a gate dielectric layer (e.g., a high-k gate dielectric layer) not being deposited on the gate plug sidewalls, effectively saving additional space for work function metal deposition. In contrast, during the so-called conventional "plug-first" approach, the metal gate fill material may be sandwiched between the plug and the fin. Since the plug in the latter approach is not aligned, the space for metal fill may be narrower and may result in voids during metal fill. In the embodiments described herein, using the "plug-last" approach, work function metal deposition can be seamless (e.g., void-free).

[0051] According to one or more embodiments of the present disclosure, an integrated circuit structure has a clean interface between the gate plug dielectric and the gate metal. It should be appreciated that many embodiments can benefit from the methods described herein, such as the plug-last method. For example, the following Figure 2B Describe the metal gate cutout on FinFET devices. A metal gate cutout scheme can be implemented for gate-all-around (GAA) devices, such as the following combined Figure 3B and Figure 4B Furthermore, the metal gate cut and plug formation may look different based on the structure being entered. For example, the plug may land on a shallow trench isolation (STI) structure, such as in conjunction with Figure 2B and Figure 3B as described; or may fall on a prefabricated gate wall made of a dielectric, such as in combination with Figure 4B The metal gate cutting method can be selective to the gate spacer dielectric, for example in combination with Figure 5B and Figure 6B as described; or may not be selective for the gate spacer material, such as in combination with Figure 5C and Figure 6CAs described. Non-selective metal gate cut embodiments may require alternative contact metal schemes to accommodate the dielectric plug between the epitaxial source / drain. Plug etch selectivity to the epitaxial source / drain material is optional. However, in one embodiment, if the epitaxial source / drain is exposed to the plug etch (e.g., due to device dimensions), the etch can anisotropically trim the source / drain, such as in the following combination. Figure 5C This approach can be implemented to achieve close end cap spacing.

[0052] A dielectric gate plug for a FinFET device can be manufactured. As a comparative example, according to an embodiment of the present disclosure, Figure 2A shows a cross-sectional view of an integrated circuit structure having fins and pre-metal gate dielectric plugs, and Figure 2B A cross-sectional view of an integrated circuit structure with fins and cut metal gate dielectric plugs is shown.

[0053] refer to Figure 2A Integrated circuit structure 200 includes a fin 202 having a portion protruding above a shallow trench isolation (STI) structure 204. A gate dielectric material layer 206, such as a high-k gate dielectric layer, is located above the protruding portion of fin 202 and above STI structure 204. It should be appreciated that, although not shown, an oxidized portion of fin 202 may be located between the protruding portion of fin 202 and gate dielectric material layer 206 and may include the oxidized portion of fin 202 together with gate dielectric material layer 206 to form a gate dielectric structure. A conductive gate layer 208, such as a work function metal layer, is located above gate dielectric material layer 206 and may be directly on gate dielectric material layer 206 as shown. A conductive gate fill material 210 is located above and may be directly on conductive gate layer 208 as shown. A dielectric gate cap 212 is located on conductive gate fill material 210. A dielectric gate plug 214 is laterally spaced apart from fin 202 and is located on STI structure 204. The gate dielectric material layer 206 and the conductive gate layer 208 are along the sides of the dielectric gate plug 214. In an embodiment, the dielectric gate plug 214 includes a cavity, for example, to form a plug including an air gap, for example, in combination with Figures 1E-1K The public.

[0054] refer to Figure 2B, integrated circuit structure 250 includes a fin 252 having a portion protruding above a shallow trench isolation (STI) structure 254. A gate dielectric material layer 256, such as a high-k gate dielectric layer, is located above the protruding portion of fin 252 and above STI structure 254. It should be appreciated that, although not shown, an oxidized portion of fin 252 may be located between the protruding portion of fin 252 and gate dielectric material layer 256 and may include the oxidized portion of fin 252 together with gate dielectric material layer 256 to form a gate dielectric structure. A conductive gate layer 258, such as a work function metal layer, is located above gate dielectric material layer 256 and may be directly on gate dielectric material layer 256 as shown. A conductive gate fill material 260 is located above conductive gate layer 258 and may be directly on conductive gate layer 258 as shown. A dielectric gate cap 262 is located on conductive gate fill material 260.

[0055] In an embodiment, dielectric gate plug 264 is laterally spaced apart from fin 252 and is on STI structure 254 but does not penetrate STI structure 254. As used throughout this disclosure, a dielectric plug referred to as "on STI structure but does not penetrate STI structure" may refer to a dielectric plug that rests on the top or uppermost surface of STI, or may refer to a plug that extends into STI but does not penetrate STI. In other embodiments, the plugs described herein may extend completely through or penetrate STI.

[0056] In an embodiment, the gate dielectric material layer 256 and the conductive gate layer 258 do not extend along the sides of the dielectric gate plug 264. Instead, the conductive gate fill material 260 contacts the sides of the dielectric gate plug 264. As a result, the area between the dielectric gate plug 264 and the fin 252 includes only one layer of the gate dielectric material layer 256 and only one layer of the conductive gate layer 258, thereby alleviating spatial constraints in such a compact area of ​​the structure 250. Alleviating spatial constraints can improve metal fill and / or can facilitate patterning of multiple VTs.

[0057] Reference again Figure 2BIn an embodiment, the dielectric gate plug 264 is formed after forming the gate dielectric material layer 256, the conductive gate layer 258, and the conductive gate fill material 260. As a result, the gate dielectric material layer 256 and the conductive gate layer 258 are not formed along the sides of the dielectric gate plug 264. In an embodiment, the dielectric gate plug 264 has an uppermost surface that is coplanar with the uppermost surface of the dielectric gate cap 262, as shown. In another embodiment not shown, the dielectric gate cap 262 is not included, and the uppermost surface of the dielectric gate plug 264 is coplanar with the uppermost surface of the conductive gate fill material 260, for example, along the plane 280. In an embodiment, the dielectric gate plug 264 includes a cavity, for example, to form a plug including an air gap, for example, in combination with Figures 1E-1K The public.

[0058] A dielectric gate plug for a nanowire device can be manufactured. As a comparative example, according to an embodiment of the present disclosure, Figure 3A shows a cross-sectional view of an integrated circuit structure having nanowires and pre-metal gate dielectric plugs, and Figure 3B A cross-sectional view of an integrated circuit structure with nanowires and cut metal gate dielectric plugs is shown.

[0059] refer to Figure 3A , the integrated circuit structure 300 includes a sub-fin 302 having a portion protruding above a shallow trench isolation (STI) structure 304. A plurality of horizontally stacked nanowires 305 are above the sub-fin 302. A gate dielectric material layer 306, such as a high-k gate dielectric layer, is above the protruding portion of the sub-fin 302, above the STI structure 304, and surrounding the horizontally stacked nanowires 305. It should be appreciated that, although not shown, the horizontally stacked nanowires 305 and the oxidized portion of the sub-fin 302 can be between the protruding portion of the sub-fin 302 and the gate dielectric material layer 306, as well as between the horizontally stacked nanowires 305 and the gate dielectric material layer 306, and can include the horizontally stacked nanowires 305 and the oxidized portion of the sub-fin 302 together with the gate dielectric material layer 306 to form a gate dielectric structure. A conductive gate layer 308, such as a work function metal layer, is above the gate dielectric material layer 306 and can be directly on the gate dielectric material layer 306 as shown. Conductive gate fill material 310 is above conductive gate layer 308 and may be directly on conductive gate layer 308 as shown. Dielectric gate cap 312 is on conductive gate fill material 310. Dielectric gate plug 314 is laterally spaced apart from sub-fin 302 and plurality of horizontally stacked nanowires 305 and is on STI structure 304. Gate dielectric material layer 306 and conductive gate layer 308 are along the sides of dielectric gate plug 314. In an embodiment, dielectric gate plug 314 includes a cavity, for example, to form a plug including an air gap, for example, in combination with a dielectric material layer 306. Figures 1E-1K The public.

[0060] refer to Figure 3B , the integrated circuit structure 350 includes a sub-fin 352 having a portion protruding above a shallow trench isolation (STI) structure 354. A plurality of horizontally stacked nanowires 355 are above the sub-fin 352. A gate dielectric material layer 356, such as a high-k gate dielectric layer, is above the protruding portion of the sub-fin 352, above the STI structure 354, and surrounding the horizontally stacked nanowires 355. It should be appreciated that, although not shown, the oxidized portion of the sub-fin 352 can be between the protruding portion of the sub-fin 352 and the gate dielectric material layer 356, as well as between the horizontally stacked nanowires 355 and the gate dielectric material layer 356, and can include the oxidized portion of the sub-fin 352 together with the gate dielectric material layer 356 to form a gate dielectric structure. A conductive gate layer 358, such as a work function metal layer, is above the gate dielectric material layer 356 and can be directly on the gate dielectric material layer 356 as shown. A conductive gate fill material 360 is above the conductive gate layer 358 and may be directly on the conductive gate layer 358 as shown. A dielectric gate cap 362 is on the conductive gate fill material 360. A dielectric gate plug 364 is laterally spaced apart from the sub-fin 352 and the plurality of horizontally stacked nanowires 355 and is on but does not pass through the STI structure 354. However, the gate dielectric material layer 356 and the conductive gate layer 358 do not follow the sides of the dielectric gate plug 364. Instead, the conductive gate fill material 360 is in contact with the sides of the dielectric gate plug 364. As a result, the area between the combination of the sub-fin 352 and the plurality of horizontally stacked nanowires 355 and the dielectric gate plug 364 includes only one layer of gate dielectric material 356 and only one layer of conductive gate layer 358, thereby alleviating spatial constraints in such a compact area of ​​the structure 350.

[0061] Reference again Figure 3B In an embodiment, dielectric gate plug 364 is formed after forming gate dielectric material layer 356, conductive gate layer 358, and conductive gate fill material 360. As a result, gate dielectric material layer 356 and conductive gate layer 358 are not formed along the sides of dielectric gate plug 364. In an embodiment, the uppermost surface of dielectric gate plug 364 is coplanar with the uppermost surface of dielectric gate cap 362, as shown. In another embodiment not shown, dielectric gate cap 362 is not included, and the uppermost surface of dielectric gate plug 364 is coplanar with the uppermost surface of conductive gate fill material 360, for example, along plane 380. In an embodiment, dielectric gate plug 364 includes a cavity, for example, to form a plug including an air gap, for example, in combination with Figures 1E-1K The public.

[0062] A dielectric gate plug can be fabricated on the gate end cap wall for a nanowire device. As a comparative example, according to an embodiment of the present disclosure, Figure 4A shows a cross-sectional view of an integrated circuit structure having nanowires and pre-metal gate dielectric plugs, and Figure 4B A cross-sectional view of an integrated circuit structure with nanowires and cut metal gate dielectric plugs is shown.

[0063] refer to Figure 4A , the integrated circuit structure 400 includes a sub-fin 402 having a portion protruding above a shallow trench isolation (STI) structure 404. A plurality of horizontally stacked nanowires 405 are above the sub-fin 402. A gate endcap structure 403, such as a self-aligned gate endcap structure, is on the STI structure 404 and is laterally spaced apart from the sub-fin 402 and the plurality of horizontally stacked nanowires 405. A gate dielectric material layer 406, such as a high-k gate dielectric layer, is above the protruding portion of the sub-fin 402, above the STI structure 404, along the sides of the gate endcap structure 403, and around the horizontally stacked nanowires 405. It should be appreciated that, although not shown, the horizontally stacked nanowires 405 and the oxidized portions of the sub-fins 402 may be between the protruding portions of the sub-fins 402 and the gate dielectric material layer 406, as well as between the horizontally stacked nanowires 405 and the gate dielectric material layer 406, and may include the horizontally stacked nanowires 405 and the oxidized portions of the sub-fins 402 together with the gate dielectric material layer 406 to form a gate dielectric structure. A conductive gate layer 408, such as a work function metal layer, is above the gate dielectric material layer 406 and may be directly on the gate dielectric material layer 406 as shown. A conductive gate fill material 410 is above the conductive gate layer 408 and may be directly on the conductive gate layer 408 as shown. A dielectric gate cap 412 is on the conductive gate fill material 410. A dielectric gate plug 414 is on the gate end cap structure 403. The gate dielectric material layer 406 and the conductive gate layer 408 are along the sides of the dielectric gate plug 414. In an embodiment, the dielectric gate plug 414 includes a cavity, for example, to form a plug including an air gap, for example, in combination with Figures 1E-1K The public.

[0064] refer to Figure 4B, the integrated circuit structure 450 includes a sub-fin 452 having a portion protruding above a shallow trench isolation (STI) structure 454. A plurality of horizontally stacked nanowires 455 are above the sub-fin 452. A gate endcap structure 453, such as a self-aligned gate endcap structure, is on but does not pass through the STI structure 454 and is laterally spaced apart from the sub-fin 452 and the plurality of horizontally stacked nanowires 455. A gate dielectric material layer 456, such as a high-k gate dielectric layer, is above the protruding portion of the sub-fin 452, above the STI structure 454, along the sides of the gate endcap structure 453, and around the horizontally stacked nanowires 455. It should be appreciated that, although not shown, the oxidized portion of sub-fin 452 may be between the protruding portion of sub-fin 452 and gate dielectric material layer 456, as well as between the horizontally stacked nanowires 455 and gate dielectric material layer 456, and may include the oxidized portion of sub-fin 452 together with gate dielectric material layer 456 to form a gate dielectric structure. A conductive gate layer 458, such as a work function metal layer, is above gate dielectric material layer 456 and may be directly on gate dielectric material layer 456 as shown. A conductive gate fill material 460 is above conductive gate layer 458 and may be directly on conductive gate layer 458 as shown. A dielectric gate cap 462 is on conductive gate fill material 460. A dielectric gate plug 464 is on gate end cap structure 453. However, gate dielectric material layer 456 and conductive gate layer 458 do not extend along the sides of dielectric gate plug 464. Instead, conductive gate fill material 460 contacts the sides of dielectric gate plug 464.

[0065] Reference again Figure 4B In an embodiment, the dielectric gate plug 464 is formed after forming the gate dielectric material layer 456, the conductive gate layer 458, and the conductive gate fill material 460. As a result, the gate dielectric material layer 456 and the conductive gate layer 458 are not formed along the sides of the dielectric gate plug 464. In an embodiment, the uppermost surface of the dielectric gate plug 464 is coplanar with the uppermost surface of the dielectric gate cap 462, as shown. In another embodiment not shown, the dielectric gate cap 462 is not included, and the uppermost surface of the dielectric gate plug 464 is coplanar with the uppermost surface of the conductive gate fill material 460, for example, along the plane 480. In an embodiment, the dielectric gate plug 464 includes a cavity, for example, to form a plug including an air gap, for example, in combination with Figures 1E-1K The public.

[0066] In another aspect, selective or non-selective versions of metal gate cuts can be implemented. As an example, Figures 5A-5C Shown are plan views of comparative integrated circuit structures according to embodiments of the present disclosure. Figure 5AThe representation shows a conventional plug-first approach of two gate plugs in adjacent gates. Figure 5B The representation shows a selective metal gate cut method of two gate plugs in adjacent gates. Figure 5C The representation shows a non-selective metal gate cut method of one long gate plug spanning multiple gates.

[0067] refer to Figure 5A , the integrated circuit structure 500 includes gate lines between dielectric spacers 517 and conductive source or drain contacts 518. Each gate line includes a gate dielectric material layer 506, a conductive gate layer 508 (e.g., a work function metal layer), and a conductive gate fill material 510. Dielectric gate plugs 514 can separate portions of the corresponding gate line. The dielectric gate plugs 514 are in contact with the conductive gate layer 508, but not in contact with the gate dielectric material layer 506 or the conductive gate fill material 510. Figure 5A The plane graph can correspond to Figure 2A 、 3A or 4A structure. It should be appreciated that although referred to above as a conductive source or drain contact 518, at an earlier stage of the process or elsewhere in the integrated circuit structure, a placeholder dielectric or dielectric plug replaces the conductive source or drain contact 518. In an embodiment, the dielectric gate plug 514 includes a cavity, for example, to form a plug including an air gap, for example, in combination with Figures 1E-1K The public.

[0068] refer to Figure 5B , the integrated circuit structure 550 includes gate lines between dielectric spacers 567 and conductive source or drain contacts 568. Each gate line includes a gate dielectric material layer 556, a conductive gate layer 558 (e.g., a work function metal layer), and a conductive gate fill material 560. Dielectric gate plugs 564 can separate portions of the corresponding gate line. The dielectric gate plugs 564 are in contact with the conductive gate fill material 560. Figure 5B The plane graph can correspond to Figure 2B 、 3B It should be appreciated that although referred to above as a conductive source or drain contact 568, at an earlier stage of the process or elsewhere in the integrated circuit structure, a placeholder dielectric or dielectric plug replaces the conductive source or drain contact 568. In an embodiment, the dielectric gate plug 564 includes a cavity, for example, to form a plug including an air gap, for example, in combination with Figures 1E-1K The public.

[0069] refer to Figure 5C, the integrated circuit structure 570 includes gate lines between dielectric spacers 587 and conductive source or drain contacts 588. Each gate line includes a gate dielectric material layer 576, a conductive gate layer 578 (e.g., a work function metal layer), and a conductive gate fill material 580. A single dielectric gate plug 584 can separate portions of the gate line and can extend through the dielectric spacers 587 and even partially or completely into one or more of the conductive source or drain contacts 588. The dielectric gate plug 584 is in contact with the conductive gate fill material 580. Figure 5C The plane graph can correspond to Figure 2B 、 3B In an embodiment, the dielectric gate plug 584 includes a cavity, such as to form a plug including an air gap, such as in combination with Figures 1E-1K The public.

[0070] Reference again Figure 5C It should be appreciated that, although referred to above as conductive source or drain contacts 588, placeholder dielectrics or dielectric plugs may replace conductive source or drain contacts 588 at earlier stages of the process or elsewhere in the integrated circuit structure. In embodiments, the etch used to form the opening in which the single dielectric gate plug 584 is ultimately formed is referred to as a non-selective etch. Where conductive source or drain contacts 588 have already been formed, the non-selective etch may etch into the conductive material of the conductive source or drain contacts 588. In other embodiments, where placeholder dielectrics or dielectric plugs replace conductive source or drain contacts 588, the non-selective etch may etch into the placeholder dielectrics or dielectric plugs. In either case, the non-selective etch may etch through and potentially separate the epitaxial semiconductor material of the source or drain regions formed below the location of the conductive source or drain contacts 588. Where conductive source or drain contacts 588 have already been formed, the epitaxial semiconductor material of the source or drain regions may include silicided portions.

[0071] Figures 6A-6C Cross-sectional views of comparative integrated circuit structures according to embodiments of the present disclosure are shown. Figure 6A Indicates the conventional plug-first method. Figure 6B Represents the selective metal gate cut method. Figure 6C Represents the non-selective metal gate cut method.

[0072] refer to Figure 6A , the integrated circuit structure 600 includes a dielectric gate plug 614 between a dielectric spacer 617 and a conductive source or drain contact 618 . Figure 6A The cross-sectional view may be corresponding to Figure 2A 、 3A, 4A or 5A. In an embodiment, the dielectric gate plug 614 includes a cavity, such as to form a plug including an air gap, such as in combination with Figures 1E-1K The public.

[0073] refer to Figure 6B , the integrated circuit structure 650 includes a dielectric gate plug 664 between a dielectric spacer 667 and a conductive source or drain contact 668 . Figure 6B The cross-sectional view may be corresponding to Figure 2B 、 3B , 4B or 5B. In an embodiment, the dielectric gate plug 664 includes a cavity, such as to form a plug including an air gap, such as in combination with Figures 1E-1K The public.

[0074] refer to Figure 6C , the integrated circuit structure 670 includes a single dielectric gate plug 684 between conductive source or drain contacts 688. The dashed box 690 shows the Figure 6B Where to align the corresponding discrete gate plug (e.g., gate plug 664) in the case of Figure 6B Where to align the non-recessed source or drain contact 668. The area between the dashed box 690 and the dashed box 692 shows the Figure 6B Where there is a dielectric spacer 667. Figure 6C The cross-sectional view may be corresponding to Figure 2B 、 3B , 4B or 5C. In an embodiment, the dielectric gate plug 684 includes a cavity, such as to form a plug including an air gap, such as in combination with Figures 1E-1K The public.

[0075] In embodiments, the metal work function can be: (a) the same metal family in NMOS and PMOS, (b) different metal families between NMOS and PMOS, and / or (c) a single material or multiple metal layers (e.g., W, TiN, TiXAlYCz, TaN, Mo, MoN). In embodiments, the metal cutting etch chemistry includes a chlorine-containing or fluorine-containing etchant, with possible additional carbon-containing or silicon-containing components providing passivation.

[0076] It should be appreciated that the embodiments described herein may also include other implementations, such as nanowires and / or nanoribbons having various widths, thicknesses, and / or materials (including but not limited to Si and SiGe). For example, III-V materials may be used.

[0077] It will be appreciated that in certain embodiments, the nanowires or nanoribbons or sacrificial intermediate layer may be composed of silicon. As used throughout, a silicon layer may be used to describe a silicon material composed of a very large amount (if not entirely) of silicon. However, it will be appreciated that, in practice, 100% pure silicon may be difficult to form and may therefore include a small percentage of carbon, germanium, or tin. Such impurities may be included as unavoidable impurities or components during silicon deposition, or may "contaminate" the silicon when diffused during post-deposition processing. Therefore, the embodiments described herein for a silicon layer may include a silicon layer that includes a relatively small amount (e.g., "impurity" level) of non-silicon atoms or substances (e.g., Ge, C, or Sn). It will be appreciated that the silicon layer as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0078] It should be appreciated that in certain embodiments, the nanowires or nanoribbons or sacrificial intermediate layer may be composed of silicon germanium. As used throughout, a silicon germanium layer may be used to describe a silicon germanium material that is composed primarily of both silicon and germanium (e.g., at least 5% of both). In some embodiments, the amount of germanium is greater than the amount of silicon. In certain embodiments, the silicon germanium layer comprises approximately 60% germanium and approximately 40% silicon (Si 40 Ge 60 In other embodiments, the amount of silicon is greater than the amount of germanium. In a particular embodiment, the silicon germanium layer comprises about 30% germanium and about 70% silicon (Si 70 Ge 30 ). It will be appreciated that, in practice, 100% pure silicon germanium (commonly referred to as SiGe) may be difficult to form and, therefore, may include minute percentages of carbon or tin. Such impurities may be included as unavoidable impurities or components during SiGe deposition, or may "contaminate" the SiGe when diffused during post-deposition processing. Accordingly, embodiments described herein involving silicon germanium layers may include silicon germanium layers that contain relatively small amounts (e.g., "impurity" levels) of non-germanium and non-silicon atoms or substances (e.g., carbon or tin). It will be appreciated that silicon germanium layers as described herein may be undoped or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0079] Described below are various devices and processing schemes that can be used to manufacture devices that can be integrated with cut metal gates. It should be appreciated that exemplary embodiments do not necessarily require all of the features described, or may include more features than described. For example, a nanowire release process can be performed by replacing the gate trench. An example of such a release process is described below. Additionally, in yet another aspect, back-end (BE) interconnect scaling may result in lower performance and higher manufacturing costs due to patterning complexity. The embodiments described herein may be implemented to achieve front-side and back-side interconnect integration of nanowire transistors. The embodiments described herein may provide methods for achieving relatively wide interconnect spacing. The result may be improved product performance and lower patterning costs. The embodiments may be implemented to achieve robust functionality of scaled nanowire or nanoribbon transistors with low power and high performance.

[0080] One or more embodiments described herein relate to bi-epitaxial (EPI) connections for nanowire or nanoribbon transistors using partial source or drain (SD) and asymmetric trench contact (TCN) depths. In an embodiment, an integrated circuit structure is fabricated by forming source-drain openings for a nanowire / nanoribbon transistor, partially filling the source-drain openings with SD epitaxy. The remaining portion of the opening is filled with a conductive material. Deep trench formation on either the source or drain side enables direct contact to a backside interconnect level.

[0081] As an exemplary process flow for manufacturing a gate-all-around device of a gate-all-around integrated circuit structure, Figures 7A-7J Cross-sectional views are illustrated illustrating various operations in a method of fabricating a gate-all-around integrated circuit structure in accordance with an embodiment of the present disclosure.

[0082] refer to Figure 7A , a method of fabricating an integrated circuit structure includes forming a starting stack comprising alternating sacrificial layers 704 and nanowires 706 over a fin 702, such as a silicon fin. Nanowires 706 may be referred to as a vertical arrangement of nanowires. As shown, a protective cap 708 may be formed over the alternating sacrificial layers 704 and nanowires 706. Also as shown, a relaxed buffer layer 752 and a defect modification layer 750 may be formed under the alternating sacrificial layers 704 and nanowires 706.

[0083] refer to Figure 7B , a gate stack 710 is formed above the vertical arrangement of horizontal nanowires 706. The vertical arrangement of the horizontal nanowires 706 is then released by removing a portion of the sacrificial layer 704 to provide a recessed sacrificial layer 704' and a cavity 712, as shown in FIG. Figure 7C As shown in .

[0084] It will be appreciated that fabrication can be accomplished without first performing the deep etch and asymmetric contact processing described below. Figure 7C In either case (e.g., with or without asymmetric contact processing), in an embodiment, the fabrication process involves using a process scheme that provides a gate-all-around integrated circuit structure with an epitaxial nub, which may be a vertically discrete source or drain structure.

[0085] refer to Figure 7D , an upper gate spacer 714 is formed at the sidewalls of the gate structure 710. A cavity spacer 716 is formed in the cavity 712 below the upper gate spacer 714. A deep trench contact etch is then optionally performed to form a trench 718 and form the recessed nanowire 706'. There may also be a patterned relaxed buffer layer 752' and a patterned defect modification layer 750', as shown.

[0086] Then, a sacrificial material 720 is formed in the trench 718, such as Figure 7E In other process schemes, an isolated trench bottom or a silicon trench bottom may be used.

[0087] refer to Figure 7F , a first epitaxial source or drain structure (e.g., left-hand feature 722) is formed at a first end of the vertical arrangement of horizontal nanowire 706'. A second epitaxial source or drain structure (e.g., right-hand feature 722) is formed at a second end of the vertical arrangement of horizontal nanowire 706'. In an embodiment, as shown, epitaxial source or drain structure 722 is a vertically discrete source or drain structure and can be referred to as an epitaxial block.

[0088] Then, an interlayer dielectric (ILD) material 724 is formed on the side of the gate electrode 710 and adjacent to the source or drain structure 722, such as Figure 7G Reference Figure 7H , a replacement gate process is used to form a permanent gate dielectric 728 and a permanent gate electrode 726. The ILD material 724 is then removed, as shown in FIG. Figure 7I The sacrificial material 720 is then removed from one of the source drain locations (eg, the right hand side) to form the trench 732 , but the sacrificial material 720 is not removed from the other of the source drain locations to form the trench 730 .

[0089] refer to Figure 7J , forming a first conductive contact structure 734 coupled to the first epitaxial source or drain structure (e.g., left-hand feature 722). A second conductive contact structure 736 is formed to couple to the second epitaxial source or drain structure (e.g., right-hand feature 722). The second conductive contact structure 736 is formed deeper along the fin 702 than the first conductive contact structure 734. In an embodiment, although Figure 7JNot shown, the method further includes forming an exposed surface of a second conductive contact structure 736 at the bottom of the fin 702. The conductive contact may include a contact resistance reduction layer and a main contact electrode layer, examples of which may include Ti, Ni, Co (for the former) and W, Ru, Co (for the latter).

[0090] In an embodiment, the second conductive contact structure 736 is deeper along the fin 702 than the first conductive contact structure 734, as shown. In one such embodiment, the first conductive contact structure 734 is not along the fin 702, as shown. In another such embodiment, not shown, the first conductive contact structure 734 is partially along the fin 702.

[0091] In an embodiment, the second conductive contact structure 736 is along the entire fin 702. In an embodiment, although not shown, the second conductive contact structure 736 has an exposed surface at the bottom of the fin 702 if the bottom of the fin 702 is exposed by a backside substrate removal process.

[0092] In an embodiment, the offset gate cut method described above may be used to form Figure 7J structure or Figures 7A-7J The relevant structure of .

[0093] On the other hand, in order to be able to reach both conductive contact structures in a pair of asymmetric source and drain contact structures, the integrated circuit structure described herein can be manufactured using a backside exposure manufacturing method of a frontside structure. In some exemplary embodiments, the exposure of the backside of a transistor or other device structure requires wafer-level backside processing. Compared to conventional TSV-type technology, the exposure of the backside of a transistor as described herein can be performed at the density of a device cell and even within a sub-region of a device. In addition, such exposure of the backside of the transistor can be performed to substantially remove all of the donor substrate on which the device layer is disposed during frontside device processing. As a result, micron-deep TSVs become unnecessary, where the thickness of the semiconductor in the device cell after the backside of the transistor is exposed may be only tens or hundreds of nanometers.

[0094] The exposure technology described herein can enable a paradigm shift from "bottom-up" device manufacturing to "center-out" manufacturing, where the "center" is any layer employed in front-side manufacturing, exposed from the backside, and employed again in back-side manufacturing. Processing of the front side and exposed backside of the device structure can address many of the challenges associated with manufacturing 3D ICs when relying primarily on front-side processing.

[0095] The method of revealing the back side of the transistor can be used, for example, to remove at least a portion of the carrier layer and the intermediate layer of the donor-host substrate assembly. The process flow begins with the input of the donor-host substrate assembly. A thickness of the carrier layer in the donor-host substrate is polished (e.g., CMP) and / or etched using a wet or dry (e.g., plasma) etching process. Any grinding, polishing and / or wet / dry etching process known to be suitable for the composition of the carrier layer can be used. For example, in the case where the carrier layer is a Group IV semiconductor (e.g., silicon), a CMP slurry known to be suitable for thinning semiconductors can be used. Similarly, any wet etchant or plasma etching process known to be suitable for thinning Group IV semiconductors can also be used.

[0096] In some embodiments, prior to the above steps, the carrier layer is split along a fracture plane substantially parallel to the intermediate layer. The splitting or fracture process can be used to remove a large portion of the carrier layer as a bulk, thereby reducing the polishing or etching time required to remove the carrier layer. For example, in the case where the carrier layer has a thickness of 400-900 μm, 100-700 μm can be split by implementing any blanket implant known to facilitate wafer-level fracture. In some exemplary embodiments, light elements (e.g., H, He, or Li) are implanted to a uniform target depth of the desired fracture plane within the carrier layer. After such a splitting process, the thickness of the carrier layer remaining in the donor-host substrate assembly can then be polished or etched to complete the removal. Alternatively, in the case where the carrier layer is not fractured, grinding, polishing, and / or etching operations can be used to remove a greater thickness of the carrier layer.

[0097] Next, the exposure of the intermediate layer is detected. Detection is used to identify the point when the backside surface of the donor substrate has advanced close to the device layer. Any endpoint detection technique known to be suitable for detecting the transition between the materials used for the carrier layer and the intermediate layer can be practiced. In some embodiments, one or more endpoint criteria are based on detecting changes in optical absorption or emission of the backside surface of the donor substrate during the polishing or etching performance. In some other embodiments, the endpoint criteria are associated with changes in optical absorption or emission of byproducts during the polishing or etching of the backside surface of the donor substrate. For example, the absorption or emission wavelength associated with the carrier layer etching byproducts can change depending on the different compositions of the carrier layer and the intermediate layer. In other embodiments, the endpoint criteria are associated with changes in the mass of substances in the byproducts of polishing or etching the backside surface of the donor substrate. For example, the byproducts of the process can be sampled by a quadrupole mass analyzer, and the changes in the mass of the substances can be related to the different compositions of the carrier layer and the intermediate layer. In another exemplary embodiment, the endpoint criteria are associated with changes in friction between the backside surface of the donor substrate and the polishing surface in contact with the backside surface of the donor substrate.

[0098] In cases where the removal process is selective for the carrier layer relative to the intermediate layer, detection of the intermediate layer can be enhanced because non-uniformities in the carrier removal process can be mitigated by the difference in etch rates between the carrier layer and the intermediate layer. If the grinding, polishing, and / or etching operation removes the intermediate layer at a rate sufficiently lower than the rate at which the carrier layer is removed, detection can even be skipped. If an endpoint criterion is not employed, then if the thickness of the intermediate layer is sufficient to achieve etch selectivity, then the grinding, polishing, and / or etching operation of a predetermined fixed duration can be stopped at the intermediate layer material. In some examples, the carrier etch rate:intermediate layer etch rate is 3:1-10:1 or greater.

[0099] When exposing the intermediate layer, at least a portion of the intermediate layer can be removed. For example, one or more component layers of the intermediate layer can be removed. For example, a thickness of the intermediate layer can be uniformly removed by polishing. Alternatively, a thickness of the intermediate layer can be removed using a masking or blanket etching process. This process can employ the same polishing or etching process as the process used to thin the carrier, or it can be a different process with different process parameters. For example, where the intermediate layer provides an etch stop for the carrier removal process, the latter operation can employ a different polishing or etching process that favors the removal of the intermediate layer relative to the removal of the device layer. Where the intermediate layer thickness is to be removed to a value less than a few hundred nanometers, the removal process can be relatively slow, optimized for cross-wafer uniformity, and more precisely controlled than the process used to remove the carrier layer. The CMP process employed can, for example, employ a slurry that provides very high selectivity (e.g., 100:1-300:1 or higher) between a semiconductor (e.g., silicon) and a dielectric material (e.g., SiO) surrounding the device layer and embedded within the intermediate layer, for example, to serve as electrical isolation between adjacent device regions.

[0100] For embodiments in which the device layer is exposed by completely removing the intermediate layer, backside processing can begin on the exposed backside of the device layer or a specific device region therein. In some embodiments, the backside device layer processing includes further polishing or wet / dry etching through the thickness of the device layer disposed between the intermediate layer and a device region previously fabricated in the device layer (e.g., a source region or a drain region).

[0101] In some embodiments where wet and / or plasma etching is used to recess the backside of the carrier layer, the intermediate layer, or the device layer, such etching may be a patterned etch or material selective etch that imparts significant non-planarity or topography to the backside surface of the device layer. As further described below, patterning may be within a device cell (i.e., "intra-cell" patterning) or may span a device cell (i.e., "inter-cell" patterning). In some patterned etch embodiments, at least a portion of the thickness of the intermediate layer is used as a hard mask for patterning the backside device layer. Thus, the shielded etch process may be performed prior to etching the corresponding shielded device layer.

[0102] The above-described processing scheme can produce a donor-host substrate assembly including an IC device having a backside of an intermediate layer, a backside of a device layer, and / or a backside of one or more semiconductor regions within a device layer, and / or exposed frontside metallization. Additional backside processing of any of these exposed regions can then be performed during downstream processing.

[0103] It should be appreciated that the structures produced by the exemplary processing schemes described above can be used in the same or similar form for subsequent processing operations to complete device fabrication, such as PMOS and / or NMOS device fabrication. As examples of completed devices, Figure 8 A cross-sectional view of a non-planar integrated circuit structure taken along a gate line according to an embodiment of the present disclosure is shown.

[0104] refer to Figure 8 , the semiconductor structure or device 800 includes a non-planar active region (e.g., a fin structure including a protruding fin portion 804 and a sub-fin region 805) within a trench isolation region 806. In an embodiment, instead of a solid fin, the non-planar active region is divided into nanowires (e.g., nanowires 804A and 804B) above the sub-fin region 805, as shown by the dashed lines. In either case, for ease of describing the non-planar integrated circuit structure 800, the non-planar active region 804 is referred to as the protruding fin portion below. In an embodiment, the sub-fin region 805 also includes a relaxed buffer layer 842 and a defect modification layer 840, as shown.

[0105] The gate line 808 is disposed over the protruding portion 804 of the non-planar active area (including the surrounding nanowires 804A and 804B, if applicable), and over a portion of the trench isolation region 806. As shown, the gate line 808 includes a gate electrode 850 and a gate dielectric layer 852. In one embodiment, the gate line 808 may also include a dielectric cap layer 854. Also visible from this view are the gate contact 814 and the gate contact via 816 thereover, as well as the metal interconnect 860 thereover, all of which are disposed in an interlayer dielectric stack or layer 870. Figure 8 It can also be seen from the perspective that in one embodiment, the gate contact 814 is disposed above the trench isolation region 806 but not above the non-planar active region. In another embodiment, the gate contact 814 is above the non-planar active region.

[0106] In an embodiment, semiconductor structure or device 800 is a non-planar device, such as, but not limited to, a fin-FET device, a tri-gate device, a nanoribbon device, or a nanowire device. In such an embodiment, the corresponding semiconductor channel region is formed by or within a three-dimensional body. In one such embodiment, the gate electrode stack of gate line 808 surrounds at least a top surface and a pair of sidewalls of the three-dimensional body.

[0107] Likewise Figure 8 As depicted in FIG, in an embodiment, an interface 880 exists between the protruding fin portion 804 and the sub-fin region 805. Interface 880 can be a transition region between the doped sub-fin region 805 and the lightly doped or undoped upper fin portion 804. In one such embodiment, each fin is approximately 10 nanometers wide or less, and sub-fin dopants are optionally supplied from an adjacent solid-state doping layer at the sub-fin location. In a particular such embodiment, each fin is less than 10 nanometers wide.

[0108] Although not in Figure 8 , but it will be appreciated that the source or drain regions of or adjacent to the protruding fin portion 804 are on either side of the gate line 808, i.e., in and out of the page. In one embodiment, the material of the protruding fin portion 804 in the source or drain position is removed and replaced with another semiconductor material, for example, by epitaxial deposition to form an epitaxial source or drain structure. The source or drain region may extend below the height of the dielectric layer of the trench isolation region 806, i.e., into the sub-fin region 805. According to embodiments of the present disclosure, the more heavily doped sub-fin region (i.e., the doped portion of the fin below the interface 880) suppresses source to drain leakage through that portion of the bulk semiconductor fin. In an embodiment, the source and drain regions have associated asymmetric source and drain contact structures, as described above in conjunction with Figure 7J As stated.

[0109] Reference again Figure 8 In an embodiment, fins 804 / 805 (and possibly nanowires 804A and 804B) are composed of a crystalline silicon germanium layer, which may be doped with charge carriers such as, but not limited to, phosphorus, arsenic, boron, gallium, or combinations thereof.

[0110] In an embodiment, the trench isolation region 806 and the trench isolation regions described throughout (trench isolation structures or trench isolation layers) may be formed of a material suitable for ultimately electrically isolating a portion of the permanent gate structure from the underlying bulk substrate, or facilitating isolation of a portion of the permanent gate structure from the underlying bulk substrate, or isolating an active region formed in the underlying bulk substrate (e.g., isolating the fin active region). For example, in one embodiment, the trench isolation region 806 is formed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0111] The gate line 808 can be formed from a gate electrode stack including a gate dielectric layer 852 and a gate electrode layer 850. In an embodiment, the gate electrode of the gate electrode stack is formed from a metal gate, and the gate dielectric layer is formed from a high-k material. For example, in one embodiment, the gate dielectric layer 852 is formed from a material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. In addition, a portion of the gate dielectric layer 852 can include a native oxide layer formed from the top layers of the substrate fin 804. In an embodiment, the gate dielectric layer 852 is composed of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer 852 is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In some embodiments, a portion of the gate dielectric is a "U" shaped structure including a bottom portion substantially parallel to a surface of the substrate and two sidewall portions substantially perpendicular to a top surface of the substrate.

[0112] In one embodiment, the gate electrode layer 850 is composed of a metal layer, such as, but not limited to, a metal nitride, a metal carbide, a metal silicide, a metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or a conductive metal oxide. In a specific embodiment, the gate electrode layer 850 is composed of a non-work function setting fill material formed above a metal work function setting layer. Depending on whether the transistor is a PMOS or NMOS transistor, the gate electrode layer 850 can be composed of a P-type work function metal or an N-type work function metal. In some embodiments, the gate electrode layer 850 can be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a conductive fill layer. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, tungsten, and conductive metal oxides, such as ruthenium oxide. The P-type metal layer will enable the formation of a PMOS gate electrode with a work function between approximately 4.9 eV and approximately 5.2 eV. For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. The N-type metal layer will enable the formation of an NMOS gate electrode with a work function between about 3.9 eV and about 4.2 eV. In some embodiments, the gate electrode may be composed of a "U"-shaped structure comprising a bottom substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another embodiment, at least one of the metal layers forming the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include a sidewall portion substantially perpendicular to the top surface of the substrate. In another embodiment of the present disclosure, the gate electrode may be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0113] The spacers associated with the gate electrode stack can be composed of a material suitable for ultimately electrically isolating the permanent gate structure from adjacent conductive contacts (e.g., self-aligned contacts) or facilitating isolation of the permanent gate structure from adjacent conductive contacts. For example, in one embodiment, the spacers are composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0114] The gate contact 814 and the gate contact via 816 thereover can be made of a conductive material. In an embodiment, one or more of the contacts or vias are made of a metallic substance. The metallic substance can be a pure metal, such as tungsten, nickel, or cobalt, or an alloy, such as a metal-metal alloy or a metal-semiconductor alloy (e.g., such as a silicide material).

[0115] In an embodiment (although not shown), a contact pattern is formed that is substantially perfectly aligned with the existing gate pattern 808 while eliminating the use of a photolithography step with a very tight registration budget. In an embodiment, the contact pattern is a vertically symmetric contact pattern, or such as a combination of Figure 7J Asymmetric contact patterns are described. In other embodiments, all contacts are front-side connected and are asymmetric. In one such embodiment, a self-aligned approach enables the use of inherently highly selective wet etching (e.g., relative to conventionally implemented dry or plasma etching) to generate contact openings. In an embodiment, the contact pattern is formed by utilizing an existing gate pattern in combination with a contact plug lithography operation. In one such embodiment, the method enables the elimination of the need for lithography operations that are critical to generating the contact pattern as used in conventional methods. In an embodiment, the trench contact grid is not patterned separately, but rather the trench contact grid is formed between the polysilicon (gate) lines. For example, in one such embodiment, the trench contact grid is formed after the gate grid is patterned but before the gate grid is cut.

[0116] In an embodiment, providing structure 800 involves manufacturing gate stack structure 808 by a replacement gate process. In such an approach, dummy gate material, such as polysilicon or silicon nitride pillar material, can be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, rather than carrying over the permanent gate dielectric layer from an earlier process. In an embodiment, the dummy gate is removed by a dry etch or wet etch process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed using a dry etch process including the use of SF6. In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed using a wet etch process including the use of an aqueous solution of NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is composed of silicon nitride and is removed using a wet etch including an aqueous solution of phosphoric acid.

[0117] Reference again Figure 8 , the arrangement of the semiconductor structure or device 800 places the gate contact above the isolation region. Such an arrangement may be considered an inefficient use of layout space. However, in another embodiment, the semiconductor device has a contact structure that contacts a portion of the gate electrode that is formed above the active region (e.g., above the fin 805) and is in the same layer as the trench contact via.

[0118] In an embodiment, the offset gate cut method described above may be used to form Figure 8 structure.

[0119] It should be appreciated that not all aspects of the above-described processes need to be practiced to fall within the spirit and scope of the embodiments of the present disclosure. In addition, the processes described herein can be used to manufacture one or more semiconductor devices. The semiconductor device can be a transistor or similar device. For example, in an embodiment, the semiconductor device is a metal oxide semiconductor (MOS) transistor for logic or memory, or a bipolar transistor. In addition, in an embodiment, the semiconductor device has a three-dimensional architecture, such as a nanowire device, a nanoribbon device, a tri-gate device, an independently accessed dual-gate device, or a FIN-FET. One or more embodiments may be particularly useful for manufacturing semiconductor devices at sub-10 nanometer (10nm) technology nodes.

[0120] In an embodiment, as used throughout this specification, an interlayer dielectric (ILD) material is composed of or includes a layer of dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, silicon oxides (e.g., silicon dioxide (SiO2)), doped silicon oxides, fluorinated silicon oxides, carbon-doped silicon oxides, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed by conventional techniques, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

[0121] In an embodiment, as also used throughout this specification, metal lines or interconnect materials (and via materials) are made of one or more metals or other conductive structures. Common examples are structures using copper wires and a barrier layer that may or may not be included between copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of various metals. For example, a metal interconnect may include a barrier layer (e.g., a layer comprising one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, etc. Therefore, the interconnect may be a single material layer, or may be formed by multiple layers comprising a conductive liner layer and a filling layer. Any suitable deposition process such as electroplating, chemical vapor deposition, or physical vapor deposition may be used to form the interconnect. In an embodiment, the interconnect is made of a conductive material, such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or its alloys. Interconnects are sometimes also referred to as traces, wires, lines, metals, or simply interconnects in the art.

[0122] In an embodiment, as also used throughout this specification, the hard mask material, cap layer, or plug is composed of a dielectric material different from the interlayer dielectric material. In one embodiment, different hard mask, cap material, or plug materials may be used in different regions to provide different growth or etch selectivities to each other and to the underlying dielectric and metal layers. In some embodiments, the hard mask layer, cap layer, or plug layer comprises a silicon nitride layer (e.g., silicon nitride) or a silicon oxide layer, or both, or a combination thereof. Other suitable materials may include carbon-based materials. Depending on the specific embodiment, other hard mask, cap layer, or plug layer known in the art may be used. The hard mask, cap layer, or plug layer may be formed by CVD, PVD, or by other deposition methods.

[0123] In an embodiment, as also used throughout this specification, the photolithography operations are performed using 193 nm immersion lithography (i193), EUV and / or EBDW lithography, etc. Positive or negative resists may be used. In one embodiment, the photolithography mask is a three-layer mask consisting of a topography shielding portion, an anti-reflective coating (ARC), and a photoresist layer. In a specific embodiment of this invention, the topography shielding portion is a carbon hard mask (CHM) layer, and the anti-reflective coating is a silicon ARC layer.

[0124] On the other hand, one or more embodiments relate to adjacent semiconductor structures or devices separated by a self-aligned gate end cap (SAGE) structure. Specific embodiments may relate to the integration of multi-width (multi-Wsi) nanowires and nanoribbons in a SAGE architecture and separated by SAGE walls. In an embodiment, the nanowires / nanoribbons are integrated with multi-Wsi in the SAGE architecture portion of the front-end process flow. Such a process flow may involve the integration of nanowires and nanoribbons of different Wsi to provide robust functionality of next generation transistors with low power and high performance. Associated epitaxial source or drain regions may be embedded (e.g., removing portions of the nanowires and then performing source or drain (S / D) growth).

[0125] To provide further context, the advantages of the self-aligned gate endcap (SAGE) architecture can include the ability to achieve higher layout density, particularly diffusion-to-diffusion spacer scaling. To provide an illustrative comparison, Figure 9 Shown are cross-sectional views taken through nanowires and fins of a non-endcap architecture (left-hand side (a)) and a self-aligned gate endcap (SAGE) architecture (right-hand side (b)) according to embodiments of the present disclosure.

[0126] refer to Figure 9On the left-hand side (a) of FIG, integrated circuit structure 900 includes a substrate 902 having a fin 904 that protrudes from substrate 902 by an amount 906 above an isolation structure 908 that laterally surrounds the lower portion of fin 904. The upper portion of the fin may include a relaxed buffer layer 922 and a defect modification layer 920, as shown. A corresponding nanowire 905 is located above fin 904. A gate structure may be formed over integrated circuit structure 900 to fabricate a device. However, such discontinuities in the gate structure may be accommodated by increasing the spacing between the fin 904 / nanowire 905 pairs.

[0127] In comparison, reference Figure 9 On the right-hand side (b) of FIG, integrated circuit structure 950 includes a substrate 952 having a fin 954 protruding from substrate 952 by an amount 956 above an isolation structure 958 that laterally surrounds the lower portion of fin 954. The upper portion of the fin may include a relaxed buffer layer 972 and a defect modification layer 970, as shown. Corresponding nanowires 955 are located above fin 954. Isolation SAGE walls 960 (which may include a hard mask thereon, as shown) are included within isolation structure 952 and between adjacent fin 954 / nanowire 955 pairs. The distance between isolation SAGE walls 960 and the nearest fin 954 / nanowire 955 pair defines a gate endcap spacer 962. Gate structures may be formed above integrated circuit structure 900 between isolation SAGE walls to fabricate devices. The discontinuity in this gate structure is imposed by the isolation SAGE walls. Because isolation SAGE walls 960 are self-aligned, limitations from conventional methods can be minimized, enabling more aggressive diffusion into the diffusion spacer. Furthermore, since the gate structure includes interruptions at all locations, the various gate structure portions can be layered together via local interconnects formed above the isolation SAGE walls 960. In an embodiment, as shown, the SAGE walls 960 each include a lower dielectric portion and a dielectric cap on the lower dielectric portion. Figure 9 The fabrication process of the associated structure involves using a process scheme that provides a gate-all-around integrated circuit structure with an epitaxial source or drain structure.

[0128] In an embodiment, an offset gate cut method, such as that described above, may be used to form Figure 9 In an embodiment, the offset gate cut method, such as that described above, may be used to form Figure 9 The structure of part (b).

[0129] A self-aligned gate endcap (SAGE) process involves forming a gate / trench contact endcap that is self-aligned with the fin, without requiring additional length to account for mask misalignment. Thus, embodiments can be implemented to enable a reduction in transistor layout area. Embodiments described herein can involve fabricating a gate endcap isolation structure, which can also be referred to as a gate wall, an isolation gate wall, or a self-aligned gate endcap (SAGE) wall.

[0130] In an exemplary processing scheme for a structure having SAGE walls separating adjacent devices, Figure 10 Cross-sectional views representing various operations in a method of fabricating a self-aligned gate end cap (SAGE) structure having a gate-all-around device are illustrated in accordance with an embodiment of the present disclosure.

[0131] refer to Figure 10 1004 , a nanowire patterned stack 1006 is formed over the nanowire patterned stack 1004. The nanowire patterned stack 1004 includes alternating sacrificial layers 1010 and nanowire layers 1012, which may be over a relaxed buffer layer 1082 and a defect modification layer 1080, as shown. A protective mask 1014 is between the nanowire patterned stack 1004 and the photolithographic patterned stack 1006. In one embodiment, the photolithographic patterned stack 1006 is a triple-layer mask consisting of a topography shielding portion 1020, an anti-reflective coating (ARC) 1022, and a photoresist layer 1024. In a particular embodiment of this invention, the topography shielding portion 1020 is a carbon hard mask (CHM) layer, and the anti-reflective coating 1022 is a silicon ARC layer.

[0132] refer to Figure 10 The stack of portion (b), portion (a) is photolithographically patterned and then etched to provide an etched structure including a patterned substrate 1002 and trenches 1030.

[0133] refer to Figure 10 1. In part (c), the structure of part (b) has an isolation layer 1040 and a SAGE material 1042 formed in the trench 1030. The structure is then planarized to leave the patterned topographical masking layer 1020' as an exposed upper layer.

[0134] refer to Figure 10 In portion (d), the isolation layer 1040 is recessed below the upper surface of the patterned substrate 1002 , for example, to define a protruding fin portion and provide a trench isolation structure 1041 below the SAGE wall 1042 .

[0135] refer to Figure 10 In the portion (e), the sacrificial layer 1010 is removed at least in the channel region to release the nanowires 1012A and 1012B. Figure 10 After forming the structure of portion (e), a gate stack can be formed around nanowire 1012B or 1012A, over the protruding fin of substrate 1002, and between SAGE walls 1042. In one embodiment, the remaining portion of protective mask 1014 is removed before forming the gate stack. In another embodiment, the remaining portion of protective mask 1014 is retained as an insulating fin cap as an artifact of the processing scheme.

[0136] Reference again Figure 10 1012A ) . Figure 10 According to an embodiment of the present disclosure, the structure of the nanowires is shown in FIG. Figure 10 The fabrication process of the associated structure involves using a process scheme that provides a gate-all-around integrated circuit structure with an epitaxial source or drain structure.

[0137] In an embodiment, an offset gate cut method, such as that described above, may be used to form Figure 10 The structure of part (e).

[0138] In an embodiment, as described throughout, a self-aligned gate end cap (SAGE) isolation structure can be composed of one or more materials suitable for ultimately electrically isolating portions of a permanent gate structure from one another, or facilitating isolation of portions of a permanent gate structure from one another. Exemplary materials or material combinations include single-material structures such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride. Other exemplary materials or material combinations include multilayer stacks having a lower portion of silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride and an upper portion of a higher dielectric constant material (e.g., hafnium oxide).

[0139] To highlight an exemplary integrated circuit structure with three vertically arranged nanowires, Figure 11A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure is shown. Figure 11B Shows the intersection along the a-a' axis Figure 11A A cross-sectional source or drain view of a nanowire-based integrated circuit structure. Figure 11C Shows the intersection along the bb' axis Figure 11ACross-sectional channel view of a nanowire-based integrated circuit structure.

[0140] refer to Figure 11A , the integrated circuit structure 1100 includes one or more vertically stacked nanowires (1104 groups) above a substrate 1102. In an embodiment, as depicted, a relaxed buffer layer 1102C, a defect modification layer 1102B, and a lower substrate portion 1102A are included in the substrate 1102, as shown. For illustrative purposes, in order to emphasize the nanowire portion, the optional fin located below the bottommost nanowire and formed from the substrate 1102 is not shown. The embodiments herein are directed to both single-wire devices and multi-wire devices. As an example, a three-nanowire-based device having nanowires 1104A, 1104B, and 1104C is shown for illustrative purposes. For ease of description, nanowire 1104A is used as an example, where the description focuses on one of the nanowires. It should be appreciated that where the properties of one nanowire are described, embodiments based on multiple nanowires may have the same or substantially the same properties for each nanowire.

[0141] Each nanowire 1104 includes a channel region 1106 in the nanowire. The channel region 1106 has a length (L). Figure 11C , the channel region also has a perimeter (Pc) orthogonal to the length (L). Figure 11A and Figure 11C In both cases, the gate electrode stack 1108 surrounds the entire perimeter (Pc) of each channel region 1106. The gate electrode stack 1108 includes a gate electrode and a gate dielectric layer (not shown) located between the channel region 1106 and the gate electrode. In an embodiment, the channel region is discrete because it is completely surrounded by the gate electrode stack 1108 without any intervening materials, such as underlying substrate material or overlying channel fabrication materials. Therefore, in an embodiment having multiple nanowires 1104, the channel regions 1106 of the nanowires are also discrete relative to each other.

[0142] refer to Figure 11A and 11BIn both cases, the integrated circuit structure 1100 includes a pair of non-discrete source or drain regions 1110 / 1112. The pair of non-discrete source or drain regions 1110 / 1112 are on either side of a channel region 1106 of a plurality of vertically stacked nanowires 1104. Furthermore, the pair of non-discrete source or drain regions 1110 / 1112 abut the channel regions 1106 of the plurality of vertically stacked nanowires 1104. In one such embodiment, not depicted, the pair of non-discrete source or drain regions 1110 / 1112 directly vertically abut the channel regions 1106 because epitaxial growth is on and between nanowire portions that extend beyond the channel regions 1106, with nanowire ends shown within the source or drain structure. In another embodiment, as Figure 11A As shown in FIG, the pair of non-discrete source or drain regions 1110 / 1112 indirectly vertically adjoin the channel region 1106 because the pair of non-discrete source or drain regions 1110 / 1112 are formed at the ends of the nanowires rather than between the nanowires.

[0143] In an embodiment, as depicted, the source or drain regions 1110 / 1112 are non-discrete in that there is not a separate and discrete source or drain region for each channel region 1106 of the nanowire 1104. Thus, in an embodiment having multiple nanowires 1104, the source or drain regions 1110 / 1112 of the nanowires are global or unified source or drain regions, rather than being discrete for each nanowire. That is, the non-discrete source or drain regions 1110 / 1112 are global, and more specifically, for more than one discrete channel region 1106, in the sense that a single unified feature is used as the source or drain region for multiple (in this case, three) nanowires 1104. In one embodiment, each of a pair of non-discrete source or drain regions 1110 / 1112 is approximately rectangular in shape, having a bottom tapered portion and a top apex portion, as seen from a cross-sectional perspective orthogonal to the length of the discrete channel region 1106. Figure 11B However, in other embodiments, the source or drain regions 1110 / 1112 of the nanowire are relatively large, but separate, non-vertically merged epitaxial structures, such as those incorporating Figures 7A-7J Description block.

[0144] According to the embodiments of the present disclosure, and as Figure 11A and 11BAs depicted in FIG, the integrated circuit structure 1100 further includes a pair of contacts 1114, each contact 1114 being on one of the pair of non-discrete source or drain regions 1110 / 1112. In one such embodiment, each contact 1114 completely surrounds the corresponding non-discrete source or drain region 1110 / 1112 in a vertical sense. On the other hand, the entire perimeter of the non-discrete source or drain region 1110 / 1112 may not be available for contact with the contacts 1114, and the contacts 1114 therefore only partially surround the non-discrete source or drain region 1110 / 1112, as shown in FIG. Figure 11B In a comparative embodiment not depicted, the entire perimeter of the non-discrete source or drain region 1110 / 1112 (as taken along the aa′ axis) is surrounded by the contact 1114 .

[0145] Reference again Figure 11A In an embodiment, the integrated circuit structure 1100 further includes a pair of spacers 1116. As depicted, outer portions of the pair of spacers 1116 can overlap portions of the non-discrete source or drain regions 1110 / 1112, thereby providing "embedded" portions of the non-discrete source or drain regions 1110 / 1112 beneath the pair of spacers 1116. Also as depicted, the embedded portions of the non-discrete source or drain regions 1110 / 1112 may not extend beneath the entirety of the pair of spacers 1116.

[0146] Substrate 1102 can be made of a material suitable for integrated circuit structure fabrication. In one embodiment, substrate 1102 includes a lower bulk substrate made of a single crystal material, which may include but is not limited to silicon, germanium, silicon germanium, germanium tin, silicon germanium tin, or a III-V compound semiconductor material. An upper insulator layer made of a material that may include but is not limited to silicon dioxide, silicon nitride, or silicon oxynitride is on the lower bulk substrate. Thus, structure 1100 can be manufactured from a starting semiconductor-on-insulator substrate. Alternatively, structure 1100 is formed directly from the bulk substrate, and local oxidation is used to form an electrically insulating portion in place of the upper insulator layer. In another optional embodiment, structure 1100 is formed directly from the bulk substrate, and doping is used to form electrically isolated active regions, such as nanowires, thereon. In one such embodiment, the first nanowire (i.e., close to the substrate) is in the form of an Ω-FET type structure.

[0147] In an embodiment, the dimensions of the nanowires 1104 may be designed as wires or ribbons as described below and may have square or rounded corners. In an embodiment, the nanowires 1104 are composed of materials such as, but not limited to, silicon, germanium, or a combination thereof. In one such embodiment, the nanowires are single crystalline. For example, for silicon nanowires 1104, the single crystalline nanowires may be based on a (100) global orientation, for example, having a z-direction of <100> As discussed below, other orientations are also contemplated. In embodiments, nanowires 1104 have nanometer-scale dimensions when viewed in cross-section. For example, in certain embodiments, the smallest dimension of nanowires 1104 is less than approximately 20 nanometers. In embodiments, nanowires 1104 are composed of strained material, particularly in channel region 1106.

[0148] refer to Figure 11C In an embodiment, each channel region 1106 has a width (Wc) and a height (Hc), with the width (Wc) being approximately the same as the height (Hc). That is, in both cases, the cross-sectional profile of the channel region 1106 is square, or if rounded, circular. On the other hand, the width and height of the channel region need not be the same, such as in the case of nanoribbons described throughout.

[0149] In embodiments, as described throughout, an integrated circuit structure includes a non-planar device, such as, but not limited to, a finFET or tri-gate device, having one or more corresponding overlying nanowire structures. In such embodiments, the corresponding semiconducting channel region is comprised of or formed within a three-dimensional body, wherein one or more discrete nanowire channel portions overlie the three-dimensional body. In one such embodiment, a gate structure surrounds at least a top surface and a pair of sidewalls of the three-dimensional body, and further surrounds each of the one or more discrete nanowire channel portions.

[0150] In an embodiment, an offset gate cut method, such as that described above, may be used to form Figures 11A-11C structure.

[0151] In an embodiment, as described throughout, the underlying substrate may be composed of a semiconductor material that can withstand the manufacturing process and in which charge can migrate. In an embodiment, the substrate is a bulk substrate composed of a crystalline silicon, silicon / germanium, or germanium layer doped with charge carriers (such as, but not limited to, phosphorus, arsenic, boron, gallium, or a combination thereof) to form an active region. In one embodiment, the concentration of silicon atoms in the bulk substrate is greater than 97%. In another embodiment, the bulk substrate is composed of an epitaxial layer grown on top of a different crystalline substrate (for example, a silicon epitaxial layer grown on top of a boron-doped bulk silicon single crystal substrate). The bulk substrate may optionally be composed of a III-V material. In an embodiment, the bulk substrate is composed of a III-V material, such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one embodiment, the bulk substrate is composed of a III-V material, and the charge carrier dopant impurity atoms are, for example, but not limited to, atoms of carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0152] The embodiments disclosed herein can be used to manufacture various types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, semiconductor memories can be manufactured. In addition, integrated circuits or other microelectronic devices can be used in various electronic devices known in the art, for example, in computer systems (e.g., desktop computers, laptop computers, servers), cellular phones, personal electronic products, and the like. Integrated circuits can be coupled to buses and other components in a system. For example, a processor can be coupled to a memory, a chipset, and the like via one or more buses. Each of the processor, memory, and chipset can potentially be manufactured using the methods disclosed herein.

[0153] Figure 12 A computing device 1200 is shown, according to one implementation of an embodiment of the present disclosure. Computing device 1200 houses a board 1202. Board 1202 may include multiple components, including, but not limited to, a processor 1204 and at least one communication chip 1206. Processor 1204 is physically and electrically coupled to board 1202. In some implementations, at least one communication chip 1206 is also physically and electrically coupled to board 1202. In further implementations, communication chip 1206 is part of processor 1204.

[0154] Depending on its application, the computing device 1200 may include other components that may or may not be physically and electrically coupled to the board 1202. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a cryptographic processor, a chipset, an antenna, a display, a touch screen display, a touch screen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (e.g., a hard drive, a compact disk (CD), a digital versatile disk (DVD), etc.).

[0155] The communication chip 1206 implements wireless communications for transmitting data to and from the computing device 1200. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data via a non-solid medium using modulated electromagnetic radiation. The term does not mean that the associated devices do not contain any wires, although in some embodiments they may not. The communication chip 1206 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, their derivatives, and any other wireless protocols designated as 3G, 4G, 5G and above. The computing device 1200 may include multiple communication chips 1206. For example, the first communication chip 1206 may be dedicated to shorter-range wireless communications such as Wi-Fi and Bluetooth, and the second communication chip 1206 may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0156] The processor 1204 of the computing device 1200 includes an integrated circuit die packaged within the processor 1204. The integrated circuit die of the processor 1204 may include one or more structures constructed according to implementations of the present disclosure, for example, a gate-all-around integrated circuit structure having a uniform grid metal gate and trench contact cuts interposed with air gap structures. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory.

[0157] The communication chip 1206 also includes an integrated circuit die packaged within the communication chip 1206. The integrated circuit die of the communication chip 1206 may include one or more structures constructed according to implementations of the present disclosure, such as a gate-all-around integrated circuit structure having a uniform grid metal gate and trench contact cuts interspersed with air gap structures.

[0158] In further embodiments, another component housed within the computing device 1200 may include an integrated circuit die comprising one or more structures constructed in accordance with embodiments of the present disclosure, such as a gate-all-around integrated circuit structure having a uniform grid metal gate and trench contact cuts interspersed with air gap structures.

[0159] In various embodiments, computing device 1200 may be a laptop computer, a netbook, a notebook, an ultrabook, a smartphone, a tablet computer, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further embodiments, computing device 1200 may be any other electronic device that processes data.

[0160] Figure 13 An interposer 1300 is shown that includes one or more embodiments of the present disclosure. Interposer 1300 is an intermediate substrate used to bridge a first substrate 1302 to a second substrate 1304. First substrate 1302 can be, for example, an integrated circuit die. Second substrate 1304 can be, for example, a memory module, a computer motherboard, or another integrated circuit die. Typically, the purpose of interposer 1300 is to extend connections to a wider spacing or to reroute connections to different connections. For example, interposer 1300 can couple an integrated circuit die to a ball grid array (BGA) 1306, which can then be coupled to second substrate 1304. In some embodiments, first substrate 1302 and second substrate 1304 are attached to opposite sides of interposer 1300. In other embodiments, first substrate 1302 and second substrate 1304 are attached to the same side of interposer 1300. And in other embodiments, three or more substrates are interconnected via interposer 1300.

[0161] The interposer 1300 may be formed from epoxy, glass fiber reinforced epoxy, ceramic material, or polymer material such as polyimide. In other embodiments, the interposer 1300 may be formed from alternative rigid or flexible materials, which may include the same materials described above for semiconductor substrates, such as silicon, germanium, and other III-V and IV materials.

[0162] Interposer 1300 may include metal interconnects 1308 and vias 1310, including but not limited to through-silicon vias (TSVs) 1312. Interposer 1300 may also include embedded devices 1314, including both passive and active devices. Such devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on interposer 1300. According to embodiments of the present disclosure, the apparatus or process disclosed herein may be used in the manufacture of interposer 1300 or the manufacture of components included in interposer 1300.

[0163] Therefore, embodiments of the present disclosure include integrated circuit structures having uniform grid metal gates and trench contact cuts interposed with air gap structures, and methods of fabricating integrated circuit structures having uniform grid metal gates and trench contact cuts interposed with air gap structures.

[0164] The above description of the illustrated implementations of the embodiments of the present disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Although specific implementations and examples of the present disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure, as will be appreciated by those skilled in the relevant art.

[0165] These modifications may be made to the present disclosure in light of the above detailed description. The terms used in the appended claims should not be construed to limit the present disclosure to the specific implementations disclosed in the specification and claims. Rather, the scope of the present disclosure is to be determined entirely by the appended claims, which are to be construed in accordance with established doctrines of claim interpretation.

[0166] Example embodiment 1: An integrated circuit structure includes a first vertical stack of horizontal nanowires, the first vertical stack of horizontal nanowires being laterally spaced apart from a second vertical stack of horizontal nanowires. A first gate structure is above the first vertical stack of horizontal nanowires, the first gate structure including a first gate electrode and a first gate dielectric. A second gate structure is above the second vertical stack of horizontal nanowires, the second gate structure including a second gate electrode and a second gate dielectric. An insulating structure is laterally located between the first gate structure and the second gate structure, wherein the insulating structure extends from a horizontal plane above the first vertical stack of horizontal nanowires and the second stack of horizontal nanowires to a horizontal plane below the first vertical stack of horizontal nanowires and the second stack of horizontal nanowires, the insulating structure including a dielectric liner, a cavity within the dielectric liner, and a dielectric cap above the cavity, wherein the dielectric liner is in contact with the first gate electrode and the second gate electrode.

[0167] Example embodiment 2: The integrated circuit structure of Example embodiment 1, wherein the dielectric cap of the insulating structure has an uppermost surface that is at the same level as the uppermost surface of the first gate electrode and the uppermost surface of the second gate electrode.

[0168] Example embodiment 3: The integrated circuit structure of Example embodiment 1 or 2, wherein the dielectric cap is within the dielectric liner.

[0169] Example embodiment 4: The integrated circuit structure according to example embodiment 1, 2 or 3 further includes a conductive trench contact portion adjacent to the first gate structure and the second gate structure, wherein the insulating structure extends through the conductive trench contact portion.

[0170] Example embodiment 5: The integrated circuit structure according to example embodiment 4 further includes a dielectric gate spacer laterally located between the conductive trench contact portion and the first gate structure and the second gate structure, wherein the insulating structure extends through the dielectric gate spacer.

[0171] Example 6: An integrated circuit structure includes a first fin laterally spaced apart from a second fin. A first gate structure is above the first fin, the first gate structure including a first gate electrode and a first gate dielectric. A second gate structure is above the second fin, the second gate structure including a second gate electrode and a second gate dielectric. An insulating structure is laterally located between the first gate structure and the second gate structure, wherein the insulating structure extends from a horizontal plane above the first fin and the second fin to a horizontal plane below the first fin and the second fin, the insulating structure including a dielectric liner, a cavity within the dielectric liner, and a dielectric cap above the cavity, wherein the dielectric liner contacts the first gate electrode and the second gate electrode.

[0172] Example embodiment 7: The integrated circuit structure of Example embodiment 6, wherein the dielectric cap of the insulating structure has an uppermost surface that is at the same level as the uppermost surface of the first gate electrode and the uppermost surface of the second gate electrode.

[0173] Example embodiment 8: The integrated circuit structure of example embodiment 6 or 7, wherein the dielectric cap is within the dielectric liner.

[0174] Example embodiment 9: The integrated circuit structure according to example embodiment 6, 7 or 8 further includes a conductive trench contact portion adjacent to the first gate structure and the second gate structure, wherein the insulating structure extends through the conductive trench contact portion.

[0175] Example embodiment 10: The integrated circuit structure according to example embodiment 9 further includes a dielectric gate spacer laterally located between the conductive trench contact portion and the first gate structure and the second gate structure, wherein the insulating structure extends through the dielectric gate spacer.

[0176] Example embodiment 11: A computing device includes a board and a component coupled to the board. The component includes an integrated circuit structure, the integrated circuit structure including a first vertical stack of horizontal nanowires or a first fin laterally spaced apart from a second vertical stack of horizontal nanowires or a second fin. A first gate structure is located above the first vertical stack of horizontal nanowires or the first fin, the first gate structure including a first gate electrode and a first gate dielectric. A second gate structure is located above the second vertical stack of horizontal nanowires or the second fin, the second gate structure including a second gate electrode and a second gate dielectric. An insulating structure is located laterally between the first gate structure and the second gate structure, wherein the insulating structure extends from a horizontal plane above the first vertical stack of horizontal nanowires or the first fin and the second stack of horizontal nanowires or the second fin to a horizontal plane below the first vertical stack of horizontal nanowires or the first fin and the second stack of horizontal nanowires or the second fin, the insulating structure including a dielectric liner, a cavity within the dielectric liner, and a dielectric cap over the cavity, wherein the dielectric liner contacts the first gate electrode and the second gate electrode.

[0177] Example Embodiment 12: The computing device of Example Embodiment 11, comprising a first vertical stack of the horizontal nanowires and a second vertical stack of the horizontal nanowires.

[0178] Example Embodiment 13: The computing device according to Example Embodiment 11, comprising the first fin and the second fin.

[0179] Example Embodiment 14: The computing device of Example Embodiment 11, 12, or 13, further comprising a memory coupled to the board.

[0180] Example embodiment 15: The computing device according to example embodiment 11, 12, 13 or 14, further comprising a communication chip coupled to the board.

[0181] Example Embodiment 16: The computing device of Example Embodiment 11, 12, 13, 14, or 15, further comprising a battery coupled to the board.

[0182] Example Embodiment 17: The computing device of Example Embodiment 11, 12, 13, 14, 15, or 16, further comprising a camera coupled to the board.

[0183] Example Embodiment 18: The computing device of Example Embodiment 11, 12, 13, 14, 15, 16, or 17, further comprising a display coupled to the board.

[0184] Example embodiment 19: The computing device of example embodiments 11, 12, 13, 14, 15, 16, 17, or 18, wherein the component is a packaged integrated circuit die.

[0185] Example embodiment 20: The computing device of example embodiment 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is selected from the group consisting of a processor, a communication chip and a digital signal processor.

Claims

1. An integrated circuit structure comprising: a first vertical stack of horizontal nanowires, the first vertical stack of horizontal nanowires laterally spaced apart from a second vertical stack of horizontal nanowires; a first gate structure overlying the first vertical stack of horizontal nanowires, the first gate structure comprising a first gate electrode and a first gate dielectric; a second gate structure overlying the second vertical stack of horizontal nanowires, the second gate structure comprising a second gate electrode and a second gate dielectric; as well as an insulating structure laterally positioned between the first gate structure and the second gate structure, wherein the insulating structure extends from a horizontal plane above the first vertical stack of horizontal nanowires and the second stack of horizontal nanowires to a horizontal plane below the first vertical stack of horizontal nanowires and the second stack of horizontal nanowires, the insulating structure comprising a dielectric liner, a cavity within the dielectric liner, and a dielectric cap over the cavity, wherein the dielectric liner contacts the first gate electrode and the second gate electrode.

2. The integrated circuit structure according to claim 1, wherein: The dielectric cap of the insulating structure has an uppermost surface that is at the same level as an uppermost surface of the first gate electrode and an uppermost surface of the second gate electrode.

3. The integrated circuit structure according to claim 1 or 2, wherein: The dielectric cap is within the dielectric liner.

4. The integrated circuit structure according to claim 1 or 2, further comprising a conductive trench contact portion and the first gate structure and the second gate structure, wherein: The insulating structure extends through the conductive trench contact.

5. The integrated circuit structure of claim 4 , further comprising a dielectric gate spacer laterally located between the conductive trench contacts adjacent to the first gate structure and the second gate structure, wherein The insulating structure extends through the dielectric gate spacer.

6. An integrated circuit structure comprising: a first fin, the first fin being laterally spaced apart from the second fin; a first gate structure overlying the first fin, the first gate structure comprising a first gate electrode and a first gate dielectric; a second gate structure overlying the second fin, the second gate structure comprising a second gate electrode and a second gate dielectric; as well as an insulating structure laterally located between the first gate structure and the second gate structure, wherein the insulating structure extends from a horizontal plane above the first fin and the second fin to a horizontal plane below the first fin and the second fin, the insulating structure comprising a dielectric liner, a cavity within the dielectric liner, and a dielectric cap above the cavity, wherein the dielectric liner contacts the first gate electrode and the second gate electrode.

7. The integrated circuit structure according to claim 6, wherein: The dielectric cap of the insulating structure has an uppermost surface that is at the same level as an uppermost surface of the first gate electrode and an uppermost surface of the second gate electrode.

8. The integrated circuit structure according to claim 6 or 7, wherein: The dielectric cap is within the dielectric liner.

9. The integrated circuit structure according to claim 6 or 7, further comprising a conductive trench contact portion and the first gate structure and the second gate structure, wherein: The insulating structure extends through the conductive trench contact.

10. The integrated circuit structure of claim 9, further comprising a dielectric gate spacer laterally located between the conductive trench contacts adjacent to the first gate structure and the second gate structure, wherein The insulating structure extends through the dielectric gate spacer.

11. A computing device comprising: plate; as well as a component coupled to the board, the component comprising an integrated circuit structure, the integrated circuit structure comprising: a first vertical stack of horizontal nanowires or a first fin, the first vertical stack of horizontal nanowires or a first fin being laterally spaced apart from a second vertical stack of horizontal nanowires or a second fin; a first gate structure over the first vertical stack of horizontal nanowires or the first fin, the first gate structure comprising a first gate electrode and a first gate dielectric; a second gate structure over the second vertical stack of horizontal nanowires or the second fin, the second gate structure comprising a second gate electrode and a second gate dielectric; and an insulating structure laterally positioned between the first gate structure and the second gate structure, wherein the insulating structure extends from a horizontal plane above the first vertical stack of horizontal nanowires or the first fin and the second stack of horizontal nanowires or the second fin to a horizontal plane below the first vertical stack of horizontal nanowires or the first fin and the second stack of horizontal nanowires or the second fin, the insulating structure comprising a dielectric liner, a cavity within the dielectric liner, and a dielectric cap over the cavity, wherein the dielectric liner contacts the first gate electrode and the second gate electrode.

12. The computing device of claim 11, comprising a first vertical stack of the horizontal nanowires and a second vertical stack of the horizontal nanowires. The computing device of claim 11 , comprising the first fin and the second fin.

14. The computing device of claim 11, 12 or 13, further comprising: A memory is coupled to the board.

15. The computing device of claim 11, 12, or 13, further comprising: A communication chip is coupled to the board.

16. The computing device of claim 11, 12, or 13, further comprising: A battery is coupled to the board.

17. The computing device of claim 11, 12, or 13, further comprising: A camera is coupled to the board.

18. The computing device of claim 11, 12, or 13, further comprising: A display is coupled to the panel.

19. The computing device of claim 11, 12 or 13, wherein: The component is a packaged integrated circuit die.

20. The computing device of claim 11, 12, or 13, wherein: The component is selected from the group consisting of a processor, a communication chip, and a digital signal processor.

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