Clock generator and asynchronous reading circuit
By using a clock generator and an asynchronous read circuit in a coordinated design, the read control clock is dynamically adjusted to avoid data flipping periods, which solves the problem of complex structure in traditional real-time counter read circuits and achieves the effects of simplified design and improved read accuracy.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NINGBO AURA SEMICON CO LTD
- Filing Date
- 2025-06-20
- Publication Date
- 2026-08-04
AI Technical Summary
The asynchronous reading circuit structure of traditional real-time counters is complex, resulting in high hardware resource consumption and complicated design, making it difficult to guarantee the accuracy of reading when reading timing values in multiple tasks.
Design a clock generator that generates a dynamically adjusted read control clock through the coordinated operation of a clock control module, a synchronization mask module, D flip-flops, NOT gates, and AND gates. This clock avoids the data flipping period of the real-time counter, ensuring that the read task is executed when the data is not flipping.
It simplifies the circuit structure, avoids dependence on the register, improves the accuracy of the read task and the reliability of the circuit, and reduces the time consumption of SPI/IIC.
Smart Images
Figure CN120743036B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of circuit technology, specifically to a clock generator and an asynchronous readout circuit. Background Technology
[0002] A real-time counter, also known as a calendar counter, typically operates on a 1-second basis, outputting six bytes of date data: year, month, day, hour, minute, and second. In practical applications, communication protocols such as SPI (Serial Peripheral Interface), IIC (Inter-Integrated Circuit), or UART (Universal Asynchronous Receiver / Transmitter) are generally used to sample and read the data from the real-time counter into the program or software.
[0003] Taking the SPI / IIC protocol for accessing a real-time counter as an example, each read task can be divided into multi-pulse read and single-pulse read. Regardless of the method, for a single read task, the date data (which may be one byte or multiple bytes) must be able to be combined to form the actual calendar time value at the sampling point. In other words, for each read, the multiple bytes of date data read must all be specific date values within a certain second; some bytes cannot be values from the previous second and others from the next second. That is, a single read task requires reading the timed date (equivalent to fixing the counter during the read task, preventing the date data from flipping until the date data is sampled, at which point counting and flipping resumes).
[0004] On the other hand, unlike the counter clock, read tasks occur asynchronously and unpredictably. This means that asynchronous data reads can result in errors, especially when the counter output is read at its toggle point. Therefore, when reading the calendar using a single-task multi-pulse method, without special technical measures, there is a significant probability of erroneous results. With multiple consecutive read tasks, depending on system requirements, the results of multiple tasks may need to be combined to form a timed date or a real-time date.
[0005] Traditional solutions often involve delaying the SPI / IIC read pulse by a certain time before reading the calendar, generating two read pulse branches with a time difference: rd_mask_p0 and rd_mask_p1. These two pulse branches are used to sample 6 bytes of date data and store them in a buffer. Then, the relative phase difference between the counter's clock and the read pulses, combined with the SPI / IIC read information, determines which buffer's data can be loaded onto the SPI / IIC bus. This design requires at least 6xN bytes of buffer, leading to complex structure and high hardware resource consumption. Furthermore, the design becomes even more complex when multiple tasks need to read timing values. Therefore, asynchronous read circuits for real-time counters suffer from structural complexity. Summary of the Invention
[0006] In view of this, this application provides a clock generator and an asynchronous readout circuit to solve the problem of complex asynchronous readout circuit structure in traditional clock generators.
[0007] This application provides a clock generator for generating a read control clock for an asynchronous read circuit in a real-time counter; The clock generator includes a clock control module, a synchronization mask module, a first D flip-flop, a first NOT gate, and a first AND gate; The clock control module is used to access a high-frequency clock and generate a first control signal WP, a second control signal P2 and a third control signal NewRS according to the high-frequency clock. The synchronization mask module is used to receive the read start signal Read, the read stop signal Stop, the power-on signal Porb, the first control signal WP, the second control signal P2, and the third control signal NewRS, and to generate the read mask signal mask and the first clear signal keeplow; The first input terminal of the first D flip-flop is connected to the read mask signal mask, the second input terminal is connected to the second control signal P2, and the clear terminal is connected to the first clear signal keeplow, so as to generate an adjustment signal CK1HZ_low according to the read mask signal mask, the second control signal P2 and the first clear signal keeplow; The first NOT gate is used to perform a logical NOT operation on the adjustment signal CK1HZ_low, so that the adjusted signal CK1HZ_low_n after the logical NOT operation is characterized as a low level during the data toggling period of the real-time counter; The first input terminal of the first AND gate is connected to the first control signal WP, the second input terminal is connected to the adjustment signal CK1HZ_low_n after the logical NOT operation, and the output terminal outputs the read control clock so that the asynchronous read circuit avoids the data flipping period when performing the read task according to the read control clock.
[0008] Optionally, the clock control module includes a frequency divider, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a first delay unit, a second delay unit, a second NOT gate, a third NOT gate, a first NAND gate, and a second NAND gate. The input of the frequency divider is connected to the high-frequency clock, and its output is connected to the first input of the second D flip-flop. The second input of the second D flip-flop is connected to the high-frequency clock, and its output is connected to the first input of the third D flip-flop, the input of the first delay unit, and the input of the second NOT gate. The second input of the third D flip-flop is connected to the high-frequency clock, and its output is connected to the first input of the fourth D flip-flop and the first input of the second NAND gate. The second input of the fourth D flip-flop is connected to the high-frequency clock, and its output is connected to the input of the third NOT gate, and is used to output the second control signal P2. The output of the third NOT gate is connected to the second input of the second NAND gate. The output of the second NAND gate is connected to the input of the second delay unit. The output of the second delay unit is used to output the first control signal WP. The first input of the first NAND gate is connected to the output of the first delay unit, its second input is connected to the output of the second NOT gate, and its output is used to output the third control signal NewRS.
[0009] Optionally, the frequency divider includes a 16-divider.
[0010] Optionally, the synchronization mask module includes a logic processing unit, a fifth D flip-flop, an OR gate, a third delay, a fourth NOT gate, a third NAND gate, and a second AND gate. The first input of the logic processing unit is connected to a power-on signal Porb, the second input is connected to a read stop signal Stop, and the output is connected to the clear terminal of the fifth D flip-flop. The first input of the fifth D flip-flop is connected to a preset voltage, the second input is connected to the read start signal Read, and the output is connected to the first input of the OR gate. The second input of the OR gate is connected to the read start signal Read, and the output is connected to the input of the third delay and the input of the fourth NOT gate, respectively, and outputs the read mask signal mask. The first input of the third NAND gate is connected to the output of the fourth NOT gate, the second input is connected to the output of the third delay, and the output is connected to the first input of the second AND gate. The second input of the second AND gate is connected to the third control signal NewRS, the third input is connected to the power-on signal Porb, and the output outputs a first clear signal keeplow.
[0011] Optionally, the logic processing unit includes a fifth NOT gate, a sixth NOT gate, and a NOR gate; the input terminal of the fifth NOT gate serves as the first input terminal of the logic processing unit, used to receive the power-on signal, and its output terminal is connected to the first input terminal of the NOR gate; the input terminal of the sixth NOT gate serves as the second input terminal of the logic processing unit, used to receive the stop signal, and its output terminal is connected to the first input terminal of the fourth NAND gate; the output terminal of the NOR gate serves as the output terminal of the logic processing unit.
[0012] This application also provides an asynchronous readout circuit, which includes any type of clock generator.
[0013] Optionally, the asynchronous read circuit further includes a multi-channel selector, a read switch, multiple data generation units, and D flip-flops corresponding to each data generation unit; each data generation unit and its corresponding D flip-flop form a corresponding data providing unit; in each of the data providing units, the clock terminal of the corresponding D flip-flop is connected to a read control clock OUT, which is used to provide time data according to the read control clock OUT; each input terminal of the multi-channel selector is connected to the output terminal of a data providing unit, the control terminal is connected to a channel selection signal, and the output terminal outputs the time data provided by the data providing unit selected according to the channel selection signal; the read switch is used to connect the data read path of the selected data providing unit according to the read start signal.
[0014] In the clock generator and asynchronous read circuit described in this application, the clock control module, synchronization mask module, first D flip-flop, first NOT gate, and first AND gate cooperate with each other to use a high-frequency clock CLK to perform logical processing on signals such as the start signal Read and / or the read stop signal Stop, which are used to determine the data flipping period of each time data providing unit in the real-time counter. This generates a read control clock OUT whose duty cycle can be dynamically adjusted according to the data flipping period of each time data providing unit. This allows the asynchronous read circuit to avoid the data flipping period of each time data providing unit when performing the read task according to the read control clock OUT, ensuring the accuracy of the read time data and thus ensuring the reliability of the asynchronous read circuit operation. The clock generator does not require any data buffer and does not consume the time margin of SPI / IIC. It only dynamically adjusts the rising edge position of the read control clock OUT of the asynchronous read circuit so that the time data reading time avoids the data flipping period, which simplifies the related design and corresponding circuit structure. Attached Figure Description
[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0016] Figure 1 This is a schematic diagram of a clock generator structure according to an embodiment of this application; Figure 2 This is a schematic diagram of the clock control module structure according to an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a synchronization mask module according to an embodiment of this application; Figure 4 This is a schematic diagram of a clock generator structure according to an embodiment of this application; Figure 5 This is a schematic diagram of the relevant signal waveforms according to an embodiment of this application; Figure 6 This is a schematic diagram of an asynchronous read circuit structure according to an embodiment of this application. Detailed Implementation
[0017] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.
[0018] The first aspect of this application provides a clock generator for generating a read control clock OUT for an asynchronous read circuit in a real-time counter. For example, the real-time counter may include multiple time data providing units for providing data such as seconds, minutes, hours, days, months, and years. The asynchronous read circuit can read the corresponding time data from each time data providing unit according to the read control clock OUT to determine the corresponding time in real time and realize real-time counting.
[0019] refer to Figure 1 As shown, the clock generator includes a clock control module 100, a synchronization mask module 200, a first D flip-flop DFF1, a first NOT gate N1, and a first AND gate A1.
[0020] The clock control module 100 has a high-frequency clock CLK connected to its input terminal, a first output terminal connected to output a first control signal WP, a second output terminal outputting a second control signal P2, and a third output terminal outputting a third control signal NewRS. The synchronization mask module 200 has a read start signal Read connected to its first input terminal, a read stop signal Stop connected to its second input terminal, a power-on signal Porb connected to its third input terminal, a fourth input terminal connected to the first output terminal of the clock control module 100 to receive the first control signal WP, a fifth input terminal connected to the second output terminal of the clock control module 100 to receive the second control signal P2, a sixth input terminal connected to the third output terminal of the clock control module 100 to receive the third control signal NewRS, a first output terminal outputting a read mask signal mask, and a second output terminal outputting a first clear signal keeplow. The first input of the first D flip-flop DFF1 is connected to the second output of the clock control module 100 to receive the second control signal P2. The first input is also connected to the first output of the synchronization mask module 200 to receive the read mask signal mask. The clear input is connected to the second output of the synchronization mask module 200 to receive the first clear signal keeplow. The output of the first gate outputs the adjustment signal CK1HZ_low. The input of the first NOT gate N1 is connected to the output of the first D flip-flop DFF1 to receive the adjustment signal CK1HZ_low. The output of the first gate outputs the adjustment signal CK1HZ_low_n after logical NOT operation (or inversion). The first input of the first AND gate A1 is connected to the first output of the clock control module 100 to receive the first control signal WP. The second input is connected to the output of the first NOT gate N1 to receive the adjustment signal CK1HZ_low_n. The output of the first gate outputs the read control clock OUT.
[0021] The clock control module 100 is used to receive a high-frequency clock CLK and generate a first control signal WP, a second control signal P2, and a third control signal NewRS based on the high-frequency clock CLK. The third control signal NewRS includes a negative pulse that generates the rising edge of the latest time of the control clock OUT. Specifically, when the control clock OUT is continuously cleared by the adjustment signal CK1Hz_low and is approaching the level of the first control signal WP, the control clock OUT needs to be high to avoid losing the cycle. Therefore, the third control signal NewRS is designed here. The narrow negative pulse of the third control signal NewRS is generated before the falling edge of the first control signal WP. When the negative pulse of the third control signal NewRS appears, it can pull the adjustment signal CK1Hz_low low, causing the control clock OUT to start following the first control signal WP (at this time, the first control signal WP is high). Optionally, the function of the third control signal NewRS can also be understood as forcibly pulling the control clock OUT signal high.
[0022] The synchronization mask module 200 is used to receive the read start signal Read, the read stop signal Stop, the power-on signal Porb, the first control signal WP, the second control signal P2, and the third control signal NewRS, and generate the read mask signal mask and the first clear signal keeplow.
[0023] The first input terminal of the first D flip-flop DFF1 is connected to the read mask signal mask, the second input terminal is connected to the second control signal P2, and the clear terminal is connected to the first clear signal keeplow, so as to generate the adjustment signal CK1HZ_low according to the read mask signal mask, the second control signal P2 and the first clear signal keeplow.
[0024] The first NOT gate N1 is used to perform a logical NOT operation on the adjustment signal CK1HZ_low, so that the adjusted signal CK1HZ_low_n after the logical NOT operation is characterized as a low level during the data toggling period of the real-time counter.
[0025] The first input terminal of the first AND gate A1 is connected to the first control signal WP, the second input terminal is connected to the adjustment signal CK1HZ_low_n after the logical NOT operation, and the output terminal outputs the read control clock OUT. This allows the duty cycle of the read control clock OUT to be dynamically adjusted according to the data flipping period of each time data providing unit in the asynchronous reading circuit. In this way, when the asynchronous reading circuit performs the reading task according to the read control clock OUT, it can avoid the data flipping period of each time data providing unit, ensuring the accuracy of the read time data and thus ensuring the reliability of the asynchronous reading circuit.
[0026] In the aforementioned clock generator, the clock control module 100, the synchronization mask module 200, the first D flip-flop DFF1, the first NOT gate N1, and the first AND gate A1 cooperate to use a high-frequency clock CLK to perform logical processing on signals such as the start signal Read and / or the read stop signal Stop, which are used to determine the data flipping periods of each time data providing unit in the real-time counter. This generates a read control clock OUT whose duty cycle can be dynamically adjusted according to the data flipping periods of each time data providing unit. This allows the asynchronous read circuit to avoid the data flipping periods of each time data providing unit when performing the read task according to the read control clock OUT, ensuring the accuracy of the read time data and thus ensuring the reliability of the asynchronous read circuit operation. The aforementioned clock generator does not require any data buffer and does not consume the time margin of SPI / IIC. It only dynamically adjusts the rising edge position of the read control clock OUT of the asynchronous read circuit, so that the time data reading time avoids the data flipping period, which simplifies the related design and corresponding circuit structure.
[0027] In some embodiments, reference Figure 2As shown, the clock control module 100 includes a frequency divider DIV, a second D flip-flop DFF2, a third D flip-flop DFF3, a fourth D flip-flop DFF4, a first delay unit td1, a second delay unit td2, a second NOT gate N2, a third NOT gate N3, a first NAND gate NAND1, and a second NAND gate NAND2.
[0028] The input of the frequency divider DIV is connected to the high-frequency clock CLK, and its output is connected to the first input of the second D flip-flop DFF2 to input the divided signal gen to the second D flip-flop DFF2. The second input of the second D flip-flop DFF2 is connected to the high-frequency clock CLK, and its output outputs a first delayed signal P0, which is connected to the first input of the third D flip-flop DFF3, the input of the first delay unit td1, and the input of the second NOT gate N2, respectively; wherein the first delayed signal P0 is delayed by half a cycle of the high-frequency clock CLK compared to the divided signal gen. The second input of the third D flip-flop DFF3 is connected to the high-frequency clock CLK, and its output outputs a second delayed signal P1, which is connected to the first input of the fourth D flip-flop DFF4 and the first input of the second NAND gate NAND2, respectively; wherein the second delayed signal P1 is delayed by half a cycle of the high-frequency clock CLK compared to the first delayed signal P0. The second input of the fourth D flip-flop DFF4 is connected to the high-frequency clock CLK, and its output is connected to the input of the third NOT gate N3, and is used to output the second control signal P2. The output of the third NOT gate is connected to the second input of the second NAND gate to perform a logical NOT operation on the second control signal P2, outputting the logically NOT second control signal P2 back to the second input of the second NAND gate. The output of the second NAND gate NAND2 is connected to the input of the second delay unit td2. The output of the second delay unit td2 is used to output the first control signal WP. The first input of the first NAND gate NAND1 is connected to the output of the first delay unit td1, and the second input is connected to the output of the second NOT gate N2. The output is used to output the third control signal NewRS.
[0029] Optionally, the frequency divider includes a 16-divider.
[0030] Optionally, the first delay unit td1 is used to delay the input first delay signal P0 by 200 ps (picoseconds) to ensure that the low level of the third control signal NewRS can fully perform the function of clearing the first D flip-flop DFF1.
[0031] Optionally, the second delay unit td2 is used to delay the input signal by 200 ps (picoseconds) or equivalent, so that the rising edge of the first control signal WP lags behind the rising edge of the adjustment signal CK1HZ_low.
[0032] In some embodiments, reference Figure 3 As shown, the synchronization mask module 200 includes a logic processing unit 210, a fifth D flip-flop DFF5, an OR gate, a third delay td3, a fourth NOT gate N4, a third NAND gate NAND3, and a second AND gate A2.
[0033] The logic processing unit 210 has a first input terminal connected to the power-on signal Porb, a second input terminal connected to the read stop signal Stop, and an output terminal connected to the clear terminal of the fifth D flip-flop DFF5, outputting a second clear signal rstb_mask. The fifth D flip-flop DFF5 has a first input terminal connected to a preset voltage vdd, a second input terminal connected to the read start signal Read, and an output terminal connected to the first input terminal of the OR gate. The OR gate has a second input terminal connected to the read start signal Read, and an output terminal connected to the input terminals of the third delay unit td3 and the fourth NOT gate N4, outputting the read mask signal mask. The third NAND gate NAND3 has a first input terminal connected to the output terminal of the fourth NOT gate N4, a second input terminal connected to the output terminal of the third delay unit td3, and an output terminal connected to the first input terminal of the second AND gate A2, outputting a keeplow_n signal to the first input terminal of the second AND gate A2. The second input terminal of the second AND gate A2 has the third control signal NewRS connected to it, a third input terminal connected to the power-on signal Porb, and an output terminal outputting a first clear signal keeplow. The third delay unit td3 can delay the read mask signal mask and output the delayed mask signal mask_del.
[0034] Optionally, the third delay unit td3 is used to delay the input read mask signal mask by 200ps to ensure that the low level of the signal keeplow_n is sufficient to clear the first D flip-flop DFF1. In some examples, such as Figure 3 As shown, the logic processing unit 210 includes a fifth NOT gate N5, a sixth NOT gate N6, and an NOR gate NOR2.
[0035] The input of the fifth NOT gate N5 serves as the first input of the logic processing unit 210, used to receive the power-on signal Porb, and its output is connected to the first input of the NOR gate NOR2. The input of the sixth NOT gate N6 serves as the second input of the logic processing unit 210, used to receive the stop signal Stop, and its output is connected to the first input of the fourth NAND gate NAND4. The output of the NOR gate NOR2 serves as the output of the logic processing unit 210, used to output the second clear signal rstb_mask.
[0036] In some examples, the overall structure diagram of the clock generator can be referenced. Figure 4 As shown, the signals generated by the clock generator during operation can be referenced. Figure 5As shown, the frequency divider DIV divides the high-frequency clock CLK by 16 to obtain the divided signal gen. The second D flip-flop DFF2 delays the divided signal gen by half a cycle of the high-frequency clock CLK to obtain the first delayed signal P0. The third D flip-flop DFF3 delays the first delayed signal P0 by half a cycle of the high-frequency clock CLK to obtain the second delayed signal P1. The fourth D flip-flop DFF4 delays the second delayed signal P1 by half a cycle of the high-frequency clock CLK to obtain the second control signal P2. The first NAND gate NAND1 performs a NAND operation on the delayed signal and the inverted signal corresponding to the first delayed signal P0, outputting the third control signal NewRS. The second NAND gate NAND2 performs a NAND operation on the inverted signals corresponding to the second delayed signal P1 and the second control signal P2; the second delay unit td2 delays the signal after the NAND operation of the second NAND gate NAND2, outputting the first control signal WP. The logic processing unit 210 has a power-on signal Porb at its first input, a read stop signal Stop at its second input, a preset level at its third input, and a third control signal NewRS at its fourth input. Its output is a second clear signal rstb_mask. The fifth D flip-flop DFF5 has a preset voltage vdd at its first input, a read start signal Read at its second input, and its output is connected to the first input of an OR gate. The OR gate performs an OR operation on the read start signal Read and the signal output from the fifth D flip-flop DFF5, outputting a read mask signal mask. The third NAND gate NAND3 performs an AND operation on the inverted signal corresponding to the mask signal mask and the delayed mask signal mask_del, outputting a keeplow_n signal. The second AND gate A2 performs an AND operation on the keeplow_n signal, the third control signal NewRS, and the power-on signal Porb, outputting a first clear signal keeplow. The first D flip-flop DFF1 delays the read mask signal mask according to the second control signal P2, and outputs the adjustment signal CK1HZ_low under the clearing control of the first clear signal keeplow. The first NOT gate N1 performs a logical NOT operation on the adjustment signal CK1HZ_low, and outputs the adjustment signal CK1HZ_low_n, which is characterized as a low level during the data toggle period of the real-time counter. The first AND gate A1 performs an AND operation on the first control signal WP and the adjustment signal CK1HZ_low_n, and outputs the read control clock OUT. The duty cycle of the read control clock OUT can be dynamically adjusted according to the data toggle period of each time data providing unit in the real-time counter. In this way, when the asynchronous read circuit performs the read task according to the read control clock OUT, it can avoid the data toggle period of each time data providing unit, ensuring the accuracy of the read time data and thus ensuring the reliability of the asynchronous read circuit.
[0037] In the above clock generator, the clock control module 100, the synchronization mask module 200, the first D flip-flop DFF1, the first NOT gate N1, and the first AND gate A1 cooperate to use a high-frequency clock CLK to perform logical processing on signals such as the start signal Read and / or the read stop signal Stop, which are used to determine the data flipping periods of each time data providing unit in the real-time counter. This generates a read control clock OUT whose duty cycle can be dynamically adjusted according to the data flipping periods of each time data providing unit. This allows the asynchronous read circuit to avoid the data flipping periods of each time data providing unit when performing the read task according to the read control clock OUT, ensuring the accuracy of the read time data and thus ensuring the reliability of the asynchronous read circuit. The above clock generator does not require any data buffer and does not consume the time margin of SPI / IIC. It only dynamically adjusts the rising edge position of the read control clock OUT of the asynchronous read circuit so that the time data reading time avoids the data flipping period, which simplifies the related design and corresponding circuit structure.
[0038] A second aspect of this application provides an asynchronous readout circuit, the asynchronous readout circuit including the clock generator described in any of the above embodiments.
[0039] In some embodiments, the asynchronous read circuit further includes a multi-channel selector, a read switch, multiple data generation units, and D flip-flops corresponding to each data generation unit. Each data generation unit and its corresponding D flip-flop form a data providing unit for providing time data such as seconds, minutes, hours, days, months, and years. For example, see reference... Figure 6 As shown, the asynchronous read circuit includes a clock generator 410, a multi-channel selector 420, a read switch 430, and multiple data supply units 440. Figure 6 The data providing unit 440 shown includes data providing units such as a second parameter providing unit, a minute parameter providing unit, an hour parameter providing unit, a day parameter providing unit, a month parameter providing unit, and a year parameter providing unit.
[0040] In each data providing unit 440, the clock terminal of the corresponding D flip-flop is connected to the read control clock OUT, which is used to provide time data, such as time data in seconds, minutes, hours, days, months and years, according to the read control clock OUT. Each input terminal of the multi-channel selector 420 is connected to the output terminal of a data providing unit 410, the control terminal is connected to a channel selection signal, and the output terminal outputs the time data provided by the data providing unit 440 selected according to the channel selection signal. The read switch 430 is used to connect the data read path of the selected data providing unit 440 according to the read start signal.
[0041] The asynchronous read circuit described above includes the clock generator described in any of the above embodiments, and has all the beneficial effects of the clock generator described in any of the preceding embodiments, which will not be repeated here.
[0042] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if structurally not equivalent to the disclosed structure performing the functions in the exemplary implementations of this specification shown herein.
[0043] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between different embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.
[0044] Furthermore, it should be understood that in the description of this application, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Additionally, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. Moreover, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0045] In this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as more preferred or advantageous than other embodiments. This application has been provided above to enable any person skilled in the art to implement and use it. Various details have been set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.
Claims
1. A clock generator, characterized in that, The clock generator is used to generate the read control clock for the asynchronous read circuit in the real-time counter; The clock generator includes a clock control module, a synchronization mask module, a first D flip-flop, a first NOT gate, and a first AND gate; The clock control module is used to access a high-frequency clock and generate a first control signal WP, a second control signal P2 and a third control signal NewRS according to the high-frequency clock. The synchronization mask module is used to receive the read start signal Read, the read stop signal Stop, the power-on signal Porb, the first control signal WP, the second control signal P2, and the third control signal NewRS, and to generate the read mask signal mask and the first clear signal keeplow; The first input terminal of the first D flip-flop is connected to the read mask signal mask, the second input terminal is connected to the second control signal P2, and the clear terminal is connected to the first clear signal keeplow, so as to generate an adjustment signal CK1HZ_low according to the read mask signal mask, the second control signal P2 and the first clear signal keeplow; The first NOT gate is used to perform a logical NOT operation on the adjustment signal CK1HZ_low, so that the adjusted signal CK1HZ_low_n after the logical NOT operation is characterized as a low level during the data toggling period of the real-time counter; The first input terminal of the first AND gate is connected to the first control signal WP, the second input terminal is connected to the adjustment signal CK1HZ_low_n after the logical NOT operation, and the output terminal outputs the read control clock so that the asynchronous read circuit avoids the data flipping period when performing the read task according to the read control clock.
2. The clock generator according to claim 1, characterized in that, The clock control module includes a frequency divider, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a first delay unit, a second delay unit, a second NOT gate, a third NOT gate, a first NAND gate, and a second NAND gate; The input terminal of the frequency divider is connected to the high-frequency clock, and the output terminal is connected to the first input terminal of the second D flip-flop; the second input terminal of the second D flip-flop is connected to the high-frequency clock, and the output terminal is connected to the first input terminal of the third D flip-flop, the input terminal of the first delay unit, and the input terminal of the second NOT gate, respectively; the second input terminal of the third D flip-flop is connected to the high-frequency clock, and the output terminal is connected to the first input terminal of the fourth D flip-flop and the first input terminal of the second NAND gate, respectively; the second input terminal of the fourth D flip-flop is connected to the high-frequency clock, and the output terminal is connected to the input terminal of the third NOT gate, and is used to output the second control signal P2; the output terminal of the third NOT gate is connected to the second input terminal of the second NAND gate; the output terminal of the second NAND gate is connected to the input terminal of the second delay unit; the output terminal of the second delay unit is used to output the first control signal WP; the first input terminal of the first NAND gate is connected to the output terminal of the first delay unit, the second input terminal is connected to the output terminal of the second NOT gate, and the output terminal is used to output the third control signal NewRS.
3. The clock generator according to claim 2, characterized in that, The frequency divider includes a 16-divider.
4. The clock generator according to claim 1, characterized in that, The synchronization mask module includes a logic processing unit, a fifth D flip-flop, an OR gate, a third delay unit, a fourth NOT gate, a third NAND gate, and a second AND gate; The logic processing unit has a first input terminal connected to a power-on signal Porb, a second input terminal connected to a read stop signal Stop, and an output terminal connected to the clear terminal of the fifth D flip-flop. The fifth D flip-flop has a first input terminal connected to a preset voltage, a second input terminal connected to the read start signal Read, and an output terminal connected to the first input terminal of the OR gate. The OR gate has a second input terminal connected to the read start signal Read, and an output terminal connected to the input terminals of the third delay unit and the fourth NOT gate, respectively, and outputs the read mask signal mask. The first input terminal of the third NAND gate is connected to the output terminal of the fourth NOT gate, the second input terminal is connected to the output terminal of the third delay unit, and the output terminal is connected to the first input terminal of the second AND gate; the second input terminal of the second AND gate is connected to the third control signal NewRS, the third input terminal is connected to the power-on signal Porb, and the output terminal outputs the first clear signal keeplow.
5. The clock generator according to claim 4, characterized in that, The logic processing unit includes a fifth NOT gate, a sixth NOT gate, and an OR NOT gate; The input terminal of the fifth NOT gate serves as the first input terminal of the logic processing unit, used to receive the power-on signal, and its output terminal is connected to the first input terminal of the NOR gate; the input terminal of the sixth NOT gate serves as the second input terminal of the logic processing unit, used to receive the stop signal, and its output terminal is connected to the first input terminal of the fourth NAND gate; the output terminal of the NOR gate serves as the output terminal of the logic processing unit.
6. An asynchronous read circuit, characterized in that, The asynchronous readout circuit includes the clock generator as described in any one of claims 1 to 5.
7. The asynchronous read circuit according to claim 6, characterized in that, The asynchronous read circuit also includes a multi-channel selector, a read switch, multiple data generation units, and D flip-flops corresponding to each data generation unit; each data generation unit and its corresponding D flip-flop form a corresponding data providing unit. In each of the data providing units, the clock terminal of the corresponding D flip-flop is connected to the read control clock OUT, which is used to provide time data according to the read control clock OUT; Each input of the multi-channel selector is connected to the output of a data providing unit, the control terminal is connected to a channel selection signal, and the output terminal outputs the time data provided by the data providing unit selected according to the channel selection signal. The read switch is used to connect the data read path of the selected data providing unit according to the read start signal.